DS1230YP-100+ [MAXIM]
Non-Volatile SRAM Module, 32KX8, 100ns, CMOS, ROHS COMPLIANT, POWERCAP MODULE-34;
| 型号： | DS1230YP-100+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Non-Volatile SRAM Module, 32KX8, 100ns, CMOS, ROHS COMPLIANT, POWERCAP MODULE-34 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5635; Rev 11/10
DS1230Y/AB
256k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
. 10 years minimum data retention in the
absence of external power
A14
A12
A7
1
28
27
VCC
WE
A13
A8
2
3
4
26
25
. Data is automatically protected during power
loss
. Replaces 32k x 8 volatile static RAM,
EEPROM or Flash memory
. Unlimited write cycles
. Low-power CMOS
A6
A5
A4
5
6
24
23
A9
A11
OE
A10
CE
A3
A2
7
8
22
21
A1
9
20
19
10
A0
DQ7
DQ6
DQ5
. Read and write access times of 70 ns
. Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
11
12
18
17
DQ0
DQ1
DQ2
GND
13
14
16
15
DQ4
DQ3
. Full ±10% VCC operating range (DS1230Y)
. Optional ±5% VCC operating range
(DS1230AB)
28-Pin Encapsulated Package
740-mil Extended
. Optional industrial temperature range of
-40°C to +85°C, designated IND
. JEDEC standard 28-pin DIP package
. PowerCap Module (PCM) package
NC
NC
A14
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
NC
NC
A13
A12
A11
A10
A9
NC
VCC
WE
OE
CE
-
-
Directly surface-mountable module
Replaceable snap-on PowerCap provides
lithium backup battery
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
GND VBAT
-
-
Standardized pinout for all nonvolatile
SRAM products
Detachment feature on PowerCap allows
easy removal using a regular screwdriver
DQ2
DQ1
DQ0
GND
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A14
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
WE
OE
VCC
GND
NC
- No Connect
1 of 10
DS1230Y/AB
DESCRIPTION
The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as
32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices
in the Low Profile Module package are specifically designed for surface-mount applications. There is no
limit on the number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
READ MODE
The DS1230 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 - A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after
address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then
WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1230Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEAL
Each DS1230 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source
is enabled for battery back-up operation.
2 of 10
DS1230Y/AB
PACKAGES
The DS1230 devices are available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM).
The 28-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1230 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
3 of 10
DS1230Y/AB
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
-0.3V to +6.0V
0°C to +70°C
Industrial:
-40°C to +85°C
Storage Temperature Range
EDIP
PowerCap
Lead Temperature (soldering, 10s)
Note: EDIP is wave or hand soldered only.
Soldering Temperature (reflow, PowerCap)
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1230AB Power Supply Voltage
DS1230Y Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0.0
V
V
V
V
5.0
VCC
0.8
Logic 0
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS1230AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1230Y)
PARAMETER
SYMBOL MIN
TYP
MAX
+1.0
UNITS NOTES
Input Leakage Current
IIL
IIO
-1.0
-1.0
-1.0
2.0
µA
µA
mA
mA
µA
µA
mA
V
+1.0
I/O Leakage Current CE ≥ VIH ≤ VCC
Output Current @ 2.4V
IOH
Output Current @ 0.4V
IOL
ICCS1
ICCS2
ICCO1
VTP
VTP
200
50
600
150
85
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
Operating Current
Write Protection Voltage (DS1230AB)
Write Protection Voltage (DS1230Y)
4.50
4.25
4.62
4.37
4.75
4.5
V
CAPACITANCE
PARAMETER
(TA = +25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
10
Input Capacitance
CIN
5
5
pF
pF
Input/Output Capacitance
CI/O
10
4 of 10
DS1230Y/AB
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS1230AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1230Y)
DS1230AB-70
DS1230Y-70
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
tRC
tACC
tOE
70
ns
ns
ns
ns
ns
Access Time
70
35
70
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
tCO
tCOE
5
5
5
5
Output High-Z from
Deselection
tOD
25
ns
ns
Output Hold from Address
Change
tOH
tWC
tWP
Write Cycle Time
Write Pulse Width
Address Setup Time
70
55
0
ns
ns
ns
3
tAW
tWR1
tWR2
tODW
tOEW
tDS
5
12
13
5
Write Recovery Time
ns
15
25
ns
ns
ns
Output High-Z from WE
Output Active from WE
Data Setup Time
5
30
0
5
4
tDH1
tDH2
12
13
Data Hold Time
ns
10
5 of 10
DS1230Y/AB
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
6 of 10
DS1230Y/AB
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL MIN
tPD
tF
TYP
MAX
UNITS NOTES
1.5
11
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V
µs
µs
150
150
VCC slew from 0V to VTP
tR
µs
tPU
tREC
2
ms
ms
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection
125
7 of 10
DS1230Y/AB
(TA = +25°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
tDR 10
TYP
MAX
Expected Data Retention Time
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1230 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1230 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
8 of 10
DS1230Y/AB
ORDERING INFORMATION
SUPPLY
TOLERANCE
5V ± 5%
SPEED GRADE
PART
TEMP RANGE
PIN-PACKAGE
(ns)
70
70
70
70
70
70
70
70
DS1230AB-70+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
28 740 EDIP
34 PowerCap*
28 740 EDIP
34 PowerCap*
28 740 EDIP
34 PowerCap*
28 740 EDIP
34 PowerCap*
DS1230ABP-70+
DS1230AB-70IND+
DS1230ABP-70IND+
DS1230Y-70+
5V ± 5%
5V ± 5%
5V ± 5%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
DS1230YP-70+
DS1230Y-70IND+
DS1230YP-70IND+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0245
LAND PATTERN NO.
—
28 EDIP
MDT28+3
—
34 PCAP
PC2+4
21-0246
9 of 10
DS1230Y/AB
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Added package information table; removed the DIP module
package drawing and dimension table
121907
9, 10
Updated the storage information, soldering temperature, and
lead temperature information in the Absolute Maximum Ratings
section; removed the -85, -100, -120, -150, and -200
MIN/MAX information from the AC Electrical Characteristics
table; updated the Ordering Information table (removed -85,
-100, -120, -150, and -200 parts and leaded -70 parts); removed
the PowerCap module drawings and updated the Package
Information table
11/10
1, 4, 5, 9
10 of 10
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