DS1238S-5+T&R [MAXIM]
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO16, 0.300 INCH, SOIC-16;
| 型号： | DS1238S-5+T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO16, 0.300 INCH, SOIC-16 光电二极管 |
| 文件： | 总14页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1238
MicroManager
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Holds microprocessor in check during power
transients
VBAT
VCCO
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
WDS
CEI
CEO
ST
ꢀ Halts and restarts an out-of-control
microprocessor
ꢀ Warns microprocessor of an impending power
failure
ꢀ Converts CMOS SRAM into nonvolatile
memory
ꢀ Unconditionally write-protects memory when
power supply is out of tolerance
ꢀ Delays write protection until completion of
the current memory cycle
VBAT
VCCO
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
WDS
CEI
CEO
ST
GND
PF
GND
RVT
PF
OSCIN
OSCSEL
NMI
IN
RVT
OSCIN
OSCSEL
NMI
IN
16-Pin DIP (300-mil)
16-Pin SOIC (300-mil)
See Mech. Drawings Section
See Mech. Drawings Section
ꢀ Consumes less than 200 nA of battery current
ꢀ Controls external power switch for high
current applications
ꢀ Debounces pushbutton reset
ꢀ Accurate 10% power supply monitoring
ꢀ Optional 5% power supply monitoring
designated DS1238-5
PIN DESCRIPTION
VBAT
VCCO
VCC
GND
PF
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
ꢀ Provides orderly shutdown in microprocessor
applications
- Power-Fail
RVT
OSCIN
OSCSEL
IN
- Reset Voltage Threshold
- Oscillator In
- Oscillator Select
- Early Warning Input
- Non-Maskable Interrupt
- Strobe Input
ꢀ Pin-for-pin compatible with MAX691
ꢀ Standard 16-pin DIP or space-saving 16-pin
SOIC
ꢀ Optional industrial temperature range -40°C
to +85°C
NMI
ST
CEO
- Chip Enable Output
- Chip Enable Input
- Watchdog Status
- Reset Output (active low)
- Reset Output (active high)
CEI
WDS
RST
RST
DESCRIPTION
The DS1238 MicroManager provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference and
comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1238 also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
1 of 14
111899
DS1238
debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to
the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins
OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and
the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS
and RVT , respectively. A block diagram of the DS1238 is shown in Figure 1.
PIN DESCRIPTION
PIN NAME
DESCRIPTION
VBAT
+3V battery input provides nonvolatile operation of control functions.
VCC output for nonvolatile SRAM applications.
+5V primary power input.
VCCO
VCC
GND
PF
System ground.
Power-fail indicator, active high, used for external power switching as shown in
Figure 9.
Reset Voltage Threshold. Indicates that VCC is below the reset voltage threshold.
Oscillator input or timing capacitor. See Table 1.
RVT
OSCIN
OSCSEL
IN
Oscillator Select. Selects internal or external clock functions. See Table 1.
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
NMI
ST
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Write protected. Used with nonvolatile SRAM applications.
Chip enable input.
CEO
CEI
Watchdog Status. Indicates that a watchdog timeout has occurred.
Active low reset output.
WDS
RST
RST
Active high reset output.
POWER MONITOR
The DS1238 employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT ,
RST, and RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation
so that the RVT , RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical).
The VCCTP for the 5% operation option (DS1238-5) is set for 4.75 volts (4.62 typical). The RST and RST
signals are excellent for microprocessor reset control, as processing is stopped at the last possible moment
of in-tolerance VCC. On power up, RVT will become inactive as soon as VCC rises above VCCTP. However,
the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after VCCTP is reached
to allow the power supply and microprocessor to stabilize.
2 of 14
DS1238
DS1238 FUNCTIONAL BLOCK DIAGRAM Figure 1
WATCHDOG TIMER
The DS1238 provides a watchdog timer function which forces the WDS , RST, and RST signals to the
active state when the strobe input (ST ) is not stimulated for a predetermined time period. This time period
is described below in Table 1. The watchdog timeout period begins as soon as RST and RST are inactive.
If a high-to-low transition occurs at the ST input prior to timeout, the watchdog timer is reset and begins
to time out again. The ST input timing is shown in Figure 2. In order to guarantee that the watchdog timer
does not time out, a high-to-low transition on ST must occur at or less than the minimum timeout of the
watchdog as described in the AC Electrical Characteristics. If the watchdog timer is allowed to time out,
the WDS , RST, and RST outputs are driven to the active state. WDS is a latched signal which indicates
the watchdog status, and is activated as soon as the watchdog timer completes a full period as outlined in
3 of 14
DS1238
Table 1. The WDS pin will remain low until one of three operations occurs. The first is to strobe the ST
pin with a falling edge, which will both set the WDS as well as the watchdog timer count. The second is
to leave the ST pin open, which disables the watchdog. Lastly, the WDS pin is active low whenever VCC
falls below VCCTP and activates the RVT signal. The ST input can be derived from microprocessor
address, data, or control signals, as well as microcontroller port pins. Under normal operating conditions,
these signals would routinely reset the watchdog timer prior to time out. The watchdog is disabled by
leaving the ST input open, or as soon as VCC falls to VCCTP
.
NON-MASKABLE INTERRUPT
The DS1238 generates a non-maskable interrupt ( NMI ) for early warning of a power failure to the
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to an on-chip
reference generated by an internal band gap. The IN pin is a high impedance input allowing for a user-
defined sense point. An external resistor voltage divider network (Figure 5) is used to interface with high
voltage signals. This sense point may be derived from the regulated 5-volt supply, or from a higher DC
voltage level closer to the main system power input. Since the IN trip point VTP is 1.27 volts, the proper
values for R1 and R2 can be determined by the equation as shown in Figure 5. Proper operation of the
DS1238 requires that the voltage at the IN pin be limited to VIH. Therefore, the maximum allowable
voltage at the supply being monitored (VMAX) can also be derived as shown in Figure 5. A simple
approach to solving this equation is to select a value for R2 of high enough value to keep power
consumption low and solve for R1. The flexibility of the IN input pin allows for detection of power loss
at the earliest point in a power supply system, maximizing the amount of time for microprocessor
shutdown between NMI and RST or RST .
When the supply being monitored decays to the voltage sense point, the DS1238 will force the NMI
output to an active state. Noise is removed from the NMI power-fail detection circuitry using built-in
time domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30kHz (33 µs/cycle). Three consecutive samplings of
out-of-tolerance supply (below VSENSE) must occur at the IN pin to active NMI . Therefore, the supply
must be below the voltage sense point for approximately 100 µs or the comparator will reset. In this way,
power supply noise is removed from the monitoring function preventing false trips. During a power-up,
any IN pin levels below VTP detected by the comparator are disabled from reaching the NMI I pin until
VCC rises to VCCTP. As a result, any potential active NMI will not be initiated until VCC reaches VCCTP
.
Removal of an active low level on the NMI pin is controlled by the subsequent rise of the IN pin above
VTP. The initiation and removal of the NMI signal during power up depends on the relative voltage
relationship between VCC and the IN pin voltage. Note that a fast-slewing power supply may cause the
NMI to be virtually nonexistent on power up. This is of no consequence, however, since an RST will be
active. The NMI voltage will follow VCC down until VCC decays to VBAT. Once VCC decays to V BAT , the
NMI pin will enter a tri-state mode.
ST INPUT TIMING Figure 2
4 of 14
DS1238
OSCILLATOR CONTROLS Table 1
Watchdog Timeout Period (typ)
OSCIN OSCSEL
First Period
Other Timeout
Reset Active
Following a Reset
Duration
641 Clks
69 ms
47 pf
85 ms
85 ms
Ext Clk
Ext Cap
Low
Low
20480 Clks
5120 Clocks
External
Internal
2.2 sec
X Cpf
47 pf
550 ms
X Cpf
47 pf
X Cpf
Low
Hi/Open
Hi/Open
2.7 sec
2.7 sec
170 ms
2.7 sec
Hi/Open
Note that the OSCIN and OSCSEL pins are tri-stated when VCC is below VBAT
.
POWER MONITOR, WATCHDOG TIMER, AND PUSHBUTTON RESET Figure 3
PUSHBUTTON RESET TIMING Figure 4
5 of 14
DS1238
NON-MASKABLE INTERRUPT Figure 5
R1+R2
VSENSE
=
x 1.27
R2
VSENSE
1.27
MAXVOLTAGE =
x 5.0 = VMAX
Example 1: 5 Volt Supply, R2 = 10k Ohms,
VSENSE = 4.8 Volts
Example 2: 12 Volt Supply, R2 = 10k Ohms,
VSENSE = 9.0 Volts
R1+10k
R1+10k
4.8 =
x 1.27 ≥ R1 = 27.8k Ohm
9.0 =
x 1.27 ≥ R1 = 60.9k Ohm
10k
10k
9.00
1.27
VMAX
=
x 5.0 = 35.4 Volts
NMI FROM IN INPUT Figure 6
6 of 14
DS1238
MEMORY BACKUP
The DS1238 provides all of the necessary functions required to battery back a static RAM. First, an
internal switch is provided to supply SRAM power from the primary 5-volt supply (VCC) or from an
external battery (VBAT), whichever is greater. Second, the same power-fail detection described in the
power monitor section is used to hold the chip enable output (CEO ) to within 0.3 volts of VCC or to within
0.7 volts of VBAT. The output voltage diode drop from VBAT (0.7 V) is necessary to prevent charging of
the battery in violation of UL standards. Write protection occurs as VCC falls below VCCTP as specified. If
CEI is low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned
high, or the period tCE expires. This delay of write protection until the current memory cycle is completed
prevents the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will
be unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage and/or shipment of an end system, the DS1238
provides an internal freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses
below ground on the IN pin required to invoke the freshness seal. The freshness seal will result in the tri-
state of outputs VCCO, RST, RST , and CEO . The WDS output will be driven active low. The PF pin is not
disabled by the freshness mode and will continue to source power from the VBAT pin whenever VCC is
below VBAT. The freshness seal will be disconnected and normal operation will begin when VCC is cycled
and reapplied to a level above VBAT
.
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to -3-volt clock to TP1.
POWER SWITCHING
When larger operating currents are required in a battery-backed system, the internal switching devices of
the DS1238 may be too small to support the required load through VCCO with a reasonable voltage drop.
For these applications, the PF output is provided to gate external power switching devices. As shown in
Figure 9, power to the load is switched from VCC to battery on power-down, and from battery to VCC on
power-p. The DS1336 is designed to use the PF output to switch between VBAT and VCC. It provides
better leakage and switchover performance than currently available discrete components. The transition
threshold for PF is set to the external battery voltage VBAT, allowing a smooth transition between sources.
Any load applied to the PF pin by an external switch will be supplied by the battery. Therefore, if a
discrete switch is used, this load should be taken into consideration when sizing the battery.
7 of 14
DS1238
NONVOLATILE SRAM Figure 7
FRESHNESS SEAL Figure 8
Note: This series of pulses must be applied during normal +5 volt operation.
8 of 14
DS1238
POWER SWITCHING Figure 9
Note: If freshness on the DS1238 is not used, PF on the DS1336 may be tied to OUT1. This will free IN4, OUT4,
and VBAT01 for system use.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 10 and Figure 11. Figure 10
illustrates the relationship for power down. As VCC falls, the IN pin voltage drops below VTP. As a result,
the processor is notified of an impending power failure via an active NMI . This gives the processor time
to save critical data in nonvolatile SRAM. As the power falls further, VCC crosses VCCTP, the power
monitor trip point. When VCC reaches VCCTP, and active RST and RST are given. At this time, CEO is
brought high to write-protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF pin.
Figure 11 shows the power-up sequence. As VCC slews above VBAT, the PF pin is deactivated. An active
reset occurs as well as an NMI . Although the NMI may be short due to slew rates, reset will be
maintained for the standard tRPU timeout period . At a later time, if the IN pin falls below VTP, a new NMI
will occur. If the processor does not issue an ST , a watchdog reset will also occur. The second NMI and
RST are provided to illustrate these possibilities.
9 of 14
DS1238
POWER-DOWN TIMING Figure 10
10 of 14
DS1238
POWER-UP TIMING Figure 11
11 of 14
DS1238
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to Ground
Voltage on I/O Relative to Ground
Voltage on IN Pin Relative to Ground
Operating Temperature
-0.5V to +7.0V
-0.5V to VCC + 0.5V
-3.5V to VCC + 0.5V
0°C to 70°C
Operating Temperature (Industrial Version)
Storage Temperature
Soldering Temperature
-40°C to +85°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
5.5
UNITS NOTES
Supply Voltage
VCC
4.5
5.0
V
V
V
V
V
V
1
1
1
1
1
1
Supply Voltage (5% Option)
Input High Level
Input Low Level
IN Input Pin
VCC
4.75
2.0
5.0
5.5
VIH
VCC+0.3
+0.8
VCC
VIL
-0.3
0
VIN
Battery Input
VBAT
2.7
4.0
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VDD= 5V ± 10%)
PARAMETER
Supply Current
Battery Current
SYMBOL
MIN
TYP
MAX
UNITS NOTES
ICC
4
mA
nA
2
2, 12
3
IBAT
0
200
100
Supply Output Current
(VCCO=VCC - 0.3V)
ICC01
mA
Supply Out Current (VCC < VBAT
Supply Output Voltage
Battery Back Voltage
Low Level @ RST
)
ICC02
VCCO
VCCO
VOL
VOH
VOHL
ILI
1
mA
V
4
1
VCC-0.3
VBAT-0.8
V
6
0.4
V
1
VCC-0.5V VCC-0.1V
V
1
Output Voltage @ -500 µA
CEO and PF Output
VBAT-0.8
V
6
Input Leakage Current
Output Leakage Current
Output Current @ 0.4V
Output Current @ 2.4V
Power Sup. Trip Point
Power Supply Trip (5% Option)
IN Input Pin Current
-1.0
-1.0
+1.0
+1.0
4.0
121
µA
µA
mA
mA
V
ILO
IOL
9
10
1
IOH
-1.0
VCCTP
VCCTP
ICCIN
VTP
4.25
4.50
-1.0
1.15
4.37
4.62
4.50
4.75
+1.0
1.35
V
µA
V
IN Input Trip Point
1.27
1
12 of 14
DS1238
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5V ± 10%)
PARAMETER
SYMBOL
tRPD
tIPD
MIN
40
TYP
100
100
85
MAX
UNITS NOTES
175
VCC Fail Detect to RST, RST
VTP to NMI
µs
µs
40
175
RESET Active OSCSEL=High
ST Pulse Width
tRST
tST
40
150
ms
20
ns
ms
µs
ns
13
PBRST @ VIL
tPB
30
VCC Slew Rate 4.75 to 4.25
Chip Enable Prop Delay
VCC Fail to Chip Enable High
VCC Valid to RST (RC=1)
VCC Valid to RST
tF
300
tPF
20
44
tCF
7
12
11
5
µs
ns
tFPU
tRPU
tFB1
tREC
100
150
40
10
100
ms
µs
µs
VCC Slew to 4.25 to VBAT
Chip Enable Output Recovery
Time
0.1
7
VCC Slew 4.25 to 4.75
tR
0
µs
µs
s
Chip Enable Pulse Width
tCE
tTD
5
8
Watchdog Time Delay Internal
Clock Long period
1.7
2.7
Short Period
110
170
ms
Watchdog Time Delay, External
Clock, after Reset
tTD
20480
clocks
Normal
5120
clocks
µs
VBAT Detect to PF
OSC IN Frequency
tPPF
2
fOSC
0
250
kHz
CAPACITANCE
PARAMETER
(tA=25°C)
UNITS NOTES
SYMBOL
CIN
MIN
TYP
MAX
Input Capacitance
Output Capacitance
5
7
pF
pF
COUT
13 of 14
DS1238
NOTES:
1. All voltages referenced to ground.
2. Measured with VCCO, CEO , PF, ST , RST, RST , and NMI pin open.
3. ICCO1 is the maximum average load which the DS1238 can supply at VCC-.3V through the VCCO pin
during normal 5-volt operation.
4. ICCO2 is the maximum average load which the DS1238 can supply through the VCCO pin during data
retention battery supply operation, with a maximum drop of 0.8 volts for commercial, 1.0V for
industrial.
5. With tR = 5 µs.
6. VCCO is approximately VBAT-0.5V at 1 µA load.
7. tREC is the minimum time required before CEI /CEO memory access is allowed.
8. tCE maximum must be met to insure data integrity on power loss.
9. All outputs except RST which is 25 µA max.
10. All outputs except RST , RVT , and NMI which is 25 µA min.
11. The ST pin will sink +50 µA in normal operation. The OSCIN pin will sink ±5 µA in normal
operation. The OSCSEL pin will sink ±10 µA in normal operation.
12. IBAT is measured with VBAT=3.0V.
13. ST should be active low before the watchdog is disabled (i.e., before the ST input is tristated).
14 of 14
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