DS1248P-100 [MAXIM]
Real Time Clock, CMOS, POWER, MODULE, DFP-34;
| 型号： | DS1248P-100 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, CMOS, POWER, MODULE, DFP-34 |
| 文件： | 总21页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
•
Real time clock keeps track of hundredths of
RST
A16
A14
A12
A7
seconds, minutes, hours, days, date of the
month, months, and years
1
32
31
VCC
A15
NC
WE
A13
A8
2
3
4
30
29
•
•
•
•
=128K x 8 NV SRAM directly replaces
volatile static RAM or EEPROM
=Embedded lithium energy cell maintains
calendar operation and retains RAM data
=Watch function is transparent to RAM
operation
=Month and year determine the number of
days in each month; valid up to 2100
=Full 10% operating range
=Operating temperature range 0°C to 70°C
=Over 10 years of data retention in the
absence of power
=Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
5
6
28
27
A6
A5
A9
7
8
26
25
A11
OE
A10
CE
A4
A3
A2
A1
9
10
24
23
11
12
22
21
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
GND
13
14
15
16
20
19
18
17
•
•
•
32-PIN ENCAPSULATED PACKAGE
740 MIL FLUSH
•
•
•
=DIP Module only
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
1
2
3
4
5
6
7
8
9
– Standard 32–pin JEDEC pinout
– Upward comparable with the DS1248
=PowerCap Module Board only
– Surface mountable package for direct
connection to PowerCap containing
battery and crystal
NC
A15
A16
A13
A12
A11
A10
A9
RST
VCC
WE
OE
CE
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
13
14
15
16
17
– Replaceable battery (PowerCap)
– Pin for pin compatible with DS1244P
and DS1251P
DQ2
DQ1
DQ0
GND
VBAT X2
X1 GND
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
1 of 21
111999
DS1248/DS1248P
ORDERING INFORMATION
DS1248YP–XXX (5 Volt)
-70 70 ns access
-100 100 ns access
blank 32-pin DIP Module
P
34-pin PowerCap Module board*
DS1243WP-XXX (3.3 Volt)
-120 120 ns access
-150 150 ns access
blank 32-pin DIP Module
P
34-pin PowerCap Module
board*
*DS9034PCX (PowerCap) Required:
(must be ordered separately)
PIN DESCRIPTION
A0–A16
– Address Inputs
CE
– Chip Enable
OE
– Output Enable
WE
– Write Enable
VCC
– Power Supply Input
– Ground
– Data In/Data Out
– No Connection
– Crystal Connection
– Battery Connection
GND
DQ0–DQ7
NC
X1,X2
VBAT
RST
– Reset
DESCRIPTION
The DS1248 1024K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as
512K words by 8 bits) with a built–in real time clock. The DS1248 has a self–contained lithium energy
source and control circuitry which constantly monitors VCC for an out–of–tolerance condition. When such
a condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent garbled data in both the memory and real time clock.
PACKAGES
The DS1248 is available in two packages (32–pin DIP and 34–Pin PowerCap module). The 32–pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34–pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1248P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the Powercap is
DS9034PCX.
2 of 21
DS1248/DS1248P
RAM READ MODE
The DS1248 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable)
is active (low). The unique address specified by the 19 address inputs (A0–A16) defines which of the
128K bytes of data is to be accessed. Valid data will be available to the eight data output drivers within
tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for
CE or tOE for OE rather than address access.
RAM READ MODE
The DS1248 executes a read cycle whenever WE(Write Enable) is inactive (high) and CE (Chip Enable)
is active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the
128K bytes of data is to be accessed. Valid data will be available to the eight data output drivers within
tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for
CE or tOE for OE rather than address access.
RAM WRITE MODE
The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
3 of 21
DS1248/DS1248P
DATA RETENTION MODE
The 5 volt device is fully accessible and data can be written or read only when VCC is greater than VPF
.
However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3 volt device is fully accessible and data can be written or read only when VCC is greater than VPF
When VCC fall as below the power fail point, VPF , access to the device is inhibited. If VPF is less than VBAT
.
,
the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF . If VPF is
greater than VBAT , the device power is switched from VCC to the backup supply (VBAT ) when VCC drops
below VBAT . RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable (CE ), Output Enable (OE ), and Write Enable ( WE ). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable.
However, the write cycles generated to gain access to the Phantom Clock are also writing data to a
location in the mated RAM. The preferred way to manage this requirement is to set aside just one address
location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared
to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location
of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not
advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64–bits, the
Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64
cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of
the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with
CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom
Clock.
4 of 21
DS1248/DS1248P
PHANTOM CLOCK REGISTER INFORMATION
The Phantom Clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This
pattern is sent to the Phantom Clock LSB to MSB.
5 of 21
DS1248/DS1248P
PHANTOM CLOCK REGISTER DEFINITION Figure 2
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode,
bit 5 is the second 10–hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the Phantom Clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
6 of 21
DS1248/DS1248P
BATTERY LONGEVITY
The DS1248 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1248 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1248 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF , the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1248 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
CLOCK ACCURACY (DIP MODULE)
The DS1248 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.
The DS1248 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1248P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
7 of 21
DS1248/DS1248P
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
–40°C to +70°C
Soldering Temperature
260°C for 10 seconds (See Note 13)
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS
NOTES
Logic 1 Voltage All Inputs
VCC = 5V±10%
VIH
VIH
VIL
VIL
2.2
2.0
VCC+0.3V
V
V
V
V
11
VCC = 3.3V±10%
VCC+0.3V
0.8
11
11
11
Logic 0 Voltage All Inputs
VCC = 5V±10%
-0.3
-0.3
VCC = 3.3V±10%
0.6
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5V ±=10%)
PARAMETER
SYMBOL MIN
TYP
MAX UNITS NOTES
Input Leakage Current
I/O Leakage Current
I IL
I IO
-1.0
-1.0
+1.0
+1.0
12
µA
µA
CE ≥ V IH∇ V CC
Output Current @ 2.4 volts
Output Current @ 0.4 volts
Standby Current CE = 2.2 volts
IOH
IOL
ICCS1
-1.0
2.0
mA
mA
mA
5
10
Standby Current CE =
VCC – 0.5 volts
ICCS2
3.0
5.0
mA
Operating Current tCYC = 70ns
Write Protection Voltage
ICC01
VPF
85
mA
V
4.25
4.37
4.50
11
11
Battery Switch Over Voltage
VSO
VBAT
V
8 of 21
DS1248/DS1248P
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 3.3V ±=10%)
PARAMETER
SYMBOL MIN
TYP
MAX UNITS NOTES
Input Leakage Current
I/O Leakage Current
I IL
I IO
-1.0
-1.0
+1.0
+1.0
12
µA
µA
CE ≥ V IH∇ V CC
Output Current @ 2.4 volts
Output Current @ 0.4 volts
Standby Current CE = 2.2 volts
Standby Current CE =
VCC – 0.5 volts
IOH
IOL
ICCS1
ICCS2
-1.0
2.0
mA
mA
mA
mA
5
2.0
7
3.0
Operating Current tCYC = 70ns
Write Protection Voltage
Battery Switch Over Voltage
ICC01
VPF
VSO
50
4.50
mA
V
V
4.25
11
11
VBAT or
VPF
CAPACITANCE
PARAMETER
Input Capacitance
(tA = 25°C)
SYMBOL MIN
TYP
5
5
MAX
10
10
UNITS NOTES
CIN
CI/O
pF
pF
Input/Output Capacitance
MEMORY AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ±=10%)
DS1248Y-70 DS1248Y-100
SYMBOL MIN MAX MIN MAX UNITS NOTES
PARAMETER
Read Cycle Time
Access Time
tRC
tACC
tOE
70
100
ns
ns
ns
70
35
100
55
OE to Output Valid
CE to Output Valid
tCO
70
100
ns
ns
tCOE
5
5
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
tOD
tOH
tWC
tWP
tAW
tWR
tODW
25
35
ns
ns
ns
ns
ns
ns
ns
5
70
50
0
5
100
70
0
3
Write Recovery Time
0
0
25
35
5
5
Output High Z from WE
tOEW
5
5
ns
Output Active from WE
Data Setup Time
tDS
tDH
30
5
40
5
ns
ns
4
4
Data Hold Time from WE
9 of 21
DS1248/DS1248P
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V±10%)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Read Cycle Time
tRC
tCO
65
ns
ns
55
55
CE Access Time
tOE
tCOE
tOEE
tOD
ns
ns
ns
OE Access Time
5
5
CE to Output Low Z
OE to Output Low Z
CE to Output High Z
25
25
ns
ns
5
5
tODO
OE to Output High Z
Read Recovery
tRR
tWC
tWP
tWR
tDS
10
65
55
10
30
0
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Write Pulse Width
Write Recovery
Data Setup Time
Data Hold Time
3
10
4
tDH
tCW
4
60
CE Pulse Width
tRST
65
ns
RESET Pulse Width
POWER-DOWN/POWER-UP TIMING
VCC = 5.0V ±10%
UNITS NOTES
µs
PARAMETER
SYMBOL MIN
TYP
MAX
tPD
0
CE at VIH before Power-Down
VCC Slew from VPF(max) to
tF
300
µs
VPF(min)(CE at VPF)
VCC Slew from VPF(min) to VSO
VCC Slew from VPF(max) to
tFB
tR
10
0
µs
µs
VPF(min)(CE at VPF)
tREC
1.5
2.5
ms
CE at VIH after Power-Up
(tA = 25°C)
PARAMETER
Expected Data Retention Time
SYMBOL MIN
tDR 10
TYP
MAX
UNITS NOTES
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
10 of 21
DS1248/DS1248P
MEMORY AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 3.3V ±=10%)
DS1248W-120 DS1248W-150
PARAMETER
Read Cycle Time
Access Time
SYMBOL MIN
MAX
MIN
150
MAX UNITS NOTES
tRC
tACC
tOE
120
ns
120
X
150
X
ns
ns
OE to Output Valid
CE to Output Valid
tCO
X
X
ns
ns
tCOE
X
X
X
X
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address
Change
tOD
tOH
X
X
ns
ns
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
tWC
tWP
tAW
tWR
120
X
X
150
X
X
ns
ns
ns
ns
ns
3
X
X
10
5
tODW
X
X
Output High Z from WE
tOEW
X
X
ns
5
Output Active from WE
Data Setup Time
tDS
tDH
X
X
X
X
ns
ns
4
4
Data Hold Time from WE
PHANTOM CLOCK AC ELECTRICALCHARACTERISTICS
(0°C to 70°C; VCC = 3.3V±10%)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Read Cycle Time
tRC
tCO
120
ns
ns
100
100
CE Access Time
tOE
tCOE
tOEE
tOD
ns
ns
ns
OE Access Time
5
5
CE to Output Low Z
OE to Output Low Z
CE to Output High Z
40
40
ns
ns
5
5
tODO
OE to Output High Z
Read Recovery
tRR
tWC
tWP
tWR
tDS
20
120
100
20
45
0
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Write Pulse Width
Write Recovery
Data Setup Time
Data Hold Time
3
10
4
tDH
tCW
4
105
CE Pulse Width
tRST
120
ns
RESET Pulse Width
11 of 21
DS1248/DS1248P
POWER-DOWN/POWER-UP TIMING
VCC = 3.3V ±10%
UNITS NOTES
µs
PARAMETER
SYMBOL MIN
TYP
MAX
tPD
0
CE at VIH before Power-Down
VCC Slew from VPF(max) to
tF
300
µs
VPF(min)(CE at VIH)
VCC Slew from VPF(max) to
tR
0
µs
VPF(min)(CE at VIH)
tREC
1.5
2.5
ms
CE at VIH after Power-Up
(tA = 25°C)
PARAMETER
Expected Data Retention Time
SYMBOL MIN
tDR 10
TYP
MAX
UNITS NOTES
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
12 of 21
DS1248/DS1248P
MEMORY READ CYCLE (NOTE 1)
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
13 of 21
DS1248/DS1248P
MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
14 of 21
DS1248/DS1248P
WRITE CYCLE TO PHANTOM CLOCK
15 of 21
DS1248/DS1248P
16 of 21
DS1248/DS1248P
AC TEST CONDITIONS
Output Load:
50 pF + 1TTL Gate
Timing Measurement Reference Levels
Input:
Output:
1.5 volts
1.5 volts
Input Pulse Levels: 0–3 volts
Input Pulse Rise and Fall Times:
5 ns
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL . If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4. tDH , t DS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle
1, the output buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the
output buffers remain in a high impedance state during this period.
9. The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running.
10. t WR is a function of the latter occurring edge of WE or CE.
11. Voltage are referencd to ground.
12. RST (Pin1) has an internal pull–up resistor.
13. Real–Time Clock Modules can be successfully processed through conventional wave–soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live – bug”).
b. Hand Soldering and touch–up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds.
To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply
flux, heatthe lead frame pad until the solder reflow and use a solder wick to remove solder.
17 of 21
DS1248/DS1248P
DS1248 4096K NV SRAM WITH PHANTOM CLOCK
KG
32-PIN
DIM
MIN
MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
1.720
43.691
0.720
18.29
0.395
10.03
0.090
2.29
1.740
44.20
0.740
18.80
0.415
10.54
0.120
3.05
E IN.
MM
0.017
0.43
0.030
0.76
F IN.
MM
0.120
3.05
0.160
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
J IN.
MM
0.590
14.99
0.008
0.20
0.630
16.00
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
18 of 21
DS1248/DS1248P
DS1248P
PKG
DIM
A
B
C
D
E
F
G
INCHES
MIN
0.920
0.980
-
0.052
0.048
0.015
0.025
NOM
0.925
0.985
-
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
NOTE:
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live – bug”).
Hand Soldering and touch–up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part,
apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
19 of 21
DS1248/DS1248P
DS1248P WITH DS9034PCX ATTACHED
PKG
INCHES
DIM MIN NOM MAX
A
B
C
D
E
F
0.920 0.925 0.930
0.955 0.960 0.965
0.240 0.245 0.250
0.052 0.055 0.058
0.048 0.050 0.052
0.015 0.020 0.025
0.020 0.025 0.030
G
COMPONENTS AND PLACEMENT MAY
VARY FROM EACH DEVICE TYPE
20 of 21
DS1248/DS1248P
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
INCHES
DIM
MIN
NOM MAX
A
B
C
D
E
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
21 of 21
相关型号：
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