DS1265AB-100+ [MAXIM]
Non-Volatile SRAM Module, 1MX8, 100ns, CMOS, 0.740 INCH, ROHS COMPLIANT, DIP-36;
| 型号： | DS1265AB-100+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Non-Volatile SRAM Module, 1MX8, 100ns, CMOS, 0.740 INCH, ROHS COMPLIANT, DIP-36 静态存储器 内存集成电路 |
| 文件： | 总8页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5616; Rev 11/10
DS1265Y/AB
8M Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
. 10 years minimum data retention in the
absence of external power
NC
NC
A18
A16
A14
A12
A7
1
2
36
35
VCC
A19
NC
A15
A17
WE
A13
A8
3
4
34
33
. Data is automatically protected during power
loss
. Unlimited write cycles
5
6
32
31
7
8
30
29
. Low-power CMOS operation
. Read and write access times of 70 ns
. Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
. Full ±10% VCC operating range (DS1265Y)
. Optional ±5% VCC operating range
(DS1265AB)
A6
A9
A11
OE
A5
9
28
27
26
A4
A3
10
11
12
13
14
15
16
17
18
25
24
23
22
21
A10
CE
A2
A1
A0
DQ7
DQ6
DQ5
DQ0
DQ1
. Optional industrial temperature range of
20
19
DQ4
DQ3
DQ2
GND
-40°C to +85°C, designated IND
36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
PIN DESCRIPTION
A0 - A19
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
WE
OE
VCC
GND
NC
- No Connect
DESCRIPTION
The DS1265 8M Nonvolatile SRAMs are 8,388,608-bit, fully static nonvolatile SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
1 of 8
DS1265Y/AB
READ MODE
The DS1265 devices execute a read cycle whenever
(Write Enable) is inactive (high) and
(Chip
CE
WE
Enable) and
(Output Enable) are active (low). The unique address specified by the 20 address inputs
OE
(A0 - A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that
and
(Output Enable) access times are also satisfied. If
and
access times are not
CE
CE
OE
OE
satisfied, then data access must be measured from the later-occurring signal (
or
) and the limiting
OE
CE
parameter is either tCO for
or tOE for
rather than tACC
.
CE
OE
WRITE MODE
The DS1265 devices execute a write cycle whenever
inputs are stable. The later-occurring falling edge of
The write cycle is terminated by the earlier rising edge of
valid throughout the write cycle.
and
WE
CE
signals are active (low) after address
CE
WE
or
will determine the start of the write cycle.
or . All address inputs must be kept
CE
WE
must return to the high state for a minimum recovery time (tWR
)
WE
before another cycle can be initiated. The
control signal should be kept inactive (high) during write
OE
cycles to avoid bus contention. However, if the output drivers are enabled (
will disable the outputs in tODW from its falling edge.
and
active) then
OE WE
CE
DATA RETENTION MODE
The DS1265AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1265Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don’t care, and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1265AB and 4.5 volts for the
DS1265Y.
FRESHNESS SEAL
Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
2 of 8
DS1265Y/AB
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
Industrial:
Storage Temperature
-0.3V to +6.0V
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
+260°C
Lead Temperature (soldering, 10s)
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1265AB Power Supply Voltage
DS1265Y Power Supply Voltage
Logic 1 Input Voltage
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0
V
V
V
V
5.0
VCC
Logic 0 Input Voltage
+0.8
DC E L E C TR IC A L C HAR AC TE R IS TIC S
(VCC=5V ±5% for DS1265AB)
(TA: See Note 10) (VCC=5V ±10% for DS1265Y)
PARAMETER
SYMBOL MIN
TYP
MAX
+2.0
UNITS NOTES
Input Leakage Current
I/O Leakage Current
Output Current @ 2.4V
Output Current @ 0.4V
IIL
IIO
-2.0
-2.0
-1.0
2.0
µA
µA
mA
mA
mA
+2.0
IOH
IOL
ICCS1
ICCS2
ICCO1
VTP
VTP
1.0
1.5
200
85
Standby Current
Standby Current
=2.2V
CE
CE
100
µA
mA
V
=V -0.5V
CC
Operating Current
Write Protection Voltage (DS1265AB)
Write Protection Voltage (DS1265Y)
4.50
4.25
4.62
4.37
4.75
4.5
V
CAPACITANCE
PARAMETER
(TA = +25°C)
UNITS NOTES
SYMBOL MIN
TYP
10
MAX
20
Input Capacitance
Output Capacitance
CIN
pF
pF
CI/O
10
20
3 of 8
DS1265Y/AB
AC E L E C TR IC A L C HAR AC TE R IS TIC S
(VCC=5V ±5% for DS1265AB)
(TA: See Note 10) (VCC=5V ±10% for DS1265Y)
DS1265AB-70
DS1265Y-70
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
Access Time
tRC
tACC
tOE
70
ns
ns
ns
70
35
70
to Output Valid
to Output Valid
OE
CE
OE
tCO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOE
tOD
tOH
tWC
tWP
tAW
5
5
5
or
to Output Active
CE
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
25
5
70
55
0
Write Pulse Width
3
Address Setup Time
tWR1
tWR2
5
12
13
5
Write Recovery Time
15
tODW
tOEW
tDS
25
Output High Z from
Output Active from
Data Setup Time
WE
WE
5
5
30
4
tDH1
tDH2
0
10
ns
ns
12
13
Data Hold Time
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
4 of 8
DS1265Y/AB
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
5 of 8
DS1265Y/AB
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL MIN
tPD
tF
TYP
MAX
UNITS NOTES
1.5
11
µs
µs
µs
ms
ms
VCC Fail Detect to
and
Inactive
WE
CE
VCC slew from VTP to 0V
VCC slew from 0V to VTP
150
150
tR
tPU
tREC
2
VCC Valid to
and
Inactive
WE
CE
VCC Valid to End of Write Protection
125
(TA= +25°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
tDR 10
TYP
MAX
Expected Data Retention Time
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
is high for a Read Cycle.
WE
2.
= VIH or VIL. If
= VIH during write cycle, the output buffers remain in a high-impedance state.
OE
OE
3. tWP is specified as the logical AND of
or
. tWP is measured from the latter of
or
going
WE
CE
WE
CE
low to the earlier of
or
going high.
WE
CE
4. tDS is measured from the earlier of
or
going high.
WE
CE
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the low transition occurs simultaneously with or latter than the
low transition, the output
high transition, the output
CE
WE
WE
buffers remain in a high-impedance state during this period.
7. If the high transition occurs prior to or simultaneously with the
CE
buffers remain in high-impedance state during this period.
6 of 8
DS1265Y/AB
8. If
is low or the
low transition occurs prior to or simultaneously with the low transition,
CE
WE
WE
the output buffers remain in a high-impedance state during this period.
9. Each DS1265 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from
13. tWR2 and tDH2 are measured from
going high.
going high.
WE
CE
14. DS1265 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
SUPPLY
TOLERANCE
SPEED GRADE
PART
TEMP RANGE
PIN-PACKAGE
(ns)
70
70
70
70
DS1265AB-70+
DS1265AB-70IND+
DS1265Y-70+
DS1265Y-70IND+
+Denotes a lead(Pb)-free/RoHS-compliant package.
36 740 EDIP
36 740 EDIP
36 740 EDIP
36 740 EDIP
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
5V ± 5%
5V ± 5%
5V ± 10%
5V ± 10%
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0245
LAND PATTERN NO.
—
36 EDIP
MDT36+1
7 of 8
DS1265Y/AB
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Updated the storage information, soldering temperature, and lead
temperature information in the Absolute Maximum Ratings section;
removed the -100 MIN/MAX information from the AC Electrical
Characteristics table; updated the Ordering Information table
(removed -100 parts and leaded -70 parts); replaced the package
outline drawing with the Package Information table
11/10
1, 3, 4, 7
8 of 8
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