DS1315 [MAXIM]
Phantom Time Chip; 幻时钟芯片
| 型号： | DS1315 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Phantom Time Chip |
| 文件： | 总21页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6080; Rev 11/11
www.dalsemi.com
DS1315
Phantom Time Chip
DESCRIPTION
FEATURES
The DS1315 Phantom Time Chip is
a
. Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years
. Automatic Leap Year Correction Valid Up to
2100
combination of a CMOS timekeeper and a
nonvolatile memory controller. In the absence of
power, an external battery maintains the
timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of
hundredths of seconds, seconds, minutes, hours,
day, date, month, and year information. The last
day of the month is automatically adjusted for
months with fewer than 31 days, including leap
year correction. The watch operates in one of two
formats: a 12-hour mode with an AM/PM
indicator or a 24-hour mode. The nonvolatile
controller supplies all the necessary support
circuitry to convert a CMOS RAM to a
nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without
leaving gaps in memory.
. No Address Space Required to Communicate
with RTC
. Provides Nonvolatile Controller Functions for
Battery Backup of SRAM
. Supports Redundant Battery Attachment for
High-Reliability Applications
. Full ±10% VCC Operating Range
. +3.3V or +5V Operation
. Industrial (-40°C to +85°C) Operating
Temperature Ranges Available
PIN DESCRIPTION
X1, X2
WE
- 32.768kHz Crystal Connection
- Write Enable
PIN CONFIGURATIONS
BAT1
GND
D
- Battery 1 Input
- Ground
- Data Input
VCC1
Q
- Data Output
1
2
3
4
5
16
15
14
13
12
X1
X2
ROM/ RAM - ROM/RAM Mode Select
VCC0
DS1315
- Chip Enable Output
- Chip Enable Input
- Output Enable
- Reset
- Battery 2 Input
CEO
CEI
BAT2
RST
WE
BAT1
GND
D
OE
OE
RST
6
7
8
11
10
9
CEI
BAT2
VCC0
VCC1
- Switched Supply Output
- Power Supply Input
Q
CEO
ROM/RAM
GND
PDIP (300 mils)
Pin Configurations continued at end of data sheet.
1 of 21
DS1315 Phantom Time Chip
ORDERING INFORMATION
VOLTAGE
(V)
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
DS1315-33+
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
3.3
3.3
5
16 PDIP (300 mils)
16 PDIP (300 mils)
16 PDIP (300 mils)
16 PDIP (300 mils)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
DS1315 336
DS1315N-33+
DS1315-5+
DS1315 336
DS1315 56
DS1315N-5+
5
DS1315 56
DS1315E-33+
DS1315EN-33+
DS1315EN-33+T&R
DS1315E-5+
3.3
3.3
3.3
5
DS1315E XXXX-336
DS1315E XXXX-336
DS1315E XXXX-336
DS1315E XXXX-56
DS1315E XXXX-56
DS1315E XXXX-56
DS1315 336
DS1315EN-5+
DS1315EN-5+T&R
DS1315S-33+
DS1315SN-33+
DS1315S-5+
5
5
3.3
3.3
5
DS1315 336
DS1315 56
DS1315SN-5+
DS1315S-5+T&R
5
DS1315S 56
5
DS1315S 56
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*A “+” symbol located anywhere on the top mark indicates a lead-free device. An “N” located in the bottom right-hand corner of the top of the
package denotes an industrial device. “xxxx” can be any combination of characters.
2 of 21
DS1315 Phantom Time Chip
Figure 1. Block Diagram
3 of 21
DS1315 Phantom Time Chip
Operation
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin (
).
CEO
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and remains high during this time, disabling the connected memory.
CEO
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input ( ), output enable ( ), and write enable ( ). Initially, a read cycle using the
CEI
OE
WE
and
control of the Time Chip starts the pattern recognition sequence by moving pointer to the
OE
CEI
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CEI
and
control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
WE
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of
pin or the
pin. Cycles to other locations
WE
OE
outside the memory block can be interleaved with
cycles without interrupting the pattern recognition
CEI
sequence or data transfer sequence to the Time Chip.
A standard 32.768kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information
on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal
Considerations with Maxim Real-Time Clocks (RTCs).
4 of 21
DS1315 Phantom Time Chip
Figure 2. Time Chip Comparison Register Definition
Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019.
5 of 21
DS1315 Phantom Time Chip
Nonvolatile Controller Operation
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/ RAM select pin. When ROM/ RAM is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output (
) to V
or VBAT-0.2 volts for external RAM write protection. During
CEO
CCI
nominal supply conditions,
will track
with a propagation delay. Internally, the DS1315 aborts
CEI
CEO
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/ RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force
low when power fails. However, the Time
CEO
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
Figure 3. DS1315-to-RAM/Time Chip Interface
6 of 21
DS1315 Phantom Time Chip
Figure 4. ROM/Time Chip Interface
Time Chip Register Information
Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1
bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time
Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a
register could produce erroneous results. These read/write registers are defined in Figure 5.
Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing
the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
AM/PM/12/24-Mode
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the 20-hour bit (20-23 hours).
Oscillator and Reset Bits
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set
to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing
data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the
oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to
increment.
7 of 21
DS1315 Phantom Time Chip
Zero Bits
Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
Figure 5. Time Chip Register Definition
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DS1315 Phantom Time Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range, Commercial
Operating Temperature Range, Industrial
Storage Temperature Range
-0.3V to +6.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
+260°C
Soldering Temperature (reflow)
Lead Temperature (soldering, 10s)
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = Over the operating range.)
PARAMETER
Power-Supply Voltage
Operation
SYMBOL
MIN
4.5
3.0
TYP
5.0
3.3
MAX
5.5
3.6
UNITS
NOTES
5V
3.3V
VCC
V
1
Input Logic 1
Input Logic 0
VIH
VIL
2.2
-0.3
VCC + 0.3
+0.6
V
V
1
1
Battery Voltage VBAT1 or
VBAT2
VBAT1,
VBAT2
2.5
3.7
V
DC OPERATING ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Average VCC Power-Supply
Current
ICC1
6
mA
6
VCC Power-Supply Current,
(VCC0 = VCCI - 0.3)
TTL Standby Current
ICC01
ICC2
ICC3
IIL
150
4
mA
mA
mA
µA
µA
V
7
6
(
= VIH)
CEI
CMOS Standby Current
= VCCI - 0.2)
1.3
+1
+1
6
(
CEI
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = 4.0 mA)
-1
-1
10
IOL
VOH
2.4
2
2
VOL
VPF
0.4
4.5
V
V
Power-Fail Trip Point
4.25
VBAT1
VBAT2
,
Battery Switch Voltage
VSW
13
9 of 21
DS1315 Phantom Time Chip
DC POWER-DOWN ELECTRICAL CHARACTERISTICS
(VCC < 4.5V, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
VCCI - 0.2
or
TYP
MAX
UNITS NOTES
VCEO
V
8
Output Voltage
CEO
VBAT1,2
0.2
-
VBAT1 or VBAT2 Battery
Current
Battery Backup Current
@ VCCO = VBAT-0.2V
IBAT
0.5
10
µA
µA
6
9
ICCO2
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/RAM = GND
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
65
TYP
MAX
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCO
tOE
55
55
Access Time
Access Time
to Output Low-Z
to Output Low-Z
to Output High-Z
to Output High-Z
CEI
OE
CEI
OE
CEI
OE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
5
5
25
25
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
10
65
55
10
30
0
55
55
65
ns
ns
ns
ns
ns
ns
4
5
5
Data Hold Time
Pulse Width
Pulse Width
Pulse Width
CEI
OE
RST
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/RAM = VCCO
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
65
TYP
MAX UNITS NOTES
ns
tCO
tOE
tCOE
tOEE
tOD
tODO
tAS
tAH
tRR
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time
Access Time
to Output Low Z
to Output Low Z
to Output High Z
to Output High Z
CEI
OE
CEI
OE
CEI
OE
5
5
25
25
Address Setup Time
Address Hold Time
Read Recovery
5
5
10
10 of 21
DS1315 Phantom Time Chip
PARAMETER
Write Cycle
SYMBOL
tWC
MIN
65
55
55
10
30
0
TYP
MAX UNITS NOTES
ns
ns
ns
tCW
tOW
tWR
tDS
tDH
tRST
Pulse Width
Pulse Width
CEI
OE
Write Recovery
Data Setup
Data Hold Time
ns
ns
ns
ns
4
5
5
65
Pulse Width
RST
DC OPERATING ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS NOTES
Average VCC Power-Supply
Current
ICC1
3
mA
6
Average VCC Power-Supply
Current,
ICC01
100
mA
7
(VCCO = VCCI - 0.3)
TTL Standby Current
ICC2
ICC3
IIL
2
mA
mA
µA
µA
V
6
6
(
= VIH)
CEI
CMOS Standby Current
= VCCI - 0.2)
1.1
+1
+1
(
CEI
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = 0.4 mA)
Output Logic 0 Voltage
(IOUT = 1.6 mA)
-1
-1
ILO
VOH
2.4
2
2
VOL
VPF
0.4
V
V
Power-Fail Trip Point
2.8
2.97
VBAT1
VBAT2
,
,
Battery Switch Voltage
VSW
14
or VPF
DC POWER-DOWN ELECTRICAL CHARACTERISTICS
(VCC < 2.97V, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
VCCI
or
VBAT1,2
- 0.2
TYP
MAX
UNITS NOTES
VCEO
V
8
Output Voltage
CEO
VBAT1 OR VBAT2 Battery Current
IBAT
0.5
10
µA
µA
6
9
Battery Backup Current
at VCCO = VBAT - 0.2
ICCO2
11 of 21
DS1315 Phantom Time Chip
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/RAM = GND
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
120
TYP
MAX UNITS NOTES
ns
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time
Access Time
to Output Low-Z
to Output Low-Z
to Output High-Z
to Output High-Z
CEI
OE
CEI
OE
CEI
OE
5
5
40
40
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
20
120
100
20
45
0
100
100
120
4
5
5
Data Hold Time
Pulse Width
Pulse Width
Pulse Width
CEI
OE
RST
12 of 21
DS1315 Phantom Time Chip
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/RAM = VCCO
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
120
TYP
MAX
UNITS
ns
NOTES
tCO
tOE
tCOE
tOEE
tOD
100
100
ns
ns
ns
ns
ns
ns
Access Time
Access Time
to Output Low-Z
to Output Low-Z
to Output High-Z
to Output High-Z
CEI
OE
CEI
OE
CEI
OE
5
5
40
40
tODO
Address Setup Time
Address Hold Time
Read Recovery
Write Cycle
tAS
tAH
tRR
tWC
tCW
tOW
tWR
10
10
20
120
100
100
20
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width
Pulse Width
CEI
OE
Write Recovery
Data Setup
4
5
5
tDS
45
Data Hold Time
tDH
0
ns
tRST
120
ns
Pulse Width
RST
CAPACITANCE
(TA = +25°C)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
MIN
TYP
MAX
10
10
UNITS
pF
NOTES
COUT
pF
13 of 21
DS1315 Phantom Time Chip
Figure 6. Timing Diagram: Read Cycle to Time Chip ROM/RAM = GND
Figure 7. Timing Diagram: Write Cycle to Time Chip ROM/RAM = GND
14 of 21
DS1315 Phantom Time Chip
Figure 8. Timing Diagram: Read Cycle to Time Chip ROM/RAM = VCCO
Figure 9. Timing Diagram: Write Cycle to Time Chip ROM/RAM = VCCO
15 of 21
DS1315 Phantom Time Chip
Figure 10. Timing Diagram: Reset Pulse
tRST
RST
5V DEVICE POWER-UP/POWER-DOWN CHARACTERISTICS—
ROM/RAM = VCCO OR GND
(TA = 0°C to +70°C)
PARAMETER
Recovery Time at Power-Up
VCC Slew Rate
SYMBOL
MIN
1.5
TYP
MAX
2.5
UNITS NOTES
tREC
ms
11
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Down
VPF(min) to VSW
tF
tFB
tR
300
10
0
µs
11
µs
µs
11
11
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
tPF
tPD
0
5
µs
ns
11
2, 3, 11
High to Power-Fail
Propagation Delay
CEI
CEI
Figure 11. 5V Power-Up Condition
16 of 21
DS1315 Phantom Time Chip
Figure 12. 5V Power-Down Condition
3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS—
ROM/RAM = VCCO OR GND
(TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Recovery Time at Power-Up
tREC
1.5
2.5
ms
12
VCC Slew Rate
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
tF
300
µs
µs
12
12
tR
0
0
tPF
tPD
µs
ns
12
2, 3, 11
High to Power-Fail
Propagation Delay
CEI
10
CEI
17 of 21
DS1315 Phantom Time Chip
NOTES:
1) All voltages are referenced to ground.
2) Measured with load shown in Figure 15.
3) Input pulse rise and fall times equal 10ns.
4) tWR is a function of the latter occurring edge of
mode.
or
in RAM mode, or
or
in ROM
WE
CE
OE
CE
OE
5) tDH and tDS are functions of the first occurring edge of
ROM mode.
or
in RAM mode, or
or
in
CE
WE
CE
6) Measured without RAM connected.
7) ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8) Applies to with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to VCCO
,
CEO
will go to a low level as VCCI falls below VBAT
.
CEO
9) ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10) Applies to all input pins except
11) See Figures 11 and 12.
.
is pulled internally to VCCI.
RST RST
12) See Figures 13 and 14.
13) VSW is determined by the larger of VBAT1 and VBAT2
.
14) VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
Figure 13. 3.3V Power-Up Condition
18 of 21
DS1315 Phantom Time Chip
Figure 14. 3.3V Power-Down Condition
Figure 15. Output Load
19 of 21
DS1315 Phantom Time Chip
PIN CONFIGURATIONS (continued)
VCC1
20
1
2
3
4
5
X1
X2
VCC1
1
2
3
16
15
14
X1
X2
VCC0
19
18
17
16
VCC0
WE
BAT2
NC
BAT2
RST
WE
BAT1
GND
D
NC
4
5
13
12
BAT1
RST
OE
6
7
GND
NC
D
15
14
13
12
11
OE
6
7
8
11
10
9
CEI
NC
Q
CEO
8
9
CEI
ROM/RAM
GND
Q
CEO
ROM/RAM
GND
10
16-Pin SO (300 mil)
20-Pin TSSOP
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
16 PDIP
PACKAGE CODE
P16+1
OUTLINE NO.
21-0043
LAND PATTERN NO.
—
16 TSSOP
16 SO
U20+1
21-0066
90-0116
90-0107
W16+2
21-0042
20 of 21
DS1315 Phantom Time Chip
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Updated the Features, Ordering Information, AM/PM/12/24-MODE,
Absolute Maximum Ratings, and Package Information sections
11/11
1, 2, 7, 9, 20
21 of 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc
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