DS1347_1202 [MAXIM]
Low-Current, SPI-Compatible Real-Time Clock; 低电流， SPI兼容实时时钟
| 型号： | DS1347_1202 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Current, SPI-Compatible Real-Time Clock |
| 文件： | 总17页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6007; Rev 2; 2/12
Low-Current, SPI-Compatible Real-Time Clock
DS1347
General Description
Features
The DS1347 SPI-compatible real-time clock (RTC) con-
tains a real-time clock/calendar and 31 x 8 bits of static
random-access memory (SRAM). The real-time
clock/calendar provides seconds, minutes, hours, day,
date, month, year, and century information. A time/date
programmable polled ALARM is included in the device.
The end-of-the-month date is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year. The clock operates in either the 24hr or
12hr format with an AM/PM indicator. The device oper-
ates with a supply voltage of +2V to +5.5V, are avail-
able in the ultra-small 8-pin TDFN package, and work
over the -40°C to +85°C industrial temperature range.
o RTC Counts Seconds, Minutes, Hours, Day of Week,
Date of Month, Month, Year, and Century
o Leap-Year Compensation
o +2V to +5.5V Wide Operating Voltage Range
o SPI (Mode 1 or 3) Interface: 4MHz at 5V, 1MHz at 2V
o 31 x 8-Bit SRAM for Scratchpad Data Storage
o Uses Standard 32.768kHz Watch Crystal
o Low Timekeeping Current (400nA at 2V)
o Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
SRAM
o Ultra-Small, 3mm x 3mm x 0.8mm, 8-Pin TDFN
Applications
Package
Point-of-Sale Equipment
Intelligent Instruments
Fax Machines
o Programmable Time/Date Polled ALARM Function
o No External Crystal Bias Resistors or Capacitors
Required
Battery-Powered Products
Portable Instruments
Typical Operating Circuit
+3.3V
0.1µF
Ordering Information
6
OSC C
(pF)
L
PART
TEMP RANGE
PIN-PACKAGE
V
CC
+3.3V
8
7
X1
X2
DS1347T+
-40°C to +85°C
12.5
8 TDFN-EP*
DS1347
32.768kHz
CRYSTAL
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
1
5
2
3
SCLK
CS
µc
DOUT
DIN
GND
4
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Current, SPI-Compatible Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
CC
All Other Pins to GND ................................-0.3V to (V
V
to GND..............................................................-0.3V to +6V
Junction Temperature .....................................................+150°C
Storage Temperature Range…………………… -55°C to +125°C
ESD Protection (All Pins, Human Body Model)................ 2000V
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
+ 0.3V)
CC
Current into Any Pin.......................................................... 20mA
Rate of Rise, V ............................................................100V/µs
CC
Continuous Power Dissipation (T = +70°C)
A
TDFN (derate 24.4mW/°C above +70°C)...................1.375mW
DS1347
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +2.0V to +5.5V, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage
Range
V
CC
2
5.5
V
V
CC
V
CC
V
CC
V
CC
V
CC
= +2V
= +5V
= +2V
= +3.6V
= +5V
0.1
0.25
0.7
Active Supply Current
(Note 2)
I
mA
µA
CC
0.35
0.35
0.4
Timekeeping Supply
Current (Note 3)
I
0.7
TK
0.8
SPI DIGITAL INPUTS (SCLK, DIN, CS)
V
V
V
V
V
= +2V
= +5V
= +2V
= +5V
1.4
2.2
CC
CC
CC
CC
IN
Input High Voltage
Input Low Voltage
V
V
V
IH
0.6
0.8
V
IL
Input Leakage Current
Input Capacitance
I
= 0 to V
-0.1
-0.1
+0.1
µA
pF
IL
CC
C
(Note 4)
10
15
IN
SPI DIGITAL OUTPUT (DOUT)
Output Leakage Current
I
CS = V
+0.1
µA
pF
O
IH
Output Capacitance
C
(Note 4)
OUT
V
CC
V
CC
V
CC
V
CC
= +2V, I
= 1.5mA
= 4mA
0.4
0.4
SINK
SINK
Output Low Voltage
V
V
V
OL
= +5V, I
= +2V, I
= +5V, I
= -0.4mA
= -1mA
1.8
4.5
SOURCE
SOURCE
Output High Voltage
V
OH
2
_______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
AC ELECTRICAL CHARACTERISTICS
(V
= +2.0V to +5.5V, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.)
CC A
CC
A
(Figure 5, Notes 1, 5)
PARAMETER
SPI SERIAL TIMING
Input Rise Time
Input Fall Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
t
DIN, SCLK, CS
DIN, SCLK, CS
5
5
ns
ns
ns
ns
rIN
fIN
Output Rise Time
Output Fall Time
t
t
DOUT, C
DOUT, C
= 100pF
10
10
rOUT
fOUT
LOAD
LOAD
= 100pF
V
= +2V
1000
238
100
100
CC
CC
SCLK Period
t
ns
CP
V
= +5V
SCLK High Time
SCLK Low Time
t
ns
ns
CH
t
CL
V
V
= +2V, C
= +5V, C
= 100pF
300
100
SCLK Fall to DOUT
Valid
CC
LOAD
LOAD
t
ns
ns
ns
DO
= 100pF
CC
DIN to SCLK Setup
Time
t
100
20
DS
DIN to SCLK Hold
Time
t
DH
V
V
= +2V
= +5V
200
50
SCLK Rise to CS
Rise Hold Time
CC
t
ns
ns
ns
CSH
CC
CS High Pulse Width
t
200
CSW
CS High to DOUT
High Impedance
t
100
CSZ
CS to SCLK Setup
Time
t
100
ns
CSS
CRYSTAL CHARACTERISTICS
PARAMETER
Nominal Frequency
Series Resistance
Load Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
kꢀ
f
32.768
O
ESR
100
C
L
12.5
pF
Note 1: All parameters are 100% tested at T = +25°C. Limits over temperature are guaranteed by design and characterization and
A
not production tested.
Note 2: I
is specified with DOUT open, CS = DIN = GND, SCLK = 4MHz at V
= +5V; SCLK = 1MHz at V
= +2.0V.
CC
CC
CC
Note 3: Timekeeping current is specified with CS = V , SCLK = DIN = GND, DOSF = 0, EGFIL = 1.
CC
Note 4: Guaranteed by design and not 100% production tested.
Note 5: All values referred to V
and V
levels.
IH(MIN)
IL(MAX)
_______________________________________________________________________________________
3
Low-Current, SPI-Compatible Real-Time Clock
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
60
40
20
0
400
350
300
250
200
T
= +25°C,
CC
T
I
= +25°C,
= 0mA,
CS = DIN = GND
A
DS1347
A
OUT
EGFIL = 1,
DOSF = 0
CS = V
f
= 4MHz
SCLK
EGFIL = 0,
DOSF = 0
f
= 1MHz
SCLK
EGFIL = 0,
DOSF = 1
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
500
400
300
200
CS = V
,
CC
+85°C
EGFIL = DOSF = 0
+70°C
+25°C
0°C
-40°C
2
3
4
5
6
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
Pin Configuration
TOP VIEW
+
SCLK
DOUT
DIN
1
2
3
4
8
7
6
5
X1
X2
DS1347
V
CC
EP
GND
CS
TDFN
Pin Description
PIN
NAME
FUNCTION
Serial-Clock Input. SCLK is used to synchronize data movement on the serial interface for either 3-wire or
SPI communications.
1
SCLK
Serial-Data Output. When SPI communication is enabled, the DOUT pin is the serial-data output for the SPI
bus.
2
DOUT
3
4
DIN
Serial-Data Input. When SPI communication is enabled, the DIN pin is the serial-data input for the SPI bus.
Ground
GND
Active-Low Chip Select. The chip-enable signal must be asserted low during a read or a write for SPI
communications.
5
CS
6
7
V
Power-Supply Input
CC
X2
X1
EP
Connections for Standard 32.768kHz Quartz Crystal (see the Crystal Characteristics table).
Exposed Pad. Connect to GND or leave unconnected.
8
—
_______________________________________________________________________________________
5
Low-Current, SPI-Compatible Real-Time Clock
Functional Diagram
X1
X2
OSCILLATOR
32.768kHz
1Hz
DIVIDER
SECONDS
MINUTES
HOURS
DATE
DS1347
DS1347
V
CONTROL
LOGIC
CC
MONTH
DAY
GND
SCLK
DIN
YEAR
INPUT SHIFT
REGISTERS
DOUT
CS
CONTROL
CENTURY
ADDRESS
REGISTER
ALARM
CONFIG
31x 8
RAM
STATUS
ALARM
THRESHOLDS
CLOCK
BURST
RAM
BURST
ALARM
CONTROL
LOGIC
ALARM OUT
6
_______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
Diagram). An on-chip 32.768kHz oscillator circuit
Detailed Description
requires only a single external crystal to operate. Table
The DS1347 is a real-time clock/calendar with an SPI-
1 shows the device’s register addresses and defini-
compatible interface and 31 x 8 bits of SRAM. It pro-
tions. Time and calendar data are stored in the regis-
vides seconds, minutes, hours, day of the week, date of
ters in binary-coded decimal (BCD) format. A polled
the month, month, and year information, held in seven
alarm function is included for scheduled timing of user-
8-bit timekeeping registers (see the Functional
defined times or intervals.
Table 1. Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
01h
0
10 SECONDS
SECONDS
Seconds
00–59
ALM
OUT
03h
05h
10 MINUTES
MINUTES
HOUR
Minutes
Hours
00–59
AM/PM
1–12+AM/PM
12/24
0
10 HR
00–23
20 HR
07h
09h
0Bh
0Dh
0Fh
13h
0
0
0
0
0
0
10 DATE
DATE
Date
Month
Day
01–31
01–12
0
0
10 MO
0
MONTH
0
0
DAY
YEAR
1–7
10 YEAR
Year
00–99
WP
0
0
0
0
0
0
ID
Control
Century
00h or 81h
00–99
1000 YEAR
100 YEAR
Alarm
Configuration
15h
YEAR
DAY
MONTH DATE
HOUR MINUTE SECOND
00h–7Fh
17h
19h
1Bh
EOSC
DOSF
EGFIL
10 SECONDS
10 MINUTES
AM/PM
0
0
OSF
1
1
Status
03h–E7h
00–59
0
0
SECONDS
Alarm Seconds
Alarm Minutes
MINUTES
HOURS
00–59
1–12 + AM/PM
1Dh
12/24
0
10 HR
Alarm Hours
00–23
20 HR
1Fh
21h
23h
25h
3Fh
41h
43h
45h
47h
49h
4Bh
4Dh
4Fh
51h
53h
55h
0
0
0
0
0
0
10 DATE
DATE
Alarm Date
Alarm Month
Alarm Day
Alarm Year
Clock Burst
RAM 0
1–31
0
0
10 MO
0
MONTH
1–12
0
DAY
YEAR
See the Data Input (Burst Write) section.
1–7
10 YEAR
00–99
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
RAM 1
RAM 2
RAM 3
RAM 4
RAM 5
RAM 6
RAM 7
RAM 8
RAM 9
RAM 10
_______________________________________________________________________________________
7
Low-Current, SPI-Compatible Real-Time Clock
Table 1. Register Map (continued)
ADDRESS
57h
BIT 7
X
BIT 6
X
BIT 5
X
BIT 4
X
BIT 3
X
BIT 2
X
BIT 1
X
BIT 0
X
FUNCTION
RAM 11
RAM 12
RAM 13
RAM 14
RAM 15
RAM 16
RAM 17
RAM 18
RAM 19
RAM 20
RAM 21
RAM 22
RAM 23
RAM 24
RAM 25
RAM 26
RAM 27
RAM 28
RAM 29
RAM 30
RAM Burst
RANGE
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
00h–FFh
—
59h
X
X
X
X
X
X
X
X
5Bh
5Dh
5Fh
X
X
X
X
X
X
X
X
DS1347
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
61h
X
X
X
X
X
X
X
X
63h
X
X
X
X
X
X
X
X
65h
X
X
X
X
X
X
X
X
67h
X
X
X
X
X
X
X
X
69h
X
X
X
X
X
X
X
X
6Bh
6Dh
6Fh
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
71h
X
X
X
X
X
X
X
X
73h
X
X
X
X
X
X
X
X
75h
X
X
X
X
X
X
X
X
77h
X
X
X
X
X
X
X
X
79h
X
X
X
X
X
X
X
X
7Bh
7Dh
7Fh
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
See the Data Input (Burst Write) section.
0 = Reads as logic 0, 1 = Reads as logic 1, X = Don’t care.
The first seven clock/calendar registers (Seconds,
Minutes, Hours, Date, Month, Day, and Year) and the
Control register are consecutively read or written, start-
ing with the MSB of the Seconds register. When writing
to the clock registers in burst mode, all seven clock/cal-
endar registers and the Control register must be written
in order for the data to be transferred. See the Example:
Setting the Clock with a Burst Write section.
Command and Control
Address/Command Byte
Each data transfer into or out of the device is initiated by
an address/command byte. The address/command byte
specifies which registers are to be accessed, and if the
access is a read or a write. Table 1 shows the
address/command bytes and their associated regis-
ters, and lists the hex codes for all read and write oper-
ations. The address/command bytes are input MSB
(bit 7) first. Bit 7 specifies a write (logic 0) or read
(logic 1). Bit 6 specifies register data (logic 0) or RAM
data (logic 1). Bits 5–1 specify the designated register
to be written or read. The LSB (bit 0) must be logic 1. If
the LSB is a zero, writes to the device are disabled.
RAM Burst Mode
Sending the RAM burst address/command (7Fh) speci-
fies burst-mode operation. In this mode, the 31 RAM
locations can be consecutively read or written, starting
at 41h. When writing to RAM in burst mode, it is not
necessary to write all 31 bytes for the data to transfer;
each complete byte written is transferred to RAM. When
reading from RAM, data is output until all 31 bytes have
been read, or until CS is driven high.
Clock Burst Mode
Sending the clock burst address/command (3Fh) spec-
ifies burst-mode operation. In this mode, multiple bytes
are read or written after a single address/command.
8
_______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
AM/PM and 12Hr/24Hr Mode
Bit 7 of the Hours register selects 12hr or 24hr mode.
When high, 12hr mode is selected. In 12hr mode, bit 5
is the AM/PM bit, logic-high for PM. In 24hr mode, bit 5
is the 20hr bit, logic-high for hours 20 through 23.
Setting the Clock
Writing to the Timekeeping Registers
The time and date are set by writing to the timekeeping
registers (Seconds, Minutes, Hours, Date, Month, Day,
Year, and Century). During a write operation, an input
buffer accepts the new time data while the timekeeping
registers continue to increment normally, based on the
crystal counter. The buffer also keeps the timekeeping
registers from changing as the result of an incomplete
write operation, and collision-detection circuitry
ensures that a time write does not occur coincident with
a Seconds register increment. The updated time is
loaded into the timekeeping registers after the rising
edge of CS, at the end of the SPI write operation. An
incomplete write operation aborts the update proce-
dure, and the contents of the input buffer are discard-
ed. The timekeeping registers reflect the new time
beginning with the first Seconds register increment
after the rising edge of CS.
Write-Protect Bit
Bit 7 of the Control register is the write-protect bit.
When high, the write-protect bit prevents write opera-
tions to all registers except itself. After initial settings
are written to the timekeeping registers, set the write-
protect bit to logic 1 to prevent erroneous data from
entering the registers during power glitches or inter-
rupted serial transfers. The lower 7 bits (bits 0–6) are
unusable, and always read zero. Any data written to
bits 0–6 are ignored. Bit 7 must be set to zero before a
single write to the clock, before a write to RAM, or dur-
ing a burst write to the clock.
Example: Setting the Clock
with a Burst Write
Although both single writes and burst writes are possi-
ble, the best way to write to the timekeeping registers is
with a burst write. With a burst write, the main time-
keeping registers (Seconds, Minutes, Hours, Date,
Month, Day, Year) and the Control register are written
sequentially following the address/command byte. They
must be written as a group of eight registers, with 8 bits
each, for proper execution of the burst write function.
All seven timekeeping registers are simultaneously
loaded into the clock counters by the rising edge of CS,
at the end of the SPI write operation.
To set the clock to 10:11:31PM, Thursday July 4th,
2002, with a burst write operation, write 3Fh as the
address/command byte, followed by 8 bytes, 31h, 11h,
B0h, 04h, 07h, 05h, 02h, and 00h (Figure 2). 3Fh is the
clock burst write address/command. The first data
byte, 31h, sets the Seconds register to 31. The second
data byte, 11h, sets the Minutes register to 11. The
third data byte, B0h, sets the Hours register to 12hr
mode, and 10PM. The fourth data byte, 04h, sets the
Date register (day of the month) to the 4th. The fifth
data byte, 07h, sets the Month register to July. The
sixth data byte, 05h, sets the Day register (day of the
week) to Thursday. The seventh data byte, 02h, sets
the Year register to 02. The eighth data byte, 00h,
clears the write-protect bit of the Control register to
allow writing to the device. The Century register is not
accessed with a burst write and therefore must be writ-
ten to separately to set the century to 20. Note the
Century register corresponds to the thousand and hun-
dred digits of the current year and defaults to 19.
If single write operations are used to enter data into the
timekeeping registers, error checking is required. If not
writing to the Seconds register, begin by reading the
Seconds register and save it as initial-seconds. Then
write to the required timekeeping registers, and finally
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process. If writing to the Seconds
register, update the Seconds register first, and then
read it back and store its value (initial-seconds).
Update the remaining timekeeping registers and then
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process.
_______________________________________________________________________________________
9
Low-Current, SPI-Compatible Real-Time Clock
Example: Reading the Clock
Reading the Clock
with a Burst Read
Reading the Timekeeping Registers
The main timekeeping registers (Seconds, Minutes,
Hours, Date, Month, Day, Year) can be read with either
single reads or a burst read. In the device, a latch
buffers each clock counter’s data. Clock counter data
is latched by the SPI read command (on the falling
edge of SCLK, after the address/command byte has
been sent by the master to read a timekeeping regis-
ter). Collision-detection circuitry ensures that this does
not happen coincident with a Seconds counter incre-
ment to ensure accurate time data is read. The clock
counters continue to count and keep accurate time dur-
ing the read operation.
To read the time with a burst read, send BFh as the
Address/Command byte. Then clock out 8 bytes,
Seconds, Minutes, Hours, Date of the month, Month,
Day of the week, Year, and finally the Control byte. All
data is output MSB first. Decode the required informa-
tion based on the register definitions listed in Table 1.
DS1347
Using the Alarm
A polled alarm function is available by reading the ALM
OUT bit. The ALM OUT bit is D7 of the Minutes time-
keeping register. A logic 1 in ALM OUT indicates the
Alarm function is triggered. There are eight registers
associated with the alarm function—seven programma-
ble alarm threshold registers and one programmable
Alarm Configuration register. The Alarm Configuration
register determines which alarm threshold registers are
compared to the timekeeping registers, and the ALM
OUT bit sets if the compared registers are equal. Table
1 shows the function of each bit of the Alarm
Configuration register. Placing a logic 1 in any given bit
of the Alarm Configuration register enables the respec-
tive alarm function. For example, if the Alarm
Configuration register is set to 0000 0011, ALM OUT is
set when both the minutes and seconds indicated in
the alarm threshold registers match the respective
timekeeping registers. Once set, ALM OUT stays high
until it is cleared by reading or writing to the Alarm
Configuration register, or by reading or writing to any of
the alarm threshold registers. The Alarm Configuration
register is located at address 15h, and is initialized to
00h on the first application of power.
The simplest way to read the timekeeping registers is to
use a burst read. In a burst read, the main timekeeping
registers (Seconds, Minutes, Hours, Date, Month, Day,
Year), and the Control register are read sequentially, in
the order listed with the Seconds register first. They are
read out as a group of eight registers, with 8 bits each.
All timekeeping registers (except Century) are latched
upon the receipt of the burst read command. The
worst-case error between the “actual” time and the
“read” time is 1s for a normal data transfer.
The timekeeping registers can also be read using sin-
gle reads. If single reads are used, it is necessary to do
some error checking on the receiving end, because it is
possible that the clock counters could change during
the read operations, and report inaccurate time data.
The potential for error is when the Seconds register
increments before all the registers are read. For exam-
ple, suppose a carry of 13:59:59 to 14:00:00 occurs
during single read operations. The net data read could
be 14:59:59, which is erroneous. To prevent errors from
occurring with single read operations, read the
Seconds register first (initial-seconds) and store this
value for future comparison. After the remaining time-
keeping registers have been read, reread the Seconds
register (final-seconds). Check that the final-seconds
value equals the initial-seconds value. If not, repeat the
entire single read process. Using single reads at a
100kHz serial speed, it takes under 2.5ms to read all
seven of the timekeeping registers, including two reads
of the Seconds register.
Using the On-Board RAM
The static RAM is 31 x 8 bits addressed consecutively
in the RAM Address/Command space. Table 1 details
the specific hex address/commands for reads and
writes to each of the 31 locations of RAM. The contents
of the RAM are static and remain valid for V
down to
CC
2V. All RAM data is lost if power is cycled. The write-
protect bit (WP in the Control register), when high, dis-
allows any writes to RAM. The RAM’s power-on state is
undefined.
10 ______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
Control Register (0Fh)
BIT 7
WP
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ID
0
0
0
0
0
0
0
0
0
0
0
0
0
WP: Write-Protect RAM. If the WP bit is logic one, writing to the 31 bytes of RAM is inhibited. This bit is cleared
(0) when power is first applied.
BIT 7
ID: Device Identification Bit. The content of this bit does not alter the component functionality. This bit is cleared
(0) when power is first applied.
BIT 0
Alarm Configuration Register (15h)
BIT 7
BIT 6
YEAR
0
BIT 5
DAY
0
BIT 4
MONTH
0
BIT 3
DATE
0
BIT 2
HOUR
0
BIT 1
MINUTE
0
BIT 0
SECOND
0
0
0
Status Register (17h)
BIT 7
EOSC
0
BIT 6
DOSF
0
BIT 5
EGFIL
0
BIT 4
BIT 3
BIT 2
OSF
1
BIT 1
BIT 0
0
0
0
0
0
1
0
1
EOSC: Enable Oscillator. When the EOSC bit is logic 0, the oscillator is enabled. When this bit is logic 1, the
oscillator is disabled. This bit is cleared (0) when power is first applied.
BIT 7
DOSF: Disable Oscillator Stop Flag. When the DOSF bit is set to 1, sensing of the oscillator conditions that would
set the OSF bit is disabled. OSF remains at 0 regardless of what happens to the oscillator. This bit is cleared (0)
on the initial application of power.
BIT 6
BIT 5
EGFIL: Enable Glitch Filter. When the EGFIL bit is 1, the 5µs glitch filter at the output of crystal oscillator is
enabled. The glitch filter is disabled when this bit is 0. This bit is cleared (0) on the initial application of power.
OSF: Oscillator Stop Flag. If the OSF bit is 1, the oscillator either has stopped or was stopped for some period and
could be used to judge the validity of the clock and calendar data. This bit is edge triggered and is set to 1 when
the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition. This bit
remains at logic 1 until written to logic 0. Attempting to write OSF to 1 leaves the value unchanged. The following
are examples of conditions that can cause the OSF bit to be set:
BIT 2
1) The first time power is applied.
2) The voltage present on V
is insufficient to support oscillation.
CC
3) The EOSC bit is set to logic 1.
4) External influences on the crystal (i.e., noise, leakage, etc.).
Alarm Seconds Register (19h)
BIT 7
BIT 6
BIT 5
10 SECONDS
1
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
SECONDS
1
1
1
1
1
1
______________________________________________________________________________________ 11
Low-Current, SPI-Compatible Real-Time Clock
Alarm Minutes Register (1Bh)
BIT 7
BIT 6
BIT 5
10 MINUTES
1
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
MINUTES
1
1
1
1
1
1
DS1347
Alarm Hours Register (1Dh)
BIT 7
12/24
1
BIT 6
BIT 5
AM/PM
20 HR
1
BIT 4
10 HR
1
BIT 3
BIT 2
BIT 1
BIT 0
0
0
HOURS
1
1
1
1
Alarm Date Register (1Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
10 DATE
DATE
1
1
1
1
1
1
Alarm Month Register (21h)
BIT 7
BIT 6
BIT 5
BIT 4
10 MO
1
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
MONTH
1
1
1
1
Alarm Day Register (23h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
DAY
1
BIT 0
0
0
0
0
0
0
0
0
0
0
1
1
Alarm Year Register (25h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
10 YEAR
YEAR
1
1
1
1
1
1
1
1
as a slave device and the microcontroller acts as the
master. CS is asserted low by the microcontroller to initi-
ate a transfer, and deasserted high to terminate a trans-
fer. DIN transfers input data from the microcontroller to
the device. DOUT transfers output data from the device
to the microcontroller. A shift clock, SCLK, is used to
synchronize data movement between the microcon-
troller and the device. SCLK, which is generated by the
SPI-Compatible Serial Interface
Interface the device with a microcontroller using a serial,
4-wire, SPI interface. SPI is a synchronous bus for
address and data transfer, and is used with Motorola or
other microcontrollers that have an SPI port. Four con-
nections are required for the interface: DOUT (serial-
data out); DIN (serial-data in); SCLK (serial clock); and
CS (chip select). In an SPI application, the device acts
12 ______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock
polarity is usually programmable on the microcontroller
side of the SPI interface. In the device, input data is
latched on the positive edge, and output data is shifted
out on the negative edge. There is one clock cycle for
each bit transferred. Address and data bits are trans-
ferred in groups of eight.
the negative edge of SCLK and data in to be sampled
on the positive edge. With CPHA equal to 1, CS can
remain low between successive data byte transfers,
allowing burst-mode data transfers to occur.
Address and data bytes are shifted MSB first into DIN
of the device, and out of DOUT. Data is shifted out at
the negative edge of SCLK, and shifted in or sampled
at the positive edge of SCLK. Any transfer requires an
address/command byte followed by one or more
bytes of data. Data is transferred out of DOUT for a
read operation, and into DIN for a write operation.
DOUT transmits data only after an address/command
byte specifies a read operation; otherwise, it is high
impedance.
The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI Control register. The
clock polarity is specified by the CPOL Control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The clock
phase control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the device,
set the control bits to CPHA = 1 and CPOL = 1. This
configures the system for data out to be launched on
Data transfer write timing is shown in Figure 1. Data
transfer read timing is shown in Figure 2. Detailed read
and write timing is shown in Figure 3.
CS
SCLK
DIN
R/W
A6
A5
A4
A3
A2
A1
1
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS/COMMAND BYTE
DATA BYTE
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
DOUT
Figure 1a. Single Write
CS
SCLK
DIN
R/W A6
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS/COMMAND BYTE*
DATA BYTE 1
DATA BYTE N
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
DOUT
*ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
Figure 2b. Burst Write
______________________________________________________________________________________ 13
Low-Current, SPI-Compatible Real-Time Clock
CS
SCLK
DIN
R/W
A6
A5
A4
A3
A2
A1
1
DS1347
ADDRESS/COMMAND BYTE
HIGH IMPEDANCE
DOUT
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
Figure 2a. Single Read
CS
SCLK
DIN
R/W
A6
1
1
1
1
1
1
ADDRESS/COMMAND BYTE*
HIGH IMPEDANCE
DOUT
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE 1
DATA BYTE N
*ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
Figure 2b. Burst Read
t
CSH
CS
t
CH
t
t
CSW
t
CP
CSS
t
CL
SCLK
t
DH
t
DS
R/W
A6
A5
1
DIN
t
CSZ
D7
D0
DOUT
t
DO
Figure 3. SPI Bus Timing Diagram
14 ______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
Chip Select
CS serves two functions. First, CS turns on the control
Applications Information
Oscillator Start Time
The device’s oscillator typically takes less than 2s to
begin oscillating. To ensure the oscillator is operating
correctly, the software should validate proper time-
keeping. This is accomplished by reading the Seconds
register. Any reading of 1s or more from the POR value
of zero seconds is a validation of proper startup.
logic that allows access to the Shift register for
address/command and data transfer. Second, CS pro-
vides a method of terminating either single-byte or mul-
tiple-byte data transfers. All data transfers are initiated
by driving CS low. If CS is high, then DOUT is high
impedance.
Serial Clock
A clock cycle on SCLK is a rising edge followed by a
falling edge. For data input, data must be valid at DIN
before the rising edge of the clock. For data outputs, bits
are valid on DOUT after the falling edge of the clock.
Power-On Reset
The device contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. Once V
rises, the POR circuit releases the
CC
registers for normal operation.
Data Input (Single-Byte Write)
Following the eight SCLK cycles that input a single-byte
write address/command, data bits are input on the ris-
ing edges of the next eight SCLK cycles. Additional
SCLK cycles are ignored. Input data MSB first.
Power-Supply Considerations
For most applications, a 0.1µF capacitor from V to
CC
GND provides adequate bypassing for the device. A
series resistor can be added to the supply line for oper-
ation in extremely harsh or noisy environments.
Data Input (Burst Write)
Following the eight SCLK cycles that input a burst-write
address/command, data bits are input on the rising
edges of the following SCLK cycles. The number of
clock cycles depends on whether the timekeeping reg-
isters or RAM are being written. A clock burst write
requires 1 address/command byte, 7 timekeeping data
bytes, and 1 control register byte. A burst write to RAM
can be terminated after any complete data byte by dri-
ving CS high. Input data MSB first (Figure 1).
PCB Considerations
The device uses a very low-current oscillator to mini-
mize supply current. This causes the oscillator pins, X1
and X2, to be relatively high impedance. Exercise care
to prevent unwanted noise pickup.
Connect the 32.768kHz crystal directly across X1 and X2
of the device. To eliminate unwanted noise pickup,
design the PCB using these guidelines (Figure 4):
1) Place the crystal as close to X1 and X2 as possible
and keep the trace lengths short.
Data Output (Single-Byte Read
and Burst Read)
2) Place a guard ring around the crystal, X1 and X2
traces (where applicable), and connect the guard
ring to GND; keep all signal traces away from
beneath the crystal, X1, and X2.
A read from the device is initiated by an address/com-
mand Write from the microcontroller (master) to the
device (slave). The address/command write portion of
the data transfer is clocked into the device on rising
clock edges. Following the eighth falling clock edge of
3) Finally, an additional local ground plane can be
added under the crystal on an adjacent PCB layer.
The plane should be isolated from the regular PCB
ground plane, and connected to ground at the IC
ground pin.
SCLK, after t
(Figure 2) data begins to be output on
DO
DOUT of the device. Data bytes are output MSB first.
Additional SCLK cycles transmit additional data bits, as
long as CS remains low. This permits continuous burst-
mode read capability.
4) Restrict the plane to be no larger than the perimeter of
the guard ring. Do not allow this ground plane to con-
tribute significant capacitance between X1 and X2.
______________________________________________________________________________________ 15
Low-Current, SPI-Compatible Real-Time Clock
GROUND PLANE
VIA CONNECTION
*
GROUND PLANE
VIA CONNECTION
V
PLANE
CC
*
0.1µF
SM CAP
GUARD RING
VIA CONNECTION
DS1347
*
*
*
*
**
**
SD3147
*
*
*
**
LAYER 2 LOCAL GROUND PLANE
CONNECT ONLY TO PIN 4
GROUND PLANE VIA
**
SM WATCH CRYSTAL
*
**
*
GROUND PLANE
VIA CONNECTION
LAYER 1 TRACE
*
Figure 4. Crystal PCB Layout
PROCESS: CMOS
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 TDFN-EP
T833+2
21-0137
90-0059
16 ______________________________________________________________________________________
Low-Current, SPI-Compatible Real-Time Clock
DS1347
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
8/11
Initial release
—
1/12
Removed all references to the DS1346
All
Removed the external oscillator text from the X1 pin description in the Pin
Description table
2
2/12
5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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