DS1670E/T&R [MAXIM]
Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO20, 4.40 MM, TSSOP-20;
| 型号： | DS1670E/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO20, 4.40 MM, TSSOP-20 计时器或实时时钟 微控制器和处理器 外围集成电路 光电二极管 |
| 文件： | 总16页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1670
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS1670 portable system controller is a circuit
that incorporates many of the functions necessary for
low-power portable products integrated into one chip.
The device provides a real-time clock (RTC), NV
RAM controller, microprocessor monitor, and a
3-channel, 8-bit analog-to-digital converter (ADC).
Communication with the DS1670 is established
through a simple 3-wire interface.
Cꢀ Provides Real-Time Clock
Counts Seconds, Minutes, Hours, Date of the
Month, Month, Day of the Week, and Year
with Leap Year Compensation Valid Up to
2100
Power-Control Circuitry Supports System
Power-On from Day/Time Alarm
Cꢀ Microprocessor Monitor
Halts Microprocessor During Power Fail
Automatically Restarts Microprocessor after
Power Failure
The RTC provides seconds, minutes, hours, day,
date, month, and year information with leap year
compensation. The RTC also provides an alarm
interrupt. This interrupt works when the DS1670 is
powered by the system power supply or when in
battery-backup operation, so the alarm can be used to
wake up a system that is powered down.
Monitors Pushbutton for External Override
Halts and Resets an Out-of-Control
Microprocessor
Cꢀ NV RAM Control
Automatic Battery Backup and Write Protection
to External SRAM
Automatic backup and write protection of an external
SRAM is provided through the VCCO, CEOL, and
CEOH pins. The backup energy source used to power
the RTC is also used to retain RAM data in the
absence of VCC through the VCCO pin. The chip-
enable outputs to RAM (CEOL and CEOH) are
controlled during power transients to prevent data
corruption.
Cꢀ 3-Channel, 8-Bit ADC
Cꢀ Simple 3-Wire Interface
Cꢀ 3.3V Operation
Cꢀ Underwriters Laboratory (UL) Recognized
PIN CONFIGURATION
TOP VIEW
VBAT
ST
1
2
3
4
5
6
20
19
18
17
16
15
14
ORDERING INFORMATION
DS1670
VCCO
SCLK
I/O
VCC
VOLTAGE PIN-
PART*
TOP MARK†
X2
AIN0
(V)
3.3
3.3
3.3
3.3
3.3
3.3
PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 SO
DS1670E
DS1670E
DS1670E
DS1670E
DS1670E
DS1670S
DS1670S
CS
DS1670E+
AIN1
CEI
CEOL
CEOH
INT
DS1670E/T&R
DS1670E+TRL
DS1670S
7
8
9
RST
13
12
11
BLE
BHE
DS1670S+
20 SO
GND
10
* All devices are specified over the 0°C to +70°C operating range.
† A “‘+” anywhere on the top mark denotes a lead-free device.
+ Denotes a lead-free/RoHS-compliant device.
TSSOP (4.4mm)
SO (300 mils)
1 of 16
REV: 080805
DS1670
DETAILED DESCRIPTION
The microprocessor monitor circuitry of the DS1670 provides three basic functions. First, a precision
temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-
tolerance condition occurs, an internal power-fail signal is generated that forces the reset to the active
state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for
250ms to allow the power supply and processor to stabilize. The second microprocessor monitor function
is pushbutton reset control. The DS1670 debounces a pushbutton input and guarantees an active-reset
pulse width of 250ms. The third function is a watchdog timer. The DS1670 has an internal timer that
forces the reset signals to the active state if the strobe input is not driven low prior to watchdog timeout.
The DS1670 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. The
converter has an internal 2.55V (typical) reference voltage generated by an on-board band-gap circuit.
The ADC is monotonic (no missing codes) and has an internal analog filter to reduce high frequency
noise.
OPERATION
The block diagram in Figure 1 shows the main elements of the DS1670. The following paragraphs
describe the function of each pin.
DS1670 BLOCK DIAGRAM Figure 1
2 of 16
DS1670
PIN DESCRIPTION
PIN
NAME
FUNCTION
Battery Input for Standard 3V Lithium Cell or Other Energy Source. UL recognized to
ensure against reverse charging when used with a lithium battery. Go to www.maxim-
ic.com/qa/info/ul/.
1
VBAT
External SRAM Power Supply Output. This pin is internally connected to VCC when VCC is
2
VCCO
within nominal limits. However, during power-fail VCCO is internally connected to the
V
BAT pin. Switchover occurs when VCC drops below the lower of VBAT or 2.7V.
3
4
SCLK
I/O
Serial Clock Input. Used to synchronize data movement on the serial interface.
Data Input/Output. This pin is the bidirectional data pin for the 3-wire interface.
Chip Select. Must be asserted high during a read or a write for communication over the 3-
wire serial interface. CS has an internal 40kꢀ pulldown resistor.
RAM Chip-Enable In. Must be driven low to enable the external RAM.
RAM Chip-Enable Out Low. Active-low chip-enable output for low-order SRAM byte.
RAM Chip-Enable Out High. Active-low chip-enable output for high-order SRAM byte.
5
CS
6
7
8
CEI
CEOL
CEOH
Interrupt Output. This pin is an active-high output that can be used as an interrupt input to
a microprocessor. The INT output remains high as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates
9
INT
when the DS1670 is powered by VCC or VBAT
.
10
11
GND
Ground. DC power is provided to the device on this pin.
Byte High-Enable Input. This pin when driven low activates the CEOH output if CEI is
BHE
also driven low.
Byte Low-Enable Input. This pin when driven low activates the CEOL output if CEI is
12
BLE
RST
also driven low.
Active-Low Reset. The RST pin functions as a microprocessor reset signal. This pin is
driven low 1) when VCC is outside of nominal limits; 2) when the watchdog timer has
timed out; 3) during the power up reset period; and 4) in response to a pushbutton reset.
The RST pin also functions as a pushbutton reset input. When the RST pin is driven low,
the signal is debounced and timed such that a RST signal of at least 250ms is generated.
This pin has an open-drain output with an internal 47kꢀ pullup resistor.
13
AIN2,
AIN1,
AIN0
14,
Analog Inputs. These pins are the three analog inputs for the 3-channel ADC.
15, 16
Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1670
must be used with a crystal that has a specified load capacitance of 6pF. There is no need
for external capacitors or resistors. Note: X1 and X2 are very high-impedance nodes. It is
recommended that they and the crystal be guard-ringed with ground and that high
frequency signals be kept away from the crystal area. For more information on crystal
selection and crystal layout considerations, refer to Application Note 58: Crystal
Considerations with Dallas Real Time Clocks. The DS1670 does not function without a
crystal.
17, 18
X2, X1
+3.3V Input DC Power. When 3.3V is applied within nominal limits, the device is fully
accessible and data can be written and read. When VCC drops below 2.88V (typical) access
to the device is prohibited. When VCC drops below the lower of VBAT and 2.7V (typical),
the device is switched over to the backup power supply.
19
20
VCC
Active-Low Strobe Input. The strobe input pin is used with the watchdog timer. If the ST
ST
pin is not driven low within the watchdog time period, the RST pin is driven low.
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DS1670
POWER-UP/POWER-DOWN CONSIDERATIONS
The DS1670 was designed to operate with a power supply of 3.3V. When 3.3V are applied within
nominal limits, the device becomes fully accessible after tRPU (250ms typical). Before tRPU elapses, all
inputs are disabled. When VCC drops below 2.88V (typical), the RST pin is driven low. When VCC drops
below the lower of 2.7V (typical) or the battery voltage, the device is switched over to the backup power
supply.
During power-up, when VCC returns to an in-tolerance condition, the RST pin is kept in the active state
for 250ms (typical) to allow the power supply and microprocessor to stabilize.
ADDRESS/COMMAND BYTE
The command byte for the DS1670 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the addresses of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a 1. The address map for the DS1670 is
shown in Figure 3.
ADDRESS/COMMAND BYTE Figure 2
7
6
5
4
3
2
1
0
RD
A6 A5 A4 A3 A2
A1
A0
WR
DS1670 ADDRESS MAP Figure 3
BIT 7
BIT 0
00
01
0
0
10 SECONDS
10 MINUTES
10 HR
SECONDS
MINUTES
12
02
0
10 HR
HOURS
24
A/P
0
03
04
05
0
0
0
0
0
0
0
0
DAY
DATE
MONTH
10 DATE
0
10
MO.
06
07
08
10 YEAR
YEAR
SECONDS ALARM
MINUTES ALARM
M
M
10 SEC ALARM
10 MIN ALARM
10 HR
12
09
M
M
10 HR
HOUR ALARM
DAY ALARM
24
A/P
0
0A
0B
0C
0D
0E
0F
7F
0
0
CONTROL REGISTER
STATUS REGISTER
WATCHDOG REGISTER
ADC REGISTER
RESERVED
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DS1670
CLOCK, CALENDAR, AND ALARM
The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that
some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note that
registers 0 Fh to 7 Fh are reserved. These registers will always read 0 regardless of how they are written.
The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format.
The DS1670 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5
is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1670 also contains a time of day alarm. The alarm registers are located in registers 07h to 0 Ah.
Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an
alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm
will occur every second.
TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
DESCRIPTION
SECONDS MINUTES HOURS DAYS
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
Alarm once per second.
Alarm when seconds match.
Alarm when minutes and seconds match
Alarm when hours, minutes and seconds match.
Alarm when day, hours, minutes and seconds.
SPECIAL PURPOSE REGISTERS
The DS1670 has two additional registers (control register and status register) that control the real-time
clock and interrupts.
CONTROL REGISTER
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC WP
AIS1 AIS0
0
0
0
AIE
EOSC (Enable Oscillator). This bit when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1670 is placed into a low-power standby mode with a current
drain of less than 200nA when in battery-backup mode. When the DS1670 is powered by VCC, the
oscillator is always on regardless of the status of the EOSC bit; however, the real-time clock is
incremented only when EOSC is a logic 0.
WP (Write Protect). Before any write operation to the real time clock or any other registers, this bit
must be logic 0. When high, the write-protect bit prevents a write operation to any register.
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DS1670
AIS0-AIS1 (Analog Input Select). These 2 bits are used to determine the analog input for the analog-to-
digital conversion. Table 2 lists the specific analog input that is selected by these two bits.
AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)
bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the
INT signal.
ANALOG INPUT SELECTION Table 2
AIS1
AIS0
ANALOG INPUT
NONE
0
0
1
1
0
1
0
1
AIN0
AIN1
AIN2
STATUS REGISTER
BIT 7
BIT 6
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IRQF
CU
LOBAT
0
0
0
0
0
CU (Conversion Update In Progress). When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488ms. When this bit is a 0, an update to the ADC Register will not occur for at
least 244ms.
LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the
V BAT pin. When VBAT is greater than 2.5V, LOBAT is set to a logic 0. When VBAT is less than 2.3
volts, LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC, TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1670 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the VCCO
pin. The DS1670 was specifically designed with the Intel 80186 and 386EX microprocessors in mind. As
such, the DS1670 can provide access to the external SRAM in either byte-wide or word-wide format.
This capability is provided by the chip enable scheme. Three input signals and two output signals are
used for enabling the external SRAM(s) (see Figure 4). CEI (chip enable in), BHE (byte high enable),
and BLE (byte low enable) are used for enabling either one or two external SRAMs through the CEOL
(chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the function of these pins.
6 of 16
DS1670
The DS1670 nonvolatilizes the external SRAM(s) by write protecting the SRAM(s) and by providing a
back-up power supply in the absence of VCC. When VCC falls below 2.88V (typical), access to the
external SRAM(s) are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE ,
and BHE . Also at this point, the SRAM power supply (VCCO) is switched from VCC to VBAT. Upon power-
up, access is prohibited until the end of tRPU
.
EXTERNAL SRAM CHIP ENABLE Table 3
FUNCTION
CEI
0
BHE
0
BLE
0
CEOL
CEOH
0
1
0
1
1
0
0
1
1
1
Word Transfer
0
0
1
Byte Transfer in upper half of data bus (D15-D8)
Byte Transfer in lower half of data bus (D7-D0)
External SRAMs disabled
0
1
0
0
1
1
1
X
X
External SRAMs disabled
EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1670 Figure 4
MICROPROCESSOR MONITOR
The DS1670 monitors three vital conditions for a microprocessor: power supply, software execution, and
external override.
First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the
RST pin to the active state, thus warning a processor-based system of impending power failure. The
power-fail trip point is 2.88V (typical). When VCC returns to an in-tolerance condition upon power-up,
the reset signal is kept in the active state for 250ms (typical) to allow the power supply and
microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator
during battery-backup mode), the reset signal will be kept in an active state for 250ms plus the startup
time of the oscillator.
The second monitoring function is pushbutton reset control. The DS1670 provides for a pushbutton
switch to be connected to the RST output pin. When the DS1670 is not in a reset cycle, it continuously
monitors the RST signal for a low-going edge. If an edge is detected, the DS1670 will debounce the
7 of 16
DS1670
switch by pulling the RST line low. After the internal 250ms timer has expired, the DS1670 will continue
to monitor the RST line. If the line is still low, the DS1670 will continue to monitor the line looking for a
rising edge. Upon detecting release, the DS1670 will force the RST line low and hold it low for 250ms.
The third microprocessor monitoring function provided by the DS1670 is a watchdog timer. The
watchdog timer function forces RST to the active state when the ST input is not stimulated within the
predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250ms, 500ms, or 1000ms (see Figure 5). If TD0 and TD1 are both set to 0,
the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set time
period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with
1000ms time delay. If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog
timer is reset and begins to time-out again. If the watchdog timer is allowed to timeout, then the RST
signal is driven to the active state for 250ms (typical). The ST input can be derived from microprocessor
address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not
timeout, a high-to-low transition must occur at or less than the minimum period.
WATCHDOG TIMEOUT CONTROL Figure 5
WATCHDOG REGISTER
BIT 7
BIT 6
BIT 5
BIT 4 BIT 3 BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
TD1
TD0
WATCHDOG TIMEOUT
TD1
TD0
WATCHDOG TIMEOUT
0
0
1
1
0
1
0
1
Watchdog disabled
250ms
500ms
1000ms
ANALOG-TO-DIGITAL CONVERTER
The DS1670 provides a 3-channel, 8-bit analog-to-digital converter. The ADC reference voltage (2.55V
typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided
through the AIN0, AIN1, and AIN2 pins. The ADC is monotonic (no missing codes) and uses a
successive approximation technique to convert the analog signal into a digital code. An A/D conversion is
the process of assigning a digital code to an analog input voltage. This code represents the input value as
a fraction of the full-scale voltage (FSV) range. Thus, the FSV range is then divided by the ADC into 256
codes (8 bits). The FSV range is bounded by an upper limit equal to the reference voltage and the lower
limit, which is ground. The DS1670 has a FSV of 2.55V (typical) that provides a resolution of 10mV. An
input voltage equal to the reference voltage converts to FFh while an input voltage equal to ground
converts to 00h. The relative linearity of the ADC is ±0.5 LSB.
The ADC selects from one of three different analog inputs (AIN0–AIN2). The input that is selected is
determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the specific analog
8 of 16
DS1670
input that is selected by these 2 bits. Note also that the converter can be turned off by these bits to reduce
power. When the ADC is turned on by setting AIS0 and AIS1 to any value other than 0,0 the analog input
voltage is converted and written to the ADC Register within 488ms. An internal analog filter at the input
reduces high frequency noise. Subsequent updates occur approximately every 10ms. If AIS0 and/or AIS1
are changed, updates will occur at the next 10ms conversion time.
The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488ms maximum.
However, when this bit is 0 an update will not occur for at least 244ms. The CU bit should be polled
before reading the ADC Register to ensure that the contents are stable during a read cycle. Once a read
cycle to the ADC Register has been started, the DS1670 will not update that register until the read cycle
has been completed. It should also be mentioned that taking CS low will abort the read cycle and will
allow the ADC Register to be updated.
Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.
CU BIT TIMING Figure 6
3-WIRE SERIAL INTERFACE
Communication with the DS1670 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must
be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the
CS input goes low, all data transfer terminates and the I/O pin goes to a high-impedance state.
9 of 16
DS1670
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by one or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit
(RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles
will occur. If this bit is 1, one or more write cycles will occur.
Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CS is driven high an
address is written to the DS1670. After the address, one or more data bytes can be read or written. For a
single-byte transfer 1 byte is read or written and then CS is driven low. For a multiple-byte transfer,
multiple bytes can be read or written to the DS1670 after the address has been written. Each read or write
cycle causes the register address to automatically increment. Incrementing continues until the device is
disabled. After accessing register 0Eh, the address wraps to 00h.
Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 7 and 8.
SINGLE-BYTE DATA TRANSFER Figure 7
CS
SCLK
RD
A0
A1 A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6 D7
WR
MULTIPLE-BYTE BURST TRANSFER Figure 8
CS
SCLK
I/O
ADDRESS
BYTE
DATA
DATA
DATA
BYTE 0
BYTE 1
BYTE N
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DS1670
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground………………………………………………………-0.3V to +6V
Operating Temperature………………………………………………………………………..0°C to +70°C
Storage Temperature………………………………………………………………………-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0LC to +70LC)
PARAMETER
Power-Supply Voltage
Input Logic 1
SYMBOL
VCC
MIN
2.97
2.0
TYP
MAX
3.63
UNITS
NOTES
3.3
V
V
V
V
1
1
1
1
VIH
VCC + 0.3
+0.8
Input Logic 0
VIL
-0.3
2.5
Battery Voltage
VBAT
3.7
11 of 16
DS1670
DC ELECTRICAL CHARACTERISTICS
(TA = 0LC to +70LC)
PARAMETER
Input Leakage
SYMBOL
ILI
MIN
TYP
MAX
+1
UNITS
ꢀA
ꢀA
V
NOTES
-1
CS Leakage
ILO
150
7
2
3
Logic 1 Output (Iout=-0.4 mA)
Logic 0 Output (Iout=1.5 mA)
VOH
2.4
VOL
0.4
1.0
V
Active Supply Current
(CS = VCC-0.2)
ICCA
0.75
300
mA
4
A/D Converter Current
Standby Current (CS=VIL)
Battery Current (Oscillator On)
Battery Current (Oscillator Off)
Internal RST Pull-up Resistor
VCC Trip Point
IADC
ICCS
200
100
500
200
60
5
6
ꢀA
ꢀA
nA
nA
kꢁ
V
IBAT1
IBAT2
RP
35
47
VCCTP
VCCSW
VADC
PBDV
PBRD
VCCO
2.80
2.62
2.47
0.8
2.88
2.70
2.55
2.97
2.78
2.63
2.0
VCC Switchover
V
12
A/D Reference Voltage
Pushbutton Detect
V
V
Pushbutton Release
0.3
0.8
V
Output Voltage
VCC-0.3
V
11
13
VCCO Output Current
(Source = VCC)
ICCO1
ICCO2
100
150
mA
VCCO Output Current
14
ꢀA
(Source = VBAT
)
CAPACITANCE
(TA = +25LC)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
I/O Capacitance
CI
CI/O
CX
10
15
6
pF
pF
pF
Crystal Capacitance
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DS1670
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = 0LC to +70LC.)
PARAMETER
Data to Clock Setup
CLK to Data Hold
CLK to Data Delay
CLK to Low Time
CLK to High Time
CLK Frequency
SYMBOL
tDC
MIN
100
TYP
MAX
UNITS
ns
NOTES
8
tCDH
tCDD
tCL
140
ns
8
400
ns
8, 9, 10
500
500
ns
8
8
8
tCH
ns
tCLK
tR, tF
tCC
1.0
MHz
ns
CLK Rise and Fall
CS to CLK Setup
CLK to CS Hold
1000
2
120
2
8
8
8
8
8
ꢀs
tCCH
tCWH
tCDZ
tCCZ
ns
CS Inactive Time
CS to I/O High-Z
SCLK to I/O High-Z
ꢀs
140
140
ns
ns
VCC Slew Rate (2.85V to
2.3V)
tF
tR
300
0
ꢀs
VCC Slew Rate (2.3V to
2.85V)
ns
VCC Detect to RST
(VCC Falling)
tRPD
100
ns
Reset Active Time
tRST
250
250
ms
ms
15
15
Pushbutton Debounce
PBDB
VCC Detect to RST
(VCC Rising)
tRPU
tST
tCED
tFB
250
ms
ns
ns
ꢀs
15, 16
ST Pulse Width
20
Chip Enable Propagation
Delay to External SRAM
8
15
Nominal Voltage to VCC
Switchover Fall Time
200
13 of 16
DS1670
TIMING DIAGRAM: READ DATA Figure 9
TIMING DIAGERAM: WRITE DATA Figure 10
14 of 16
DS1670
PUSHBUTTON RESET Figure 11
RST
VOH
PBDV
PBRD
PBDB
tRST
POWER-UP Figure 12
VCCTP
VCC
tRPU
VOH
RST
POWER-DOWN Figure 13
VCC
VCCTPMAX
VCCTP
VCCSWMIN
RST
VOL
tRPD
tFB
15 of 16
DS1670
NOTES:
1. All voltages are referenced to ground.
2. Logic 1 voltages are specified at VCC = 3.3V, VOH = VCC for capacitive loads. Excludes
3. Logic 0 voltages are specified at VCC = 3.3V, VOL = GND for capacitive loads.
pin.
RST
4. ICCA is specified with outputs open, CS set to a logic 1, SCLK = 500kHz, oscillator enabled, and
DAC enabled.
5.
6.
I
I
ADC is specified with CS, VCCO open and I/O, SCLK at logic 0. ADC is enabled.
CCS is specified with CS, VCCO open and I/O, SCLK at logic 0. ADC is disabled.
7. CS has a 40kꢁ pulldown resistor to ground.
8. Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time.
9. Measured at VOH = 2.4V or VOL = 0.4V.
10. Load capacitance = 50 pF.
11. ICCO = 100 mA, VCC > VCCTP
.
12. VCCO switchover from VCC to VBAT occurs when VCC drops below the lower of VCCSW and VBAT
13. Current from VCC input pin to VCCO output pin.
.
14. Current from VBAT input pin to VCCO output pin.
15. Time base is generated by very accurate crystal oscillator. Accuracy of this time period is based on
the crystal that is used. A typical crystal with a specified load capacitance of 6pF will provide an
accuracy within ±100ppm over the 0°C to +70°C temperature range.
16. If the EOSC bit in the Control Register is set to a logic 1, tRPU is equal to 250ms plus the startup time
of the crystal oscillator.
PACKAGE INFORMATION
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
16 of 16
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products S Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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