DS1742W-150 [MAXIM]
Y2KC Nonvolatile Timekeeping RAMwww.; Y2KC非易失时钟RAMwww 。
| 型号： | DS1742W-150 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Y2KC Nonvolatile Timekeeping RAMwww. |
| 文件： | 总16页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1742
Y2KC Nonvolatile Timekeeping
RAM
www.maxim-ic.com
FEATURES
PIN CONFIGURATION
ꢀ Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
ꢀ Clock Registers are Accessed Identically to
the Static RAM; These Registers are
Resident in the Eight Top RAM Locations
ꢀ Century Byte Register
ꢀ Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
ꢀ BCD Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the year 2100
TOP VIEW
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DS1742
9
DQ0
DQ1
DQ2
GND
10
11
12
ENCAPSULATED DIP
ꢀ Battery Voltage Level Indicator Flag
ꢀ Power-Fail Write Protection Allows for ±10%
VCC Power Supply Tolerance
ꢀ Lithium Energy Source is Electrically
Disconnected to Retain Freshness until
Power is Applied for the First Time
ꢀ Standard JEDEC Bytewide 2k x 8 Static
RAM Pinout
ꢀ Quartz Accuracy ±1 Minute a Month at
+25°C, Factory Calibrated
ꢀ
Underwriters Laboratories (UL®)
Recognized
ORDERING INFORMATION
PART
VOLTAGE (V)
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
24 EDIP (0.740a)
TOP MARK**
DS1742-85
DS1742-85+
DS1742-100
DS1742-100+
DS1742-100IND
DS1742-100IND+
DS1742W-120
DS1742W-120+
DS1742W-150
DS1742W-150+
5.0
5.0
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
DS1742-85
DS1742-85+
DS1742-100
DS1742-100+
DS1742-100IND
DS1742-100IND+
DS1742W-120
DS1742W-120+
DS1742W-150
DS1742W-150+
+Denotes a lead-free/RoHS-compliant device.
**The top mark will include a “+” on lead-free devices.
UL is a registered trademark of Underwriters Laboratories, Inc.
1 of 16
REV: 102808
DS1742
PIN DESCRIPTION
PIN
1
NAME
A7
FUNCTION
2
A6
3
A5
4
A4
5
A3
Address Input
6
A2
7
A1
8
A0
19
22
23
9
A10
A9
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
10
11
13
14
15
16
17
12
18
20
21
24
Data Input/Output
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
Power-Supply Input
OE
WE
VCC
DESCRIPTION
The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and
2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished
with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in
the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day,
hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month
and leap year are made automatically.
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1742 also
contains its own power-fail circuitry, which deselects the device when the VCC supply is in an
out-of-tolerance condition. This feature prevents loss of data from unpredictable system
operation brought on by low VCC as errant access and update cycles are avoided.
2 of 16
DS1742
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data,
internal updates to the DS1742 clock registers should be halted before clock data is read to
prevent reading of data in transition. However, halting the internal clock register updating
process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit,
bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is
halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was
current at the moment the halt command was issued. However, the internal clock registers of
the double-buffered system continue to update so that the clock accuracy is not affected by the
access of data. All of the DS1742 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500μs to ensure the external
registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM
Table 1. TRUTH TABLE
VCC
MODE
Deselect
Write
Read
Read
DQ
POWER
Standby
Active
Active
Active
CE OE
WE
X
VIL
VIH
VIL
X
X
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
VCC > VPF
VIL VIL VIH
VIL VIH VIH
VSO < VCC < VPF
VCC < VSO < VPF
X
X
X
X
X
X
Deselect
Deselect
CMOS Standby
Data Retention Mode
3 of 16
DS1742
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like
the read bit, halts updates to the DS1742 registers. The user can then load them with the
correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then
transfers those values to the actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be
turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the
seconds registers, see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit
is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512
Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency
as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for
seconds register remain valid and stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. Dallas
Semiconductor calibrates the RTC at the factory using nonvolatile tuning elements. The
DS1742 does not require additional calibration. For this reason, methods of field clock
calibration are not available and not necessary. Clock accuracy is also affected by the electrical
environment and caution should be taken to place the RTC in the lowest level EMI section of
the PCB layout. For additional information refer to Application Note 58.
Table 2. REGISTER MAP
DATA
B4
ADDRES
S
FUNCTION
RANGE
B7
B6
B5
B3
B2
Year
B1
B0
7FF
10 Year
Year
00–99
01–12
10
Month
10 Date
7FE
X
X
X
FT
X
X
Month
Month
7FD
7FC
7FB
7FA
7F9
7F8
X
BF
X
Date
Day
Hour
Date
Day
Hour
Minutes
Seconds
Control
01–31
01–07
00–23
00–59
00–59
00–39
X
X
X
10 Hour
X
10 Minutes
10 Seconds
Minutes
Seconds
Century
OSC
W
R
10 Century
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
FT = FREQUENCY TEST
BF = BATTERY FLAG
X = SEE NOTE BELOW
Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation.
4 of 16
DS1742
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is
high, and CE (chip enable) is low. The device architecture allows ripple-through access to any
of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA
after the last address input is stable, providing that the CE and OE access times and states are
satisfied. If CE or OE access times and states are not met, valid data will be available at the
latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data
input/output pins (DQ) is controlled by CE , and OE . If the outputs are activated before tAA, the
data lines are driven to an intermediate state until tAA. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then
go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a
write is referenced to the latter occurring transition of WE on CE . The addresses must be held
valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the
initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and
remain valid for tDH afterward. In a typical application, the OE signal will be high during a write
cycle. However, OE can be active provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the data bus can become active with read
data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ
after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than
VPF
.
However, when VCC is below the power fail point, VPF (point at which write protection
,
occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC
pin to the backup battery. RTC operation and SRAM data are maintained from the battery until
V
CC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or
read only when VCC is greater than VPF When VCC falls below the power fail point, VPF access to
the device is inhibited. If VPF is less than Vso the device power is switched from VCC to the
backup supply (VBAT) when VCC drops below VPF
switched from VCC to the backup supply (VBAT when VCC drops below Vso
.
,
,
.
If VPF is greater than Vso
,
.
the device power is
RTC operation and
)
SRAM data are maintained from the battery until VCC is returned to nominal levels.
5 of 16
DS1742
BATTERY LONGEVITY
The DS1742 has a lithium power source that is designed to provide energy for clock activity,
and clock and RAM data retention when the VCC supply is not present. The capability of this
internal power supply is sufficient to power the DS1742 continuously for the life of the
equipment in which it is installed. For specification purposes, the life expectancy is 10 years at
25°C with the internal clock oscillator running in the absence of VCC power. Each DS1742 is
shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy
source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be
much longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit
(bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not
writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium
energy source is indicated and both the contents of the RTC and RAM are questionable.
6 of 16
DS1742
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………..-0.3V to +6.0V
Storage Temperature Range………………………………………………………...-40°C to +85°C
Soldering Temperature (EDIP, leads)..……………………..+260°C for 10 seconds (See Note 7)
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMPERATURE
0°C to +70°C (noncondensing)
-40°C to +85°C (noncondensing)
VCC
3.3V ±10% or 5V ±10%
3.3V ±10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(Over the operating range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Logic 1
Voltage
(All Inputs)
VCC = 5V ±10%
VIH
2.2
VCC + 0.3V
V
V
V
V
1
1
1
1
VCC = 3.3V
±10%
VIH
VIL
VIL
2.0
-0.3
-0.3
VCC + 0.3V
+0.8
Logic 0
Voltage
(All Inputs)
VCC = 5V ±10%
VCC = 3.3V
±10%
+0.6
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
ICC
15
50
mA
2, 3
TTL Standby Current (CE =
VIH)
CMOS Standby Current
(CE ≥VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
ICC1
1
1
3
mA
2, 3
ICC2
IIL
3
mA
A
2, 3
-1
-1
+1
+1
IOL
A
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOH
VOL
2.4
1
1
0.4
Write Protection Voltage
VPF
VSO
4.25
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
7 of 16
DS1742
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
ICC
10
30
mA
2, 3
TTL Standby Current (CE =
VIH)
CMOS Standby Current
(CE ≥VCC - 0.2V)
Input Leakage Current (any
input)
Output Leakage Current
(Any Output)
ICC1
0.7
0.7
2
mA
2, 3
ICC2
IIL
2
mA
A
2, 3
-1
-1
+1
+1
IOL
A
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH
2.4
1
Output Logic 0 Voltage
(IOUT =2.1mA)
Write Protection Voltage
VOL
VPF
VSO
0.4
1
1
2.80
2.97
V
V
VBAT or
VPF
Battery Switchover Voltage
1, 4
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V ±10%, Over the operating range.)
85ns
100ns ACCESS UNITS
ACCESS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Read Cycle Time
Address Access Time
CE to DQ Low-Z
CE Access Time
CE Data Off time
OE to DQ Low-Z
OE Access Time
tRC
tAA
85
5
100
ns
ns
ns
ns
ns
ns
ns
ns
85
100
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
5
5
85
30
100
35
5
5
45
30
55
35
OE Data Off Time
Output Hold from
Address
tOH
5
ns
8 of 16
DS1742
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V ±10%, Over the operating range.)
120ns
150ns
ACCESS
ACCESS
PARAMETER
SYMBOL
UNITS
MIN
MAX
MIN
MAX
Read Cycle Time
Address Access Time
CE to DQ Low-Z
tRC
tAA
120
5
150
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
150
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
120
40
150
50
CE Access Time
CE Data Off time
OE to DQ Low-Z
5
5
5
5
100
35
130
35
OE Access Time
OE Data Off Time
Output Hold from Address
READ CYCLE TIMING DIAGRAM
9 of 16
DS1742
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V ±10%, Over the operating range.)
100ns
ACCESS
85ns ACCESS
PARAMETER
SYMBOL
UNITS
MIN
85
0
MAX
MIN
100
0
MAX
Write Cycle Time
Address Access Time
WE Pulse Width
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWEW
tCEW
tDS
65
70
35
0
70
75
40
0
CE Pulse Width
Data Setup Time
Data Hold time
tDH
Address Hold Time
WE Data Off Time
Write Recovery Time
tAH
5
5
30
tWEZ
tWR
35
5
5
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V ±10%, Over the operating range.)
120ns
150ns
PARAMETER
SYMBOL
ACCESS
ACCESS
UNITS
MIN
MAX
MIN
MAX
Write Cycle Time
Address Setup Time
WE Pulse Width
tWC
tAS
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWEW
tCEW
tDS
100
110
80
0
130
140
90
0
CE Pulse Width
Data Setup Time
Data Hold Time
tDH
Address Hold Time
WE Data Off Time
Write Recovery Time
tAH
0
0
tWEZ
tWR
40
50
10
10
10 of 16
DS1742
WRITE CYCLE TIMING DIAGRAM—WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM—CHIP-ENABLE CONTROLLED
11 of 16
DS1742
POWER-UP/POWER-DOWN CHARACTERISTICS (5V)
(VCC = 5.0V ±10%, Over the operating range.)
PARAMETER
SYMBOL MIN
TYP MAX UNITS NOTES
tPD
0
μs
CE or WE at VIH, Before Power-Down
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recover Time
tF
tFB
tR
300
10
0
μs
μs
μs
tREC
35
ms
Expected Data Retention Time
(Oscillator On)
tDR
10
years
5, 6
POWER-UP/POWER-DOWN WAVEFORM TIMING (5V DEVICE)
12 of 16
DS1742
POWER-UP/POWER-DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V ±10%, Over the operating range.)
PARAMETER
SYMBOL MIN
TYP MAX UNITS NOTES
CE or WE at VIH, Before Power-
Down
tPD
0
s
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recovery Time
tF
tR
300
0
s
s
tREC
35
ms
Expected Data Retention Time
(Oscillator On)
tDR
10
years
5, 6
POWER-UP/POWER-DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
Capacitance on All Input Pins
SYMBOL
CIN
MIN
TYP
MAX
7
UNITS NOTES
pF
pF
Capacitance on All Output
Pins
CO
10
13 of 16
DS1742
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0.0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltage referenced to ground.
2) Typical values are at 25°C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery voltage or VPF.
5) Data retention time is at 25°C.
6) Each DS1742 has a built-in switch that disconnects the lithium source until VCC is first
applied by the user. The expected tDR is defined as a cumulative time in the absence of VCC
starting from the time power is first applied by the user.
7) Real-time clock modules can be successfully processed through conventional wave-
soldering techniques as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post-solder cleaning with water washing
techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to
the crystal.
14 of 16
DS1742
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/packages.)
15 of 16
DS1742
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Added “UL Recognized” bullet to Features and new Ordering
Information table.
1
Added new Pin Description table.
Updated note for Table 2
2
4
041305
updated Operating Temperature Range for Absolute Maximum
Ratings.
Corrected 24-pin to 28-pin package and top mark items in
Ordering Information table.
Removed reference to J-STD-020 and indicated the lead
soldering temperature of +260°C for 10 seconds max.
Added DS1742-85, DS1742-85+ to the Ordering Information
table; removed DS1742P-100+ (PowerCap) package.
Removed the –70 ordering numbers from the Ordering
Information table.
7
1
7
1
1
071905
060706
022207
102808
16 of 16
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
相关型号：
DS1743-100IND+
Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, ROHS COMPLIANT, EDIP MODULE-28
MAXIM
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