DS1743W-120IND+ [MAXIM]
Y2K-Compliant, Nonvolatile Timekeeping RAMs;
| 型号： | DS1743W-120IND+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 文件： | 总17页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1743/DS1743P
Y2K-Compliant, Nonvolatile Timekeeping
RAMs
FEATURES
PIN CONFIGURATIONS
. Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
. Clock Registers are Accessed Identically to
the Static RAM. These Registers Reside in
the Eight Top RAM Locations.
TOP VIEW
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DS1743
. Century Byte Register
. Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
. BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
through 2099
A0
DQ0
DQ1
DQ2
GND
28-Pin Encapsulated Package
(28 PIN 740)
. Low-Battery-Voltage Level Indicator Flag
. Power-Fail Write Protection Allows for ±10%
VCC Power-Supply Tolerance
. Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
. DIP Module Only
Standard JEDEC Bytewide 8k x 8 Static
RAM Pinout
. PowerCap Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
34
N.C.
N.C.
N.C.
1
2
3
N.C.
N.C.
N.C.
DS1743P
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
A12
A11
A10
A9
4
5
6
RST
VCC
WE
7
OE
8
CE
A8
9
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
13
14
15
16
17
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND VBAT
X1
X2
Replaceable Battery (PowerCap)
Power-On Reset Output
34-Pin PowerCap Module Board
(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
Pin-for-Pin Compatible with Other Densities
of DS174XP Timekeeping RAM
.
Underwriters Laboratories (UL) Recognized
to Prevent Charging of the Internal Lithium
Battery
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, click here: www.maximintegrated.com/errata.
1 of 17
19-6719; Rev 9/13
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
PIN
NAME
FUNCTION
NAME
FUNCTION
PDIP
PowerCap
1, 2, 3,
31–34
30
PDIP
20
PowerCap
Chip Enable,
Active Low
Address Input
Output Enable,
Active Low
1
N.C.
No Connection
8
28
7
CE
A10
OE
2
3
A12
A7
21
25
24
23
22
21
20
19
18
16
15
14
17
13
12
11
10
9
22
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
DQ7
23
24
25
26
29
27
26
—
A11
A9
Address Input
Address Input
A8
CE2
Chip Enable 2
Write Enable,
Active Low
Power-Supply
Input
27
28
6
5
WE
VCC
Data Input/
Output
Power-On Reset
Output, Active
Low
—
4
RST
Ground
Crystal
Connection
Battery
Connection
—
—
X1, X2
VBAT
Data Input/
Output
2 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
VOLTAGE
PART
TEMP RANGE PIN-PACKAGE
TOP MARK**
DS1743-85
(V)
DS1743-85+
DS1743-100+
0°C to +70°C
0°C to +70°C
28 EDIP Module
28 EDIP Module
5
5
DS1743-100
DS1743-100 IND+
DS1743P-85+
DS1743P-100+
-40°C to +85°C 28 EDIP Module
5
5
5
DS1743-100-IND
DS1743P-85
DS1743P-100
0°C to +70°C
0°C to +70°C
34 PowerCap*
34 PowerCap*
DS1743P-100IND+
DS1743W-120+
DS1743W-120 IND+
DS1743W-150+
DS1743W-150 IND+
DS1743WP-120+
DS1743WP-120 IND+
DS9034PCX+
-40°C to +85°C 34 PowerCap*
0°C to +70°C 28 EDIP Module
-40°C to +85°C 28 EDIP Module
0°C to +70°C 28 EDIP Module
-40°C to +85°C 28 EDIP Module
0°C to +70°C 34 PowerCap*
-40°C to +85°C 34 PowerCap*
0°C to +70°C PowerCap
-40°C to +85°C PowerCap IND
5
DS1743P-100 IND
DS1743W-120
DS1743W-120 IND
DS1743W-150
DS1743W-150 IND
DS1743WP-120
DS1743WP-120 IND
DS9034PC
3.3
3.3
3.3
3.3
3.3
3.3
—
—
DS9034I-PCX+
DS9034PCI
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX+ or DS9034I-PCX+ required (must be ordered separately).
**A ‘+’ indicates lead(Pb)-free. The top mark will include a ‘+’ symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM
locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in
24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the timekeeping
countdown continues unabated by access to time register data. The DS1743 also contains its own power-
fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. When
VCC is above VPF, the device is fully accessible. When VCC is below VPF, the internal CE signal is forced
high, preventing any access. When VCC rises above VPF, access remains inhibited for TREC, allowing time
for the system to stabilize. These features prevent loss of data from unpredictable system operation brought
on by low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin
DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surface-
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers.
3 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the
RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The
contents of the time and date registers are in the BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register
updating process has been re-enabled. Updating is within a second after the read bit is written to 0.
The READ bit must be a zero for a minimum of 500µs to ensure the external registers are updated.
4 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Dallas
Semiconductor
DS1743
Table 1. Truth Table
CE
VIH
X
VIL
VIL
VIL
X
OE WE
VCC
CE2
X
VIL
VIH
MODE
Deselect
Deselect
Write
Read
Read
DQ
POWER
Standby
Standby
Active
Active
X
X
X
X
X
VIL
High-Z
High-Z
Data In
Data Out
High-Z
High-Z
VCC > VPF
VIH VIL VIH
VIH VIH VIH
Active
VSO < VCC < VPF
VCC<VSO<VPF
X
X
X
Deselect
CMOS Standby
Data-Retention
Mode
X
X
X
X
Deselect
High-Z
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the DS1743 registers. The user can subsequently load correct date and time values into all eight
registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new
settings into the clock, allowing timekeeping operations to resume from the new set-point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the DS1743 registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous
set-point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle
to Control if the W bit is being cleared to 0 in that write operation.
5 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write
cycle to Control if the R bit is being cleared to 0 in that write operation.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the
RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. The
electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, please refer to Application
Note 58: Crystal Considerations with Dallas Real-Time Clocks.
6 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
DATA
B4
ADDRESS
FUNCTION
RANGE
B7
B6
B5
X
B3
B2
Year
B1
B0
1FFF
1FFE
10 Year
Year
00–99
01–12
10
Month
10 Date
X
X
Month
Date
Month
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
X
BF
X
X
FT
X
Date
Day
01–31
01–07
00–23
00–59
00–59
00–39
X
X
X
Day
Hour
10 Hour
Hour
X
10 Minutes
10 Seconds
Minutes
Seconds
Century
Minutes
Seconds
Control
OSC
W
R
10 Century
R = READ BIT
FT = FREQUENCY TEST
BF = BATTERY FLAG
OSC = STOP BIT
W = WRITE BIT
X = SEE NOTE BELOW
Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in
the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable,
providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states
are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access
time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are
activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are
changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but
will then go indeterminate until the next address access.
7 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write
cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical
application, the OE signal will be high during a write cycle. However, OE can be active provided that care
is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus
can become active with read data defined by the address inputs. A low transition on WE will then disable
the outputs tWEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time (PowerCap only) the power-
fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. When
VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC
in to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF
.
When VCC falls below the power-fail point, VPF, access to the device is inhibited. At this time the power-
fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. If VPF
is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops
below VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT
)
when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels. The RST (PowerCap only) signal is an open-drain output and requires a pullup
resistor. Except for RST, all control, data, and address signals must be powered down when VCC is
powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the VCC supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writeable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and
both the contents of the RTC and RAM are questionable.
8 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………-0.3V to +6.0V
Storage Temperature Range……………………………………………………………………….-40°C to +85°C
Soldering Temperature (EDIP) (leads, 10 seconds)…………………….……………………………..…+260°C
Soldering Temperature…………………………………………..….See J-STD-020 Specification (See Note 8)
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMP RANGE
0°C to +70°C
-40°C to +85°C
VCC
3.3V ±10% or 5V ±10%
3.3V ±10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range.)
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX
UNITS NOTES
VCC
+0.3V
VCC
2.2
V
1
V
CC = 5V ±10%
Logic 1 Voltage All Inputs
VIH
VIL
VCC = 3.3V
±10%
2.0
-0.3
-0.3
V
V
V
1
1
1
+0.3V
+0.8
VCC = 5V ±10%
Logic 0 Voltage All Inputs
VCC = 3.3V
±10%
+0.6
DC ELECTRICAL CHARACTERISTICS (5V)
( VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN TYP MAX
UNITS NOTES
Active Supply Current
ICC
15
1
50
3
mA
mA
2, 3
2, 3
TTL Standby Current
(CE = VIH, CE2 = VIL)
CMOS Standby Current
(CE ≥ VCC - 0.2V; CE2 = GND + 0.2V)
ICC1
ICC2
1
3
mA
2, 3
Input Leakage Current (Any Input)
IIL
-1
-1
+1
+1
µA
µA
Output Leakage Current (Any Output)
IOL
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = 2.1mA)
VOH
2.4
1
1
VOL1
0.4
Write-Protection Voltage
VPF
VSO
4.20
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
9 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
10
MAX
30
UNITS
mA
NOTES
2, 3
Active Supply Current
ICC
TTL Standby Current (CE = VIH)
ICC1
0.7
2
mA
2, 3
CMOS Standby Current
(CE ≥ VCC - 0.2V;
CE2 = GND + 0.2V)
Input Leakage Current
(Any Input)
ICC2
0.7
2
mA
2, 3
IIL
IOL
-1
-1
+1
+1
µA
µA
Output Leakage Current
(Any Output)
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH
2.4
1
Output Logic 0 Voltage
(IOUT =2.1mA)
VOL1
VPF
0.4
1
1
Write-Protection Voltage
2.75
2.97
V
V
VBAT
or
Battery Switchover Voltage
VSO
1, 4
VPF
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
ACCESS
85ns
PARAMETER
SYMBOL
70ns
100ns
UNITS NOTES
MIN MAX MIN MAX MIN MAX
Read Cycle Time
tRC
tAA
70
85
100
ns
ns
Address Access Time
CE to CE2 to DQ Low-Z
CE Access Time
70
85
100
tCEL
tCEA
tCE2A
5
5
5
ns
ns
ns
5
5
5
70
80
85
95
100
105
CE2 Access Time
CE and CE2 Data-Off
Time
tCEZ
25
30
35
ns
OE to DQ Low-Z
OE Access Time
OE Data-Off Time
tOEL
tOEA
tOEZ
5
5
5
5
5
5
ns
ns
ns
35
25
45
30
55
35
Output Hold from
Address
tOH
ns
10 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
ACCESS
120ns
150ns
PARAMETER
SYMBOL
UNITS
NOTES
MIN MAX MIN MAX
Read Cycle Time
tRC
tAA
120
5
150
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
CE and CE2 Low to DQ Low-Z
CE Access Time
120
150
tCEL
tCEA
tCE2A
tCEZ
tOEL
tOEA
tOEZ
tOH
5
5
5
5
120
140
40
150
170
50
CE2 Access Time
CE and CE2 Data-Off time
OE Low to DQ Low-Z
OE Access Time
5
5
5
5
100
35
130
35
OE Data-Off Time
Output Hold from Address
READ CYCLE TIMING DIAGRAM
11 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
ACCESS
85ns
PARAMETER
SYMBOL
70ns
100ns
UNITS NOTES
MIN MAX MIN MAX MIN MAX
Write Cycle Time
Address Setup Time
WE Pulse Width
tWC
tAS
70
0
85
0
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
tWEW
tCEW
tCE2W
tDS
50
60
65
30
0
65
70
75
35
0
70
75
85
40
0
CE Pulse Width
5
5
5
5
5
5
CE2 Pulse Width
Data Setup Time
Data Hold Time CE
Data Hold Time CE2
Address Hold Time
WE Data-Off Time
Write Recovery Time
tDH
tDH
8
8
8
tAH
5
5
5
tWEZ
tWR
25
30
35
10
10
10
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
ACCESS
120ns
150ns
PARAMETER
SYMBOL
UNITS
NOTES
MIN MAX MIN MAX
Write Cycle Time
tWC
tAS
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
WE Pulse Width
5
tWEW
tCEW
tDS
100
110
80
0
130
140
90
0
CE and CE2 Pulse Width
Data Setup Time
5
5
5
5
5
Data Hold Time CE
Data Hold Time CE2
Address Hold Time
WE Data-Off Time
Write Recovery Time
tDH
tDH
10
0
10
0
tAH
tWEZ
tWR
40
50
10
10
12 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5)
WRITE CYCLE TIMING—CE/CE2-CONTROLLED (See Note 5)
13 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS—5V
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or WE at VIH, CE2 at VIL, Before
Power-Down
tPD
0
µs
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recover Time
tF
tFB
tR
300
10
0
µs
µs
µs
ms
tREC
35
Expected Data-Retention Time
(Oscillator On)
tDR
10
years
6, 7
POWER-UP/DOWN TIMING (5V DEVICE)
14 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS—3.3V
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or WE at VIH, Before
Power-Down
tPD
0
µs
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Rise Time: VPF(MIN) to VPF(MAX)
tF
tR
300
0
µs
µs
VPF to RST High
tREC
35
ms
Expected Data-Retention Time
(Oscillator On)
tDR
10
years
6, 7
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
Capacitance on All Input Pins
Capacitance on All Output Pins
SYMBOL
CIN
MIN
TYP
MAX
7
UNITS
pF
NOTES
CO
10
pF
15 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25°C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) The CE2 control signal functions the same as the CE signal except that the logic levels for active and
inactive levels are opposite. If CE2 is used to terminate a write, the CE2 data hold time (tDH) applies.
6) Data-retention time is at +25°C.
7) Each DS1743 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting
from the time power is first applied by the user.
8) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is
acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for
details regarding the PowerCap package.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
28 EDIP (740)
34 PWRCP
PACKAGE CODE
MDF28+2
OUTLINE NO.
21-0245
LAND PATTERN NO.
—
—
PC1+2
21-0246
16 of 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISION HISTORY
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
Updated the Ordering Information table; updated the Setting the Clock
section added the parameter tCE2A for 3.3V read operation in the AC
Characteristics—Read Cycle (3.3V) table
9/13
3, 4, 11
17 of 17
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
相关型号：
DS1743W-150IND+
Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, ROHS COMPLIANT, EDIP MODULE-28
MAXIM
DS1743WP-120+
Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, ROHS COMPLIANT, POWERCAP MODULE-34
MAXIM
DS1743WP-120IND+
Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, ROHS COMPLIANT, POWERCAP MODULE-34
MAXIM
©2020 ICPDF网 联系我们和版权申明