DS1747WP-C01 [MAXIM]
Real Time Clock, CMOS, POWERCAP MODULE BOARD-34;
| 型号： | DS1747WP-C01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, CMOS, POWERCAP MODULE BOARD-34 双倍数据速率 外围集成电路 |
| 文件： | 总16页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1747/DS1747P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
PIN CONFIGURATIONS
. Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control
Circuit, and Lithium Energy Source
TOP VIEW
A18
VCC
A15
A17
WE
A13
A8
1
32
31
A16
A14
A12
A7
Dallas
2
3
4
. Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Semiconductor 30
DS1747
29
Resident in the Eight Top RAM Locations
5
6
28
27
A6
A5
. Century Byte Register (Y2K Compliant)
A9
A11
7
8
26
25
A4
A3
. Totally Nonvolatile with Over 10 Years of
OE
A10
CE
9
10
24
23
Operation in the Absence of Power
A2
A1
11
12
22
21
. BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the Year 2100
DQ7
DQ6
DQ5
DQ4
DQ3
A0
13
14
15
16
20
19
18
17
DQ0
DQ1
DQ2
. Battery Voltage-Level Indicator Flag
GND
. Power-Fail Write Protection Allows for
Encapsulated DIP
(512k x 8)
±10% VCC Power-Supply Tolerance
. Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
N.C.
A15
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Dallas
Semiconductor
DS1747P
. DIP Module Only:
A13
A12
A11
A10
A9
RST
VCC
Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
. PowerCap Module Board Only:
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
WE
OE
CE
A8
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
VBAT
X1
GND
X2
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
PowerCap Module Board
(Uses DS9034PCX PowerCap)
. Also Available in Industrial Temperature
Range: -40°C to +85°C
PowerCap is a registered trademark of Maxim Integrated Products, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 16
REV: 112906
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
NAME
FUNCTION
EDIP
1
PowerCap
34
3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
2
3
4
5
6
7
8
9
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
33
2
16
15
14
13
12
11
10
9
Address Input
10
11
12
23
25
26
27
28
30
31
13
14
15
17
18
19
20
21
16
22
24
29
32
—
—
—
A8
A13
A17
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
Data Input/Output
17
8
7
6
5
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
Power-Supply Input
No Connection
Active-Low Power-On Reset Output
OE
WE
VCC
N.C.
RST
1
4
(See Pin
Configuration)
(See Pin
X1, X2
VBAT
Crystal Input, Output Connections
Battery Connection
—
Configuration)
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
SUPPLY
PART
VOLTAGE
(V)
5.0
TEMP RANGE
PIN-PACKAGE
TOP MARK†
DS1747-70
DS1747-70 IND
DS1747P-70
DS1747P-70 IND
DS1747W-120
DS1747W-120 IND
DS1747WP-120
DS1747WP-120 IND
DS1747-70
DS1747-70 IND
DS1747P-70
DS1747P-70 IND
DS1747W-120
DS1747W-120 IND
DS1747WP-120
DS1747WP-120 IND
DS1747-70
DS1747-70IND
DS1747P-70
DS1747P-70IND
DS1747W-120
DS1747W-120IND
DS1747WP-120
DS1747WP-120IND
DS1747-70+
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap
5.0
5.0
5.0
3.3
3.3
3.3
3.3
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
DS1747-70IND+
DS1747P-70+
DS1747P-70IND+
DS1747W-120+
DS1747W-120IND+
DS1747WP-120+
DS1747WP-120IND+
*DS9034PCX, DS9034I-PCX, DS9034PCX+, DS9034I-PCX required (must be ordered separately).
†A “+” indicates a lead(Pb) free. The top mark will include a “+” symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1747 also
contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on
by low VCC as errant access and update cycles are avoided.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Dallas
Semiconductor
DS1747
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers. The part number for the
PowerCap is DS9034PCX.
TIME AND DATE OPERATIONS
The contents of the time and date registers are in BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register (see
Table 2). As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500s to ensure the external registers will be updated.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
CE
OE
WE
VCC
MODE
DQ
POWER
VIH
VIL
VIL
VIL
X
X
X
VIL
VIH
X
X
Deselect
Write
Read
Read
Deselect
High-Z
Data In
Data Out
High-Z
High-Z
Standby
Active
Active
VIL
VIH
VIH
X
VCC>VPF
Active
VSO<VCC<VPF
VCC<VSO<VPF
CMOS Standby
Data-Retention
Mode
X
X
X
Deselect
High-Z
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date
and time data in 24-hour format. Resetting the write bit to a zero then transfers those values to the actual
clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not
require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. The electrical environment also affects the clock accuracy, and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer
to Application Note 58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within 1.53 minutes per month (35 ppm) at +25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, refer to Application
Note 58.
5 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
DATA
ADDRESS
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
7FFFF
7FFFE
7FFFD
10 Year
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
X
X
X
X
X
10 Month
10 Date
7FFFC
7FFFB
7FFFA
7FFF9
BF
X
X
FT
X
X
X
X
Day
Day
Hour
Minutes
Seconds
01-07
00-23
00-59
00-59
10 Hour
Hour
10 Minutes
10 Seconds
Minutes
Seconds
Century
OSC
W
7FFF8
R
10 Century
Century
00-39
R = Read Bit
X = See Note
FT = Frequency Test
BF = Battery Flag
OSC = Stop Bit
W = Write Bit
NOTE: All indicated “X” bits are unused, but must be set to “0” during write cycles to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip-enable access (tCEA
)
or at output enable
access time (tOEA . The state of the data input/output pins (DQ) is controlled by CE and OE. If the
)
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output tWEZ after WE goes active.
6 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF
.
However, when VCC is below the power failing point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is
greater than VPF When VCC falls below the power fail point, VPF, access to the device is inhibited. At
.
this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns
to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF
.
If VPF is greater than Vso
,
the device power is switched from VCC to
the backup supply (VBAT) when VCC drops below VSO RTC operation and SRAM data are maintained
.
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down
when VCC is powered down.
BATTERY LONGEVITY
The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running
in the absence of VCC power. Each DS1747 is shipped from Dallas Semiconductor with its lithium
energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level
greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1747 will be much longer than 10 years since no lithium battery energy is
consumed when VCC is present.
BATTERY MONITOR
The DS1747 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7)
of the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
7 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………..-0.3V to +6.0V
Operating Temperature Range (Noncondensing)...………………………………………...0°C to +70°C (Commercial)
……………………………………………………..…………………………………………….-40°C to +85°C (Industrial)
Storage Temperature Range………………………………………………………………………………...-40°C to +85°C
Soldering Temperature (EDIP) (Leads, 10 seconds) (Note 7)……………………….………….………………..+260°C
Soldering Temperature (Note 7)………………….See IPC/JEDEC Standard J-STD-020 for Surface-Mount Devices
This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VCC
5V10%
VCC
3.3V10%
VCC
5V10%
VCC
3.3V10%
=
VCC
0.3V
VCC
0.3V
+
VIH
2.2
V
1
Logic 1 Voltage
All Inputs
=
+
VIH
VIL
VIL
2.0
-0.3
-0.3
V
V
V
1
1
1
=
+0.8
+0.6
Logic 0 Voltage
All Inputs
=
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
TTL Standby Current
Icc
85
mA
2, 3
Icc1
6
mA
mA
2, 3
2, 3
(CE = VIH)
CMOS Standby Current
Icc2
IIL
4
(CE VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
-1
-1
+1
+1
A
A
IOL
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOH
VOL
2.4
1
1
0.4
Write Protection Voltage
VPF
VSO
4.25
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
8 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Icc
30
mA
2, 3
Icc1
2
mA
mA
2, 3
2, 3
(CE = VIH)
CMOS Standby Current
Icc2
IIL
2
(CE VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
-1
-1
+1
+1
A
A
IOL
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH
2.4
1
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOL
VPF
0.4
1
1
Write Protection Voltage
2.80
2.97
V
V
VBAT
or
Battery Switchover Voltage
VSO
1, 4
VPF
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
TYP
MAX
UNITS
ns
NOTES
70
tAA
70
ns
Address Access Time
CE to DQ Low-Z
tCEL
5
5
5
ns
tCEA
tCEZ
70
25
ns
CE E Access Time
CE Data Off Time
OE to DQ Low-Z
OE Access Time
ns
tOEL
ns
tOEA
tOEZ
35
25
ns
ns
OE Data Off Time
Output Hold from Address
tOH
ns
9 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
TYP
MAX
UNITS
ns
NOTES
120
Address Access Time
tAA
120
ns
tCEL
5
5
5
ns
CE to DQ Low-Z
CE E Access Time
CE Data Off Time
OE to DQ Low-Z
OE Access Time
tCEA
tCEZ
120
40
ns
ns
tOEL
ns
tOEA
tOEZ
100
35
ns
ns
OE Data Off Time
Output Hold from Address
tOH
ns
READ CYCLE TIMING DIAGRAM
10 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
Write Cycle Time
SYMBOL
tWC
MIN
70
0
TYP
MAX
UNITS
ns
NOTES
Address Setup Time
tAS
ns
tWEW
tCEW
tDS
50
60
30
0
ns
WE Pulse Width
CE Pulse Width
Data Setup Time
Data Hold Time
Data Hold Time
Address Hold Time
Address Hold Time
ns
ns
tDH1
ns
8
9
8
9
tDH2
0
ns
tAH1
5
ns
tAH2
5
ns
tWEZ
tWR
25
ns
WE Data Off Time
Write Recovery Time
5
ns
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
Write Cycle Time
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
tWC
120
ns
Address Setup Time
tAS
tWEW
tCEW
tCEW
tDS
0
100
110
110
80
0
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width
CE Pulse Width
CE and CE2 Pulse Width
Data Setup Time
Data Hold Time
tDH1
tDH2
tAH1
tAH2
tWEZ
tWR
8
9
8
9
Data Hold Time
0
Address Hold Time
Address Hold Time
0
10
40
WE Data Off Time
Write Recovery Time
10
11 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
12 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or WE at VH
Before Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to
VPF(MIN)
tF
tFB
tR
300
10
0
s
s
s
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to
VPF(MAX)
Power-Up Recover Time
VPF to RST High (PowerCap
Only)
Expected Data-Retention Time
(Oscillator ON)
tREC
tDR
35
ms
10
years
5, 6
POWER-UP/DOWN TIMING (5V DEVICE)
13 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or WE at VH, Before
Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tF
300
0
s
s
tR
Power-Up Recover Time
tREC
tDR
35
ms
VPF to RST High (PowerCap
Only)
Expected Data-Retention Time
(Oscillator ON)
10
years
5, 6
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
14
UNITS
pF
NOTES
Capacitance on All Input Pins
Capacitance on All Output Pins
CO
10
pF
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF
5) Data-retention time is at +25C.
.
6) Each DS1747 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined for DIP modules and assembled PowerCap modules as accumulative time
in the absence of VCC starting from the time power is first applied by the user.
7) RTC encapsulated DIP (EDIP) modules can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85C. Post-solder cleaning with water-washing techniques
is acceptable, provided that ultra-sonic vibration is not used.
See the PowerCap package drawing on our website for details regarding the PowerCap package
(www.maxim-ic.com/packages).
8) tAH1, tDH1 are measured from WE going high.
9) tAH2, tDH2 are measured from CE going high.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
32 EDIP
PACKAGE CODE
MDT32+4
DOCUMENT NO.
21-0245
34 PWRCP
PC2+1
21-0246
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