DS1803Z-050/T&R [MAXIM]
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO16, 0.150 INCH, SOIC-16;
| 型号： | DS1803Z-050/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO16, 0.150 INCH, SOIC-16 光电二极管 |
| 文件： | 总15页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1803
Addressable Dual Digital Potentiometer
www.maxim-ic.com
FEATURES
3V or 5V Operation
PIN ASSIGNMENT
Ultra-Low Power Consumption
Two Digitally Controlled, 256-Position
Potentiometers
14-Pin TSSOP (173 mil) and 16-Pin SO (150
mil) Packaging Available for Surface-Mount
Applications
H1
L1
1
2
3
4
14
13
12
11
10
9
VCC
NC
W1
A2
H0
L0
A1
5
W0
SDA
SCL
A0
6
7
Addressable Using 3 Address Inputs
2-Wire Serial Interface
GND
8
Operating Temperature Range:
DS1803 14-PIN TSSOP (173 MIL)
-
Industrial: -40°C to +85°C
Standard Resistance Values:
-
-
-
DS1803-010
DS1803-050
DS1803-100
10kΩ
50kΩ
100kΩ
H1
NC
L1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
NC
H0
W1
A2
L0
W0
NC
PIN DESCRIPTION
A1
L0, L1
H0, H1
W0,W1
VCC
- Low End of Resistor
- High End of Resistor
- Wiper terminal of Resistor
- 3V/5V Power Supply Input
A0
SDA
SCL
GND
A0, A1, A2 - Chip Select Inputs
DS1803Z 16-PIN SO (150 MIL)
SDA
SCL
GND
NC
- Serial Data I/O
- Serial Clock Input
- Ground
DS1803 16-PIN DIP (300 MIL)
See Mech. Drawings Section on Website
- No Connection
DESCRIPTION
The DS1803 addressable dual digital potentiometer features two independently controlled 256-position
potentiometers. Device control is achieved through a 2-wire serial interface. Three address pins allow up
to 8 DS1803’s to share the same 2-wire interface. The exact wiper position of each potentiometer can be
written or read. The DS1803 is available in a 16-pin DIP, 16-pin SO, and 14-pin TSSOP package. The
device is available in three standard resistance values: 10kΩ, 50kΩ, and 100kΩ and is specified over the
industrial temperature range.
1 of 11
110706
DS1803
DEVICE OPERATION
The DS1803 is an addressable, digitally controlled device which has two 256-position potentiometers. A
functional block diagram of the part is shown in Figure 1. Communication and control of the device is
accomplished via a 2-wire serial interface. Address inputs A0, A1, and A2 allow up to 8 DS1803s to
share the same 2-wire interface.
Each potentiometer is composed of a 256 position resistor array. Two 8-bit registers, each assigned to a
respective potentiometer, are used to set the wiper position on the resistor array. The wiper terminal is
multiplexed to one of 256 positions on the resistor array based on its corresponding 8-bit register value.
For example, the high-end terminals, H0 and H1, have wiper position values FFh while the low-end
terminals, L0 and L1, have wiper position values 00h.
The DS1803 is a volatile device that does not maintain the position of the wiper during power-down or
loss of power. On power-up, the DS1803 wipers’ position will be set to position 00h - the low-end
terminals. The user may then set the wiper value to a desired position.
Communication with the DS1803 takes place over the 2-wire serial interface consisting of the bi-
directional pin, SDA, and the serial clock input, SCL. Complete details of the 2-wire interface are
discussed in the section entitled “2-wire Serial Data Bus.”
Application Considerations
The DS1803 is offered in three standard resistor values, which include 10kΩ, 50kΩ, and 100kΩ. The
resolution of the potentiometer is defined as RTOT/255, where RTOT is the total resistor value of the
potentiometer. The DS1803 is designed to operate using 3V or 5V power supplies over the industrial
(-40°C to +85°C) temperature range. Maximum input signal levels across the potentiometer cannot
exceed the operating power supply of the device.
2-WIRE SERIAL DATA BUS
The DS1803 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data
on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master”. The devices that are controlled by the master are “slaves”. The bus must
be controlled by a master device which generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1803 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 2).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
2 of 11
DS1803
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/ W * bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1. Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the
master is the control byte (slave address). Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver: The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1803 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1803 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
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DS1803
SLAVE ADDRESS
The control byte is the first byte received following the START condition from the master device. The
control byte consists of a four bit control code; for the DS1803, this is 0101 binary. The next three bits of
the control byte are the device select bits (A2, A1, A0). They are used by the master device to select
which of the devices on the bus are to be accessed. The last bit of the control byte (R/ W *) defines the
operation to be performed. When set to a one a read operation is selected, and when set to a zero a write
operation is selected. Figure 3 shows the control byte for the DS1803.
Following the START condition, the DS1803 monitors the SDA bus for the control byte being
transmitted. Upon receiving a matching control byte, the DS1803 outputs an acknowledge signal on the
SDA line.
COMMAND AND PROTOCOL
The command and protocol structure of the DS1803 allows the user to read or write the potentiometer(s).
The command structures for the part are presented in Figures 4 and 5. Data is transmitted most significant
bit (MSB) first. During communication, the receiving unit always generates the acknowledge.
Reading the DS1803
As shown in Figure 4, the DS1803 provides one read command operation. This operation allows the user
to read both potentiometers. Specifically, the R/ W bit of the control byte is set equal to a 1 for a read
operation. Communication to read the DS1803 begins with a START condition which is issued by the
master device. The control byte from the master device will follow the START condition. Once the
control byte has been received by the DS1803, the part will respond with an ACKNOWLEDGE. The
R/ W bit of the control byte as stated should be set equal to ‘1’ for reading the DS1803.
When the master has received the ACKNOWLEDGE from the DS1803, the master can then begin to
receive potentiometer wiper data. The value of the potentiometer-0 wiper position will be the first
returned from the DS1803. Once the eight bits of the potentiometer-0 wiper position has been transmitted,
the master will need to issue an ACKNOWLEDGE, unless it is the only byte to be read, in which case the
master issues a NOT ACKNOWLEDGE. If desired the master may stop the communication transfer at
this point by issuing the STOP condition. However, if the value of the potentiometer-1 wiper position
value is needed, communication transfer can continue by clocking the remaining eight bits of the
potentiometer-1 value, followed by an NOT ACKNOWLEDGE. Final communication transfer is
terminated by issuing the STOP command.
Writing the DS1803
A data flow diagram for writing the DS1803 is shown in Figure 5. The DS1803 has three write
commands. These include write pot-0, write pot-1, and write pot-0/1. The write pot-0 command allows
the user to write the value of potentiometer-0 and as an option the value of potentiometer-1. The write-1
command allows the user to write the value of potentiometer-1 only. The last write command, write-0/1,
allows the user to write both potentiometers to the same value with one command and one data value
being issued.
All the write operations begin with a START condition. Following the START condition, the master
device will issue the control byte. The read/write bit of the control byte will be set to ‘0’ for writing the
DS1803. Once the control byte has been issued and the master receives the acknowledgment from the
DS1803, the command byte is transmitted to the DS1803. As mentioned above, there exist three write
4 of 11
DS1803
operations that can be used with the DS1803. The binary value of each write command is shown in Figure
5 and also in the Table 1.
2-WIRE COMMAND WORDS Table 1
COMMAND
COMMAND VALUE
101010 01
Write Potentiometer-0
Write Potentiometer-1
Write Both Potentiometers
101010 10
101011 11
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DS1803
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
-40° to +85°C; industrial
-55°C to +125°C
Storage Temperature
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(-40°C to +85°C)
PARAMETER
Supply Voltage
Resistors Inputs
SYMBOL
MIN
TYP
MAX
5.5
UNITS NOTES
VCC
+2.7
V
V
1
1
L,H,W
GND-0.5
VCC+0.5
DC ELECTRICAL CONDITIONS
(-40°C to +85°C; VCC=2.7V to 5.5V)
PARAMETER
Supply Current (Active)
Input Leakage
SYMBOL CONDITION
MIN
TYP MAX UNITS NOTES
ICC
ILI
200
+1
μA
μA
ohms
mA
V
3
-1
Wiper Resistance
Wiper Current
RW
IW
400
1000
1
Input Logic 1
VIH
VIL
0.7VCC
-0.5
VCC+0.5
0.3VCC
2
2
Input Logic 0
V
Input Logic Levels A0, A1,
A2
Input Logic 1
Input Logic 0
0.7VCC
-0.5
VCC+0.5
0.3VCC
V
12
Input Current each I/O Pin
Standby Current
0.4<VI/O<0.9VCC
-10
+10
40
μA
μA
V
ISTBY
VOL1
20
4
Low Level Output Voltage
3 mA sink
current
0.0
0.0
0.4
VOL2
6 mA sink
current
0.6
V
I/O Capacitance
CI/0
tSP
10
50
pF
ns
Pulse Width of Spikes
which must be suppressed
by the input filter
Fast Mode
0
6 of 11
DS1803
ANALOG RESISTOR CHARACTERISTICS
(-40°C to +85°C;VCC=2.7V to 5.5V)
PARAMETER
End-to-End Resistor Tolerance
Absolute Linearity
SYMBOL MIN
TYP
MAX
UNITS NOTES
-20
+20
%
17
13
14
11
LSB
±0.75
±0.3
LSB
Relative Linearity
-3 dB Cutoff Frequency
Temperature Coefficient
fCUTOFF
Hz
ppm/°C
pF
750
Capacitance
CI
5
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C;VCC=2.7V to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
0
0
400
100
15
SCL Clock Frequency
fSCL
kHz
16
Bus Free Time Between
STOP and START Condition
Hold Time (Repeated)
START Condition
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
15
16
tBUF
tHD:STA
tLOW
μs
μs
μs
μs
μs
ns
ns
ns
5
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
tHIGH
tHD :DAT
tSU :DAT
tR
0.9
6,7
8
0
100
250
Data Setup Time
Rise Time of both SDA and
SCL Signals
Fall Time of both SDA and
SCL Signals
300
1000
300
20+1CB
20+1CB
9
tF
9
300
Setup Time for STOP
Condition
0.6
4.0
tSU:STO
CB
µs
pF
Capacitive Load for each Bus
Line
400
9
NOTES:
1. All voltages are referenced to ground. Currents flowing into device pins are positive. Currents out of
the device pins are negative.
2. I/O pins of fast mode devices will not obstruct SDA and SCL even if VCC is switched off.
3. ICC specified with SDA pin open, SCL = 400 kHz clock rate.
4. ISTBY specified with VCC at 5.0V and SDA, SCL = 5.0V.
7 of 11
DS1803
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX+ tSU:DAT = 1000 + 250=1250 ns before the SCL line is released.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
10. Typical values are for tA = 25°C and nominal supply voltage.
11. -3 dB cutoff frequency characteristics for the DS1803 depend on potentiometer total resistance:
DS1803-010; 1 MHz, DS1803-50; 200 kHz, DS1803-100; 100 kHz.
12. Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
13. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits are ±1.6 LSB.
14. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
15. Fast mode.
16. Standard mode.
17. Valid at 25°C only.
8 of 11
DS1803
DS1803 BLOCK DIAGRAM Figure 1
2–WIRE DATA TRANSFER OVERVIEW Figure 2
9 of 11
DS1803
CONTROL BYTE Figure 3
2–WIRE READ PROTOCOL Figure 4
2–WIRE WRITE PROTOCOL Figure 5
Write Pot-0
10 of 11
DS1803
TIMING DIAGRAM Figure 6
DS1803 ORDERING INFORMATION
ORDERING
PACKAGE
NUMBER
OPERATING
TEMPERATURE
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
VERSION
DS18030-010
DS18030-050
DS18030-100
DS1803E-010
DS1803E-050
DS1803E-100
DS1803Z-010
DS1803Z-050
DS1803Z-100
DS1803E-010+
DS1803E-50+
DS1803E-100+
16L DIP
16L DIP
16L DIP
14L TSSOP (173 MIL)
14L TSSOP (173 MIL)
14L TSSOP (173 MIL)
16L SOIC (150 MIL)
16L SOIC (150 MIL)
16L SOIC (150 MIL)
14L TSSOP (173 MIL) LEAD FREE
14L TSSOP (173 MIL) LEAD FREE
14L TSSOP (173 MIL) LEAD FREE
14L TSSOP (173 MIL) LEAD FREE
T&R
10 kΩ
50 kΩ
100 kΩ
10 kΩ
50 kΩ
100 kΩ
10 kΩ
50 kΩ
100 kΩ
10 kΩ
50 kΩ
100 kΩ
DS1803E-010+T&R
DS1803E-50+T&R
-40°C TO +85°C
-40°C TO +85°C
10 kΩ
50 kΩ
14L TSSOP (173 MIL) LEAD FREE
T&R
DS1803Z-010+
DS1803Z-050+
DS1803Z-100+
16L SOIC (150 MIL) LEAD FREE
16L SOIC (150 MIL) LEAD FREE
16L SOIC (150 MIL) LEAD FREE
16L SOIC (150 MIL) LEAD FREE
T&R
16L SOIC (150 MIL) LEAD FREE
T&R
16L SOIC (150 MIL) LEAD FREE
T&R
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
10 kΩ
50 kΩ
100 kΩ
DS1803Z-010+T&R
DS1803Z-050+T&R
DS1803Z-100+T&R
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
10 kΩ
50 kΩ
100 kΩ
DS1803-100+T&R
DS1803E-10/T&R
DS1803E-50/T&R
DS1803E-100/T&R
DS1803Z-010/T&R
DS1803Z-050/T&R
DS1803Z-100/T&R
16L DIP T&R
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
100 kΩ
10 kΩ
50 kΩ
100 kΩ
10 kΩ
50 kΩ
100 kΩ
14L TSSOP (173 MIL) T&R
14L TSSOP (173 MIL) T&R
14L TSSOP (173 MIL) T&R
16L SOIC (150 MIL) T&R
16L SOIC (150 MIL) T&R
16L SOIC (150 MIL) T&R
11 of 11
EN GL ISH • ? ? ? ? • ? ? ? • ? ? ?
C OM PA N Y M EM B ER S
WH AT ' S N EW PR ODUCTS SO LU TI ONS D E SI G N
AP P NOT ES SUPP ORT
BU Y
DS 1 80 3
Pa r t Nu mb e r T ab l e
N o te s:
1 . S ee t he DS1 803 Q uic kVie w D at a Sh ee t f or f urt her inf orm ati on o n th is p rodu ct f ami l y or d ow n lo a d th e DS180 3 ful l data s heet
( PD F, 304kB) .
2. O th er o p ti on s a n d l in ks fo r p urch asi ng p arts a re l is te d at : h t tp : / /w w w. m a xi m -i c . co m /s al es .
3 . Did n' t F ind W ha t You Ne ed ? As k o u r ap p l ic at i o n s e n gi n ee r s . E x p er t as s is t a nc e i n fi ndi ng pa r ts , us ua lly wi th in one bus iness day.
4. Pa r t n u mb e r suf f ix e s: T o r T &R = ta p e a n d r e e l; + = Ro HS/le ad - fr e e ; # = Ro H S/lea d - e xe m p t. Mo r e : S e e fu ll da t a sh e et o r Par t
Nam ing Conve nti ons .
5 . * S ome p ackages hav e variations, listed on the drawing. " PkgCode/Variation" tells w hi ch vari at i on th e pro d uct u se s.
P ar t Num ber
N ot es
F r ee
Sa mp le
B uy
D i re c t
T em p
R oHS/L ead- Fr ee?
Ma t e ri a l s A n a ly s is
P a c ka g e : TY PE P INS S IZE
D R A WI N G C O D E / VA R *
D S 1 8 0 3 0 - 0 1 0
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 8 0 3 0 - 0 5 0
D S 1 8 0 3 0 - 1 0 0
D S 1 8 0 3 0 - 1 0 0 +
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
Use pkgcode/v ariation : P16+ 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S 1 8 0 3 0 - 0 5 0 +
D S 1 8 0 3 0 - 0 1 0 +
D S1 80 3Z -0 10 /C 0 3
D S1 80 3 Z- 0 10 +
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
Use pkgcode/v ariation : P16+ 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
P DIP ; 16 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 2 A (P D F )
Use pkgcode/v ariation : P16+ 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
1 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
DS 18 03Z -10 0+ T &R 100k ohm s
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S1 8 03 Z - 0 5 0+
5 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
DS 18 03Z -05 0+ T &R 5 0k o h ms
DS 18 03Z -01 0+ T &R 1 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S1 8 03 Z - 1 0 0+
D S1 8 0 3 Z - 1 0 0
D S1 8 0 3 Z - 0 5 0
100k ohm s
100k ohm s
5 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S16+ 2 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1 8 0 3 Z - 0 1 0
1 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1 80 3Z -10 0/ T& R 100k ohm s
D S1 80 3Z -05 0/ T& R 5 0k o h ms
D S1 80 3Z -01 0/ T& R 1 0k o h ms
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 6 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 6- 1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1803E- 010
1 0k o h ms
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1803E - 5 0+ T& R
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 1*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
DS 18 03E -10 0+ T &R 100k ohm s
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 1*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S1 8 0 3 E - 1 0 0
D S1 8 0 3 E - 0 5 0
D S1 8 03 E - 1 0 0+
D S1 8 03 E - 0 5 0+
100k ohm s
5 0k o h ms
100k ohm s
5 0k o h ms
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 1*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 1*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S18 03 E-5 0/ T&R
D S1 8 03 E - 0 1 0+
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
1 0k o h ms
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 2*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S18 03 E-1 0/ T&R
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1 80 3E -10 0/ T& R 100k ohm s
DS 18 03E -01 0+ T &R 1 0k o h ms
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
U se p kg co de /v ar ia ti on : U14 -1 *
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
TSSOP ;14 pin;173
Dwg : 5 6 - G 2 0 1 5 - 0 0 0 B (P D F )
Use pkgc ode / va r ia tion: U14+ 2*
- 4 0 C t o + 8 5 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
Di dn ' t F ind W ha t You Ne e d ?
CO NT ACT U S: SE ND US AN EMAI L
Co p y rig h t 2 00 7 b y M a x im I n te g r a te d Pr o d u c ts , D a lla s S em i co n d u c to r • Le ga l N ot i ce s • P ri va c y P o l ic y
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