DS1806S-050+T&R [MAXIM]

Digital Potentiometer, 50000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO20, 0.300 INCH, SO-20;
DS1806S-050+T&R
型号: DS1806S-050+T&R
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Digital Potentiometer, 50000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO20, 0.300 INCH, SO-20

光电二极管 转换器
文件: 总8页 (文件大小:280K)
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DS1806  
Digital Sextet Potentiometer  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
§ Six digitally controlled 64-position  
potentiometers  
§ 3-wire serial port provides for reading and  
setting each potentiometer  
§ Devices can be cascaded for single processor  
multi-device control  
§ Standard resistance values:  
W1  
W2  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
H1  
2
L1-3  
W3  
3
H2  
4
H3  
W4  
5
H4  
L4-6  
W6  
6
H5  
-
-
-
DS1806-010  
DS1806-050  
DS1806-100  
10 kW  
50 kW  
100 kW  
7
W5  
H6  
RST  
CLK  
GND  
8
9
DIN  
COUT  
§ Operating Temperature Range:  
10  
-
Industrial temperature: -40°C to +85°C  
DS1806 20-Pin DIP (300-mil)  
DS1806S 20-Pin SOIC (300-mil)  
DS1806E 20-Pin TSSOP (173-mil)  
See Mech. Drawings Section  
PIN DESCIPTION  
VCC  
- 3V or 5V Supply  
RST  
DIN  
- Serial Port Reset Input  
- Serial Port Data Input  
- Serial Port Clock Input  
- Cascade Data Output  
- High End terminal of Pot  
- Wiper Terminal of Pot  
- Ground  
CLK  
COUT  
H1 - H6  
W1 - W6  
GND  
L1-3  
- Low Terminal Pots 1 through 3  
- Low Terminal Pots 4 through 6  
L4-6  
DESCRIPTION  
The DS1806 Digital Sextet Potentiometer is a six-channel, digitally controlled, solid-state linear  
potentiometer. Each potentiometer is comprised of 63 equiresistive sections as illustrated in the block  
diagram of Figure 1. Each potentiometer has three terminals accessible to the user. These include the high  
side terminals, HX, the wiper terminals, WX, and the low-end terminals, L1-3 and L4-6. Potentiometers 1  
through 3 share the same low-end terminal L1-3; likewise, potentiometers 4 through 6 share the low-end  
terminal L4-6.  
Each wiper’s position is selected via an 8-bit register value. Communication and control of the device is  
accomplished via a 3-wire serial port interface. This interface in conjunction with a cascade output allows  
the value of the device wiper settings to be read.  
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For multiple device and single processor environments, the DS1806 can be cascaded or daisy-chained.  
This feature allows a single processor to control multiple devices.  
The DS1806 is available in 10, 50 and 100-kohm versions and is specified over the industrial temperature  
range. Packages for the device include 20-lead DIPs, SOICs, and TSSOPs.  
OPERATION  
A block diagram of the device is provided in Figure 1. As shown, the DS1806 contains six 64-position  
potentiometers whose wiper positions are set by an 8-bit value. The DS1806 contains a 48-bit I/O shift  
register which is used to store the respective wiper position data for each of the six potentiometers.  
Each potentiometer has three terminals accessible to the user. These include the high side terminals, HX,  
the wiper terminals, WX, and the low-end terminals, L1-3 and L4-6. Potentiometers 1 through 3 share the  
same low-end terminal L1-3. And likewise, potentiometers 4 through 6 share the low-end terminal L4-6.  
Control of the DS1806 is accomplished via a 3-wire serial communication interface which allows the user  
to set the wiper position value for each potentiometer. The 3-wire serial interface consists of the control  
signals RST , DIN, and CLK. On power-up, the wiper positions of each potentiometer are set to the low-  
end terminal LX (00000000).  
The RST control signal is used to enable 3-wire serial port operation. The RST signal (3-wire serial port)  
is active when in a high state. Any communication intended to change wiper settings must begin with the  
transition of the RST from the low state to the high state.  
The CLK signal input is used to provide timing synchronization for data input and output. Wiper position  
data is loaded into the DS1806 through the DIN input terminal. This data is shifted one bit at a time into  
the 48-bit I/O shift register of the part, LSB first. Figure 3 provides an illustration of the 48-bit shift  
register.  
Figure 4 provides 3-wire serial port protocol and timing diagrams. As shown, the 3-wire port is inactive  
when the RST signal input is low. Once RST has transitioned from the low to the high state, the serial  
port becomes active. When active, data is loaded into the I/O shift register on the low-to-high transition of  
the CLK.  
Data is transmitted in order of LSB first. Potentiometers are designated from 1 through 6 and the value  
for potentiometer-1 will be the first data entered into the shift register, followed by that of potentiometer-  
2 and so forth.  
Each wiper has an 8-bit register which is used for setting the position of the wiper on the resistor array.  
Because the DS1806 is a 64-position potentiometer, only six bits of information are needed to set wiper  
position. The remaining two bits of information are used to provide a “don’t change” feature. Wiper  
position is controlled by bit positions 0 through 5 of each register. The “don’t change” feature is  
controlled by bits 6 and 7 of each register. When bits 6 and 7 have value “11 xxxxxx,” wiper position will  
not change regardless of the states of bits 0 through 5. If bits 6 and 7 are set to any other value, bits 0  
through 5 will be used as the new wiper position. The “don’t change” feature allows the user to change  
the value of any potentiometer of the DS1806 without affecting or having to remember the remaining  
positions of the potentiometer wipers. Figure 2 provides the format for a wiper’s register.  
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Wiper placement for each potentiometer is such that position-63 corresponds to the HX terminal of the de-  
vice while position-0 corresponds to the ground terminal. For example, to set a potentiometer’s wiper  
position to 15 (decimal), the binary value shifted into the wiper register should be 00001111. This will  
place the wiper tap at the 15th step above the low-end terminal, LX.  
All communication transactions should provide the total 48 bits of information when writing or reading  
from the part. This is especially true for applications using all six potentiometers. If a complete set of 48  
bits is not transmitted to the part, undesired wiper position settings may occur.  
DS1806 BLOCK DIAGRAM Figure 1  
WIPER REGISTER CONFIGURATION Figure 2  
48-BIT I/O SHIFT REGISTER Figure 3  
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3-WIRE SERIAL PORT TIMING Figure 4  
CASCADE OPERATION  
A feature of the DS1806 is the ability to control multiple devices from a single processor. Multiple  
DS1806s can be linked or daisy chained as shown in Figure 5. As a data bit is entered into the I/O shift  
register of the DS1806, a bit will appear at the COUT terminal before a maximum delay of 50 nanoseconds.  
The LSB of potentiometer-1 will always be the first out of the part at the beginning of a transaction.  
Additionally, the COUT terminal is always active regardless of the state RST . However, DIN and CLK  
inputs are ignored when RST is in the low state.  
The COUT output of the DS1806 can be used to drive the DIN input of another DS1806. When cascading  
multiple devices, the total number of bits transmitted is always 48 multiplied by the total number of  
DS1806s being cascaded.  
An optional feedback resistor can be placed between the COUT terminal of the last device and the first  
DS1806 DIN input, which allows the controlling processor to read as well as write data or circularly clock  
data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1  
kW to 10 kW.  
To read data, the reading device configures itself as an input and monitors the state of the DIN line, which  
is driven by COUT through the isolation resistor. When RST is driven high, bit 48 is present on the COUT  
pin, which is fed back to the input DIN pin through the isolation resistor. When the CLK input transitions  
low to high, bit 48 is loaded into the first position of the I/O shift register and bit 47 becomes present on  
COUT and DIN of the next device. After 48 bits (or 48 times the number of the DS1806s in the daisy  
chain), the data has shifted completely around and back to its original position. When RST transitions to  
the low state to end data transfer, the value (the same as before the read occurred) is loaded in the shift  
register.  
ABSOLUTE AND RELATIVE LINEARITY  
Absolute linearity is defined as the difference between the actual measured output voltage and the  
expected output voltage. Absolute linearity is given in terms of a minimum increment or expected output  
when the wiper is moved one position. The DS1806 is specified to have an absolute linearity of ±0.50  
LSB.  
Relative linearity is a measure of error between two adjacent wiper position points. The DS1806 is  
specified to have a relative linearity of ±0.25 LSB.  
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TYPICAL APPLICATION CONFIGURATIONS  
Figure 6 shows the typical application configuration of the DS1806 as a fixed gain attenuator. In this  
configuration, the DS1806 adjusts the attenuation level of the incoming signal. Variations in wiper  
resistance are minimized by connecting the wiper terminal of the part to a high impedance load.  
Depending on voltage across the wiper, its resistance may vary from 400 ohms to 1000 ohms. Note that  
the resistance R1 in Figure 6 should be chosen to be much greater than the wiper resistance RW .  
CASCADING MULTIPLE DEVICES Figure 5  
FIXED GAIN ATTENUATOR Figure 6  
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ABSOLUTE MAXIMUM RATINGS*  
Voltage on Any Pin Relative to Ground  
Operating Temperature  
-0.5V to +7.0V  
-40°C to +85°C; industrial  
-55°C to +125°C  
Storage Temperature  
Soldering Temperature  
260°C for 10 seconds  
* This is a stress rating only and functional operation of the device at these or any other conditions above  
those indicated in the operation sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods of time may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
(-40°C to +85°C)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS NOTES  
Supply Voltage  
VCC  
+2.7  
5.5  
V
1
DC ELECTRICAL CONDITIONS  
(-40°C to +85°C; VCC=2.7 to 5.5V)  
PARAMETER  
Supply Current Active  
Input Leakage  
SYMBOL  
MIN  
TYP  
MAX  
UNITS NOTES  
ICC  
IIL  
1.3  
2
mA  
µA  
W
-1  
+1  
Wiper Resistance  
Wiper Current  
RW  
IW  
400  
1000  
1
mA  
Input Logic 1  
VIH  
VIL  
2.0  
VCC+0.5  
+0.8  
+0.6  
V
V
1
Input Logic 0  
-0.5  
1,6  
Logic 1 Output @ 2.4 volts  
Logic 0 Output @ 0.4 Volts  
IOH  
IOL  
-1  
mA  
mA  
µA  
µA  
µA  
4
6
9
Standby Current  
3 Volts  
5 Volts  
ISTBY  
12  
20  
40  
Resistor Inputs  
HX, LX, WX GND-0.5  
VCC+0.5  
2
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ANALOG RESISTOR CHARACTERISTICS  
(-40°C to +85°C;VCC=2.7 to 5.5V)  
PARAMETER  
End-to-End Resistor Tolerance  
Absolute Linearity  
SYMBOL MIN  
TYP  
MAX  
UNITS NOTES  
-20  
+20  
%
10  
7
-0.5  
+0.5  
LSB  
-0.25  
LSB  
Relative Linearity  
+0.25  
8
-3 dB Cutoff Frequency  
Temperature Coefficient  
ICUTOFF  
Hz  
4
750  
ppm/°C  
CAPACITANCE  
(tA =25°C)  
PARAMETER  
SYMBOL  
CIN  
MIN  
TYP  
MAX  
UNITS NOTES  
Input Capacitance  
Output Capacitance  
5
7
pF  
pF  
3
3
COUT  
AC ELECTRICAL CHARACTERISTICS  
(-40°C to +85°C;VCC=2.7 to 5.5V)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS NOTES  
Clock Frequency  
Width of CLK Pulse  
Data Setup Time  
Data Hold Time  
fCLK  
tCH  
DC  
50  
30  
0
10  
MHz  
ns  
5
5
5
5
5
tDC  
ns  
tCDH  
tPLH  
ns  
Propagation Delay Time Low  
to High Level Clock to  
Output  
50  
ns  
tCC  
50  
50  
ns  
ns  
5
5
RST High to Clock Input  
High  
tHLT  
RST Low to Clock Input  
High  
tRLT  
tCR  
125  
ns  
ns  
5
5
RST Inactive  
CLK Rise Time, CLK Fall  
Time  
50  
NOTES:  
1. All voltages are referenced to ground.  
2. Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by 0.5 volts in the positive  
direction.  
3. Capacitance values apply at 25°C.  
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4. -3 dB cutoff frequency characteristics for the DS1806 depend on potentiometer total resistance:  
DS1806-010; 1 MHz; DS1806-050; 200 kHz, DS1806-100; 100 kHz.  
5. See Figure 4.  
6. For VCC = 5V ± 10% maximum VIL = +0.8V. For VCC = 3.0 ± 10% VIL= +0.6V.  
7. Absolute linearity is to used measure expected wiper voltage versus measured wiper voltage as  
determined by wiper position. The DS1806 is specified to provide an absolute linearity of +0.5 LSB.  
8. Relative linearity is used to determine the change in wiper voltage between two adjacent wiper  
positions. The DS1806 is specified to provide a relative linearity of +0.25 LSB.  
9. Standby current levels apply when all inputs are driven to appropriate supply levels.  
10. Valid at 25°C only.  
DS1806 ORDERING INFORMATION  
ORDERING  
NUMBER  
OPERATING  
TEMPERATURE  
PACKAGE  
VERSION  
DS1806-010  
20L DIP  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
-40°C TO +85°C  
10 kW  
50 kW  
DS1806-050  
DS1806-100  
DS1806E-010  
DS1806E-050  
DS1806E-100  
DS1806S-010  
DS1806S-050  
DS1806S-100  
20L DIP  
20L DIP  
100 kW  
10 kW  
50 kW  
20L TSSOP (173-mil)  
20L TSSOP (173-mil)  
20L TSSOP (173-mil)  
20L SOIC (300-mil)  
20L SOIC (300-mil)  
20L SOIC (300-mil)  
100 kW  
10 kW  
50 kW  
100 kW  
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