DS1843D+ [MAXIM]
Fast Sample-and-Hold Circuit; 快速采样和保持电路
| 型号： | DS1843D+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Fast Sample-and-Hold Circuit |
| 文件： | 总8页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4539; Rev 0; 5/09
Fast Sample-and-Hold Circuit
DS1843
General Description
Features
The DS1843 is a sample-and-hold circuit useful for cap-
turing fast signals where board space is constrained. It
includes a differential, high-speed switched capacitor
input sample stage, offset nulling circuitry, and an out-
put buffer. The DS1843 is optimized for use in optical
line transmission (OLT) systems for burst-mode RSSI
measurement in conjunction with an external sense
resistor.
♦ Fast Sample Time < 300ns
♦ Hold Time > 100µs
♦ Low Input Offset
♦ Buffered Output
♦ Small, 8-Pin µDFN (2mm x 2mm) Pb-Free Package
Applications
Gigabit Passive Optical Network (GPON) OLT
Gigabit Ethernet Passive Optical Network (GEPON) OLT
GPON Optical Network Unit
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 μDFN
DS1843D+
DS1843D+TRL
8 μDFN
Sample and Hold
+Denotes a lead(Pb)-free/RoHS-compliant package.
TRL = Tape and reel.
Typical Operating Circuit
SDA
2
I C
DS1842/
MAX4007
SCL
INTERFACE
MAIN MEMORY
EEPROM/SRAM
V
CC
3.3V
A/D CONFIG/RESULTS,
SYSTEM STATUS BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
MON1
BMD
V
V
CC
DS1843
INP
V
OUTP
MON3P
USER MEMORY
MON3N
MON4
C
C
IN
C
C
S
V
OUTN
MOD
DAC
R
IN
12-BIT
ADC
S
IN
TEMP
BIAS
DAC
SENSOR
V
INN
3.3V
SEN
DEN
SEN
STROBE
CONTROL
LOGIC
STROBE
GND
CONTROLLER
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Fast Sample-and-Hold Circuit
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V .............................................-0.5V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature..............................................Refer to the
IPC/JEDEC J-STD-020 Specification.
CC
Voltage Range on V
, V
,
OUTP OUTN
V , V , SEN, DEN............................-0.5V to (V
INP INN
+ 0.5V)*
CC
*Subject to not exceeding +6V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS1843
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
(Note 1)
+2.97
+5.5
V
DC ELECTRICAL CHARACTERISTICS
(V = +2.97V to +5.5V, T = -40°C to +85°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mA
Supply Current
I
(Note 1)
All pins (Note 2)
and V (Note 2)
5.7
9
7
CC
Input Capacitance
Sample Capacitance
C
pF
IN
C
V
5
pF
S
INN
INP
0.3 x
Logic-Input Low
Logic-Input High
V
SEN and DEN inputs
SEN and DEN inputs
V
V
IL
V
CC
0.7 x
V
IH
V
CC
Input Leakage
Input Voltage
I
V
V
V
or V
SEN = 0
INP,
1
μA
V
IN
INN
V
= V
- V
INN
0
0
1.0
1.0
IN
IN
INP
= V
- V
; 100kꢀ load on
OUTN
OUT
OUTP
Output Voltage
V
V
OUT
each output pin
Output Impedance
R
V
(Note 2)
1
1.3
50
6.1
1
kꢀ
pF
OUTMAX
Output Capacitive Load
C
Capacitance for stable operation
= 2.9V, 1μs sample time, V = 6mV
OUT
V
CC
3.6
3.4
mV
Total Input Referenced Voltage
Offset: Differential
IN
OS-DIFF
Voltco (V = 2.9V to 5.5V)
mV/V
mV
CC
V
CC
= 2.9V, 1μs sample time, V = 6mV
8
Total Input Referenced Voltage
Offset: Single-Ended
IN
V
OS-SE
Voltco (V = 2.9V to 5.5V)
1
mV/V
CC
2
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit
DS1843
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.97V to +5.5V, T = -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram.)
A
PARAMETER
SYMBOL
CONDITIONS
is within 1%
MIN
300
260
10
TYP
MAX
UNITS
ns
V
V
OUT
OUT
Sample Time Minimum (Note 3)
Delay Time Minimum
Output Time
t
S
is within 35%
t
(Note 4)
ns
DEL
Delay from SEN falling edge until valid
t
2
μs
OUT
output at V
OUT to 1% accuracy
Hold Time
t
(Note 5)
t
100
2
μs
HOLD
OUT
1V step, DEN = high
Output Step Recovery Time
(Note 6)
t
μs
REC
3V step, DEN = high or low
3.5
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Guaranteed by design.
Note 3: V
at the end of the 10μs hold time is within specified % of V during the sample window; a 2.5kΩ resistor connected in
OUT
IN
series to both V
and V
(V
- V
= 1V). External capacitance to ground for both V
and V
is approximately 10pF.
INP
INN INP
INN
INP
INN
Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
must be low for a short period of time, t , before the input changes.
DEL
Note 5: V
at the end of the hold time is within 1% of V during the sample window (V
- V
= 1V).
OUT
IN
INP
INN
Note 6: Voltage step applied across V
to V
through a 5pF capacitor connected to each pin. This models the load presented
OUTP
OUTN
by an ADC while it is sampling the DS1843’s output. See the Output Buffer section. Settled within 1% of initial voltage.
Timing Diagram
V
INP
- V
INN
t
S
t
DEL
SEN
t
t
HOLD
OUT
VOLTAGE INVALID
V
OUTP
- V
OUTN
t
REC
t
ADC:ST
t
ADC:CT
EXTERNAL
ADC DATA
DATA VALID
t
t
= EXTERNAL ADC SAMPLING TIME.
= EXTERNAL ADC CONVERSION TIME.
ADC:ST
ADC:CT
DEN IS CONNECTED TO V FOR DIFFERENTIAL OUTPUT.
CC
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
_______________________________________________________________________________________
3
Fast Sample-and-Hold Circuit
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
I
vs. V
CC
I
CC
vs. TEMPERATURE
I
vs. TEMPERATURE
CC
CC
5.9
5.8
5.7
5.6
5.5
5.4
5.3
6.5
6.3
6.1
5.9
5.7
5.5
5.3
6.5
6.3
6.1
5.9
5.7
5.5
5.3
DEN = V
DEN = GND
CC
DS1843
V
= 5V
DEN = GND
DEN = V
CC
V
= 5V
CC
V
= 3.3V
CC
CC
V
= 3.3V
CC
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
DIFFERENTIAL OUTPUT DURING SAMPLING
(V = 6mV)
OUTPUT HOLD TIME vs. TEMPERATURE
OUTPUT HOLD TIME vs. TEMPERATURE
INP
DS1843 toc06
1000
100
10
1000
100
10
100mV/div
V
OUTP
V
OUTN
1.5V/div
V
SEN
DEN = GND
DEN = V
CC
V
- V
OUTN
OUTP
5mV/div
1
1
-40
-15
10
35
60
85
-40
-15
10
35
60
85
500ns/div
TEMPERATURE (°C)
TEMPERATURE (°C)
SINGLE-ENDED OUTPUT DURING SAMPLING
(V = 6mV)
DIFFERENTIAL OUTPUT, TRANSIENT
SINGLE-ENDED OUTPUT, TRANSIENT
WITH 10% V STEP (V = 6mV)
WITH 10% V STEP (V = 6mV)
INP
CC
INP
CC
INP
DS1843 toc07
DS1843 toc08
DS1843 toc09
V
SEN
100mV/div
V
OUTN
V
OUTP
V
SEN
V
V
V
= 3.3V
2.0V/div
CC
SEN
CC
V
V
= 3.3V
1.5V/div
V
OUTP
1V/div
= 3.0V
100mV/div
ZOOMED
500ns/div
CC
V
ZOOM
OUTP
= 3.0V
CC
V
- V
OUTN
OUTP
2mV/div
5mV/div
100mV/div
V
OUTP
20ns/div
100μs/div
100μs/div
4
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit
DS1843
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DIFFERENTIAL OUTPUT, TRANSIENT
SINGLE-ENDED OUTPUT, TRANSIENT
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (V = 6mV)
WITH 10% V STEP (V = 1V)
WITH 10% V STEP (V = 1V)
CC
INP
CC
INP
INP
DS1843 toc10
DS1843 toc11
DS1843 toc12
V
V
SEN
SEN
2V/div
= 3.3V
V
(200mV/div)
(1V/div)
OUTP
V
V
CC
V
OUTN
(200mV/div)
2V/div
= 3.3V
V
OUTP
V
V
SEN
CC
= 3.0V
1V/div
CC
V
OUTN
200mV/div
10mV/div
V
- V
OUTN
OUTP
V
- V
OUTN
OUTP
V
= 3V
CC
V
OUTP
200mV/div
1V/div
100μs/div
100μs/div
50μs/div
SINGLE-ENDED STEP RECOVERY,
1V OUTPUT STEP (V = 1V)
SINGLE-ENDED OUTPUT, STEP RECOVERY,
1V OUTPUT STEP (V = 1V, ZOOMED IN)
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (V = 1V)
INP
INP
INP
DS1843 toc13
DS1843 toc14
DS1843 toc15
V
(200mV/div)
(1V/div)
OUTP
V
(200mV/div)
V
OUTP
SEN
OUTPUT STEP (200mV/div)
V
(1V/div)
SEN
V
(200mV/div)
- V
OUTN
OUTN
500mV/div
500mV/div
V
OUTP
V
STEP (200mV/div)
OUTP
V
OUTP
200mV/div
50μs/div
50ns/div
50μs/div
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (V = 1V, ZOOMED IN)
INP
DS1843 toc16
200mV/div
V
OUTP
V
OUTP
- V
OUTN
V
OUTN
(200mV/div)
(200mV/div)
50ns/div
_______________________________________________________________________________________
5
Fast Sample-and-Hold Circuit
Pin Description
PIN
1
NAME
FUNCTION
V
Power-Supply Input
CC
INP
INN
2
V
V
Positive Voltage Input. Input to sample circuit.
Negative Voltage Input. Input to sample circuit.
3
DS1843
4
DEN
GND
Differential Output Enable. Connect to V for differential output or GND for single-ended output.
CC
5
Ground Terminal
Sampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or
connect to GND for single-ended output mode.
6
V
OUTN
OUTP
7
8
V
Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor.
Sample Enable. Enables input sampling. This input is pulsed.
SEN
also have parasitic capacitance (C ). These capaci-
Block Diagram
IN
tors must fully charge before SEN is switched to low in
order to ensure accurate sampling. An RC time con-
stant is created by the resistance of the voltage source
connected to the DS1843’s input and the capacitances
on this node. See the Applications Information section
for details.
DS1843
V
CC
V
INP
V
OUTN
C
C
IN
V
OUTP
Output Buffer
After sampling is complete, the sampling capacitor is
switched to the output buffer. This buffer requires a
C
C
S
DEN
S
IN
small amount of time to settle, t
. When an ADC is
OUT
used to measure the DS1843’s output, a step occurs at
the ADC’s input caused by the ADC’s internal sampling
V
INN
capacitor. The DS1843’s recovery time, t
, is depen-
REC
CONTROL
LOGIC
SEN
dent on the size of the ADC’s sampling capacitor and
the voltage applied across the ADC. To maximize
accuracy, the ADC’s sampling speed (ADC clock fre-
quency) should be reduced until the ADC’s conversion
GND
window (t
, as shown in the Timing Diagram) is
ADC:ST
larger than the DS1843’s recovery time. Refer to the
ADC’s documentation for t
.
ADC:ST
Detailed Description
The DS1843 consists of a fully differential sampling
capacitor, switches, and a differential output buffer. It is
designed to operate in fiber optic burst-mode systems;
however, it can be used in other applications requiring
a fast sample-and-hold circuit. The output can be con-
figured for single-ended operations.
Sampling Time and Output Error
As the sampling time (t ) is decreased, the output error
S
increases. The output error is largely dependent on the
settling time of the sampling capacitor and, to a lesser
degree, the output buffer’s gain error and offset volt-
age. Settling time can be reduced by driving the
DS1843 with a lower impedance. In a typical fiber optic
application, a current is applied across a 5kΩ resistor.
By using a stronger current source, the resistance and
the settling time can be reduced (see the Applications
Information section for details).
Input Sampling Capacitor
The input voltage is sampled using a 5pF capacitor on
the positive input and another on the negative input.
The capacitors are connected to the input when SEN is
high. In addition to the sampling capacitors, the inputs
6
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit
DS1843
DS1843
INPUT MODEL
CURRENT
MIRROR OUTPUT
R
R
SW
SW
V
V
INP
INN
C
C
C
C
C
PAR
IN
S
S
R
IN
IN
Figure 1. Input Impedances for Settling Time Calculations Diagram
Figure 1 shows the simplified diagram of input imped-
ances for settling time calculations. Sample time is
divided into two parts:
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1843,
1) t : Internal settling time (max 250ns). During this
IST
decouple the power-supply pin, V , with a 0.01μF or
CC
time, voltage V (V
stant of:
- V
) rises with a time con-
INN
IN INP
0.1μF capacitor. Use a high-quality X7R or equivalent
ceramic surface-mount capacitor.
R
IN
x (C + C
)
PAR
IN
DS1843 Estimated Settling Time
The settling time is dependent on the gain ratio of the
current mirror used at the input of the DS1843. For
example, the MAX4007 includes a 10:1 ratio current
mirror. This requires a 5kΩ resistor to create a 1V full-
scale output with 2mA current input to the MAX4007.
This resistor can be decreased to 2.5kΩ by using the
DS1842, which has a 5:1 ratio current mirror.
2) t : During this period two things happen:
RC
a. Input V keeps increasing from its value at t
IN
to its final value with a new time constant of:
IST
2
2
⎧
⎨
⎩
⎫
⎬
⎭
R
× C + C
+ R
(
× C
SW S
(
)
)
(
)
IN
IN
PAR
b. R
and C track this V (input) with a time con-
SW
SW
stant of R
S IN
x C , which is 12.5ns (worst case).
S
Variable Definitions:
Example:
R : Input resistor. The current mirror creates a voltage
IN
across this resistor.
Approximate accuracy calculations can be done for an
input voltage based on the above impedance values.
These calculations can be divided into three parts.
R
: Resistance of series switch that connects internal
SW
circuitry to input pins after t
time.
IST
1) Accuracy of input at t
(250ns):
IST
C : 7pF parasitic (ESD) capacitor.
IN
C
: External parasitic capacitance. A current mirror's
−t
PAR
1
output and typical trace capacitance are less than
10pF.
⎡
⎤
R
× C +C
(
)
IN
IN
PAR
⎣
⎦
Accuracy = 1− e
C : 5pF sample capacitor.
S
where t = t
= 250ns.
1
IST
t
: Internal settling time based on t from the AC elec-
S
IST
At t
the internal circuit tags input impedance.
IST
trical specification. The minimum t includes one time
S
This causes charge redistribution to occur, which
causes a dip in the input voltage. The worst-case
constant. t
removes this time constant.
IST
value of the input voltage at t
IST
is:
t
: RC settling time of the input.
RC
−t
⎡
⎤
⎥
⎥
⎥
IST
⎡
⎤
⎢
C
⎡
⎤
R
× C +C
(
)
S
IN
IN
PAR
⎣
⎦
V
= ⎢1−
⎥ × 1− e
× V
IN
⎢
IN@t
IST
C
+ C
+ C
PAR S
⎢
⎣
(
)
⎥
⎢
IN
⎦
⎢
⎥
⎣
⎦
_______________________________________________________________________________________
7
Fast Sample-and-Hold Circuit
2) Accuracy of internal circuitry between t - t
:
IST
S
Pin Configuration
−t
2
R
×C
S
(
)
SW
Accuracy = 1− e
TOP VIEW
where t = (t - t ) and (R
x C ) ~ = 12ns.
S
2
S
IST
SW
V
1
2
3
4
8
7
6
5
SEN
V
CC
3) Total accuracy of input at sampling time, t :
S
DS1843
V
INP
OUTP
−t
⎡
⎢
⎤
⎥
⎥
2
−t
newRC
⎡
⎤
⎥
⎥
⎦
2
DS1843
R
×C
(
)
⎢
SW
S
Accuracy = 1− 1− V
× e
× 1− e
(
)
IN@t
⎢
IST
V
V
OUTN
⎢
⎣
INN
⎢
⎣
⎥
⎦
DEN
GND
2
2
⎧
⎫
⎬
⎭
where newRC =
R
× C + C
+ R
(
× C
SW S
(
)
)
⎨
⎩
(
)
IN
IN
PAR
μDFN
(2mm × 2mm)
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0164
8 μDFN
L822+1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
DS1844-010+
QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDIP20, 0.300 INCH, DIP-20
MAXIM
DS1844-100
Digital Potentiometer, 4 Func, 100000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDIP20, 0.300 INCH, DIP-20
MAXIM
©2020 ICPDF网 联系我们和版权申明