DS1859B-020 [MAXIM]
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors; 双路，温控电阻，内置校准监视器
| 型号： | DS1859B-020 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 文件： | 总28页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 11/03
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
General Description
Features
The DS1859 dual, temperature-controlled, nonvolatile
(NV) variable resistors with three monitors consists of
two 50kΩ or two 20kΩ, 256-position, linear, variable
resistors; three analog monitor inputs (MON1, MON2,
MON3); and a direct-to-digital temperature sensor. The
device provides an ideal method for setting and tem-
perature-compensating bias voltages and currents in
control applications using minimal circuitry. The vari-
able resistor settings are stored in EEPROM memory
and can be accessed over the 2-wire serial bus.
♦ SFF-8472 Compatible
♦ Five Monitored Channels (Temperature, V
,
CC
MON1, MON2, MON3)
♦ Three External Analog Inputs (MON1, MON2, MON3)
That Support Internal and External Calibration
♦ Scalable Dynamic Range for External Analog Inputs
♦ Internal Direct-to-Digital Temperature Sensor
♦ Alarm and Warning Flags for All Monitored
Channels
♦ Two 50kΩ or Two 20kΩ, Linear, 256-Position,
Nonvolatile Temperature-Controlled Variable
Resistors
♦ Resistor Settings Changeable Every 2°C
♦ Access to Monitoring and ID Information
Configurable with Separate Device Addresses
♦ 2-Wire Serial Interface
Applications
Optical Transceivers
♦ Two Buffers with TTL/CMOS-Compatible Inputs and
Optical Transponders
Instrumentation and Industrial Controls
RF Power Amps
Open-Drain Outputs
♦ Operates from a 3.3V or 5V Supply
♦ Operating Temperature Range of -40°C to +95°C
Diagnostic Monitoring
Ordering Information
PART
DS1859E-050
DS1859E-020
RESISTANCE PIN-PACKAGE
50kΩ
20kΩ
16 TSSOP
16 TSSOP
16 TSSOP
(Tape-and-Reel)
Typical Operating Circuit
DS1859E-050/T&R
DS1859E-020/T&R
50kΩ
20kΩ
16 TSSOP
(Tape-and-Reel)
V
CC
DS1859B-050
DS1859B-020
50kΩ
20kΩ
16-Ball CSBGA
16-Ball CSBGA
V
= 3.3V
CC
4.7kΩ
2-WIRE
4.7kΩ
DECOUPLING
CAP
0.1µF
16
1
V
CC
Pin Configurations
SDA
15
14
2
TO LASER BIAS
CONTROL
H1
L1
INTERFACE
SCL
3
4
TOP VIEW
A
OUT1
IN1
TO LASER
MODULATION
CONTROL
13
12
Tx-FAULT
1
2
3
4
5
6
7
8
SDA
SCL
V
CC
H0
L0
16
15
14
13
12
11
10
V
IN1
SCL
SDA
IN2
H1
L1
CC
5
6
H1
L1
DS1859
OUT2
IN2
LOS
11
10
9
Rx POWER*
OUT1
IN1
MON3
MON2
MON1
B
C
D
OUT2
H0
7
8
Tx POWER*
Tx BIAS*
H0
GROUND TO
DISABLE WRITE
PROTECT
DIAGNOSTIC
INPUTS
WPEN
GND
DS1859
OUT2
IN2
L0
WPEN
OUT1
MON3
MON3
MON2
MON1
WPEN
GND
*SATISFIES SFF-8472 COMPATIBILITY
GND
1
L0
2
MON1
3
MON2
4
9
CSBGA (4mm x 4mm)
1.0mm PITCH
TSSOP
______________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Relative to Ground ...........-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A
CC
Voltage Range on Inputs Relative
to Ground* ................................................-0.5V to V
Voltage Range on Resistor Inputs Relative
to Ground* ................................................-0.5V to V
+ 0.5V
CC
+ 0.5V
CC
Current into Resistors............................................................5mA
*Not to exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 1)
(Note 2)
(Note 2)
2.97
5.5
V
V
CC
Input Logic 1 (SDA, SCL, WPEN)
Input Logic 0 (SDA, SCL, WPEN)
Resistor Inputs (L0, L1, H0, H1)
Resistor Current
V
0.7 x Vcc
-0.3
V
+ 0.3
CC
IH
V
+0.3 x V
V
IL
CC
-0.3
V
+ 0.3
+3
V
CC
I
-3
mA
µA
RES
High-Z Resistor Current
I
0.001
0.1
ROFF
Input logic 1
Input logic 0
1.5
Input Logic Levels (IN1, IN2)
V
0.9
DC ELECTRICAL CHARACTERISTICS
(V
= 2.97V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
Input Leakage
I
(Note 3)
1
2
mA
CC
I
-200
+200
0.4
nA
IL
V
V
3mA sink current
6mA sink current
0
0
OL1
OL2
Low-Level Output Voltage
(SDA, OUT1, OUT2)
V
0.6
Full-Scale Input (MON1, MON2,
MON3)
At factory setting
(Note 4)
2.4875
2.5
2.5125
V
V
At factory setting
(Note 5)
Full-Scale V
Monitor
6.5208 6.5536 6.5864
10
CC
I/O Capacitance
C
pF
kΩ
V
I/O
WPEN Pullup
R
40
1.0
2.0
65
100
2.2
2.6
WPEN
Digital Power-On Reset
Analog Power-On Reset
POD
POA
V
2
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
ANALOG RESISTOR CHARACTERISTICS
(V
= 2.97V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
0.65
40
TYP
1.0
50
MAX
1.35
60
UNITS
kΩ
Position 00h Resistance (50kΩ)
Position FFh Resistance (50kΩ)
Position 00h Resistance (20kΩ)
Position FFh Resistance (20kΩ)
Absolute Linearity
T
T
T
T
= +25°C
= +25°C
= +25°C
= +25°C
A
A
A
A
kΩ
0.20
16
0.40
20
0.55
24
kΩ
kΩ
(Note 6)
(Note 7)
(Note 8)
-2
+2
LSB
LSB
ppm/°C
Relative Linearity
-1
+1
Temperature Coefficient
50
ANALOG VOLTAGE MONITORING
(V
= 2.97V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µV
Input Resolution
∆VMON
610
1.6
Supply Resolution
∆V
mV
CC
Input/Supply Accuracy
(MON1, MON2, MON3, V
% FS
(full scale)
A
At factory setting
0.25
30
0
0.5
45
5
CC
)
CC
Update Rate for MON1, MON2,
MON3, Temp, or V
t
ms
frame
CC
Input/Supply Offset
(MON1, MON2, MON3, V
V
(Note 14)
LSB
OS
)
CC
DIGITAL THERMOMETER
(V
= 2.97V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
CC
PARAMETER
Thermometer Error
SYMBOL
CONDITIONS
-40°C to +95°C
MIN
TYP
MAX
3.0
UNITS
T
°C
ERR
NONVOLATILE MEMORY CHARACTERISTICS
(V
= 2.97V to 5.5V)
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
50,000
EEPROM Writes
+70°C
_____________________________________________________________________
3
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
AC ELECTRICAL CHARACTERISTICS
(V
= 2.97V to 5.5V, T = -40°C to +95°C, unless otherwise noted. See Figure 6.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
Fast mode (Note 9)
MIN
0
TYP
MAX
400
UNITS
SCL Clock Frequency
f
kHz
SCL
Standard mode (Note 9)
Fast mode (Note 9)
0
100
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
Bus Free Time Between STOP and
START Condition
t
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
BUF
Standard mode (Note 9)
Fast mode (Notes 9, 10)
Standard mode (Notes 9, 10)
Fast mode (Note 9)
Hold Time (Repeated)
START Condition
t
HD:STA
LOW Period of SCL Clock
HIGH Period of SCL Clock
Data Hold Time
t
LOW
Standard mode (Note 9)
Fast mode (Note 9)
t
HIGH
Standard mode (Note 9)
Fast mode (Notes 9, 11, 12)
Standard mode (Notes 9, 11, 12)
Fast mode (Note 9)
0.9
t
HD:DAT
0
100
250
0.6
4.7
20 + 0.1C
Data Setup Time
t
SU:DAT
Standard mode (Note 9)
Fast mode (Note 9)
START Setup Time
t
SU:STA
Standard mode (Note 9)
Fast mode (Note 13)
Standard mode (Note 13)
Fast mode (Note 13)
Standard mode (Note 13)
Fast mode
300
1000
300
B
Rise Time of Both SDA and SCL
Signals
t
R
20 + 0.1C
B
20 + 0.1C
20 + 0.1C
0.6
B
B
Fall Time of Both SDA and SCL
Signals
t
F
300
Setup Time for STOP Condition
t
SU:STO
Standard mode
4.0
Capacitive Load for Each Bus Line
EEPROM Write Time
C
(Note 13)
400
20
pF
B
t
W
(Note 14)
10
ms
Note 1: All voltages are referenced to ground.
Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
is switched off.
CC
Note 3: SDA and SCL are connected to V
and all other input signals are connected to well-defined logic levels.
CC
Note 4: Full Scale is user programmable. The maximum voltage that the MON inputs read is approximately Full Scale, even if the volt-
age on the inputs is greater than Full Scale.
Note 5: This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V voltage.
CC
Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8: See the Typical Operating Characteristics.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
> 250ns must then be met. This
SU:DAT
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
+ t
= 1000ns + 250ns = 1250ns
RMAX
SU:DAT
4
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum t
only has to be met if the device does not stretch the LOW period (t
) of the SCL signal.
HD:DAT
LOW
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
of the SCL signal) to
IH MIN
bridge the undefined region of the falling edge of SCL.
Note 13: C —total capacitance of one bus line, timing referenced to 0.9 x V
and 0.1 x V
.
B
CC
CC
Note 14: Guaranteed by design.
Typical Operating Characteristics
(V
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
A
CC
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. VOLTAGE
RESISTANCE vs. SETTING
720
700
650
600
550
500
450
400
60
50
40
30
20
10
0
50kΩ VERSION
SDA = SCL = V
SDA = SCL = V
CC
CC
680
640
600
560
520
-40
-20
0
20
40
60
80
100
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
TEMPERATURE (°C)
VOLTAGE (V)
SETTING (DEC)
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
RESISTOR 0 INL (LSB)
RESISTANCE vs. SETTING
1.0
0.8
20
15
10
5
760
720
680
640
600
560
20kΩ VERSION
SDA = V
CC
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
0
50
100
150
200
250
0
100
200
300
400
SETTING (DEC)
SCL FREQUENCY (kHz)
_____________________________________________________________________
5
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Typical Operating Characteristics (continued)
(V
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
A
CC
RESISTOR 1 INL (LSB)
RESISTOR 0 DNL (LSB)
RESISTOR 1 DNL (LSB)
1.0
1.0
0.8
1.0
0.8
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
RESISTANCE
vs. POWER-UP VOLTAGE
RESISTANCE
vs. POWER-UP VOLTAGE
120
120
110
100
>1MΩ
20kΩ VERSION
110
100
>1MΩ
50kΩ VERSION
90
80
90
80
PROGRAMMED
RESISTANCE
(80h)
70
60
50
70
60
50
PROGRAMMED
RESISTANCE
(80h)
40
30
20
40
30
20
10
0
10
0
0
1
2
3
4
5
0
1
2
3
4
5
POWER-UP VOLTAGE (V)
POWER-UP VOLTAGE (V)
POSITION 00h RESISTANCE
vs. TEMPERATURE
1.00
50kΩ VERSION
0.99
0.98
0.97
0.96
0.95
-40 -25 -10
5
20 35 50 65 80 95
TEMPERATURE (°C)
6
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Typical Operating Characteristics (continued)
= 5.0V, T = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
A
(V
CC
POSITION 00h RESISTANCE
vs. TEMPERATURE
POSITION FFh RESISTANCE
vs. TEMPERATURE
POSITION FFh RESISTANCE
vs. TEMPERATURE
0.38
0.37
0.36
0.35
0.34
0.33
52.00
51.80
51.60
51.40
51.20
51.00
20.00
19.80
19.50
19.40
19.20
19.00
20kΩ VERSION
50kΩ VERSION
20kΩ VERSION
-40 -25 -10
5
20 35 50 65 80 95
-40 -25 -10
5
20 35 50 65 80 95
-40 -25 -10
5
20 35 50 65 80 95
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE COEFFICIENT vs. SETTING
TEMPERATURE COEFFICIENT vs. SETTING
800
700
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
20kΩ VERSION
50kΩ VERSION
+25°C TO +95°C
+25°C TO -40°C
+25°C TO +95°C
+25°C TO -40°C
0
-50
-100
-100
0
50
100
150
200
250
0
50
100
150
200
250
SETTING (DEC)
SETTING (DEC)
LSB ERROR vs. FULL-SCALE INPUT
LSB ERROR vs. FULL-SCALE INPUT
6
5
4
3
2
+3 SIGMA
+3 SIGMA
3
2
1
1
0
MEAN
MEAN
0
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-3 SIGMA
-3 SIGMA
0
25
50
75
100
0
3.125
6.250
9.375
12.500
NORMALIZED FULL SCALE (%)
NORMALIZED FULL SCALE (%)
_______________________________________________________________________________________
7
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Pin Description
PIN
1
BALL
B2
NAME
SDA
FUNCTION
2-Wire Serial Data I/O Pin. Transfers serial data to and from the device.
2-Wire Serial Clock Input. Clocks data into and out of the device.
2
A2
SCL
3
C3
OUT1 Open-Drain Buffer Output
4
A1
IN1
TTL/CMOS-Compatible Input to Buffer
5
B1
OUT2 Open-Drain Buffer Output
6
C2
IN2
TTL/CMOS-Compatible Input to Buffer
Write Protect Enable. The device is not write protected if WPEN is connected to ground. This pin has
7
C1
WPEN
an internal pullup (R
). See Table 6.
WPEN
8
9
D1
D3
D4
C4
GND
Ground
MON1 External Analog Input
MON2 External Analog Input
MON3 External Analog Input
10
11
Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential
less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor
terminals cannot exceed the power-supply voltage, V , or go below ground.
CC
12
13
D2
B3
L0
High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a
potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of
H0
the resistor terminals cannot exceed the power-supply voltage, V , or go below ground.
CC
14
15
16
B4
A4
A3
L1
Low-End Resistor 1 Terminal
High-End Resistor 1 Terminal
Supply Voltage
H1
V
CC
Two buffers are provided to convert logic-level inputs
Detailed Description
into open-drain outputs. Typically, these buffers are
used to implement transmit (Tx) fault and loss-of-signal
(LOS) functionality. Additionally, OUT1 can be asserted
in the event that one or more of the monitored values
go beyond user-defined limits.
The user can read the registers that monitor the V
,
CC
MON1, MON2, MON3, and temperature analog signals.
After each signal conversion, a corresponding bit is set
that can be monitored to verify that a conversion has
occurred. The signals also have alarm and warning flags
that notify the user when the signals go above or below
the user-defined value. Interrupts can also be set for
each signal.
The position values of each resistor can be indepen-
dently programmed. The user can assign a unique
value to each resistor for every 2°C increment over the
-40°C to +102°C range.
8
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
PROT
AUX
PROT
MAIN
PROT
MAIN
AD
MD
MD
AD (AUXILIARY DEVICE ENABLE A0h)
MD (MAIN DEVICE ENABLE)
TABLE
SELECT
TABLE
SELECT
EEPROM
72 x 8 BIT
80h-C7h
EEPROM
72 x 8 BIT
80h-C7h
DEVICE
ADDRESS
EEPROM
128 x 8 BIT
00h-7Fh
ADDRESS
ADDRESS
R/W
ADDRESS
R/W
DEVICE ADDRESS
TABLE 02
RESISTOR 0
LOOK-UP
TABLE
TABLE 03
RESISTOR 1
LOOK-UP
TABLE
R/W
STANDARDS
ADEN ADFIX
SDA
SCL
ADDRESS
DATA BUS
2-WIRE
INTERFACE
TEMP INDEX
TEMP INDEX
R/W
PROT
MAIN
TxF
Tx FAULT
MD
OUT1
H0
MONITORS LIMIT
HIGH
RESISTOR 0
ADDRESS
R/W
50kΩ OR 20kΩ FULL SCALE
EEPROM
96 x 8 BIT
00h-5Fh
LIMITS
256 POSITIONS
MONITORS LIMIT
LOW
MINT
L0
TEMP INDEX
MINT (BIT)
H1
SRAM
32 x 8 BIT
60h-7Fh
IN1
RESISTOR 1
INV1
TxF
50kΩ OR 20kΩ FULL SCALE
RxL
256 POSITIONS
NOT PROTECTED
LOS
L1
OUT2
TABLE SELECT
PROT
MAIN
MEASUREMENT
WARNING FLAGS
MD R/W
INV2
ALARM FLAGS
INV1 (BIT)
INV2 (BIT)
APEN (BIT)
MPEN (BIT)
ADEN (BIT)
ADFIX (BIT)
RIGHT
SHIFTING
IN2
TABLE SELECT
ADDRESS
INTERNAL
CALIBRATION
TABLE 01
INTERNAL
TEMP
V
CC
EEPROM
16 x 8 BIT
80h-8Fh
DS1859
ADC
12-BIT
MUX
MON1
MON2
MON3
DEVICE ADDRESS
VENDOR
MONITORS LIMIT HIGH
A/D
MASKING (TMP, V , MON1, MON2, MON3)
CC
CTRL
MUX
CTRL
MONITORS LIMIT LOW
V
CC
V
CC
MINT
MEASUREMENT
INTERRUPT
V
R
WPEN
CC
PROT AUX
APEN
GND
COMPARATOR
COMP CTRL
WARNING FLAGS
PROT MAIN
MPEN
ALARM FLAGS
WPEN
Figure 1. Block Diagram
_____________________________________________________________________
9
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 1. Scales for Monitor Channels at
Factory Setting
Table 3. Look-up Table Address for
Corresponding Temperature Values
+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
SIGNAL
TEMPERATURE
(°C)
CORRESPONDING LOOK-UP
TABLE ADDRESS
Temperature 127.984°C
7FFC
FFF8
FFF8
FFF8
FFF8
-128°C
0V
8000
0000
0000
0000
0000
<-40
-40
80h
80h
81h
82h
83h
—
V
6.5528V
2.4997V
2.4997V
2.4997V
CC
MON1
MON2
MON3
0V
-38
0V
-36
0V
-34
—
Table 2. Signal Comparison
+98
+100
+102
>+102
C5h
C6h
C7h
C7h
SIGNAL
FORMAT
Unsigned
Unsigned
Unsigned
Unsigned
V
CC
MON1
MON2
Monitor Conversion Example
MON3
Temperature
Two’s complement
MSB (BIN)
11000000
10000000
LSB (BIN)
00000000
10000000
VOLTAGE (V)
1.875
Monitored Signals
1.255
Each signal (V , MON1, MON2, MON3, and tempera-
CC
ture) is available as a 16-bit value with 12-bit accuracy
(left-justified) over the serial bus. See Table 1 for signal
scales and Table 2 for signal format. The four LSBs
should be masked when calculating the value.
To calculate V , convert the unsigned 16-bit value to
CC
decimal and multiply by 100µV.
To calculate MON1, MON2, or MON3, convert the
unsigned 16-bit value to decimal and multiply by
38.147µV.
For the 20kΩ version, the 3 LSBs are internally masked
with 0s.
To calculate the temperature, treat the two’s comple-
ment value binary number as an unsigned binary num-
ber, then convert to decimal and divide by 256. If the
result is greater than or equal to 128, subtract 256 from
the result.
The signals are updated every frame rate (t
round-robin fashion.
) in a
frame
The comparison of all five signals with the high and low
user-defined values are done automatically. The corre-
sponding flags are set to 1 within a specified time of
the occurrence of an out-of-limit condition.
Temperature: high byte: -128°C to +127°C signed; low
byte: 1/256°C.
Calculating Signal Values
Temperature Bit Weights
The LSB = 100µV for V , and the LSB = 38.147µV for
CC
6
5
4
3
2
1
0
the MON signals when using factory default settings.
S
2
2
2
2
2
2
2
-1
-2
-3
-4
-5
-6
-7
-8
2
2
2
2
2
2
2
2
Monitor/V
Bit Weights
CC
15
14
13
12
11
3
10
2
9
1
8
0
Temperature Conversion Examples
MSB
LSB
2
2
2
2
2
2
2
2
2
2
7
6
5
4
2
2
2
2
2
2
MSB (BIN)
01000000
01000000
01011111
11110110
11011000
LSB (BIN)
00000000
00001111
00000000
00000000
00000000
TEMPERATURE (°C)
64
64.059
95
V
CC
Conversion Examples
MSB (BIN)
10000000
11000000
LSB (BIN)
10000000
11111000
VOLTAGE (V)
3.29
-10
4.94
-40
10
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 4. ADEN Address Configuration
Table 5. ADEN and ADFIX Bits
AUXILIARY
ADDRESS
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADEN
ADFIX
MAIN ADDRESS
ADDITIONAL
INFORMATION
ADDRESSES
0
0
1
1
0
1
0
1
A0h
A2h
EEPROM
(Table 01, 8Ch)
0
1
2
See Figure 2
See Figure 3
A0h
N/A
N/A
1 (Main Device only)
A2h
EEPROM
(Table 01, 8Ch)
MAIN DEVICE ENABLE
AUXILIARY DEVICE ENABLE
DEC
0
0
EN
AUXILIARY
DEVICE
MAIN
DEVICE
0
EN
5Fh
60h
EN
7Fh
TABLE 01
TABLE 02
TABLE 03
7Fh
TABLE SELECT
EN
EN
EN
80h
80h
95
96
80h
MON LOOK-UP
TABLE CONTROL
DECODER
R0 LOOK-UP
TABLE
R1 LOOK-UP
TABLE
8Fh
SEL
127
128
SEL C7h
SEL C7h
143
199
F0h
F0h
RESERVED
FFh
RESERVED
FFh
MEMORY PARTITION WITH ADEN BIT = 0
Figure 2. Memory Organization, ADEN = 0
Variable Resistors
Memory Description
Main and auxiliary memories can be accessed by two
separate device addresses. The Main Device address
is A2h (or value in Table 01 byte 8Ch, when ADFIX = 1)
and the Auxiliary Device address is A0h. A user option
is provided to respond to one or two device addresses.
This feature can be used to save component count in
SFF applications (Main Device address can be used)
or other applications where both GBIC (Auxiliary
Device address can be used) and monitoring functions
are implemented and two device addresses are need-
ed. The memory blocks are enabled with the corre-
sponding device address. Memory space from 80h and
The value of each variable resistor is determined by
a temperature-addressed look-up table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in manu-
al mode and the temperature indexing is disabled. The
user sets the resistors in manual mode by writing to
addresses 82h and 83h in Table 01 to control resistors
0 and 1, respectively.
____________________________________________________________________ 11
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
MAIN DEVICE ENABLE
0
DEC
EN
MAIN
DEVICE
0
5Fh
60h
EN
7Fh
TABLE 01
TABLE 02
TABLE 03
EN
EN
EN
80h
80h
95
96
80h
TABLE SELECT
DECODER
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
TABLE
R1 LOOK-UP
TABLE
TABLE 00
80h
8Fh
SEL
127
128
SEL C7h
SEL C7h
AUXILIARY
DEVICE
143
EN
F0h
F0h
RESERVED
FFh
RESERVED
FFh
199
255
FFh
MEMORY PARTITION WITH ADEN BIT = 1
Figure 3. Memory Organization, ADEN = 1
above is accessible only through the Main Device
address. This memory is organized as three tables. The
desired table can be selected by the contents of mem-
ory location 7Fh, Main Device. The Auxiliary Device
address has no access to the tables, but the Auxiliary
Device address can be mapped into the Main Device’s
memory space as a fourth table. Device addresses are
programmable with two control bits in EEPROM.
ADEN configures memory access to respond to differ-
ent device addresses (see Tables 4 and 5).
The default device address for EEPROM-generated
addresses is A2h.
If the ADEN bit is 1, additional 128 bytes of EEPROM
are accessible through the Main Device, selected as
Table 00 (see Figure 3). In this configuration, the
Auxiliary Device is not accessible. APEN controls the
protection of Table 00 regardless of ADEN’s setting.
ADFIX (address fixed) determines whether the Main
Device address is determined by an EEPROM byte
(Table 01, byte 8Ch, when ADFIX = 1). There can be
up to 128 devices sharing a common 2-wire bus, with
each device having its own unique device address.
Table 6. Main Device
WPEN
MPEN
PROTECT MAIN
0
X
1
X
0
1
No
No
Yes
Table 7. Auxiliary Device
APEN
WPEN
PROTECT AUXILIARY
0
1
X
X
No
Yes
12
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Register Map
Bytes designated as "Reserved" have been set aside
for added functionality in future revisions of this device.
A description of the registers is below. The registers
are read only (R) or read/write (R/W). The R/W registers
are writable only if write protect has not been asserted
(see the Memory Description section).
Auxiliary Device
MEMORY LOCATION
(hex)
DEFAULT SETTING
EEPROM/SRAM
R/W
NAME OF LOCATION
FUNCTION
(hex)
00 to 7F
EEPROM
R/W
00
Standards Data
—
Main Device
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
Contains upper limit settings for temperature.
If the limit is violated, an alarm flag in Main
Device byte 70h is set.
00 to 01
02 to 03
04 to 05
06 to 07
08 to 09
0A to 0B
0C to 0D
0E to 0F
10 to 11
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
00
00
00
00
00
00
00
00
TMPlimhi (MSB to LSB)
Contains lower limit settings for temperature. If
TMPlimlo (MSB to LSB) the limit is violated, an alarm flag in Main
Device byte 70h is set.
Contains upper limit settings for temperature.
If the limit is violated, a warning flag in Main
Device byte 74h is set.
TMPwrnhi (MSB to LSB)
Contains lower limit settings for temperature. If
TMPwrnlo (MSB to LSB) the limit is violated, a warning flag in Main
Device byte 74h is set.
Contains upper limit settings for V . If the
CC
limit is violated, an alarm flag in Main Device
byte 70h is set.
V
V
limhi (MSB to LSB)
CC
CC
Contains lower limit settings for V . If the
CC
limit is violated, an alarm flag in Main Device
byte 70h is set.
limlo (MSB to LSB)
Contains upper limit settings for V . If the
CC
V
wrnhi (MSB to LSB) limit is violated, a warning flag in Main Device
byte 74h is set.
CC
Contains lower limit settings for V . If the
CC
limit is violated, a warning flag in Main Device
byte 74h is set.
V
wrnlo (MSB to LSB)
CC
Contains upper limit settings for MON1. If the
MON1limhi (MSB to LSB) limit is violated, an alarm flag in Main Device
byte 70h is set.
Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults.
____________________________________________________________________ 13
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
R/W
R/W
R/W
NAME OF LOCATION
FUNCTION
Contains lower limit settings for MON1. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
12 to 13
14 to 15
16 to 17
EEPROM
EEPROM
EEPROM
00
00
00
MON1limlo (MSB to LSB)
Contains upper limit settings for MON1. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
MON1wrnhi
(MSB to LSB)
Contains lower limit settings for MON1. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
MON1wrnlo
(MSB to LSB)
Contains upper limit settings for MON2. If the
18 to 19
1A to 1B
1C to 1D
1E to 1F
EEPROM
EEPROM
EEPROM
EEPROM
R/W
R/W
R/W
R/W
00
00
00
00
MON2limhi (MSB to LSB) limit is violated, an alarm flag in Main Device
byte 70h is set.
Contains lower limit settings for MON2. If the
MON2limlo (MSB to LSB)
limit is violated, an alarm flag in Main Device
byte 70h is set.
Contains upper limit settings for MON2. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
MON2wrnhi
(MSB to LSB)
Contains lower limit settings for MON2. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
MON2wrnlo
(MSB to LSB)
Contains upper limit settings for MON3. If the
limit is violated, an alarm flag in Main Device
byte 71h is set.
20 to 21
22 to 23
24 to 25
26 to 27
EEPROM
EEPROM
EEPROM
EEPROM
R/W
R/W
R/W
R/W
00
00
00
00
MON3limhi (MSB to LSB)
MON3limlo (MSB to LSB)
Contains lower limit settings for MON3. If the
limit is violated, an alarm flag in Main Device
byte 71h is set.
Contains upper limit settings for MON3. If the
limit is violated, a warning flag in Main Device
byte 75h is set.
MON3wrnhi
(MSB to LSB)
Contains lower limit settings for MON3. If the
limit is violated, a warning flag in Main Device
byte 75h is set.
MON3wrnlo
(MSB to LSB)
28 to 37
38 to 5F
EEPROM
EEPROM
—
—
—
Reserved
Memory
—
—
R/W
Measured TMP
(MSB to LSB)
Digitized measured value for temperature.
See Table 1.
60 to 61
62 to 63
64 to 65
66 to 67
SRAM
SRAM
SRAM
SRAM
R
R
R
R
—
—
—
—
Measured V
Digitized measured value for V
.
CC
CC
(MSB to LSB)
See Table 1.
Measured MON1
(MSB to LSB)
Digitized measured value for MON1.
See Table 1.
Measured MON2
(MSB to LSB)
Digitized measured value for MON2.
See Table 1.
14
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
Measured MON3
(MSB to LSB)
Digitized measured value for MON3.
See Table 1.
68 to 69
SRAM
R
—
6A to 6D
6E
SRAM
SRAM
—
—
—
—
Reserved
—
—
Logic states
Resistor status bit. A high indicates that both
resistors are in high-impedance mode. A low
indicates that both resistors are operating
normally.
Bit 7
—
R
X
HIZSTA
Resistor control bit. Setting this bit high
causes both resistors to go into a high-
impedance state.
6
—
R/W
0
HIZCO
5
4
—
—
—
—
X
X
X
X
—
—
This status bit is high when OUT1 is high,
assuming there is an external pullup resistor
on OUT1.
2
3
1
—
—
—
R
—
R
X
X
X
TXF
X
—
This status bit is high when OUT2 is high,
assuming there is an external pullup resistor
on OUT2.
RXL
This status bit goes high when V
below the POA level.
has fallen
CC
0
—
R
X
RDYB
6F
SRAM
—
—
Conversion updates
—
This bit goes high after a temperature and
address update has occurred for the
corresponding measurement in bytes 60h to
61h. This bit can be written to a 0 by the user
and monitored to verify that a conversion has
occurred.
Bit 7
—
R/W
0
TAU
This bit goes high after a V
update has
CC
occurred for the corresponding measurement
in bytes 62h to 63h. This bit can be written to
a 0 by the user and monitored to verify that a
conversion has occurred.
6
5
—
—
R/W
R/W
0
0
V
U
CC
This bit goes high after a MON1 update has
occurred for the corresponding measurement
in bytes 64h to 65h. This bit can be written to
a 0 by the user and monitored to verify that a
conversion has occurred.
MON1U
____________________________________________________________________ 15
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
This bit goes high after a MON2 update has
occurred for the corresponding measurement
in bytes 66h to 67h. This bit can be written to
a 0 by the user and monitored to verify that a
conversion has occurred.
4
3
—
—
R/W
0
0
MON2U
This bit goes high after a MON3 update has
occurred for the corresponding measurement
in bytes 68h to 69h. This bit can be written to
a 0 by the user and monitored to verify that a
conversion has occurred.
—
MON3U
2
1
—
—
—
—
—
R
0
0
0
—
—
—
—
—
—
—
0
—
70
SRAM
Alarm flags
This alarm flag goes high when the upper limit
of the temperature setting is violated.
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMPhi
TMPlo
This alarm flag goes high when the lower limit
of the temperature setting is violated.
6
5
4
3
2
1
This alarm flag goes high when the upper limit
V
V
hi
lo
CC
of the V
setting is violated.
CC
This alarm flag goes high when the lower limit
of the V setting is violated.
CC
CC
This alarm flag goes high when the upper limit
of the MON1 setting is violated.
MON1hi
MON1lo
MON2hi
This alarm flag goes high when the lower limit
of the MON1 setting is violated.
This alarm flag goes high when the upper limit
of the MON2 setting is violated.
This alarm flag goes high when the lower limit
of the MON2 setting is violated.
0
—
SRAM
—
—
R
—
—
—
MON2lo
Alarm flags
MON3hi
71
—
This alarm flag goes high when the upper limit
of the MON3 setting is violated.
Bit 7
—
This alarm flag goes high when the lower limit
of the MON3 setting is violated.
6
—
—
—
MON3lo
5
4
—
—
—
—
—
—
X
X
—
—
16
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
3
2
1
—
—
—
—
—
—
—
—
—
X
X
X
—
—
—
A mask of all flags located in Table 01 byte
88h determines the value of MINT. MINT is
maskable to 0 if no interrupt is desired by
setting Table 01 byte 88h to 0.
0
—
—
—
MINT
72 to 73
74
SRAM
SRAM
—
R
—
—
Reserved
—
—
Warning flags
This warning flag goes high when the upper
limit of the temperature setting is violated.
Bit 7
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMPhi
TMPlo
This warning flag goes high when the lower
limit of the temperature setting is violated.
This warning flag goes high when the upper
5
V
V
hi
lo
CC
limit of the V
setting is violated.
CC
This warning flag goes high when the lower
limit of the V setting is violated.
4
CC
CC
This warning flag goes high when the upper
limit of the MON1 setting is violated.
3
MON1hi
MON1lo
MON2hi
MON2lo
This warning flag goes high when the lower
limit of the MON1 setting is violated.
2
This warning flag goes high when the upper
limit of the MON2 setting is violated.
1
This warning flag goes high when the lower
limit of the MON2 setting is violated.
0
____________________________________________________________________ 17
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
75
SRAM
—
R
—
0
Warning Flags
MON3hi
—
This warning flag goes high when the upper
limit of the MON3 setting is violated.
Bit 7
—
This warning flag goes high when the lower
limit of the MON3 setting is violated.
6
—
—
0
MON3lo
5
—
—
—
—
—
—
—
—
R/W
—
—
—
—
—
—
0
0
X
—
—
—
—
—
—
—
—
—
—
—
—
—
4
X
3
—
0
X
2
—
0
X
1
—
0
X
76 to 7E
SRAM
SRAM
—
—
—
0
Reserved
7F
Bit 7
6
Table select
X
X
X
X
X
X
—
0
5
—
0
4
—
0
3
—
0
2
—
0
Set bits = 00 to select Table 00, set bits = 01
to select Table 01, set bits = 10 to select
Table 02, set bits = 11 to select Table 03.
1
0
—
—
—
—
0
0
Table select bits
18
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 01h
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
NAME OF
LOCATION
R/W
FUNCTION
80
Bit 7
6
SRAM
—
R/W
—
Mode
—
—
—
—
—
—
—
0
0
0
0
0
0
X
X
X
X
X
X
—
—
5
—
—
4
—
—
3
—
—
2
—
—
If TEN = 0, the resistors can be controlled manually. The
user sets the resistor in manual mode by writing to
addresses 82h and 83h in Table 01 to control resistors 0
and 1, respectively.
1
—
—
1
TEN
AEN
AEN = 0 is a test mode setting and provides manual
control of the temperature index (Table 01, address 81h).
0
—
—
R
1
This byte is the temperature-calculated index used to
select the address of resistor settings in the look-up
tables (Tables 02 and 03, addresses 80h through C7h).
Temperature
index
81
SRAM
—
82
83
SRAM
SRAM
SRAM
R/W
R/W
—
FF
FF
—
Resistor 0
Resistor 1
Reserved
Resistor 0 position values from 00h to FFh.
Resistor 1 position values from 00h to FFh.
—
84 to 87
This byte configures a maskable interrupt, determining
which event asserts a buffer 1 output (MINT set to 1, see
register 89h in Table 01). If any combination of
88
EEPROM
R/W
Interrupt enable
temperature, V , MON1, MON2, or MON3 is desired to
CC
generate an interrupt, the corresponding bits are set to 1.
If interrupt generation is not desired, set all bits to 0.
Bit 7
6
—
—
—
1
1
1
1
1
0
0
0
TMP
—
—
—
—
—
—
—
—
—
—
—
V
CC
5
—
—
MON1
4
—
—
MON2
3
—
—
MON3
2
—
—
X
1
—
—
—
X
0
—
X
89
Bit 7
6
EEPROM
—
R/W
—
Configuration
0
0
X
X
—
—
____________________________________________________________________ 19
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 01h (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
NAME OF
LOCATION
R/W
—
FUNCTION
Controls if the device responds to one or two device
addresses (see the Memory Description section and
Table 5).
5
4
—
—
0
0
ADEN
ADFIX
Controls the means by which Main and Auxiliary Device
addresses are set (see the Memory Description section
and Table 5).
—
Controls auxiliary write protect. See the Memory
Description section.
3
2
1
—
—
—
—
—
—
0
0
0
APEN
MPEN
INV1
Controls main write protect. See the Memory Description
section.
Configures buffer 1 with OUT1 = MINT +
(INV1 [XOR] IN1).
0
—
—
—
0
INV2
Configures buffer 2 with OUT2 = INV2 [XOR] IN2.
8A to 8B
EEPROM
—
Reserved
Contains Main Device address if the bit ADFIX = 1. If
ADFIX = 0, then address A2h is used.
8C
8D
EEPROM
EEPROM
R/W
—
A2
—
Device address
Reserved
—
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
8E
EEPROM
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
MON1
MON1
MON1
—
Right Shift Control MSB
Right Shift Control LSB
Right Shift Control MSB
Right Shift Control LSB
2
1
0
MON2
MON2
MON2
2
1
0
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
8F
EEPROM
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
MON3
MON3
MON3
—
Right Shift Control MSB
Right Shift Control LSB
2
1
0
—
—
—
20
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 01h (continued)
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
NAME OF
LOCATION
R/W
FUNCTION
90 to 91
92 to 93
EEPROM
EEPROM
—
0
Reserved
Gain registers for internal calibration. See the Internal
Calibration section.
R/W
Gain Cal V
CC
94 to 95
96 to 97
98 to 99
9A to 9F
A0 to A1
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
R/W
R/W
R/W
—
Gain Cal Mon1
Gain Cal Mon2
Gain Cal Mon3
Reserved
—
Reserved
Factory
Programmed
Offset registers for internal calibration.
See the Internal Calibration section.
A2 to A3
EEPROM
R/W
Offset Cal V
CC
A4 to A5
A6 to A7
A8 to A9
AA to AD
AE to AF
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
R/W
R/W
R/W
—
Offset Cal Mon1
Offset Cal Mon2
Offset Cal Mon3
Reserved
R/W
Offset Cal Tmp
Offset calibration for temperature calibrated at factory.
Table 02h
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
80 to C7
F0 to F7
EEPROM
EEPROM
R/W
—
FF
—
Resistor 0 Temp LUT
Look-up table for Resistor 0.
—
Reserved
Factory
Programmed
Calibration constants for Resistor 0.
(See Table 8)
F8 to FF
EEPROM
R
Resistor 0 Cal Constants
Table 03h
MEMORY
LOCATION
(hex)
DEFAULT
SETTING
(hex)
EEPROM/
SRAM
R/W
NAME OF LOCATION
FUNCTION
80 to C7
F0 to F7
EEPROM
EEPROM
R/W
—
FF
—
Resistor 1 Temp LUT
Reserved
Look-up table for Resistor 1.
—
Factory
Programmed
Calibration constants for Resistor 1.
(See Table 8)
F8 to FF
EEPROM
R
Resistor 1 Cal Constants
____________________________________________________________________ 21
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Programming the Look-up Table (LUT)
The following equation can be used to determine which
M6
resistor position setting, 00h to FFh, should be written in
the LUT to achieve a given resistance at a specific tem-
perature.
M5
DECREASING
TEMPERATURE
2
⎡
⎣
⎤
R − u• 1+ v • C − 25 + w • C − 25
(
)
(
)
M4
M3
M2
M1
⎢
⎥
⎦
pos α,R,C =
− α
(
)
2
⎡
⎤
x • 1+ y • C − 25 + z • C − 25
( ) )
(
)
(
⎢
⎥
α = 3.852357 for the 20kΩ resistor
α = 4.5680475 for the 50kΩ resistor
R = the resistance desired at the output terminal
INCREASING
TEMPERATURE
C = temperature in degrees Celsius
u, v, w, x , x , y, and z are calculated values found in the
1
0
corresponding look-up tables. The variable x from the
2
4
6
8
10
12
equation above is separated into x (the MSB of x) and x
1
0
TEMPERATURE (°C)
(the LSB of x). Their addresses and LSB values are given
below. Resistor 0 variables are found in Table 1, and
Resistor 1 variables are found in Table 2.
Figure 4. Look-Up Table Hysteresis
When shipped from the factory, all other memory loca-
tions in the LUTs are programmed to FFh.
assume that the LSB of the lowest weighted bit is
50µV, then the FS value is 65,535 x 50µV = 3.27675V).
Table 8. Calibration Constants
A binary search is used to scale the gain of the con-
verter. This requires forcing two known voltages to the
input pin. It is preferred that one of the forced voltages
is the null input and the other is 90% of FS. Since the
LSB of the least significant bit in the digital reading reg-
ister is known, the expected digital results are also
known for both inputs (null/LSB = CNT1 and 90%FS/
LSB = CNT2).
ADDRESS (Hex)
VARIABLE
LSB
0
F8
F9
FA
FB
FC
FD
FE
FF
u
v
2
20E-6
100-9
w
1
x
x
2
1
0
-7
2
The user might not directly force a voltage on the input.
Instead they have a circuit that transforms light, fre-
quency, power, or current to a voltage that is the input
to the DS1859. In this situation, the user does not need
to know the relationship of voltage to expected digital
result but instead knows the relationship of light, fre-
quency, power, or current to the expected digital result.
y
2E-6
10E-9
—
z
Reserved
Internal Calibration
The DS1859 has two methods for scaling an analog
input to a digital result. The two methods are gain and
offset. Each of the inputs (V , MON1, MON2, and
CC
MON3) has a unique register for the gain and the offset
found in Table 01h, 92h to 99h, and A2h to A9h.
To scale the gain and offset of the converter for a spe-
cific input, you must first know the relationship between
the analog input and the expected digital result. The
input that would produce a digital result of all zeros is
the null value (normally this input is GND). The input
that would produce a digital result of all ones is the full-
scale (FS) value. The FS value is also found by multiply-
ing an all-ones digital answer by the weighted LSB
(e.g., since the digital reading is a 16-bit register, let us
22
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
An explanation of the binary search used to scale the
gain is best served with the following example pseudo-
code:
The calculated offset is now written to the DS1859 and
the gain and offset scaling is now complete.
Right-Shifting A/D Conversion Result
(Scalable Dynamic Ranging)
/* Assume that the Null input is 0.5V. */
/* In addition, the requirement for LSB is 50µV. */
The right-shifting method is used to regain some of the
lost ADC range of a calibrated system. If a system is
calibrated such that the maximum expected input
results in a digital output value of less than 7FFFh (1/2
FS), then it is a candidate for using the right-shifting
method.
FS = 65535 x 50E-6;
CNT1 = 0.5 / 50E-6;
/* 3.27675 */
/* 10000 */
CNT2 = 0.90 x FS / 50E-6;
/* 58981.5 */
/* Thus the null input 0.5V and the 90% of FS input is
2.949075V. */
If the maximum desired digital output is less than 7FFFh,
then the calibrated system is using less than 1/2 of the
ADC’s range. Similarly, if the maximum desired digital
output is less than 1FFFh, then the calibrated system is
only using 1/8 of the ADC’s range. For example, if using
a zero for the right-shift during internal calibration and
the maximum expected input results in a maximum digi-
tal output less than 1FFCh, only 1/8 of the ADC’s range is
used. If left like this, the three MS bits of the ADC will
never be used. In this example, a value of 3 for the right-
shifting will maximize the ADC range. No resolution is
lost since this is a 12-bit converter that is left justified.
The value can be right-shifted four times without losing
resolution. Table 9 shows when the right-shifting method
can be used.
Set the trim-offset-register to zero;
Set Right-Shift register to zero (typically zero.
See Right-Shifting section);
gain_result = 0h;
Clamp = FFF8h/2^(Right_Shift_Register);
For n = 15 down to 0
begin
gain_result = gain_result + 2^n;
Force the 90% FS input (2.949075V);
Meas2 = read the digital result from
the part;
If Meas2 >= Clamp then
gain_result = gain_result – 2^n;
Else
Table 9. Right Shifting
OUTPUT RANGE USED
WITH ZERO RIGHT-SHIFTS
NUMBER OF
RIGHT-SHIFTS NEEDED
Force the null input (0.5V);
0h .. FFFFh
0h .. 7FFFh
0h .. 3FFFh
0h .. 1FFFh
0h .. 0FFFh
0
1
2
3
4
Meas1 = read the digital result from
the part;
if (Meas2 – Meas1) > (CNT2 –
CNT1) then
gain_result = gain_result – 2^n;
end;
Memory Protection
Set the gain register to gain_result;
Memory access from either device address can be
either read/write or read only. Write protection
is accomplished by a combination of control bits in
EEPROM (APEN and MPEN in configuration register
89h) and a write-protect enable (WPEN) pin. Since the
WPEN pin is often not accessible from outside the mod-
ule, this scheme effectively allows the module to be
locked by the manufacturer to prevent accidental writes
by the end user.
The gain register is now set and the resolution of the
conversion will best match the expected LSB. The next
step is to calibrate the offset of the DS1859. With the
correct gain value written to the gain register, again
force the null input to the pin. Read the digital result
from the part (Meas1). The offset value is equal to the
negative value of Meas1.
Separate write protection is provided for the Auxiliary
and Main Device address through distinct bits APEN
and MPEN. APEN and MPEN are bits from configura-
tion register 89h, Table 01. Due to the location, the
APEN and MPEN bits can only be written through the
Meas1
2
⎡
⎤
Offset_Register= 4000h−
XOR 4000h
[
]
⎢
⎥
⎦
⎣
____________________________________________________________________ 23
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Main Device address. The control of write privileges
through the Auxiliary Device address depends on the
value of APEN. Care should be taken with the setting of
MPEN, once set to a 1, assuming WPEN is high.
Access through the Main Device is thereafter denied
unless WPEN is taken to a low level. By this means,
inadvertent end-user write access can be denied.
age window (between POD and the EEPROM recall)
regardless of the programmed state of ADEN.
Furthermore, as the device powers up, the V lo alarm
CC
flag (bit 4 of 70h in Main Device) defaults to a 1 until the
first V
analog-to-digital conversion occurs and sets or
CC
clears the flag accordingly.
2-Wire Operation
Main Device address space 60h to 7Fh is SRAM and is
not write protected by APEN, MPEN, or WPEN. For
example, the user may reset flags set by the device.
Note that in single device mode (ADEN bit = 1), APEN
determines the protection level of Table 00, indepen-
dent of WPEN.
Clock and Data Transitions: The SDA pin is normally
pulled high with an external resistor or device. Data on
the SDA pin may only change during SCL-low time
periods. Data changes during SCL-high periods will
indicate a START or STOP condition depending on the
conditions discussed below. See the timing diagrams
in Figures 5 and 6 for further details.
The write-protect operation, for both Main and Auxiliary
Devices, is summarized in Tables 6 and 7.
START Condition: A high-to-low transition of SDA with
SCL high is a START condition that must precede any
other command. See the timing diagrams in Figures 5
and 6 for further details.
Temperature Conversion
The direct-to-digital temperature sensor measures tem-
perature through the use of an on-chip temperature
measurement technique with an operating range from
-40°C to +102°C. Temperature conversions are initiated
upon power-up, and the most recent conversion is
stored in memory locations 60h and 61h of the Main
STOP Condition: A low-to-high transition of SDA with
SCL high is a STOP condition. After a read or write
sequence, the stop command places the DS1859 into a
low-power mode. See the timing diagrams in Figures 5
and 6 for further details.
Device, which are updated every t
. Temperature
frame
conversions do not occur during an active read or write
to memory.
Acknowledge: All address and data bytes are trans-
mitted through a serial protocol. The DS1859 pulls the
SDA line low during the ninth clock pulse to acknowl-
edge that it has received each word.
The value of each resistor is determined by the tempera-
ture-addressed look-up table. The look-up table assigns
a unique value to each resistor for every 2°C increment
with a 1°C hysteresis at a temperature transition over the
operating temperature range (see Figure 4).
Standby Mode: The DS1859 features a low-power
mode that is automatically enabled after power-on,
after a STOP command, and after the completion of all
internal operations.
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until V
CC
Device Addressing: The DS1859 must receive an 8-bit
device address following a START condition to enable
a specific device for a read or write operation. The
address is clocked into this part MSB to LSB. The
address byte consists of either A2h or the value in
Table 01 8Ch for the Main Device or A0h for the
Auxiliary Device, then the R/W bit. This byte must
match the address programmed into Table 01 8Ch or
A0h (for the Auxiliary Device). If a device address
match occurs, this part will output a zero for one clock
cycle as an acknowledge and the corresponding block
of memory is enabled (see the Memory Organization
section). If the R/W bit is high, a read operation is initi-
ated. If the R/W is low, a write operation is initiated (see
the Memory Organization section). If the address does
not match, this part returns to a low-power mode.
exceeds the digital power-on-reset voltage (POD). At this
voltage, the digital circuitry, which includes the 2-wire
interface, becomes functional. However, EEPROM-
backed registers/settings cannot be internally read
(recalled into shadow SRAM) until V
exceeds the ana-
CC
log power-on-reset voltage (POA), at which time the
remainder of the device becomes fully functional. Once
V
CC
exceeds POA, the RDYB bit in byte 6Eh of the Main
Device memory is timed to go from a 1 to a 0 and indi-
cates when analog-to-digital conversions begin. If V
CC
ever dips below POA, the RDYB bit reads as a 1 again.
Once a device exceeds POA and the EEPROM is
recalled, the values remain active (recalled) until V falls
CC
below POD.
For 2-wire device addresses sourced from EEPROM
(ADFIX = 1), the device address defaults to A2h until V
CC
exceeds POA and the EEPROM values are recalled. The
Auxiliary Device (A0h) is always available within this volt-
24
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
sequence. The master must terminate the write cycle
with a STOP condition or the data clocked into the
DS1859 will not be latched into permanent memory.
Write Operations
After receiving a matching address byte with the R/W
bit set low, if there is no write protect, the device goes
into the write mode of operation (see the Memory
Organization section). The master must transmit an 8-
bit EEPROM memory address to the device to define
the address where the data is to be written. After the
byte has been received, the DS1859 transmits a zero
for one clock cycle to acknowledge the address has
been received. The master must then transmit an 8-bit
data word to be written into this address. The DS1859
again transmits a zero for one clock cycle to acknowl-
edge the receipt of the data. At this point, the master
must terminate the write operation with a STOP condi-
tion. The DS1859 then enters an internally timed write
The address counter rolls on a page during a write. The
counter does not count through the entire address
space as during a read. For example, if the starting
address is 06h and 4 bytes are written, the first byte
goes into address 06h. The second goes into address
07h. The third goes into address 00h (not 08h). The
fourth goes into address 01h. If more than 9 bytes or
more are written before a STOP condition is sent, the
first bytes sent are overwritten. Only the last 8 bytes of
data are written to the page.
Acknowledge Polling: Once the internally timed write
has started and the DS1859 inputs are disabled,
acknowledge polling can be initiated. The process
involves transmitting a START condition followed by the
device address. The R/W bit signifies the type of opera-
tion that is desired. The read or write sequence will only
be allowed to proceed if the internal write cycle has
completed and the DS1859 responds with a zero.
process t to the EEPROM memory. All inputs are dis-
w
abled during this byte write cycle.
Page Write
The DS1859 is capable of an 8-byte page write. A page
is any 8-byte block of memory starting with an address
evenly divisible by eight and ending with the starting
address plus seven. For example, addresses 00h
through 07h constitute one page. Other pages would
be addresses 08h through 0Fh, 10h through 17h, 18h
through 1Fh, etc.
Read Operations
After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. There are three read operations: current address
read, random read, and sequential address read.
A page write is initiated the same way as a byte write,
but the master does not send a STOP condition after
the first byte. Instead, after the slave acknowledges the
data byte has been received, the master can send up
to seven more bytes using the same nine-clock
Current Address Read
The DS1859 has an internal address register that main-
tains the address used during the last read or write
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERRED
CONDITION
Figure 5. 2-Wire Data Transfer Protocol
____________________________________________________________________ 25
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
Figure 6. 2-Wire AC Characteristics
operation, incremented by one. This data is maintained
as long as V is valid. If the most recent address was
the last byte in memory, then the register resets to the
first address.
The sequential read operation is terminated when the
master initiates a STOP condition. The master does not
respond with a zero.
CC
The following section provides a detailed description of
the 2-wire theory of operation.
Once the device address is clocked in and acknowl-
edged by the DS1859 with the R/W bit set to high, the
current address data word is clocked out. The master
does not respond with a zero, but does generate a
STOP condition afterwards.
2-Wire Serial-Port Operation
The 2-wire serial-port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device that receives data as a receiver.
The device that controls the message is called a mas-
ter. The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions. The DS1859 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL.
Timing diagrams for the 2-wire serial port can be found
in Figures 5 and 6. Timing information for the 2-wire
serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
Single Read
A random read requires a dummy byte write sequence to
load in the data byte address. Once the device and data
address bytes are clocked in by the master and acknowl-
edged by the DS1859, the master must generate another
START condition. The master now initiates a current
address read by sending the device address with the
R/W bit set high. The DS1859 acknowledges the device
address and serially clocks out the data byte.
Sequential Address Read
Sequential reads are initiated by either a current
address read or a random address read. After the mas-
ter receives the first data byte, the master responds
with an acknowledge. As long as the DS1859 receives
this acknowledge after a byte is read, the master can
clock out additional data words from the DS1859. After
reaching address FFh, it resets to address 00h.
The following bus protocol has been defined:
◆
Data transfer may be initiated only when the bus is
not busy.
◆
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
26
____________________________________________________________________
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
the data line while the clock line is high will be
interpreted as control signals.
(the command/control byte) to the slave. The
slave then returns an acknowledge bit. Next fol-
lows a number of data bytes transmitted by the
slave to the master. The master returns an
acknowledge bit after all received bytes other
than the last byte. At the end of the last received
byte, a not acknowledge can be returned.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data
line from high to low while the clock is high defines a
START condition.
The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended with
a STOP condition or with a repeated START condition.
Since a repeated START condition is also the beginning
of the next serial transfer, the bus is not released.
Stop data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the high period of the clock signal.
The data on the line can be changed during the low peri-
od of the clock signal. There is one clock pulse per bit of
data. Figures 5 and 6 detail how data transfer is accom-
plished on the 2-wire bus. Depending on the state of the
R/W bit, two types of data transfer are possible.
The DS1859 can operate in the following three modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware
after the slave (device) address and direction bit
have been received.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP con-
ditions is not limited and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
2) Slave Transmitter Mode: The first byte is
received and handled as in the slave receiver
mode. However, in this mode the direction bit
indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS1859,
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer.
Within the bus specifications, a standard mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS1859 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the byte
has been received. The master device must generate an
extra clock pulse, which is associated with this acknowl-
edge bit.
3) Slave Address: Command/control byte is the first
byte received following the START condition from
the master device. The command/control byte
consists of 4-bit control code. They are used by
the master device to select which of eight possi-
ble devices on the bus is to be accessed. When
reading or writing to the DS1859, the device-
select bits must match one of two valid device
addresses, 00h or the address registered in Table
01 location 8Ch. The last bit of the command/con-
trol byte (R/W) defines the operation to be per-
formed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The slave address can be set by the
EEPROM. Following the START condition, the
DS1859 monitors the SDA bus checking the
device type identifier being transmitted. Upon
receiving the 1010 control code, the appropriate
device address bits, and the read/write bit, the
slave device outputs an acknowledge signal on
the SDA line.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that
the SDA line is a stable low during the high period of the
acknowledge-related clock pulse. Setup and hold times
must be taken into account. A master must signal an end
of data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows
a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2) Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte
____________________________________________________________________ 27
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Chip Information
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
TRANSISTOR COUNT: 47,191
SUBSTRATE CONNECTED TO GROUND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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