DS1865T+T&R [MAXIM]
PON Triplexer Control and Monitoring Circuit; PON三工器控制及监测电路
| 型号： | DS1865T+T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PON Triplexer Control and Monitoring Circuit |
| 文件： | 总66页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 3/07
PON Triplexer Control and
Monitoring Circuit
General Description
Features
The DS1865 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) triplexer. It has an APC
loop with tracking-error compensation that provides the
reference for the laser driver bias current and a temper-
ature-indexed lookup table (LUT) that controls the mod-
ulation current. It continually monitors for high output
current, high bias current, and low and high transmit
power with its internal fast comparators to ensure that
laser shutdown for eye safety requirements are met with-
out adding external components. Six ADC channels
ꢀ Meets GEPON, BPON, and GPON Timing
Requirements for Burst-Mode Transmitters
ꢀ Bias Current Control Provided by APC Loop with
Tracking-Error Compensation
ꢀ Modulation Current is Controlled by a
Temperature-Indexed Lookup Table
ꢀ Laser Power Leveling from -6dB to +0dB
ꢀ Two 8-Bit Analog Outputs, One is Controlled by
MON4 Voltage for Video Amplifier Gain Control
monitor V , internal temperature, and four external
CC
monitor inputs (MON1–MON4) that can be used to meet
transmitter and video receive signal monitoring require-
ments. Two digital-to-analog converter (DAC) outputs
are available for biasing the video receiver channel, and
five digital I/O pins are present to allow additional moni-
toring and configuration.
ꢀ Internal Direct-to-Digital Temperature Sensor
ꢀ Six Analog Monitor Channels: Temperature, V
,
CC
MON1, MON2, MON3, and MON4
ꢀ Five Digital I/O Pins for Additional Control and
Monitoring Functions
ꢀ Comprehensive Fault Management System with
Applications
Optical Triplexers with GEPON, BPON, or GPON
Transceiver
Maskable Laser Shutdown Capability
ꢀ Two-Level Password Access to Protect
Calibration Data
ꢀ 120 Bytes of Password 1 Protected Nonvolatile
Memory
ꢀ 128 Bytes of Password 2 Protected Nonvolatile
Pin Configuration
Memory in Main Device Address
ꢀ 128 Bytes of Nonvolatile Memory Located at A0h
TOP VIEW
Slave Address
2
ꢀ I C-Compatible Interface for Calibration and
28 27 26 25 24 23 22
Monitoring
ꢀ Operating Voltage: 2.85V to 5.5V
ꢀ Operating Temperature Range: -40°C to +95°C
BEN
TX-D
TX-F
FETG
1
2
3
4
5
6
7
21
20
19
MOD
BIAS
V
CC
ꢀ Packaging: 28-Pin Lead-Free TQFN (5mm x 5mm
18 GND
x 0.8mm)
DS1865
V
M4DAC
17
16
15
CC
GND
N.C.
DAC1
Ordering Information
MON4
PART
TEMP RANGE
PIN-PACKAGE
8
9
10 11 12 13 14
28 TQFN-EP*
(5mm x 5mm x 0.8mm)
DS1865T+
-40°C to +95°C
28 TQFN-EP*
(5mm x 5mm x 0.8mm)
tape-and-reel
TQFN
(5mm x 5mm x 0.8mm)
DS1865T+T&R -40°C to +95°C
+Denotes lead-free package.
*EP = Exposed pad.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PON Triplexer Control and
Monitoring Circuit
ABSOLUTE MAXIMUM RATINGS
Voltage Range on MON1–MON4, BEN, BMD, and
Operating Temperature Range ...........................-40°C to +95°C
TX-D Pins Relative to Ground.................-0.5V to (V
+ 0.5V)
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 Specification
CC
(subject to not exceeding +6V)
Voltage Range on V , SDA, SCL, D0–D3, and
CC
TX-F Pins Relative to Ground ...............................-0.5V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
+2.85
0.7 x
TYP
MAX
UNITS
V
(Note 1)
+5.5
V
CC
High-Level Input Voltage
(SDA, SCL, BEN)
V
+
CC
V
V
V
V
V
IH:1
V
0.3
CC
Low-Level Input Voltage
(SDA, SCL, BEN)
0.3 x
V
-0.3
2.0
IL:1
V
CC
High-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
V
+
CC
V
IH:2
0.3
Low-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
V
-0.3
0.8
IL:2
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Notes 1, 2)
5
10
mA
CC
Output Leakage
(SDA, TX-F, D0, D1, D2, D3)
I
1
µA
V
LO
I
I
= 4mA
= 6mA
0.4
0.6
OL
Low-Level Output Voltage
(SDA, TX-F, FETG, D0, D1, D2, D3)
V
OL
OL
High-Level Output Voltage
(FETG)
V
0.4
-
CC
V
I
= 4mA
V
OH
OH
FETG Before Recall
(Note 3)
10
100
1
nA
µA
Input-Leakage Current
(SCL, BEN, TX-D, LOSI)
I
LI
Digital Power-On Reset
Analog Power-On Reset
POD
POA
1.0
2.1
2.2
V
V
2.75
2
_____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
ELECTRICAL CHARACTERISTICS (DAC1 and M4DAC)
(VCC = +2.85V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
DAC Output Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0
2.5
DAC Output Resolution
DAC Output Integral Nonlinearity
DAC Output Differential Nonlinearity
DAC Error
8
Bits
LSB
LSB
LSB
% FS
µV
-2
-1
+2
+1
T
= +25°C
-1.25
-2
+1.25
+2
A
DAC Temperature Drift
DAC Offset
V
= 2.85V to 3.6V
-20
-500
+20
+500
250
CC
Maximum Load
µA
Maximum Load Capacitance
pF
ANALOG INPUT CHARACTERISTICS (BMD, TXP-HI, TXP-LO, HBIAS)
(VCC = +2.85V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
BMD, TXP-HI, TXP-LO Full-Scale Voltage
HBIAS Full-Scale Voltage
BMD Input Resistance
Resolution
SYMBOL
CONDITIONS
MIN
TYP
2.5
1.25
50
MAX
UNITS
V
V
(Note 4)
APC
mA
35
65
kΩ
(Note 4)
8
Bits
%FS
LSB
LSB
%FS
Error
T
= +25°C (Note 5)
2
A
Integral Nonlinearity
Differential Nonlinearity
Temperature Drift
-1
-1
+1
+1
-2.5
+2.5
ANALOG OUTPUT CHARACTERISTICS
(VCC = +2.85V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
BIAS Current
Shutdown Current
SYMBOL
CONDITIONS
MIN
TYP
1.2
10
MAX
UNITS
mA
nA
I
(Note 1)
BIAS
I
I
100
1.4
BIAS
BIAS:OFF
Voltage at I
0.7
1.2
1.25
3
V
BIAS
MOD Full-Scale Voltage
MOD Output Impedance
V
(Note 6)
(Note 7)
V
MOD
kΩ
V
V
V
V
Error
T
A
= +25°C (Note 8)
-2.5
-3
+2.5
+3
%FS
LSB
LSB
%FS
MOD
MOD
MOD
MOD
Integral Nonlinearity
Differential Nonlinearity
Temperature Drift
-1
+1
-2
+2
_____________________________________________________________________
3
PON Triplexer Control and
Monitoring Circuit
ANALOG VOLTAGE MONITORING
(V
CC
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
610
1.6
MAX
UNITS
µV
Input Resolution
∆VMON
Supply Resolution
∆V
mV
CC
Input/Supply Accuracy
(MON1, MON2, MON3, MON4, V
% FS
(full scale)
A
At factory setting
0.25
30
0
0.5
45
5
CC
)
CC
Update Rate for MON1, MON2,
MON3, MON4 Temp, or V
t
ms
FRAME
CC
Input/Supply Offset
(MON1, MON2, MON3, MON4, V
V
(Note 14)
LSB
OS
)
CC
MON1, MON2,
MON3, MON4
2.5
Factory Setting
V
V
CC
6.5536
DIGITAL THERMOMETER
(V
CC
= 2.85V to 5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
Thermometer Error
SYMBOL
CONDITIONS
-40°C to +95°C
MIN
TYP
MAX
UNITS
T
3.0
°C
ERR
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK-TRIP)
(VCC = +2.85V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
PARAMETER
First MD Sample Following BEN
Remaining Updates During BEN
BEN High Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
(Note 9)
(Note 9)
FIRST
t
UPDATE
t
400
96
ns
ns
ms
µs
µs
µs
µs
BEN:HIGH
BEN Low Time
t
BEN:LOW
Output-Enable Time Following POA
BIAS and MOD Turn-Off Delay
BIAS and MOD Turn-On Delay
FETG Turn-On Delay
t
10
INIT
OFF
t
5
5
5
5
t
ON
t
FETG:ON
t
FETG:OFF
FETG Turn-Off Delay
BIAS
Samples
Binary Search Time
t
(Note 10)
5
13
75
SEARCH
ADC Round-Robin Time
t
ms
RR
4
_____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
2
I C AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, T = -40°C to +95°C, timing referenced to V
and V .) (See Figure 9.)
IH(MIN)
A
IL(MAX)
PARAMETER
SCL Clock Frequency
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
f
(Note 11)
400
SCL
Clock Pulse-Width Low
Clock Pulse-Width High
t
1.3
0.6
LOW
t
µs
HIGH
Bus-Free Time Between STOP and
START Condition
t
1.3
µs
BUF
Start Hold Time
Start Setup Time
Data in Hold Time
t
0.6
0.6
0
µs
µs
µs
HD:STA
t
SU:STA
t
0.9
HD:DAT
Data in Setup Time
t
100
ns
ns
ns
SU:DAT
Rise Time of Both SDA and SCL
Signals
20 +
t
R
(Note 12)
(Note 12)
300
300
0.1C
B
Fall Time of Both SDA and SCL
Signals
20 +
t
F
0.1C
B
STOP Setup Time
t
0.6
µs
pF
ms
SU:STO
Capacitive Load for Each Bus Line
EEPROM Write Time
C
(Note 12)
(Note 13)
400
20
B
t
W
NONVOLATILE MEMORY CHARACTERISTICS
(V
= +2.85V to +5.5V)
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
At +70°C
50,000
Note 1: All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2: Digital inputs are at rail. FETG is disconnected. SDA = SCL = V . DAC1 and M4DAC are not loaded.
CC
Note 3: See the Safety Shutdown (FETG) Output section for details.
Note 4: Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5: This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6: Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V.
Note 7: The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9: See the APC and Quick-Trip Shared Comparator Timing section for details.
Note 10: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be 1% within the time specified by the binary search time. See the Bias and MOD Output During
Power-Up section.
2
2
Note 11: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I C stan-
dard mode.
Note 12: C total capacitance of one bus line in picofarads.
B
Note 13: EEPROM write begins after a STOP condition occurs.
Note 14: Guaranteed by design.
_____________________________________________________________________
5
PON Triplexer Control and
Monitoring Circuit
Typical Operating Characteristics
(VCC = 3.3V, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
DAC1 AND M4DAC DNL
7.000
6.500
7.000
6.500
1.0
0.8
SDA = SCL = V
SDA = SCL = V
CC
CC
0.6
6.000
5.500
6.000
5.500
+95°C
0.4
V
= 5.5V
CC
0.2
0
5.000
4.500
5.000
4.500
-0.2
-0.4
-0.6
-0.8
-1.0
+25°C
V
= 2.85V
CC
-40°C
4.000
3.500
3.000
4.000
3.500
3.000
2.850 3.350 3.850 4.350
4.80
5.350
-40 -20
0
20
40
60
0
50
100
150
200
250
80
V
(V)
TEMPERATURE (°C)
DAC1 AND M4DAC POSITION (DEC)
CC
DAC1 AND M4DAC OFFSET VARIATION
vs. LOAD CURRENT
DAC1 AND M4DAC INL
DAC1 AND M4DAC OFFSET vs. V
CC
0.002
0
1.0
0.8
0.05
V
= 2.85V
CC
T
= -40°C TO +95°C
A
0.04
0.03
0.02
0.01
LOAD = -0.5mA TO +0.5mA
0.6
V
= 3.6V
-0.002
-0.004
CC
0.4
0.2
0
0
-0.01
-0.02
-0.03
-0.04
-0.05
V
= 5.0V
CC
-0.006
-0.008
-0.2
-0.4
-0.6
-0.8
-1.0
V
= 5.5V
CC
-0.010
-0.012
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5
0
50
100
150
200
250
2.85
3.35
3.85
4.35
(V)
4.85
5.35
LOAD CURRENT (mA)
DAC1 AND M4DAC POSITION (DEC)
V
CC
CALCULATED AND DESIRED % CHANGE
DESIRED AND CALCULATED CHANGE
DAC1 AND M4DAC OUTPUT
vs. LOAD CURRENT
IN V
vs. MOD RANGING
IN V
vs. COMP RANGING
MOD
BMD
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1.255
1.254
1.253
1.252
DESIRED VALUE
DESIRED VALUE
OUTPUT WITHOUT OFFSET
CALCULATED VALUE
CALCULATED VALUE
V
= 2.85V
CC
1.251
1.250
1.249
V
= 5.0V
CC
1.248
1.247
1.246
1.245
000 001 010 011 100 101 110 111
MOD RANGING VALUE (DEC)
000 001 010 011 100 101 110 111
COMP RANGING (DEC)
-0.5 -0.4 -0.3 -0.2 -0.1
0 0.1 0.2 0.3 0.4 0.5
LOAD CURRENT (mA)
6
_____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Typical Operating Characteristics (continued)
(VCC = 3.3V, T = +25°C, unless otherwise noted.)
A
MON1–MON4 INL
MON1–MON4 DNL
1.0
0.8
1.0
0.8
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
MON1–MON4 INPUT VOLTAGE (V)
MON1–MON4 INPUT VOLTAGE (V)
V
MOD
INL vs. MOD INDEX
V
BMD
INL vs. APC INDEX
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
50
100
150
200
250
0
50
100
150
200
250
MOD INDEX (DEC)
APC INDEX (DEC)
_____________________________________________________________________
7
PON Triplexer Control and
Monitoring Circuit
Pin Description
PIN
1
NAME
BEN
FUNCTION
Burst Enable Input. Triggers the sampling of the APC and quick-trip monitors.
Transmit Disable Input. Disables BIAS and MOD outputs.
Transmit Fault Output, Open Drain
2
TX-D
TX-F
3
4
FETG
Output to FET Gate. Signals an external n- or p-channel MOSFET to enable/disable the laser’s current.
5, 19
6, 18
V
Supply Voltage
Ground
CC
GND
7, 10, 11,
25
N.C.
No Connection
2
2
8
9
SDA
SCL
I C Serial Data. Input/output for I C data.
2
2
I C Serial Clock. Input for I C clock.
External Monitor Input 1–4. The voltage at these pins are digitized by the internal analog-to-digital
2
12–15
MON1–MON4 converter and can be read through the I C interface. Alarm and warning values can be assigned to
interrupt the processor based on the ADC result.
Digital-to-Analog Output DAC1 and M4DAC. Two 8-bit DAC outputs for generating analog voltages.
Typically used to control the video photodiode bias. M4DAC is controlled by the input voltage on MON4
and Table 06h LUT.
16
DAC1
17
20
M4DAC
BIAS
Bias Current Output. This current DAC generates the bias current reference for the MAX3643.
Modulation Output Voltage. This 8-bit voltage output has eight full-scale ranges from 1.25V to 0.3125V.
This pin is connected to the MAX3643’s VMSET input to control the modulation current.
21
MOD
22
23
BMD
LOSI
Monitor Diode Input (Feedback Voltage, Transmit Power Monitor)
2
Loss-of-Signal Input. This input is accessible in the status register through the I C interface.
Digital I/O 0. This signal is either the open-drain output driver for LOSI, or can be controlled by the
OUT0 bit (D0OUT). The logic level of this pin is indicated by the D0IN and LOS status bits.
24
D0
26, 27,
28
Digital I/O 1–3. These are bidirectional pins controlled by internally addressable bits. The outputs are
open-drain.
D1, D2, D3
EP
—
Exposed Pad. This contact should be connected to GND.
8
_____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Block Diagram
V
CC
DS1865 MEMORY ORGANIZATION
V
CC
MAIN MEMORY
EEPROM/SRAM
SDA
SCL
SRAM RESET
2
I C
ADC CONFIGURATION/RESULTS
SYSTEM STATUS BITS
ALARM/WARNING COMPARISON RESULTS/THRESHOLDS
INTERFACE
TABLE 01h (EEPROM)
TABLE 04h (EEPROM)
MODULATION LUT
EEPROM
128 BYTES AT
A0h SLAVE
ADDRESS
PW1 USER MEMORY, ALARM TRAP
TABLE 02h (EEPROM)
CONFIGURATION AND CALIBRATION
TABLE 05h (EEPROM)
APC LUT
POWER-ON ANALOG
> V
V
TABLE 03h (EEPROM)
PW2 USER MEMORY
TABLE 06h (EEPROM)
M4DAC (VIDEO GAIN LUT)
CC
V
CC
POA
NONMASKABLE
INTERRUPT
MON1
MON2
MON3
MON4
TX-F
INTERRUPT
MASK
INTERRUPT
LATCH
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
13-BIT
ADC
LATCH
ENABLE
TEMP
SENSOR
INTERRUPT
MASK
INTERRUPT
LATCH
FETG
SAMPLE
CONTROL
BIAS MAX
QUICKTRIP
BEN
MUX
BMD
HBIAS QUICK-
TRIP LIMIT
MUX
HTXP QUICK-
TRIP LIMIT
8-BIT DAC
W/SCALING
MUX
LTXP QUICK-
TRIP LIMIT
DIGITAL APC
INTEGRATOR
13-BIT
DAC
BIAS
MOD
APC SET POINT
FROM APC LUT
DS1865
8-BIT DAC
W/SCALING
MOD LUT
TX-D
D0
TTL
D0 IN/LOS STATUS
D0 OUT
INV LOSI
0
1
TTL
TTL
TTL
TTL
LOSI
D1
MUX LOSI
M4DAC
8-BIT, 2.5V
FULL SCALE
TABLE 06h
VIDEO POWER
LOOKUP TABLE
M4DAC
DAC1
D1 IN
2
D1 OUT
I C CONTROL
DAC1
8-BIT, 2.5V
FULL SCALE
2
I C PROGRAMMED
NONVOLATILE SETTING
D2
D3
D2 IN
D2 OUT
D3 IN
D3 OUT
GND
_____________________________________________________________________
9
PON Triplexer Control and
Monitoring Circuit
Typical Operating Circuit
3.3V
IN+
V
CC
IN-
OUT+
OUT-
BIAS-
BEN+
BEN-
DIS
MAX3643
BIAS+
MDIN
COMPACT BURST-MODE
LASER DRIVER
MDOUT
12V
SDA
SCL
TX-F
TX-D
LOSI
D0
BMD
MON1
MON2
MON3
MON4
FETG
2
3.3V
I C COMMUNICATION
FAULT OUTPUT
DISABLE INPUT
TRANSMIT POWER
RECEIVE POWER
DS1865
MAX3654
CATV
BURST-MODE
MONITOR/CONTROL CIRCUIT
FTTH CATV
RECEIVER LOS
TIA
OPEN-DRAIN LOS OUTPUT
D1
DAC1
ADDITIONAL
DIGITAL I/O
D2
M4DAC
D3
THERMISTOR
APD BOOST DC-DC
Table 1. Acronyms
Detailed Description
The DS1865 integrates the control and monitoring func-
tionality required to implement a PON system using
Maxim’s MAX3643 compact burst-mode laser driver.
The compact laser driver solution offers a considerable
cost benefit by integrating control and monitoring fea-
tures in the low-power CMOS process, while leaving
only the high-speed portions to the laser driver. Key
components of the DS1865 are shown in the Block
Diagram and described in subsequent sections. Table 1
contains a list of acronyms used in this data sheet.
ACRONYM
DEFINITION
ADC
APC
ATB
DAC
LUT
NV
Analog-to-Digital Converter
Average Power Control
Alarm Trap Bytes
Digital-to-Analog Converter
Lookup Table
Nonvolatile
PON
QT
Passive Optical Network
Quick Trip
APC Control
BIAS current is controlled by an average power control
(APC) loop. The APC loop uses digital techniques to
overcome the difficulties associated with controlling
burst-mode systems.
SEE
TE
Shadowed EEPROM
Tracking Error
TXP
Transmit Power
10
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
The APC loop’s feedback is the monitor diode (BMD)
current, which is converted to a voltage using an exter-
nal resistor. The feedback voltage is compared to an 8-
bit scaleable voltage reference that determines the
APC set point of the system. Scaling of the reference
voltage accommodates the wide range in photodiode
sensitivities. This allows the application to take full
advantage of the APC reference’s resolution.
All quick-trip alarm flags are masked until the binary
search is completed. However, the BIAS MAX alarm is
monitored during this time to prevent the bias output
from exceeding MAX IBIAS. During the bias current ini-
tialization, the bias current is not allowed to exceed
MAX IBIAS. If this occurs during the I
sequence,
STEP
the binary search routine begins. If MAX IBIAS is
exceeded during the binary search, the next smaller
step is activated. I
or binary increments that would
STEP
The DS1865 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The TE LUT (Table 05h) has 36
entries that determine the APC setting in 4°C windows
between -40°C to +100°C. Ranging of the APC DAC is
possible by programming a single byte in Table 02h.
cause I
to exceed MAX IBIAS are not taken.
BIAS
Masking the alarms until the completion of the binary
search prevents false trips during startup.
I
is programmed by the customer using the Startup
STEP
Step register. This value should be programmed to the
maximum safe current increase that is allowable during
startup. If this value is programmed too low, the DS1865
will still operate, but it could take significantly longer for
the algorithm to converge and hence to control the aver-
age power.
Modulation Control
The MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643’s VMSET input. An external
resistor to ground from the MAX3643’s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. Then
the MOD output’s scaling is used to calibrate the full-
scale (FS) modulation output to a particular laser’s
requirements. This allows the application to take full
advantage of the MOD output’s resolution. The modula-
tion LUT can be programmed in 2°C increments over the
-40°C to +102°C range.
If a fault is detected and TX-D is toggled to re-enable the
outputs, the DS1865 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1865 already has determined the present tem-
perature, so the t
time is not required for the DS1865
INIT
to recall the APC and MOD set points from EEPROM.
If the Bias-En bit (Table 02h, Register 80h) is written to
0, the BIAS DAC is manually controlled by the MAN
IBIAS register (Table 02h, Registers F8h–F9h).
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal oper-
BIAS and MOD Output
During Power-Up
On power-up, the modulation and bias outputs remain
ation, the outputs are disabled within t
. When TX-D
OFF
is deasserted (logic 0), the DS1865 turns on the MOD
output with the value associated with the present tem-
perature, and initializes the BIAS using the same
search algorithm used at startup. When asserted, the
soft TX-D (Lower Memory, Register 6Eh) offers a soft-
ware control identical to the TX-D pin (see Figure 2).
off until V
is above V
and a temperature conver-
POA
CC
sion has been completed. If the V
LO ADC alarm is
CC
enabled, then a V
defined V
conversion above the customer-
CC
low alarm level is required before the
CC
outputs are enabled with the value determined by the
temperature conversion and the modulation LUT.
APC and Quick-Trip Shared
Comparator Timing
When the MOD output is enabled and BEN is high, the
BIAS output is turned on to a value equal to I
(see
As shown in Figure 3, the DS1865’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP-HI, TXP-LO, and BIAS HI). The
comparator polls the alarms in a round-robin multi-
plexed sequence. Six of every eight comparator read-
ings are used for APC loop-bias current control. The
other two updates are used to check the HTXP/LTXP
(monitor diode voltage) and the HBIAS (MON1) signals
against the internal APC and BIAS reference. The
HTXP/LTXP comparison checks HTXP to see if the last
STEP
Figure 1). The startup algorithm checks if this bias cur-
rent causes a feedback voltage above the APC set point,
and if it does not it continues increasing the BIAS by
I
until the APC set point is exceeded. When the APC
STEP
set point is exceeded, the DS1865 begins a binary
search to quickly reach the bias current corresponding
to the proper power level. After the binary search is com-
pleted the APC integrator is enabled, and single LSB
steps are taken to tightly control the average power.
____________________________________________________________________ 11
PON Triplexer Control and
Monitoring Circuit
V
POA
V
CC
t
INIT
V
MOD
t
SEARCH
4x I
STEP
APC
INTEGRATOR
ON
3x I
STEP
BINARY SEARCH
I
BIAS
2x I
STEP
I
STEP
BIAS
SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. Power-Up Timing
edge of BEN. The internal clock is asynchronous to BEN,
causing a 50ns uncertainty regarding when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples occur on a regular interval,
TX-D
t
ON
I
t
t
. Table 2 shows the sample rate options available.
BIAS
OFF
REP
t
V
ON
MOD
t
OFF
Table 2. Update Rate Timing
MINIMUM TIME
FROM BEN TO
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SR –SR
3
0
Figure 2. TX-D Timing (Normal Operating Conditions)
FIRST SAMPLE
(t 50ns
)
SAMPLE (t
)
FIRST
REP
bias update comparison was above the APC set point,
and checks LTXP to see if the last bias update compari-
son was below the APC set point. Depending on the
results of the comparison, the corresponding alarms
and warnings (TXP-HI, TXP-LO) are asserted or
deasserted.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b*
350ns
550ns
800ns
1200ns
1600ns
2000ns
2800ns
3200ns
3600ns
4400ns
6000ns
6400ns
750ns
950ns
1350ns
1550ns
1750ns
2150ns
2950ns
3150ns
The DS1865 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable
for burst-mode transmitter data rates between 155Mbps
and 1250Mbps. The rising edge of the burst enable
(BEN) triggers the sample to occur, and the Update Rate
register (Table 02h, Register 88h) determines the sam-
*All codes greater than 1001b (1010b–1111b) use the maximum
sample time of code 1001b.
pling time. The first sample occurs t
after the rising
FIRST
12
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PON Triplexer Control and
Monitoring Circuit
t
FIRST
BEN
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
LAST BURST'S
BIAS SAMPLE
BIAS DAC CODE
t
REP
HTXP/LTXP
SAMPLE
HBIAS
SAMPLE
QUICK-TRIP
SAMPLE TIMES
Figure 3. APC and Quick-Trip Alarm Sample Timing
Updates to the TXP-HI, TXP-LO, and BIAS HI quick-trip
alarms do not occur during the burst-enable low time.
Any quick-trip alarm that is detected by default remains
active until a subsequent comparator sample shows the
condition no longer exists.
current is above specification. I
is not allowed to
BIAS
exceed the value set in the MAX IBIAS register. When
the DS1865 detects that the bias is at the limit, it sets the
BIAS MAX status bit and holds the bias current at the
MAX IBIAS level. The quick-trips are routed to the TX-F
and FETG outputs through interrupt masks to allow com-
binations of these alarms to be used to trigger these out-
puts. When FETG is triggered, the DS1865 also disables
the MOD and BIAS outputs. See the BIAS and MOD
Output During Power-Up section for details.
A second bias-current monitor (BIAS MAX) compares
the DS1865’s BIAS DAC’s code to a digital value stored
in the MAX IBIAS register. This comparison is made
every bias-current update to ensure that a high bias
current is quickly detected.
Six ADC Monitors And Alarms
Monitors and Fault Detection
The ADC monitors six channels that measure tempera-
Monitors
Monitoring functions on the DS1865 include four quick-
trip comparators and six ADC channels. This monitor-
ing, combined with the interrupt masks, determines
when/if the DS1865 shuts down its outputs and triggers
the TX-F and FETG outputs. All the monitoring levels
and interrupt masks are user programmable.
ture (internal temp sensor), V , MON1, MON2, MON3,
CC
and MON4 using an analog multiplexer to measure
them round-robin with a single ADC. Each channel has
a customer-programmable full-scale range and offset
value that is factory programmed to a default value (see
Table 3). Additionally, MON1–MON4 can right shift
results by up to 7 bits before the results are compared
2
to alarm thresholds or read over the I C bus. This
Four Quick-Trip Monitors and Alarms
Four quick-trip monitors are provided to detect potential
laser safety issues. These monitor:
allows customers with specified ADC ranges to cali-
brate the ADC full scale to a factor of 1/2n of their spec-
ified range to measure small signals. The DS1865 can
then right shift the results by n bits to maintain the bit
weight of their specification.
1) High Bias Current (HBIAS)
2) Low Transmit Power (LTXP)
3) High Transmit Power (HTXP)
4) Max Output Current (MAX IBIAS)
Table 3. ADC Default Monitor Full-Scale
Ranges
The high and low transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick-trip com-
pares the MON1 input (generally from the MAX3643
bias monitor output) against its threshold setting to
determine if the present bias current is above specifica-
tion. The BIAS MAX quick-trip is a digital comparison
that determines if the BIAS DAC indicates that the bias
+FS
SIGNAL
+FS
HEX
-FS
SIGNAL
SIGNAL (UNITS)
-FS HEX
Temperature (oC)
127.996
6.5528
7FFF
FFF8
-128
0V
8000
0000
V
(V)
CC
MON1–MON4 (V)
2.4997
FFF8
0V
0000
____________________________________________________________________ 13
PON Triplexer Control and
Monitoring Circuit
The ADC results (after right shifting, if used) are com-
pared to high alarm thresholds, low alarm thresholds,
and the warning threshold after each conversion, and
the corresponding alarms are set, which can be used
to trigger the TX-F or FETG outputs. These ADC thresh-
olds are user programmable, as are the masking regis-
ters that can be used to prevent the alarms from
triggering the TX-F and FETG outputs.
ations are allowed and are executed as a part of every
conversion before the results are compared to the high
and low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
62h–6Bh). This is true during the setup of internal cali-
bration as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the six ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable through the TX-F mask to cause TX-F to
assert. All alarms, with the exception of FETG, only
cause TX-F to remain active while the alarm condition
persists. However, the TX-F latch bit can enable the TX-F
output to remain active until it is cleared by the TX-F
reset bit, TX-D, soft TX-D, or by power cycling the part. If
the FETG output is configured to trigger TX-F, it indicates
that the DS1865 is in shutdown, and requires TX-D, soft
TX-D, or cycling power to reset. The QT alarms are
masked until the completion of the binary search. Only
enabled alarms will activate TX-F. See Figure 5.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4. The
total time required to convert all six channels is t (see
RR
Timing Characteristics (Control Loop and Quick-Trip)
for details).
Right Shifting ADC Result
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale value defined by a
standard’s specification, then right shifting can be used
to adjust the predetermined full-scale analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1865’s range is wide enough to cover all
requirements; when the maximum input value is far
short of the FS value, right shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8th the specified predetermined full-
scale value, so only 1/8th the converter’s range is used.
An alternative is to calibrate the ADC’s full-scale range
to 1/8th the readable predetermined full-scale value
and use a right-shift value of 3. With this implementa-
tion, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
Table 4 shows TX-F as a function of TX-D and the alarm
sources.
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
the FETG output is always latched in case it is triggered
by an unmasked alarm condition. Its output polarity is
programmable to allow an external nMOSFET or
pMOSFET to open during alarms to shut off the laser
diode current. If the FETG output triggers, indicating that
the DS1865 is in shutdown, it requires TX-D, soft TX-D, or
cycling power to be reset. Under all conditions, when the
analog outputs are reinitialized after being disabled, all
The right-shift operation on the ADC result is carried out
based on the contents of Right Shift Control registers
(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four ana-
log channels, MON1–MON4, each have 3 bits allocated
to set the number of right shifts. Up to 7 right-shift oper-
the alarms with the exception of the V
low ADC alarm
CC
are cleared. The V
low alarm must remain active to
CC
prevent the output from attempting to operate when
ONE ROUND-ROBIN ADC CYCLE
MON4
TEMP
VCC
MON1
MON2
MON3
MON4
TEMP
VCC
t
RR
NOTE: AT POWER-UP, IF THE V LOW ALARM IS SET FOR EITHER THE TX-F OR FETG OUTPUT, THE ADC ROUND-ROBIN
CC
TIMING CYCLES BETWEEN TEMP AND V ONLY UNTIL V IS ABOVE THE V LOW THRESHOLD.
CC
CC
CC
Figure 4. ADC Round-Robin Timing
14
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PON Triplexer Control and
Monitoring Circuit
TX-F LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
TX-F NON LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-F
Figure 5. TX-F Timing
Determining Alarm Causes
Table 4. TX-F as a Function of TX-D and
Alarm Sources
2
Using the I C Interface
To determine the cause of the TX-F or FETG alarm, the
NONMASKED
system processor can read the DS1865’s Alarm Trap
V
CC
> V
TX-D
TX-F
POA
2
TX-F ALARM
Bytes (ATB) through the I C interface (in Table 01h). The
ATB has a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1865 sets the
corresponding bit in the ATB. Active ATB bits remain set
No
Yes
Yes
Yes
X
0
0
1
X
0
1
X
1
0
1
0
2
until written to zeros through the I C interface. On power-
up, the ATB is zeros until alarms dictate otherwise.
Die Identification
The DS1865 has an ID hard coded to its die. Two regis-
ters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h reads 65h to identify the part as the
DS1865, byte 87h reads the die revision.
inadequate V
exists to operate the laser driver. Once
CC
adequate V
is present to clear the V
low alarm, the
CC
CC
outputs are enabled following the same sequence as the
power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOSFET or
pMOSFET. This requires that the FETG output can sink
or source current. Because the DS1865 does not know
Low-Voltage Operation
The DS1865 contains two power-on reset (POR) levels.
The lower level is a digital POR (V
) and the higher
POD
level is an analog POR (V
). At startup, before the
POA
if it should sink or source current before V
exceeds
CC
supply voltage rises above V
, the outputs are dis-
POA
V
, which triggers the EE recall, this output will
POA
abled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM), and all analog circuitry is dis-
be high impedance when V
is below V
(see the
POA
CC
Low-Voltage Operation section for details and
diagram). The application circuit must use a pullup or
pulldown resistor on this pin that pulls FETG to the
alarm/shutdown state (high for a pMOS, low for a
abled. When V
reaches V
, the SEE is recalled,
POA
CC
and the analog circuitry is enabled. While V
remains
CC
above V
, the device is in its normal operating state,
POA
nMOS). Once V
is above V
, the DS1865 pulls the
CC
POA
and it responds based on its nonvolatile configuration.
If during operation V falls below V but is still
FETG output to the state determined by the FETG DIR
bit (Table 02h, Register 89h). FETG DIR is 0 if an nMOS
is used and 1 if a pMOS is used.
CC
POA
above V
, the SRAM retains the SEE settings from
POD
____________________________________________________________________ 15
PON Triplexer Control and
Monitoring Circuit
DETECTION OF
FETG FAULT
TX-D
t
t
ON
ON
t
t
I
OFF
BIAS
V
MOD
OFF
t
t
FETG:ON
FETG:OFF
FETG*
*FETG DIR = 0
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected)
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
until V
exceeds V
allowing the device address to
CC
POA
be recalled from the EEPROM.
MOD AND
BIAS
OUTPUTS
V
V
>
POA
NONMASKED
FETG ALARM
CC
TX-D
FETG
Power-On Analog (POA)
POA holds the DS1865 in reset until V is at a suitable
CC
Yes
Yes
Yes
0
0
1
0
1
X
FETG DIR
FETG DIR
FETG DIR
Enabled
Disabled
Disabled
level (V
> V
) for the part to accurately measure
CC
POA
with its ADC and compare analog signals with its quick-
trip monitors. Because V cannot be measured by the
CC
ADC when V
CC
is less than V
low alarm, which is cleared by a V
sion greater than the customer-programmable V
, POA also asserts the
CC
POA
V
ADC conver-
CC
the first SEE recall, but the device analog is shut down
and the outputs are disabled. FETG is driven to its
alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
low
CC
ADC limit. This prevents the TX-F and FETG outputs
from glitching during a slow power-up. The TX-F and
FETG outputs do not latch until there is a conversion
above V
, the device immediately resumes normal
above V
low limit.
POA
CC
functioning. If the supply voltage falls below V
, the
POD
The POA alarm is nonmaskable. The TX-F and FETG
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
outputs are asserted when V
is below V
. See the
CC
POA
Low-Voltage Operation section for more information.
The EEPROM recall occurs the next time V
POA
voltage varies.
exceeds
CC
V
. Figure 7 shows the sequence of events as the
DAC1 Output
The DAC1 output has a 0 to 2.5V range, 8 bits of resolu-
2
tion, and is programmed through the I C interface. The
2
Any time V
is above V
, the I C interface can be
CC
POD
DAC1 setting is nonvolatile and password 2 (PW2) pro-
tected.
used to determine if V
is below the V
level. This is
CC
POA
accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
M4DAC Output
The M4DAC output has a 0 to 2.5V range, 8 bits of res-
olution, and is controlled by an LUT indexed by the
MON4 voltage. The M4DAC LUT (Table 06h) is non-
volatile and PW2 protected. See the Memory
Organization section for details.
V
CC
is below V
. When V
rises above V , RDYB
POA
POA
CC
is timed (within 500µs) to go to 0, at which point the part
is fully functional.
16
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
SEE RECALL
SEE RECALL
V
POA
V
CC
V
POD
HIGH
NORMAL
OPERATION
DRIVEN TO
FETG DIR
HIGH
NORMAL
OPERATION
NORMAL
HIGH
DRIVEN TO
FETG DIR
DRIVEN TO
FETG DIR
FETG
SEE*
IMPEDANCE
IMPEDANCE
OPERATION
IMPEDANCE
PRECHARGED
TO 0
RECALLED
VALUE
PRECHARGED
TO 0
RECALLED
VALUE
PRECHARGED
TO 0
*SEE = SHADOWED EEPROM
Figure 7. Low-Voltage Hysteresis Example
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
Digital I/O Pins
Five digital I/O pins are provided for additional monitor-
ing and control of the triplexer. By default the LOSI pin
is used to convert a standard comparator output for
loss of signal (LOSI) to an open-collector output. This
means the mux shown on the block diagram by default
selects the LOSI pin as the source for the D0 output
transistor. The level of the D0 pin can be read in the
status byte (Lower Memory, Register 6Eh) as the LOS
status bit. The LOS status bit reports back the logic
level of the D0 pin, so an external pullup resistor must
be provided for this pin to output a high level. The LOSI
signal can be inverted before driving the open-drain
output transistor using the XOR gate provided. The
mux LOSI allows the D0 pin to be used identically to the
D1, D2, and D3 pins. However, the mux setting (stored
Memory Organization
The DS1865 features eight banks of memory composed
of the following.
The Lower Memory is addressed from 00h to 7Fh
and contains alarm and warning thresholds, flags,
masks, several control registers, password entry
area (PWE), and the table select byte. The table
select byte determines which table (01h–06h) will be
mapped into the upper memory locations, namely
80h–FFh (unless stated otherwise).
Table 01h primarily contains user EEPROM (with
PW1 level access) as well as some alarm and warn-
ing status bytes.
in the EEPROM) does not take effect until V
> V
,
POA
CC
Table 02h is a multifunction space that contains
configuration registers, scaling and offset values,
passwords, interrupt registers, as well as other mis-
cellaneous control bytes.
allowing the EEPROM to recall. This requires the LOSI
pin to be grounded for D0 to act identical to the D1, D2,
and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high logic levels. The levels of these input pins
can be read by reading the DIN byte (Lower Memory,
Register 79h), and the open-drain outputs can be con-
trolled using the DOUT byte (Lower Memory, Register
Table 03h is strictly user EEPROM that is protected
by a PW2 level access.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation
LUT can be programmed in 2°C increments over the
-40°C to +102°C range. This register is protected by
a PW2 level access.
78h). When V
ance. Once V
< V
, these outputs are high imped-
, the outputs go to the power-on
CC
CC
POA
≥ V
POA
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM determined default state of the pin
can be modified with PW2 access. After the default state
has been recalled, the SRAM registers controlling out-
puts can be modified without password access. This
Table 05h contains another LUT, which allows the
APC set point to change as a function of tempera-
ture to compensate for tracking error (TE). This TE
LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C to +100°C. This reg-
ister is protected by a PW2 level access.
____________________________________________________________________ 17
PON Triplexer Control and
Monitoring Circuit
2
2
I C SLAVE ADDRESS A0h
00h
I C SLAVE ADDRESS A2h (DEFAULT)
DEC HEX
0
0
00h
AUXILLARY MEMORY
LOWER MEMORY
EEPROM
DIGITAL DIAGNOSTIC
FUNCTIONS
PASSWORD ENTRY (PWE)
(4 BYTES)
7Fh
TABLE SELECT BYTE 7Fh
127 7F
128 80
80h
80h
80h
80h
80h
80h
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 04h
TABLE 05h
TABLE 06h
PW1 LEVEL ACCESS
EEPROM
(120 BYTES)
CONFIGURATION AND
CONTROL
PW2 LEVEL ACCESS
EEPROM
(128 BYTES)
MODULATION LUT
APC LUT
M4DAC LUT
A7h
9Fh
C7h
C7h
C8h
NO MEMORY
F7h
FFh
F7h
FFh
F8h
F8h
ATB
MISC. CONTROL
BITS
255 FF
FFh
Figure 8. Memory Map
Table 06h contains a MON4-indexed LUT for con-
trol of the M4DAC voltage. The M4DAC LUT has 32
entries that are configurable to act as one 32-entry
LUT or two 16-entry LUTs. When configured as one
32-byte LUT, each entry corresponds to an incre-
ment of 1/32 of the full scale. When configured as
two 16-byte LUTs, the first 16 bytes and the last 16
bytes each correspond to 1/16 of full scale. Either
of the two sections is selected with a separate con-
figuration bit. This LUT is protected by a PW2 level
access.
EEPROM. Shadowed EEPROM (SEE) can be configured
as either volatile or nonvolatile memory using the SEEB
bit in Table 02h, Register 80h.
The DS1865 uses shadowed EEPROM memory for key
memory addresses that can be rewritten many times. By
default the shadowed EEPROM bit, SEEB, is not set and
these locations act as ordinary EEPROM. By setting
SEEB, these locations function like SRAM cells, which
allow an infinite number of write cycles without concern
of wearing out the EEPROM. This also eliminates the
requirement for the EEPROM write time, t . Because
WR
Auxiliary Memory is EEPROM accessible at the
changes made with SEEB enabled do not affect the
EEPROM, these changes are not retained through
power cycles. The power-up value is the last value writ-
ten with SEEB disabled. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during nor-
mal operation, helping to reduce the number of times
EEPROM is written. The Memory Organization descrip-
tion indicates which locations are shadowed EEPROM.
2
I C slave address, A0h.
See the register map tables for a more complete detail
of each byte’s function, as well as for read/write permis-
sions for each byte.
Shadowed EEPROM
In addition to volatile memory (SRAM) and nonvolatile
memory (EEPROM), the DS1865 also features shadowed
18
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
I2C Definitions
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
The following terminology is commonly used to
2
describe I C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 9 for
applicable timing.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 9 for
applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated START
conditions are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 9 for
applicable timing.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave addressing byte (Figure 9) sent
immediately following a START condition. The slave
address byte contains the slave address in the most sig-
nificant 7 bits and the R/W bit in the least significant bit.
The DS1865 responds to two slave addresses. The auxil-
2
iary memory always responds to a fixed I C slave address,
A0h. The Lower Memory and tables 01h–06h respond to
2
I C slave addresses that can be configured to any value
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (Figure 9). Data is shift-
ed into the device during the rising edge of the SCL.
between 00h–FEh using the Device Address byte (Table
02h, Register 8Ch). The user also must set the ASEL bit
(Table 02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W = 0, the master
indicates it will write data to the slave. If R/W = 1, the mas-
ter reads data from the slave. If an incorrect slave address
is written, the DS1865 assumes the master is communicat-
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es including when it is reading bits from the slave.
2
ing with another I C device and ignores the communica-
tions until the next START condition is sent.
2
Memory Address: During an I C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Acknowledgement (ACK and NACK): An acknowledge-
ment (ACK) or not acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
____________________________________________________________________ 19
PON Triplexer Control and
Monitoring Circuit
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
2
Figure 9. I C Timing Diagram
I2C Communication
condition, and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
Writing a Single Byte to a Slave: The master must
2
generate a START condition, write the I C slave address
Acknowledge Polling: Any time an EEPROM location
byte (R/W = 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
is written, the DS1865 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the byte of data to EEPROM. During the EEPROM write
time, the device does not acknowledge its slave
address because it is busy. It is possible to take advan-
tage of that phenomenon by repeatedly addressing the
DS1865, which allows the next page to be written as
soon as the DS1865 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOP condition. The DS1865 writes 1 to 8 bytes
(1 page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte is
sent. The address counter limits the write to one 8-byte
page (one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages result in the address counter
wrapping around to the beginning of the present row.
mum period of t to elapse before attempting to write
W
again to the DS1865.
EEPROM Write Cycles: When EEPROM writes occur
to the memory, the DS1865 writes to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte
repeatedly. The DS1865’s EEPROM write cycles are
specified in the Nonvolatile Memory Characteristics
table. The specification shown is at the worst-case tem-
perature. It can handle approximately 10 times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating the
EEPROM’s estimated lifetime.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h contain 11h and 22h, respectively, and
the third data byte, 33h, is written to address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a STOP condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new START
20
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave, the master generates a
START condition, writes the slave address byte with R/W
= 1, reads the data byte with a NACK to indicate the end
of the transfer, and generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master gen-
erates a START condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires to
read, generates a repeated START condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a STOP condition.
____________________________________________________________________ 21
PON Triplexer Control and
Monitoring Circuit
Register Maps
Lower Memory Register Map
This register map shows each byte/word in terms of the
row it is on in the memory. The first byte in the row is
located in memory at the hexadecimal row address in
the left-most column. Each subsequent byte on the row
is one/two memory locations beyond the previous
byte/word’s address. A total of 8 bytes are present on
each row. For more information about each of these
bytes, see the corresponding register description in the
following tables.
LOWER MEMORY
WORD 1
BYTE 2/A BYTE 3/B
TEMP ALARM LO
ALARM LO
WORD 0
BYTE 0/8 BYTE 1/9
TEMP ALARM HI
ALARM HI
WORD 2
BYTE 4/C BYTE 5/D
TEMP WARN HI
WARN HI
WORD 3
BYTE 6/E BYTE 7/F
TEMP WARN LO
WARN LO
ROW
(HEX)
ROW
NAME
00
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
<1>THRESHOLD
<1>THRESHOLD
<1>THRESHOLD
<1>THRESHOLD
<1>THRESHOLD
<1>THRESHOLD
<1>PW2 EE
0
1
2
3
4
5
V
CC
V
CC
V
CC
V
CC
MON1 ALARM HI
MON2 ALARM HI
MON3 ALARM HI
MON4 ALARM HI
MON1 ALARM LO
MON2 ALARM LO
MON3 ALARM LO
MON4 ALARM LO
MON1 WARN HI
MON2 WARN HI
MON3 WARN HI
MON4 WARN HI
MON1 WARN LO
MON2 WARN LO
MON3 WARN LO
MON4 WARN LO
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
<1>PW2 EE
<1>PW2 EE
<1>PW2 EE
<1>PW2 EE
EE
EE
EE
EE
EE
<1>PW2 EE
<2>ADC VALUES
<0> ADC VALUES
<2>ALARM/WARN
<0>TABLE SELECT
TEMP VALUE
<2>MON3 VALUE
ALARM ALARM
V
VALUE
MON1 VALUE
<2>RESERVED
WARN WARN
2
MON2 VALUE
0
CC
<2> MON4 VALUE
<0>STATUS
<3>UPDATE
1
ALARM
ALARM
RESERVED
3
2
1
0
3
<2>DOUT
<2>DIN
<6>RESERVED
<6>PWE MSB
<6>PWE LSB
<5>TBL SEL
ACCESS CODE
<0>
<1>
<2>
<3>
All
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
22
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 01h Register Map
TABLE 01h (PW1)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
ROW
(HEX)
NAME
BYTE 0/8
BYTE 1/9
EE
BYTE 2/A
BYTE 3/B
EE
BYTE 4/C
BYTE 5/D
EE
BYTE 6/E
BYTE 7/F
EE
80
88
90
98
A0
A8
B0
B8
C0
C8
D0
D8
E0
E8
F0
F8
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<7>PW1 EE
<11>ALARM TRAP
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
ALARM
ALARM
2
ALARM
ALARM
0
WARN
WARN
2
RESERVED
3
1
3
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
____________________________________________________________________ 23
PON Triplexer Control and
Monitoring Circuit
Table 02h Register Map
TABLE 02h (PW2)
WORD 0
WORD 1
BYTE 2/A BYTE 3/B
<4> MOD DAC <4> APC DAC
WORD 2
WORD 3
BYTE 6/E BYTE 7/F
<10> DEVICE ID <10> DEVICEVER
ROW
ROW
(HEX)
NAME
BYTE 0/8
BYTE 1/9
BYTE 4/C
BYTE 5/D
80
88
<0> CONFIG
<8> CONFIG
<8> SCALE
<8>MODE
<4>T INDEX
<4> V INDEX
<4> M4DAC
0
UPDATE
RATE
STARTUP
STEP
MOD
RANGING
DEVICE
COMP
CONFIG
RSHIFT
RSHIFT
0
1
1
ADDRESS
RANGING
90
98
RESERVED
V
CC
SCALE
MON1 SCALE
MON2 SCALE
RESERVED
0
<8> SCALE
MON3 SCALE
RESERVED
MON4 SCALE
OFFSET
RESERVED
MON1 OFFSET
RESERVED
1
A0
<8> OFFSET
<8> OFFSET
V
CC
MON2 OFFSET
0
*
A8
MON3 OFFSET
PW1 MSW
MON4 OFFSET
PW1 LSW
INTERNAL TEMP OFFSET
PW2 LSW
1
B0
<9> PWD VALUE
<8> INTERRUPT
<8> CNTL OUT
EMPTY
PW2 MSW
B8
FETG EN
FETG EN
TX-F EN
TX-F EN
HTXP
LTXP
HBIAS
RESERVED
EMPTY
MAX IBIAS
M4 LUT CNTL
EMPTY
1
0
1
0
C0
DPU
RESERVED
RESERVED
RESERVED
DAC1
RESERVED
EMPTY
C8-F7
F8
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
<0> MAN IBIAS <4> MAN IBIAS <4> MAN IBIAS
<4> MAN_CNTL <10> BIAS DAC
<10> BIAS DAC
0
RESERVED
RESERVED
RESERVED
1
0
1
*The final result must be XORed with BB40h before writing to this register.
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
24
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 03h Register Map
TABLE 03h (PW3)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
ROW
(HEX)
NAME
BYTE 0/8
BYTE 1/9
EE
BYTE 2/A
BYTE 3/B
EE
BYTE 4/C
BYTE 5/D
EE
BYTE 6/E
BYTE 7/F
EE
80
88
90
98
A0
A8
B0
B8
C0
C8
D0
D8
E0
E8
F0
F8
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
____________________________________________________________________ 25
PON Triplexer Control and
Monitoring Circuit
Table 04h Register Map
TABLE 04h (MOD LUT)
WORD 1
BYTE 2/A
WORD 0
BYTE 0/8
WORD 2
BYTE 4/C
WORD 3
BYTE 6/E
ROW
(HEX)
ROW
NAME
BYTE 1/9
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
BYTE 3/B
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
BYTE 5/D
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
BYTE 7/F
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
80
88
90
98
A0
A8
B0
B8
C0
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
Table 05h Register Map
TABLE 05h (APC LUT)
WORD 0
WORD 1
WORD 2
BYTE 4/C
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
APC REF
APC REF
APC REF
APC REF
APC REF
BYTE 2/A
APC REF
APC REF
APC REF
APC REF
APC REF
BYTE 3/B
APC REF
APC REF
APC REF
APC REF
BYTE 5/D
APC REF
APC REF
APC REF
APC REF
BYTE 6/E
APC REF
APC REF
APC REF
APC REF
BYTE 7/F
APC REF
APC REF
APC REF
APC REF
80
88
90
98
A0
<8>LUT5
<8>LUT5
<8>LUT5
<8>LUT5
<8>LUT5
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF RESERVED RESERVED RESERVED RESERVED
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
26
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 06h Register Map
TABLE 06h (LUT FOR M4DAC)
WORD 1
BYTE 2/A
WORD 0
BYTE 0/8
WORD 2
BYTE 4/C
WORD 3
BYTE 6/E
ROW
(HEX)
ROW
NAME
BYTE 1/9
M4DAC
M4DAC
M4DAC
M4DAC
BYTE 3/B
M4DAC
M4DAC
M4DAC
M4DAC
BYTE 5/D
M4DAC
M4DAC
M4DAC
M4DAC
BYTE 7/F
M4DAC
M4DAC
M4DAC
M4DAC
80
88
90
98
<8>LUT6
<8>LUT6
<8>LUT6
<8>LUT6
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
____________________________________________________________________ 27
PON Triplexer Control and
Monitoring Circuit
AUX A0h Memory Register Map
AUX MEMORY (A0h)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
ROW
(HEX)
NAME
BYTE 0/8
BYTE 1/9
EE
BYTE 2/A
BYTE 3/B
EE
BYTE 4/C
BYTE 5/D
EE
BYTE 6/E
BYTE 7/F
EE
00
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
See each
bit/byte
separately
All and
DS1865
hardware
PW2 +
mode bit
Write Access
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
28
____________________________________________________________________
Springer
PON Triplexer Control and
Monitoring Circuit
Lower Memory Registers
Lower Memory, Register 00h to 01h: Temp Alarm Hi
Lower Memory, Register 04h to 05h: Temp Warn Hi
FACTORY DEFAULT:
READ ACCESS
7FFFh
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
00h, 04h
01h, 05h
S
2-1
26
2-2
25
2-3
24
2-4
23
2-5
22
2-6
21
2-7
20
2-8
bit7
bit0
Temperature measurement updates above this two’s complement threshold will set its corresponding alarm or warning bit.
Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit.
Lower Memory, Register 02h to 03h: Temp Alarm Lo
Lower Memory, Register 06h to 07h: Temp Warn Lo
FACTORY DEFAULT:
READ ACCESS
8000h
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
02h, 06h
03h, 07h
S
2-1
26
2-2
25
2-3
24
2-4
23
2-5
22
2-6
21
2-7
20
2-8
bit7
bit0
Temperature measurement updates above this two’s complement threshold will set its corresponding alarm or warning bit.
Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit.
____________________________________________________________________ 29
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 08h to 09h: V Alarm Hi
cc
Lower Memory, Register 0Ch to 0dh: V Warn Hi
cc
Lower Memory, Register 10h to 11h: MON1 Alarm Hi
Lower Memory, Register 14h to 15h: MON1 Warn Hi
Lower Memory, Register 18h to 19h: MON2 Alarm Hi
Lower Memory, Register 1Ch to 1Dh: MON2 Warn Hi
Lower Memory, Register 20h to 21h: MON3 Alarm Hi
Lower Memory, Register 24h to 25h: MON3 Warn Hi
Lower Memory, Register 28h to 29h: MON4 Alarm Hi
Lower Memory, Register 2Ch to 2Dh: MON4 Warn Hi
FACTORY DEFAULT:
READ ACCESS
FFFFh
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
08, 0C, 10,
14, 18, 1C,
20, 24, 28,
2Ch
215
214
213
212
211
210
29
28
09, 0D, 11,
15, 19, 1D,
21, 25, 29,
2Dh
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold will clear its alarm or warning bit.
30
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 0Ah to 0Bh: V Alarm Lo
cc
Lower Memory, Register 0Eh to 0Fh: V Warn Lo
cc
Lower Memory, Register 12h to 13h: MON1 Alarm Lo
Lower Memory, Register 16h to 17h: MON1 Warn Lo
Lower Memory, Register 1Ah to 1Bh: MON2 Alarm Lo
Lower Memory, Register 1Eh to 1Fh: MON2 Warn Lo
Lower Memory, Register 22h to 23h: MON3 Alarm Lo
Lower Memory, Register 26h to 27h: MON3 Warn Lo
Lower Memory, Register 2Ah to 2Bh: MON4 Alarm Lo
Lower Memory, Register 2Eh to 2Fh: MON4 Warn Lo
FACTORY DEFAULT:
READ ACCESS
0000h
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
0A, 0E, 12,
16, 1A, 1E,
22, 26, 2A,
2Eh
215
214
213
212
211
210
29
28
0B, 0F, 13,
17, 1B, 1F,
23, 27, 2B,
2Fh
27
26
25
24
23
22
21
20
bit7
bit0
Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold will clear its alarm or warning bit.
Lower Memory, Register 30h to 5Fh: PW2 EE
FACTORY DEFAULT:
READ ACCESS
00h
All
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (EE)
30h to 5Fh
EE
EE
EE
EE
EE
EE
EE
EE
bit7
bit0
PW2 level access controlled EEPROM.
____________________________________________________________________ 31
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 60h to 61h: Temp Value
POWER-ON VALUE
READ ACCESS
0000h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
26
2-2
25
2-3
24
2-4
23
2-5
22
2-6
21
2-7
20
2-8
60h
61h
S
2-1
bit7
Signed two’s complement direct-to-temperature measurement.
bit0
Lower Memory, Register 62h to 63h: V
Value
CC
Lower Memory, Register 64h to 65h: MON1 Value
Lower Memory, Register 66h to 67h: MON2 Value
Lower Memory, Register 68h to 69h: MON3 Value
Lower Memory, Register 6Ah to 6Bh: MON4 Value
POWER-ON VALUE
READ ACCESS
0000h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
214
62, 64, 66,
68, 6Ah
215
27
213
25
212
24
211
23
210
22
29
21
28
63, 65, 67,
69, 6Bh
26
20
bit7
bit0
Left-justified unsigned voltage measurement.
Lower Memory, Register 6Ch to 6D: Reserved
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
6C, 6Dh
0
0
0
0
00
0
0
0
bit7
These registers are reserved. The value when read is 00h.
bit0
32
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 6Eh: Status
POWER-ON VALUE
READ ACCESS
x000 0x0x b
All
WRITE ACCESS
See Below
MEMORY TYPE:
Volatile
ALL
Write Access
6Eh
N/A
N/A
ALL
ALL
N/A
N/A
N/A
FETG
STATUS
SOFT
FETG
TX-F
RESET
SOFT
TX-D
TX-F
STATUS
LOS
STATUS
RESERVED
RDYB
bit7
bit0
FETG STATUS: Reflects the active state of FETG. The FETG-DIR bit in Table 02h, Register 89h
defines the polarity of FETG.
bit7
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
SOFT FETG:
0 = (Default)
bit6
bit5
bit4
1 = Forces the bias and modulation outputs to their off states and asserts the FETG output.
RESERVED (Default = 0)
TX-F RESET:
0 = Does not affect the TX-F output. (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after the reset.
SOFT TX-D: This bit allows a software control is identical to the TX-D pin. See the section on TX-D for
further information. Its value is wired-ORed with the logic value of the TX-D pin.
bit3
bit2
bit1
0 = Internal TX-D signal is equal to external TX-D pin.
1 = Internal TX-D signal is high.
TX-F STATUS: Reflects the active state of TX-F.
0 = TX-F pin is not active.
1 = TX-F pin is active.
LOS STATUS: Loss of Signal. Reflects the logic level of the D0 input pin. Note that with the use of the
MUX LOSI and INV LOSI bits (Table 02h, Register C0h), the D0 pin is controlled by the LOSI pin.
0 = D0 is logic-low.
1 = D0 is logic-high.
RDYB: Ready Bar.
0 = V is above POA.
CC
bit0
2
1 = V
is below POA or too low to communicate over the I C bus.
CC
____________________________________________________________________ 33
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 6Fh: Update
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
All + DS1865 Hardware
MEMORY TYPE:
Volatile
6Fh TEMP RDY
bit7
V
RDY
MON1 RDY MON2 RDY MON3 RDY
MON4 RDY
RESERVED
RESERVED
bit0
CC
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed.
These bits can be cleared so that a completion of a new conversion is verified.
34
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 70h: Alarm
3
POWER-ON VALUE
READ ACCESS
10h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
70h
TEMP HI
TEMP LO
V
HI
V
LO
CC
MON1 HI
MON1 LO
MON2 HI
MON2 LO
bit0
CC
bit7
TEMP HI: High Alarm Status for Temperature Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit7
TEMP LO: Low Alarm Status for Temperature Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit6
bit5
V
CC
HI: High Alarm Status for V
Measurement.
CC
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
V
LO: Low Alarm Status for V
Measurement. This bit is set when the V
supply is below the
CC
CC
CC
POA trip point value. It will clear itself when a V
the low threshold.
measurement is completed and the value is above
CC
bit4
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
MON1 HI: High Alarm Status for MON1 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit3
bit2
bit1
bit0
MON1 LO: Low Alarm Status for MON1 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
MON2 HI: High Alarm Status for MON2 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON2 LO: Low Alarm Status for MON2 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
____________________________________________________________________ 35
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 71h: Alarm
2
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
71h
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit0
bit7
MON3 HI: High Alarm Status for MON3 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit7
MON3 LO: Low Alarm Status for MON3 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit6
bit5
MON4 HI: High Alarm Status for MON4 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON4 LO: Low Alarm Status for MON4 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit4
bit3:0
RESERVED
Lower Memory, Register 72h: Alarm
1
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
72h RESERVED
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TXP HI
TXP LO
bit0
bit7
bit7:4
RESERVED
BIAS HI: High Alarm Status Bias; Fast Comparison.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
bit3
bit2
bit1
RESERVED
TXP HI: High Alarm Status TX-P; Fast Comparison.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
TXP LO: Low Alarm Status TX-P; Fast Comparison.
0 = (Default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
bit0
36
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 73h: Alarm
0
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
73h RESERVED
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
RESERVED
bit0
bit7
bit7:4
RESERVED
BIAS MAX: Alarm Status for Maximum Digital Setting of I
.
BIAS
0 = (Default) The value for I
is equal to or below the MAX IBIAS setting.
bit3
BIAS
1 = Requested value for I
is greater than the MAX IBIAS setting.
BIAS
bit2:0
RESERVED
____________________________________________________________________ 37
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 74h: Warn
3
POWER-ON VALUE
READ ACCESS
10h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
74h
TEMP HI
TEMP LO
V
HI
V
LO
CC
MON1 HI
MON1 LO
MON2 HI
MON2 LO
bit0
CC
bit7
TEMP HI: High Warning Status for Temperature Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit7
TEMP LO: Low Warning Status for Temperature Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit6
bit5
V
CC
HI: High Warning Status for V
Measurement.
CC
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
V
LO: Low Warning Status for V
Measurement. This bit is set when the V
supply is below the
CC
CC
CC
POA trip point value. It will clear itself when a V
the low threshold.
measurement is completed and the value is above
CC
bit4
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
MON1 HI: High Warning Status for MON1 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit3
bit2
bit1
bit0
MON1 LO: Low Warning Status for MON1 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
MON2 HI: High Warning Status for MON2 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON2 LO: Low Warning Status for MON2 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
38
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 75h: Warn
2
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
75h
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit0
bit7
MON3 HI: High Warning Status for MON3 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
bit7
MON3 LO: Low Warning Status for MON3 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
bit6
bit5
MON4 HI: High Warning Status for MON4 Measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON4 LO: Low Warning Status for MON4 Measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
RESERVED
bit4
bit3:0
Lower Memory, Register 76h to 77h: Reserved
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
76, 77h
0
0
0
0
00
0
0
0
bit7
These registers are reserved. The value when read is 00h.
bit0
____________________________________________________________________ 39
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 78h: DOUT
POWER-ON VALUE
READ ACCESS
Recalled from Table 02h, Register C0h
All
All
WRITE ACCESS
MEMORY TYPE:
Volatile
78h RESERVED
bit7
RESERVED
RESERVED
RESERVED
D3 OUT
D2 OUT
D1 OUT
D0 OUT
bit0
At power-on, these bits are defined by the value stored in the DPU byte (Table 02h, Register C0h).
These bits define the value of the logic states of their corresponding output pins.
Lower Memory, Register 79h: DIN
POWER-ON VALUE
READ ACCESS
See description
All
WRITE ACCESS
N/A
MEMORY TYPE:
Volatile
79h RESERVED
RESERVED
INV LOSI
MUX LOSI
D3 IN
D2 IN
D1 IN
D0 IN
bit0
bit7
bit7:6
RESERVED
INV LOSI: Allows for inversion of LOSI pin to D0 pin. MUX LOSI bit must be set to 1 or this bit does
not affect the output. This bit is controlled (or set) by the DPU byte (Table 02h, Register C0h).
bit5
1 = LOS buffered OUT is inverted.
0
MUX LOSI: Determines control of D0 pin. This bit is controlled (or set) by the DPU byte (Table 02h,
Register C0h).
bit4
0 = Logic value of D0 is controlled by DOUT byte.
1 = Logic value of D0is controlled by LOSI pin and INV LOSI bit.
bit3
bit2
bit1
bit0
D3 IN: Reflects the logic value of D3 pin.
D2 IN: Reflects the logic value of D2 pin.
D1 IN: Reflects the logic value of D1 pin.
D0 IN: Reflects the logic value of D0 pin.
Lower Memory, Register 7Ah: Reserved
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
N/A
MEMORY TYPE:
7Ah
0
0
0
0
00
0
0
0
bit7
This register is reserved. The value when read is 00h.
bit0
40
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE)
POWER-ON VALUE
READ ACCESS
FFFF FFFFh
N/A
All
WRITE ACCESS
MEMORY TYPE:
Volatile
7Bh
7Ch
7Dh
7Eh
231
223
215
27
230
222
214
26
229
221
213
25
228
220
212
24
227
219
211
23
226
218
210
22
225
217
29
224
216
28
21
20
bit7
bit0
Password Entry. There are two passwords for the DS1865. Each password is 4 bytes long. The lower level password (PW1) will
have access to all unprotected areas plus those made available with PW1. The higher level password (PW2) will have all the
access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside of PW2 memory. At
power-up, all PWE bits are set to 1. All reads at this location are 0.
Lower Memory, Register 7Fh: Table Select (TBL SEL)
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
All
MEMORY TYPE
7Fh
Volatile
26
27
bit7
The upper memory tables (Table 01h–06h) of the DS1865 are accessible by writing the desired table value in this register.
25
24
23
22
21
20
bit0
____________________________________________________________________ 41
PON Triplexer Control and
Monitoring Circuit
Table 01h Register Descriptions
Table 01h, Register 80h to F7h: PW1 EEPROM
POWER-ON VALUE
READ ACCESS
00h
PW1
PW1
WRITE ACCESS
MEMORY TYPE
80h-F7h
Nonvolatile (EE)
EE
EE
EE
EE
EE
EE
EE
EE
bit7
bit0
EEPROM for PW1 level access.
Table 01h, Register F8h: Alarm
3
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
F8h
TEMP HI
bit7
TEMP LO
V
HI
V
LO
CC
MON1 HI
MON1 LO
MON2 HI
MON2 LO
bit0
CC
Layout is identical to Alarm in Lower Memory, Register 70h with two exceptions.
3
1.
2.
V
low alarm is not set at power-on.
CC
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register F9h: Alarm
2
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
F9h
MON3 HI
bit7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit0
Layout is identical to Alarm in Lower Memory, Register 71h with one exception.
2
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
42
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 01h, Register FAh: Alarm
1
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
FAh RESERVED
bit7
RESERVED
RESERVED
BIAS HI
RESERVED
RESERVED
TXP HI
TXP LO
bit0
Layout is identical to Alarm in Lower Memory, Register 72h with one exception.
1
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FBh: Alarm
0
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
FBh RESERVED
bit7
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
RESERVED
bit0
Layout is identical to Alarm in Lower Memory, Register 73h with one exception.
0
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FCh: Warn
3
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
FCh
TEMP HI
bit7
TEMP LO
V
HI
V
LO
CC
MON1 HI
MON1 LO
MON2 HI
MON2 LO
bit0
CC
Layout is identical to Warn in Lower Memory, Register 74h with two exceptions.
3
1.
2.
V
Low Warning is not set at power-on.
CC
These bits are latched. They are cleared by power-down or a write with PW1 access.
____________________________________________________________________ 43
PON Triplexer Control and
Monitoring Circuit
Table 01h, Register FDh: Warn
2
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
FDh
MON3 HI
bit7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED
bit0
Layout is identical to Warn in Lower Memory, Register 75h with one exception.
2
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FEh to FFh: Reserved
POWER-ON VALUE
READ ACCESS
00h
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
These registers are reserved.
44
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PON Triplexer Control and
Monitoring Circuit
Table 02h Register Descriptions
Table 02h, Register 80h: Mode
POWER-ON VALUE
READ ACCESS
1Fh
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Volatile
80h
SEEB
bit7
RESERVED
RESERVED
M4DAC-EN
AEN
MOD-EN
APC-EN
BIAS-EN
bit0
SEEB:
0 = (Default) Enables EEPROM writes to SEE bytes.
bit7
bit6:5
bit4
1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is
not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE
locations again for data to be written to the EEPROM.
RESERVED
M4DAC-EN:
0 = M4DAC is writeable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for M4DAC. The output is updated with the
2
new value at the end of the write cycle. The I C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for M4DAC.
AEN:
0 = The temperature-calculated index value (T INDEX) is writeable by the user and the updates of
calculated indexes are disabled. This allows users to interactively test their modules by controlling the
indexing for the lookup tables. The recalled values from the LUTs will appear in the DAC registers
after the next completion of a temperature conversion (just like it would happen in auto mode). Both
DACs will update at the same time (just like in auto mode).
bit3
1 = (Default) Enables auto control of the LUT.
MOD-EN:
0 = MOD DAC is writeable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for modulation. The output is updated with
the new value at the end of the write cycle. The I C STOP condition is the end of the write cycle.
bit2
bit1
2
1 = (Default) Enables auto control of the LUT for modulation.
APC-EN:
0 = APC DAC is writeable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for APC reference. The output is updated
2
with the new value at the end of the write cycle. The I C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for APC reference.
BIAS-EN:
0 = BIAS DAC is controlled by the user and the APC is open loop. The BIAS DAC value is written to
the MAN IBIAS register. All values that are written to MAN IBIAS and are greater than the MAX IBIAS
register setting are not updated and will set the BIAS MAX alarm bit. The BIAS DAC register will
continue to reflect the value of the BIAS DAC. This allows users to interactively test their modules by
bit0
writing the DAC value for I
. The output is updated with the new value at the end of the write cycle
2
BIAS
to the MAN IBIAS register. The I C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control for the APC feedback.
____________________________________________________________________ 45
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 81h: Tindex
POWER-ON VALUE
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (AEN = 0)
MEMORY TYPE
81h
Volatile
27
bit7
26
25
24
23
22
21
20
bit0
Holds the calculated index based on the Temperature Measurement. This index is used for the address during lookup of tables 04h
and 05h. Temperature measurements below -40°C or above 102°C are clamped to 00h and C7h, respectively. The calculation of
Tindex is as follows:
Temp + 40°C
Tindex =
+ 80h
2°C
For the two temperature-indexed LUTs, the index used during the lookup function for each table is as follows:
Table 04h MOD
Table 05h APC
1
1
Tindex6
0
Tindex5
Tindex6
Tindex4
Tindex5
Tindex3
Tindex4
Tindex2
Tindex3
Tindex1
Tindex2
Tindex0
Tindex1
Table 02h, Register 82h: MOD DAC
POWER-ON VALUE
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (MOD-EN = 0)
MEMORY TYPE
82h
Volatile
27
bit7
26
25
24
23
22
21
20
bit0
The digital value used for MOD and recalled from Table 04h at the adjusted memory address is found in Tindex. (R.O.)
This register is updated at the end of every temperature conversion.
Table 02h, Register 83h: APC DAC
POWER-ON VALUE
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (APC-EN = 0)
MEMORY TYPE
83h
Volatile
27
bit7
26
25
24
23
22
21
20
bit0
The digital value used for APC reference and recalled from Table 05h at the adjusted memory address found in Tindex. (R.O.)
This register is updated at the end of the temperature conversion.
46
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PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 84h: Vindex
FACTORY DEFAULT
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (AEN = 0)
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
20
84h
bit7
bit0
Holds the calculated index based on the MON4 voltage measurement. This index is used for the address during lookup of Table
06h. M4DAC LUT (Table 06h) is 32 bytes from address 80h to 9Fh. The calculation of Vindex is as follows:
Mon4
800h
Vindex =
+ 80h
When configured as a single LUT, all 32 bytes are used for lookup.
When configured as a double LUT, the first 16 bytes (80h-8Fh) form the lower LUT and the last 16 bytes (90h-9Fh) form the upper LUT.
For the three different modes, the index used during the lookup function of Table 06h is as follows:
Single
1
1
1
0
0
0
0
0
0
Vindex4
Vindex3
Vindex4
Vindex4
Vindex2
Vindex3
Vindex3
Vindex1
Vindex2
Vindex2
Vindex0
Vindex1
Vindex1
Double / Lower
Double / Upper
0
1
Table 02h, Register 85h: M4DAC
FACTORY DEFAULT
READ ACCESS
00 00h
PW2
WRITE ACCESS
PW2 and (M4DAC-EN = 0)
Volatile
MEMORY TYPE:
85h
27
26
25
24
23
22
21
20
bit7
bit0
The digital value used for M4DAC and recalled from Table 06h at the adjusted memory address is found in Vindex. (R.O.)
This register is updated at the end of the MON4 conversion.
Table 02h, Register 86h: Device ID
FACTORY DEFAULT
READ ACCESS
65h
PW2
N/A
WRITE ACCESS
MEMORY TYPE
86h
ROM
1
0
1
0
0
1
0
1
bit7
Hardwired connections to show device ID.
bit0
____________________________________________________________________ 47
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 87h: Device VER
FACTORY DEFAULT
READ ACCESS
Device Version
PW2
N/A
WRITE ACCESS
MEMORY TYPE
87h
ROM
DEVICE VERSION
bit7
bit0
Hardwired connections to show device version.
Table 02h, Register 88h: Update Rate
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE
Nonvolatile (SEE)
Defines the update rate for comparison of APC control.
88h
0
0
0
0
SR3
SR2
SR1
SR0
bit0
bit7
bit7:4
bit3:0
0:
SR(3:0): 4-bit sample rate for comparison of APC control.
MINIMUM TIME
FROM BEN TO
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
BIT SR –SR
3
0
FIRST SAMPLE
(t 50ns
)
SAMPLE (t
)
FIRST
REP
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
*1001b
350ns
550ns
800ns
1200ns
1600ns
2000ns
2800ns
3200ns
3600ns
4400ns
6000ns
6400ns
750ns
950ns
1350ns
1550ns
1750ns
2150ns
2950ns
3150ns
*All codes greater than 1001b (1010b–1111b) use the maximum
sample time of code 1001b.
48
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 89h: Config
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
89h
FETG DIR
bit7
TX-F EN
RESERVED
ASEL
RESERVED
RESERVED
RESERVED RESERVED
bit0
Configure the memory location and the polarity of the digital outputs.
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
0 = (Default) Under normal operation, FETG is pulled low. Intended for use with nMOS.
1 = Under normal operation, FETG is pulled high. Intended for use with pMOS.
bit7
bit6
TX-F EN: The TX-F output pin always reflects the wired-OR of all TXF enabled alarm states. This bit
will enable the latching of the alarm state for the TXF output pin.
0 = (Default) Not latched.
1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If V _Lo_Alarm is
CC
enabled for either FETG or TX-F then latching is disabled until the after the first V
measurement is
CC
made above the V _Lo set point to allow for proper operation during slow power-on cycles.
CC
bit5
bit4
RESERVED
ASEL: Address Select.
0 = (Default) Device Address of A2h.
2
1 = I C slave address is determined by the value programmed in the DEVICE ADDRESS byte
(Table 02h, Register 8Ch).
bit3:0
RESERVED
Table 02h, Register 8Ah: Startup Step
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
8Ah
Nonvolatile (SEE)
212
bit7
211
210
29
28
27
26
25
bit0
This value will define the maximum allowed step for the upper 8 bits of I
output during startup. Programming this value to 00h
BIAS
cause the device to take single LSB (20) steps towards convergence. See the BIAS and MOD Output During Power-Up section for
details.
____________________________________________________________________ 49
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 8Bh: MOD Ranging
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
8Bh
RESERVED
bit7
The lower nibble of this byte controls the full-scale range of the modulation DAC.
RESERVED
RESERVED
RESERVED
RESERVED
MOD2
MOD1
MOD0
bit0
bit7:3
bit2:0
RESERVED (Default = 0)
MOD2, MOD1, MOD0: MOD FS Ranging. 3-bit value to select the FS output voltage for VMOD.
Default is 000b and creates a FS of 1.25V.
MOD – MOD
% OF 1.25V
100.00
80.05
FS VOLTAGE (V)
1.250
2
0
000b
001b
010b
011b
100b
101b
110b
111b
1.001
66.75
0.833
50.13
0.627
40.16
0.502
33.50
0.419
28.75
0.359
25.18
0.315
Table 02h, Register 8Ch: Device Address
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
8Ch
Nonvolatile (SEE)
26 25
27
bit7
24
23
22
21
20
bit0
2
This value becomes the I C slave address for the main memory when the ASEL bit (Table 02h, Register 89h) is set.
50
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PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 8Dh: Comp Ranging
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
8Dh
RESERVED
bit7
BIAS2
BIAS1
BIAS0
RESERVED
APC2
APC1
APC0
bit0
The upper nibble of this byte controls the Full-Scale range of the Quick-Trip monitoring for BIAS. The Lower nibble of this byte
controls the Full-Scale range for the Quick-Trip monitoring of the APC reference as well as the closed loop monitoring of APC.
bit7
bit6.4
bit3
RESERVED (Default = 0)
BIAS2, BIAS1, BIAS0: BIAS FS Ranging: 3-bit value to select the FS comparison voltage for BIAS
found on MON1. Default is 000b and creates an FS of 1.25V.
RESERVED (Default = 0)
APC2, APC1, APC0: APC FS Ranging: 3-bit value to select the FS comparison voltage for BMD with
the APC. Default is 000b and creates an FS of 2.5V.
bit2:0
BIAS – BIAS
% OF 1.25V
100.00
80.10
FS VOLTAGE (V)
1.250
2
0
000b
001b
010b
011b
100b
101b
110b
111b
1.001
66.83
0.835
50.25
0.628
40.30
0.504
33.66
0.421
28.92
0.362
25.39
0.317
APC – APC
% OF 2.50V
100.00
80.10
FS VOLTAGE (V)
1.250
2
0
000b
001b
1.001
010b
011b
66.83
0.835
50.25
0.628
100b
40.30
0.504
101b
110b
33.66
0.421
28.92
0.362
0.317
111b
25.39
____________________________________________________________________ 51
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 8Eh: Right Shift (RSHIFT )
1
1
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
MON12 MON11
8Eh
RESERVED
bit7
MON10
RESERVED
MON22
MON21
MON20
bit0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the measurements to
the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. See the Right
Shifting ADC Results section for details.
Table 02h, Register 8Fh: Right Shift (RSHIFT )
0
0
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
MON32 MON31
8Fh
RESERVED
bit7
MON30
RESERVED
MON42
MON41
MON40
bit0
Allows for right-shifting the final answer of MON3 and MON4 voltage measurements. This allows for scaling the measurements to
the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. See the Right
Shifting ADC Results section for details.
Table 02h, Register 90h to 91h: Reserved
FACTORY DEFAULT:
READ ACCESS
0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
52
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register 92h to 93h: V
Scale
CC
Table 02h, Register 94h to 95h: MON1 Scale
Table 02h, Register 96h to 97h: MON2 Scale
Table 02h, Register 98h to 99h: MON3 Scale
Table 02h, Register 9Ah to 9Bh: MON4 Scale
FACTORY CALIBRATED
READ ACCESS
WRITE ACCESS
PW2
PW2
MEMORY TYPE:
Nonvolatile (SEE)
92, 94, 96,
98, 9Ah
215
214
26
213
25
212
24
211
23
210
22
29
21
28
93, 95, 97,
99, 9Bh
27
20
bit7
bit0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for
and 2.5V for MON1, MON2, MON3, and MON4.
V
CC
Table 02h, Register 9Ch to A1h: Reserved
FACTORY DEFAULT:
READ ACCESS
0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register A2h to A3h: V
Offset
CC
Table 02h, Register A4h to A5h: MON1 Offset
Table 02h, Register A6h to A7h: MON2 Offset
Table 02h, Register A8h to A9h: MON3 Offset
Table 02h, Register AAh to ABh: MON4 Offset
FACTORY DEFAULT:
READ ACCESS
0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
A2, A4, A6,
S
S
215
27
214
26
213
25
212
24
211
23
210
A8, AAh
A3, A5, A7,
A9, ABh
29
28
22
bit7
bit0
Allows for offset control of these voltage measurements if desired.
____________________________________________________________________ 53
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register ACh to ADh: Reserved
FACTORY DEFAULT:
READ ACCESS
0000 0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register AEh to AFh: Internal Temp Offset
FACTORY CALIBRATED
READ ACCESS
WRITE ACCESS
PW2
PW2
MEMORY TYPE
Nonvolatile (SEE)
28
20
27
2-1
26
2-2
25
2-3
24
2-4
23
2-5
22
2-6
AEh
AFh
S
21
bit7
bit0
Allows for offset control of the temperature measurement if desired. The final result must be XORed with BB40h before writing to
this register. Factory calibration contains the desired value for a reading in degrees Celsius.
Table 02h, Register B0h to B3h: PW1
FACTORY DEFAULT
READ ACCESS
FFFF FFFFh
N/A
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B0h
B1h
B2h
B3h
231
230
222
214
26
229
221
213
25
228
220
212
24
227
219
211
23
226
218
210
22
225
217
29
224
216
28
223
215
27
21
20
bit7
bit0
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all
ones. Thus, writing these bytes to all ones grants PW1 access on power-up without writing the password entry. All reads of this
register are 00h.
54
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register B4h to B7h: PW2
FACTORY DEFAULT
READ ACCESS
FFFF FFFFh
N/A
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B4h
B5h
B6h
B7h
231
230
222
214
26
229
221
213
25
228
220
212
24
227
219
211
23
226
218
210
22
225
217
29
224
216
28
223
215
27
21
20
bit7
bit0
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all
ones. Thus, writing these bytes to all ones grants PW2 access on power-up without writing the password entry. All reads of this
register are 00h.
____________________________________________________________________ 55
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register B8h: FETG Enable (FETG EN )
1
1
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
EN MON1 EN
B8h
TEMP EN
bit7
V
MON2 EN
MON3 EN
MON4 EN
RESERVED RESERVED
bit0
CC
Configures the maskable interrupt for the FETG pin.
TEMP EN: Enables/disables active interrupts on the FETG pin due to temperature measurements
outside the threshold limits.
bit7
bit6
bit5
bit4
bit3
0 = Disable (Default).
1 = Enable.
V
CC
EN: Enables/disables active interrupts on the FETG pin due to V
measurements outside the
CC
threshold limits.
0 = Disable (Default).
1 = Enable.
MON1 EN: Enables/disables active interrupts on the FETG pin due to MON1 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON2 EN: Enables/disables active interrupts on the FETG pin due to MON2 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON3 EN: Enables/disables active interrupts on the FETG pin due to MON3 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON4 EN: Enables/disables active interrupts on the FETG pin due to MON4 measurements
outside the threshold limits.
bit2
0 = Disable (Default).
1 = Enable.
RESERVED (Default = 0)
bit1:0
56
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register B9h: FETG Enable (FETG EN )
0
0
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
LTXP EN BIAS-HI EN BIAS MAX EN RESERVED
B9h
HTXP EN
bit7
RESERVED
RESERVED
RESERVED
bit0
Configures the maskable interrupt for the FETG pin.
HTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons above
the threshold limit.
bit7
bit6
bit5
0 = Disable (Default).
1 = Enable.
LTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons below
the threshold limit.
0 = Disable (Default).
1 = Enable.
BIAS HI EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons
above the threshold limit.
0 = (Default) Disable.
1 = Enable.
BIAS MAX EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons
below the threshold limit.
bit4
0 = (Default) Disable.
1 = Enable.
bit3:0
RESERVED (Default = 0)
____________________________________________________________________ 57
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register BAh: TX-F Enable (TX-F EN )
1
1
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
EN MON1 EN
BAh
TEMP EN
bit7
V
MON2 EN
MON3 EN
MON4 EN
RESERVED
RESERVED
bit0
CC
Configures the maskable interrupt for the TX-F pin.
TEMP EN: Enables/disables active interrupts on the TX-F pin due to temperature measurements
outside the threshold limits.
bit7
bit6
bit5
bit4
bit3
0 = Disable (Default).
1 = Enable.
V
CC
EN: Enables/disables active interrupts on the TX-F pin due to V
measurements outside the
CC
threshold limits.
0 = Disable (Default).
1 = Enable.
MON1 EN: Enables/disables active interrupts on the TX-F pin due to MON1measurements outside
the threshold limits.
0 = Disable (Default).
1 = Enable.
MON2 EN: Enables/disables active interrupts on the TX-F pin due to MON2 measurements outside
the threshold limits.
0 = Disable (Default).
1 = Enable.
MON3 EN: Enables/disables active interrupts on the TX-F pin due to MON3 measurements outside
the threshold limits.
0 = Disable (Default).
1 = Enable.
MON4 EN: Enables/disables active interrupts on the TX-F pin due to MON4 measurements outside
the threshold limits.
bit2
0 = Disable (Default).
1 = Enable.
bit2:0
RESERVED (Default = 0)
58
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PON Triplexer Control and
Monitoring Circuit
Table 02h, Register BBh: TX-F Enable (TX-F EN )
0
0
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
LTXP EN BIAS-HI EN BIAS MAX EN RESERVED
BBh
HTXP EN
bit7
RESERVED
RESERVED
FETG EN
bit0
Configures the maskable interrupt for the Tx-F pin.
HTXP EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons above
the threshold limit.
bit7
bit6
bit5
bit4
0 = Disable (Default).
1 = Enable.
LTXP EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons below
the threshold limit.
0 = Disable (Default).
1 = Enable.
BIAS-HI EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons
above the threshold limit.
0 = Disable (Default).
1 = Enable.
BIAS MAX EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons
above the threshold limit.
0 = Disable (Default).
1 = Enable.
bit3:1
bit0
RESERVED (Default = 0)
FETG EN:
0 = Normal FETG operation (Default).
1 = Enables FETG to act as an input to TX-F output.
____________________________________________________________________ 59
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register BCh: HTXP
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
BCh
Nonvolatile (SEE)
27
bit7
26
25
24
23
22
21
20
bit0
Fast-comparison DAC threshold adjust for high transmit power. This value is added to the APC_DAC value recalled from Table 04h.
If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than APC_DAC plus this value, found on the BMD pin, will
create a TXP-HI alarm.
Table 02h, Register BDh: LTXP
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
BDh
Nonvolatile (SEE)
27
bit7
26
25
24
23
22
21
20
bit0
Fast-comparison DAC threshold adjust for low transmit power. This value is subtracted from the APC_DAC value recalled from
Table 04h. If the difference is less than 0x00, 0x00 is used. Comparisons less than APC_DAC minus this value, found on the BMD
pin, create a TXP-LO alarm.
Table 02h, Register BEh: HBIAS
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
BEh
Nonvolatile (SEE)
27
bit7
26
25
24
23
22
21
20
bit0
Fast-comparison DAC setting for high BIAS. Comparisons greater than this value, found on the MON1 pin, create a BIAS HI alarm.
Table 02h, Register BFh: MAX IBIAS
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
BFh
212
bit7
This value defines the maximum DAC value allowed for the upper 8 bits of I
211
210
29
28
27
26
25
bit0
output during all operations. During the intial step and
BIAS
binary search, this value will not cause an alarm but will still clamp the I
DAC output. After the startup seqence (or normal APC
BIAS
operations), if the APC loop tries to create an I
value greater than this setting, it is clamped and creates a BIAS MAX alarm. Settings
BIAS
00h through FEh are intended for normal APC mode of operation. Setting FFh is reserved for manual IBIAS mode.
60 ____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register C0h: DPU
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
C0h
RESERVED RESERVED
bit7
INV LOSI
MUX LOSI
D3 CNTL
D2 CNTL
D1 CNTL
D0 CNTL
bit0
Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin.
Bit7:6
Bit5
RESERVED
INV LOSI: Inverts the buffered input pin LOSI to output pin D0 if MUX LOSI is set. If MUX LOSI is not
set then this bit’s value is a don’t care.
0 = (Default) noninverted LOSI to D0 pin.
1 = Inverted LOSI to D0 pin.
MUX LOSI: chooses the control for D0 output pin.
0 = (Default) DO is controlled by bit D0 OUT found in Lower Memory, Register 78h.
1 = LOSI is buffered to D0 pin.
Bit4
D3 CNTL: At power-on, this value is loaded into bit D3 OUT of Lower Memory, Register 78h to
Bit3
Bit2
bit1
bit0
control the output pin D3.
D2 CNTL: At power-on, this value is loaded into bit D2 OUT of Lower Memory, Register 78h to
control the output pin D2.
D1 CNTL: At power-on, this value is loaded into bit D1 OUT of Lower Memory, Register 78h to
control the output pin D1.
D0 CNTL: At power-on, this value is loaded into bit D0 OUT of Lower Memory, Register 78h to
control the output pin D0.
Table 02h, Register C1h to C3h: Reserved
FACTORY DEFAULT:
READ ACCESS
0000 0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C4h: DAC1
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
27
26
25
24
23
22
21
20
C4h
bit7
bit0
Register to control DAC1.
____________________________________________________________________ 61
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register C5h to C6h: Reserved
FACTORY DEFAULT:
READ ACCESS
0000 0000h
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C7h: M4 LUT Cntl
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
C7h
RESERVED
bit7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DBL_SB
UP_LOWB
bit0
Controls the size and location of LUT functions for the MON4 measurement.
Bit7:2
Bit1
RESERVED: Default = 000000b.
DBL_SB: Chooses the size of LUT for Table 06h.
0 = (Default) Single LUT of 32 bytes.
1 = Double LUT of 16 bytes.
UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of this
bit is a don’t care.
Bit0
0 = (Default) Chooses the lower 16 bytes of Table 06h (Registers 80h-8Fh).
1 = Chooses the upper 16 bytes of Table 06h (Registers 90h-9Fh).
Table 02h, Register C8h to F7h: No Memory
Table 02h, Register F8h to F9h: MAN IBIAS
FACTORY DEFAULT:
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (BIAS-EN = 0)
MEMORY TYPE:
Volatile
212
25
211
24
210
23
29
22
28
21
27
20
F8h
RESERVED
RESERVED
26
27
F9h
bit7
bit0
When BIAS-EN (Table 02h, Register 80h) is written to 0, writes to these bytes will control the I
Register FAh) for details.
DAC. See MAN_CNTL (Table 02h,
BIAS
62
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 02h, Register FAh: MAN_CNTL
FACTORY DEFAULT:
READ ACCESS
00h
PW2
WRITE ACCESS
PW2 and (Bias-En = 1)
MEMORY TYPE:
Volatile
FAh RESERVED
bit7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MAN_CLK
bit0
When BIAS-EN (Table 02h, Register 80h) is written to zero, bit zero of this byte will control the updates of the MAN IBIAS value to
the BIAS output. The values of MAN IBIAS should be written with a separate write command. Setting bit zero to a 1 will clock the
MAN IBIAS value to the output DAC for control of I
.
BIAS
1.
2.
3.
Write the MAN IBIAS value with a write command.
Set the MAN_CLK bit to a 1 with a separate write command.
Clear the MAN_CLK bit to a 0 with a separate write command.
Table 02h, Register FBh to FCh: BIAS DAC
FACTORY DEFAULT:
READ ACCESS
00 00h
PW2
N/A
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
212
25
211
24
210
23
29
22
28
21
27
20
FBh
0
27
0
26
FCh
bit7
bit0
The digital value indicating the DAC value used for I
output.
BIAS
Table 02h, Register FDh to FFh: Reserved
FACTORY DEFAULT:
READ ACCESS
WRITE ACCESS
PW2
N/A
MEMORY TYPE:
FDh
FEh
FFh
0
0
0
0
X
0
0
X
0
0
X
0
0
X
0
0
X
0
0
X
0
X
X
X
bit7
bit0
These registers are reserved.
____________________________________________________________________ 63
PON Triplexer Control and
Monitoring Circuit
Table 03h Register Descriptions
Table 03h, Register 80h to FFh: PW2 EEPROM
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (EE)
80h-FFh
EE
bit7
PW2 protected EEPROM.
EE
EE
EE
EE
EE
EE
EE
bit0
Table 04h Register Descriptions
Table 04h, Register 80h to C7h: MOD LUT
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (EE)
80h-C7h
27
bit7
26
25
24
23
22
21
20
bit0
The digital value for the modulation DAC output.
The Modulation LUT is a set of registers assigned to hold the temperature profile for the modulation DAC. The values in this table
combined with the MOD bits in the MOD Ranging register (Table 02h, Register 8Bh) determine the set point for the modulation
voltage. The temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 2°C increments from -40°C
to +102°C, starting at 80h in Table 04h. Register 80h defines the -40°C to -38°C MOD output, register 81h defines -38°C to -36°C
MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD_DAC (Table 02h, Register 82h)
location that holds the value until the next temperature conversion. The part can be placed into a manual mode (MOD-EN bit, Table
02h, Register 80h), where MOD_DAC is directly controlled for calibration. If the temperature compensation functionality is not
required, then program the entire Table 04h to the desired modulation setting.
64
____________________________________________________________________
PON Triplexer Control and
Monitoring Circuit
Table 05h Register Descriptions
Table 05h, Register 80h to A3h: APC Tracking Error LUT (APC REF)
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (EE)
80h-A3h
27
bit7
26
25
24
23
22
21
20
bit0
The Tracking Error LUT is set of registers assigned to hold the temperature profile for the APC reference DAC. The values in this
table combined with the APC bits in the Comp Ranging register (Table 02h, Register 8Dh) determine the set point for the APC loop.
The temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 4°C increments from -40°C to
+100°C, starting at register 80h in Table 05h. Register 80h defines the -40°C to -36°C APC reference value, register 81h defines
-36°C to -32°C APC reference value, and so on. Values recalled from this EEPROM memory table are written into the APC DAC
(Table 02h, Register 83h) location that holds the value until the next temperature conversion. The part can be placed into a manual
mode (APC-EN bit, Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If tracking error
temperature compensation is not required by the application, program the entire LUT to the desired APC set point.
Table 05h, Register A4h to A7h: Reserved
FACTORY DEFAULT:
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
____________________________________________________________________ 65
PON Triplexer Control and
Monitoring Circuit
Table 06h Register Descriptions
Table 06h, Register 80h to 9Fh: M4DAC LUT
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (EE)
80h-9Fh
27
bit7
26
25
24
23
22
21
20
bit0
The M4DAC LUT is set of registers assigned to hold the voltage profile for the M4DAC. The values in this table determine the set
point for the M4DAC. The MON4 voltage measurement is used to index the LUT (Vindex, Table 02h, Register 84h), starting at
register 80h in Table 06h. Values recalled from this EEPROM memory table are written into the M4DAC (Table 02h, Register 85h)
location that holds the value until the next MON4 voltage conversion. The part can be placed into a manual mode (M4DAC-EN bit,
Table 02h, Register 80h), where M4DAC is directly controlled for calibration. If voltage compensation is not required by the
application, program the entire LUT to the desired M4DAC set point.
Auxiliary Memory A0h Register Descriptions
Auxiliary Memory A0h, Register 00h to 7fh: EEPROM
FACTORY DEFAULT
READ ACCESS
00h
PW2
PW2
WRITE ACCESS
MEMORY TYPE:
Nonvolatile (EE)
00h-7Fh
EE
bit7
EE
EE
EE
EE
EE
EE
EE
bit0
EEPROM
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
66 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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