DS1881Z-050+T&R
更新时间：2024-09-18 19:00:47
品牌：MAXIM
描述：Digital Potentiometer, 2 Func, 45000ohm, 2-wire Serial Control Interface, 64 Positions, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16
概述
规格参数
数据手册DS1881Z-050+T&R 概述
Digital Potentiometer, 2 Func, 45000ohm, 2-wire Serial Control Interface, 64 Positions, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16 数模转换器 数字电位计
DS1881Z-050+T&R 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, | 针数： | 16 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 6 weeks |
| 风险等级： | 5.46 | 标称带宽： | 5 kHz |
| 控制接口： | 2-WIRE SERIAL | 转换器类型： | DIGITAL POTENTIOMETER |
| JESD-30 代码： | R-PDSO-G16 | JESD-609代码： | e3 |
| 长度： | 4.89 mm | 湿度敏感等级： | 1 |
| 功能数量： | 2 | 位置数： | 64 |
| 端子数量： | 16 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 认证状态： | Not Qualified | 电阻定律： | LOGARITHMIC |
| 最大电阻容差： | 20% | 最大电阻器端电压： | 5.5 V |
| 最小电阻器端电压： | 座面最大高度： | 1.75 mm | |
| 标称供电电压： | 5 V | 表面贴装： | YES |
| 标称温度系数： | 750 ppm/°C | 温度等级： | INDUSTRIAL |
| 端子面层： | MATTE TIN | 端子形式： | GULL WING |
| 端子节距： | 0.635 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 标称总电阻： | 45000 Ω |
| 宽度： | 3.9 mm | Base Number Matches： | 1 |
DS1881Z-050+T&R 数据手册
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Dual NV Audio Taper Digital Potentiometer
General Description
Features
♦ Dual, Audio Log Taper Potentiometers
♦ Low THD+N and Crosstalk
The DS1881 is a dual, nonvolatile (NV) digital poten-
tiometer designed to operate in audio systems that
require 5V signal levels. The potentiometer settings can
be stored in EEPROM so that they are retained when the
power is cycled. The DS1881 has separate supplies for
♦ 5V Analog Supply (Independent of Digital Supply)
♦ 3V to 5V Digital Supply Range
♦ Potentiometer Settings Configurable as NV
the potentiometers (V ) and the communication circuit-
CC
ry (V ). For clickless/popless operation, a zero-crossing
DD
or Volatile
detector allows the wiper position to change when there
is no voltage across the potentiometer. The device is
also designed to minimize crosstalk, and the two digital
potentiometers provide 0.5dB channel-to-channel match-
ing to prevent volume differences between channels.
Total harmonic distortion (THD) is also minimal as long
as the wiper drives a high-impedance load.
♦ Zero-Crossing Detector Eliminates Switching
Noise
♦ Two User-Configurable Attenuation Options
♦ Configuration Option 1: 63 Positions Provide 1dB
Attenuation Steps from 0dB to -62dB Plus Mute
♦ Configuration Option 2: (Software-Compatible
with the DS1808): 33 Positions Plus Mute as
Follows
Two attenuation configuration options provide optimum
flexibility for the specific application. Configuration
Option 1 provides 63 logarithmic tapered steps (0dB to
-62dB, 1dB/step) plus a mute setting. Configuration
Option 2 has 32 logarithmic steps plus mute and pro-
vides software compatibility with the DS1808. When
Configuration Option 2 is used in combination with the
16-pin SO package, the DS1881 is both software and pin
compatible with the DS1808 in 5V applications.
Positions 0–12: 1dB per Step for 12 Steps
Positions 13–24: 2dB per Step for 12 Steps
Positions 25–32: 3dB per Step for 8 Steps
2
♦ I C-Compatible Serial Interface
♦ Three Address Pins Allow Up to 8 Devices on
2
I C Bus
♦ 45kΩ Potentiometer End-to-End Resistance
♦ Industrial Temperature Range (-40°C to +85°C)
♦ 16-Pin TSSOP or SO Package
Applications
Notebook and PC Audio
Portable Audio Equipment
Car Stereo
Ordering Information
Consumer Audio/Video
TEMP
RANGE
VERSION PIN-
PART
(kΩ)
PACKAGE
Pin Configuration
16 TSSOP
(173 mils)
DS1881E-050+
-40°C to +85°C
45
TOP VIEW
+
16 TSSOP
GND
A2
1
2
3
4
5
6
7
8
16 V
15 V
DD
DS1881E-050+T&R -40°C to +85°C
45
45
45
(173 mils)
Tape-and-Reel
CC
A1
14 SCL
13 SDA
12 CE
11 W1
10 H1
16 SO
(150 mils)
DS1881Z-050+
-40°C to +85°C
N.C.
A0
DS1881
16 SO
(150 mils)
Tape-and-Reel
W0
L0
DS1881Z-050+T&R -40°C to +85°C
+Denotes lead-free package.
H0
9 L1
TSSOP/SO
Typical Operating Circuit appears at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual NV Audio Taper Digital Potentiometer
ABSOLUTE MAXIMUM RATINGS
Voltage on V , SDA, and SCL Relative to GND .....-0.5V to +6.0V
Maximum Resistor Current .................................................±±mA
Operating Temperature Range ...........................-40°C to +85°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 Specification
DD
Voltage on A2, A1, A0, and CE Relative
to GND.................-0.5V to (V
+ 0.5V), not to exceed +6.0V
DD
Voltage on V
Relative to GND...........................-0.5V to +6.0V
CC
Voltage on H1, H0, W1, W0, L1, and L0 Relative
to GND...............................................................-0.5V to +6.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
4.5
0
TYP
MAX
5.5
5.5
5.5
1
UNITS
V
Digital Supply Voltage
Analog Supply Range
Potentiometer Voltages
(Notes 1, 2)
(Notes 1, 2)
V
V
DD
V
CC
V
Wiper Current
mA
DC ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, V
= +4.5V to +5.5V, T = -40°C to +85°C.)
DD
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
200
0.9
MAX
250
5
UNITS
µA
Digital Supply Current
Analog Supply Current
I
I
(Note 3)
(Note 4)
DD
CC
µA
Input Logic 0
(CE, SDA, SCL, A0, A1, A2)
0.3x
V
DD
V
(Note 5)
(Note 5)
-0.3
V
V
V
IL
Input Logic 1
(CE, SDA, SCL, A0, A1, A2)
0.7 x
V
+
DD
V
IH
V
0.3
DD
I
I
= 4mA
= 6mA
0.4
0.6
+1
OL
Output-Voltage Low (SDA)
V
OL
OL
Input Leakage Current
I/O Pin Input Current (SDA)
I/O Capacitance
I
-1
µA
µA
pF
ms
LI
0.4V < V
(Note 6)
< (0.9 x V )
CC
-10
+10
10
1
SDA
C
I/O
Power-Up Time
t
PU
2
_____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
ANALOG POTENTIOMETER CHARACTERISTICS
(V
= +2.7V to +5.5V, V = +4.5V to +5.5V, T = -40°C to +85°C.)
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
kΩ
End-to-End Resistance
R
+25°C
+25°C
(Note 6)
45
EE
End-to-End Resistance Tolerance
Ratiometric Temperature Coefficient
-20
+20
%
30
ppm/°C
End-to-End Resistance Temperature
Coefficient
(Note 6)
750
160
ppm/°C
Wiper Resistance
R
250
Ω
dB
W
Absolute Attenuation Tolerance
Mute Position Attenuation
Step Size Deviation from Nominal
Interchannel Matching
(Note 7)
-0.5
+0.5
80
dB
(Note 7)
(Note 7)
10pF load
-0.25
-0.5
+0.25
+0.5
dB
dB
-3dB Cutoff Frequency
5
MHz
(20Hz to 20kHz, grounded input,
tap = -6dB)
Output Noise
Crosstalk
2.2
µV
RMS
(1kHz, grounded input, tap = -6dB)
-110
0.005
38
dB
%
1kHz, tap = -6dB, C = 10pF
L
(Note 8)
THD+N
Zero-Crossing Detection
t
50
ms
ZCD
2
I C CHARACTERISTICS (See Figure 4)
(V
= +2.7V to +5.5V, V
= +4.5V to +5.5V, T = -40°C to +85°C. Timing referenced to V
and V
.)
DD
CC
A
IL(MAX)
IH(MIN)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 9)
0
400
kHz
SCL
Bus Free Time Between STOP and
START Conditions
t
1.3
µs
BUF
Hold Time (Repeated) START Condition
Low Period of SCL
t
0.6
1.3
0.6
0
µs
µs
µs
µs
ns
µs
HD:STA
t
LOW
High Period of SCL
t
HIGH
Data Hold Time
t
0.9
HD:DAT
Data Setup Time
t
100
0.6
SU:DAT
START Setup Time
t
SU:STA
20 +
SDA and SCL Rise Time
SDA and SCL Fall Time
t
(Note 10)
(Note 10)
300
300
ns
ns
R
0.1C
B
20 +
t
F
0.1C
B
STOP Setup Time
t
0.6
µs
pF
ms
SU:STO
SDA and SCL Capacitive Loading
EEPROM Write Time
C
(Note 10)
(Note 11)
400
10
B
t
W
5
_____________________________________________________________________
3
Dual NV Audio Taper Digital Potentiometer
NV MEMORY CHARACTERISTICS
(V
= +2.7V to +5.5V, V
= +4.5V to +5.5V, T = 0°C to +70°C.)
DD
CC
A
PARAMETER
SYMBOL
CONDITIONS
+70°C (Note 6)
MIN
TYP
MAX
UNITS
Writes
50,000
Note 1: All voltages are referenced to ground.
Note 2: The value of V should never exceed V , including during power-ups. V
must be applied before V
.
DD
CC
CC
DD
Note 3:
Note 4:
I
I
is specified with SDA = SCL = CE = V , resistor pins floating, and digital inputs connected to V
or GND.
or GND, after zero-
DD
DD
DD
DD
is specified with SDA = SCL = CE = V , resistor pins floating, and digital inputs connected to V
CC
DD
crossing detection has timed out.
Note 5: The DS1881 will not obstruct the SDA and SCL lines if V
is switched off as long as the voltages applied to these inputs
DD
do not violate their minimum and maximum input voltage levels.
Note 6: Guaranteed by design.
Note 7: Above Position 50, these are typical maximum. Guaranteed by characterization.
Note 8: Load is representative of the input of a low-noise audio amp.
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C standard-mode timing.
2
Note 10: C —Total capacitance of one bus line in picofarads.
B
Note 11: If zero-crossing detection is enabled, the EEPROM write does not begin until the current zero-crossing detection is com-
plete. Otherwise, EEPROM write begins after a STOP condition occurs.
Typical Operating Characteristics
(V
= V
= +5.0V, T = +25°C.)
CC A
DD
I
vs. V
I
vs. TEMPERATURE
I
vs. SCL FREQUENCY
DD
DD
DD
DD
300
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
SDA = SCL = V
CC
SDA = SCL = V
SDA = V
DD
DD
280
260
240
220
200
180
160
140
120
100
0
0
4.5
4.7
4.9
5.1
5.3
5.5
-40
-20
0
20
40
60
80
0
50 100 150 200 250 300 350 400
SCL FREQUENCY (kHz)
VOLTAGE (V)
TEMPERATURE (°C)
4
_____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Typical Operating Characteristics (continued)
(V
= V
= +5.0V, T = +25°C.)
CC A
DD
POTENTIOMETER 0 (CONFIGURATON 1)
ATTENUATION vs. SETTING
POTENTIOMETER 0 (CONFIGURATON 2)
ATTENUATION vs. SETTING
POTENTIOMETER 1 (CONFIGURATON 1)
ATTENUATION vs. SETTING
0
0
-20.0
-40.0
-60.0
-80.0
-100.0
0
-20.0
-40.0
-60.0
-80.0
-100.0
-20.0
-40.0
-60.0
-80.0
-100.0
0
9
18
27
36
45
54
63
0
3
6
9
12 15 18 21 24 27 30 33
SETTING (DEC)
0
9
18
27
36
45
54
63
SETTING (DEC)
SETTING (DEC)
RESISTANCE vs. POWER-UP VOLTAGE
POTENTIOMETER 1 (CONFIGURATON 2)
ATTENUATION vs. SETTING
END-TO-END RESISTANCE PERCENT
CHANGE FROM +25°C vs. TEMPERATURE
100
80
60
40
20
0
HIGH IMPEDANCE
0
-20.0
-40.0
-60.0
-80.0
-100.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
PROGRAMMED
RESISTANCE (-6dB)
MUTE WHILE
EEPROM
LOADS
POTENTIOMETER 1
POTENTIOMETER 0
0
1
2
3
4
5
POWER-UP VOLTAGE (V)
0
3
6
9
12 15 18 21 24 27 30 33
SETTING (DEC)
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
RESISTANCE
vs. POWER-DOWN VOLTAGE
SUPPLY CURRENT
vs. ZERO-CROSSING TIMING
100
80
60
40
20
0
1000
900
800
700
600
500
400
300
200
100
0
ZERO-CROSSING
DETECTION
ZERO-CROSSING
TIMEOUT OR ZERO-
CROSSING EVENT
ACTIVATED
PROGRAMMED
RESISTANCE (-6dB)
TYPICAL
TIMEOUT
OF 50ms
MUTE
1
0
2
3
4
5
TIME (ms)
POWER-UP VOLTAGE (V)
_____________________________________________________________________
5
Dual NV Audio Taper Digital Potentiometer
Typical Operating Characteristics (continued)
(V
= V
= +5.0V, T = +25°C.)
CC A
DD
THD+N vs. FREQUENCY (0dB)
CROSSTALK vs. FREQUENCY (-6dB)
0.0018
0.0016
0.0014
0.0012
0.0010
0.0008
0.0006
0.0004
0.0002
0
0
-20
-40
-60
-80
-100
-120
-140
0.01
0.1
1
10
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Pin Description
PIN
NAME
GND
A2
FUNCTION
1
2
3
4
5
6
7
8
9
Ground
2
2
I C Address Inputs. Inputs A0, A1, and A2 determine the I C slave address of the device.
A1
N.C.
A0
No Connection
2
2
I C Address Input. Inputs A0, A1, and A2 determine the I C slave address of the device.
Wiper Terminal for Potentiometer 0
W0
L0
Low Terminal for Potentiometer 0
H0
High Terminal for Potentiometer 0
L1
Low Terminal for Potentiometer 1
10
11
12
13
14
15
16
H1
High Terminal for Potentiometer 1
W1
CE
Wiper Terminal for Potentiometer 1
2
Chip Enable. Enables SDA and SCL pins for I C communication.
2
SDA
SCL
I C Serial-Data Open-Drain I/O
2
I C Serial-Clock Input
V
V
Analog Voltage Supply
Digital Voltage Supply
CC
DD
6
_____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Block Diagram
SDA
SCL
A2
A1
A0
V
DD
V
CC
CONFIGURATION
REGISTER
V
CC
2
I C
V
DD
INTERFACE
POTENTIOMETER
SETTING
REGISTERS
GND
DS1881
CE
GND
POTENTIOMETER 0
POTENTIOMETER 1
VALUE
DECODER
VALUE
H0
W0
L0
H1
W1
L1
ZERO-CROSSING
DETECTOR
ZERO-CROSSING
DETECTOR
UPDATE
UPDATE
_____________________________________________________________________
7
Dual NV Audio Taper Digital Potentiometer
Table 1. Configuration Option 1
Detailed Description
The DS1881 is a dual-channel, digitally controlled,
audio potentiometer. The Block Diagram illustrates the
features of the DS1881. The following sections discuss
these features in detail.
TAP POSITION
ATTENUATION (dB)
0
1
0
1
2
2
Potentiometer Configurations
The DS1881 potentiometers have two possible attenua-
tion configuration options. The Configuration Register
section discusses how to change between the two
options. Note that both potentiometers are always set to
the same option.
3
3
4
4
5
5
6
6
7
7
The factory default for both potentiometers is Option 1
(see Table 1). Option 1 provides 64 positions with 1dB
attenuation per step for positions 0 through 62 and
mute as position 63. Option 2 (see Table 2) is a 34-
position configuration. From position 0, the first 12
steps have 1dB attenuation per step, the next 12 have
2dB attenuation per step, and the following 8 steps
have 3dB attenuation per step. The last position, posi-
tion 33, is the mute setting.
8
8
…
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
…
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
80
Zero-Crossing Detection
Zero-crossing detection is a user-selectable feature
used to help eliminate clicking or popping noises dur-
ing changes of potentiometer settings. See the
Configuration Register section to learn how to enable
the zero-crossing detection feature.
After the I2C master issues a command to change the
wiper position and the DS1881 has responded with an
acknowledge (ACK) to the command, the DS1881 has
a 50ms window to change the wiper position. The
DS1881 constantly monitors the voltage of the high and
low terminals of both potentiometers. During the 50ms
window, if the zero-crossing detection is enabled, then
each potentiometer’s wiper will change position if the
high and low terminals of the same potentiometer
become equal in potential (i.e., the magnitude of the
input signal is zero). If a zero-crossing event does not
occur within the 50ms window, then the wiper is
allowed to change to the new position regardless of the
state of the input signal. When the zero-crossing detec-
tion feature is not enabled, the DS1881 will allow wiper
movement as soon as the DS1881 has issued the
acknowledge to the master-controlling device.
8
_____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Command Byte
The Command Byte determines both the potentiometer
wiper settings and the configuration of both poten-
tiometers. This is done by setting the two MSBs of the
Command Byte to one of three values. If 00 is set as
the value for the two MSBs, then the wiper setting for
Potentiometer 0 is to be programmed. If 01 is set as the
value, then the wiper setting of Potentiometer 1 is to be
programmed. See the Potentiometer Wiper Setting sec-
tion for more details about writing the wiper setting. A
value of 10 indicates that the Configuration Register is
to be programmed. A value of 11 is reserved and is not
to be used. See the Configuration Register section for
more information. Any values other than the three dis-
cussed above will result in no action by the part. See
below for the Command Byte structure.
Table 2. Configuration Option 2
TAP POSITION
ATTENUATION (dB)
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
10
11
12
14
16
18
20
22
24
26
28
30
32
34
36
39
42
45
48
51
54
57
60
80
Command Byte Structure
CONFIGURATION
SELECTION
REGISTER
SETTINGS
MSB
LSB
_____________________________________________________________________
9
Dual NV Audio Taper Digital Potentiometer
Potentiometer Wiper Setting
If 00 or 01 are the values of the two MSBs of the
Command Byte, then the wiper settings of the poten-
tiometers are to be programmed. The lower 6 LSBs of
the Command Byte are then used to store the wiper
settings for the selected potentiometer. See below for
the potentiometer wiper setting details.
POTENTIOMETER WIPER REGISTER
Factory Default:
Memory Type:
XX111111b
NV (EEPROM)
0
X
WIPER SETTING
b7
b6
b5
b4
b3
b2
b1
b0
Configuration Selection: Selects which potentiometer will be programmed.
00 = Potentiometer 0 will be programmed.
bits 7, 6
01 = Potentiometer 1 will be programmed.
These bits determine the wiper setting of the selected potentiometer. Available wiper settings are determined by
the attenuation option as described in the Configuration Register section.
bits 5–0
10
____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Configuration Register
If 10 is entered as the value of the two MSBs of the
Command Byte, then the Configuration Register is to
be modified. The three LSBs of the Configuration
Register control the NV/volatile wiper setting, the zero-
crossing detection feature, and the potentiometer atten-
uation configuration.
CONFIGURATION REGISTER
Factory Default:
Memory Type:
87h
NV (EEPROM)
V/NV
CONTROL
ZERO-
CROSSING
POT
CONFIG
1
0
X
X
X
b7
b6
b5
b4
b3
b2
b1
b0
Configuration Selection: When bit 7 is set to a 1 and bit 6 is set to a 0, the following configuration bits can be set
and stored in EEPROM.
bits 7, 6
bits 5, 4, 3
These bits have no function.
Volatile/Nonvolatile Potentiometer Register Control Bit: A control bit that sets the potentiometer registers to be
either volatile or nonvolatile memory.
bit 2
0 = Potentiometer registers are set to nonvolatile memory storage.
1 = Potentiometer registers are set to volatile memory storage. On power-up, the potentiometer wipers are in the
mute position (default).
Zero-Crossing Detection Enable Bit: A bit used to enable and disable the zero-crossing functionality.
0 = Zero-crossing detection is disabled.
1 = Zero-crossing detection is enabled (default).
bit 1
bit 0
Potentiometer Position Configuration: A control bit used to select the number of positions both potentiometers
have.
0 = Potentiometers have 63 positions and mute.
1 = Potentiometers have 33 positions and mute (default).
____________________________________________________________________ 11
Dual NV Audio Taper Digital Potentiometer
I2C Interface for the DS1881
The CE pin serves as a communication enable pin.
When active (CE = 0), the inputs SDA and SCL are rec-
ognized by the device. If inactive (CE = 1), pins SDA
and SCL are disabled, making I2C communication
impossible.
the DS1881 is allowed to receive communications from
the I2C bus.
The I2C slave address byte is shown below. This is the
first byte transmitted from the master to the DS1881.
The upper nibble value is fixed to 0101. Bit values A2,
A1, and A0 are determined by the states of the corre-
sponding pins. The LSB, R/W, determines whether a
read or write will be performed.
Three pins, A0, A1, A2, serve as slave address inputs.
For multidrop configurations, they allow eight such
devices to be addressed by the same I2C bus. If the
I2C address matches the hardware levels of these bits,
The next byte to be transmitted is the Command Byte
(see the Command Byte section for details).
SLAVE ADDRESS BYTE
A2
0
1
0
1
A1
A0
R/W
MSB
LSB
of Potentiometer 0 is the first returned from the DS1881.
It is then followed by the value of Potentiometer 1 and
then the value of the Configuration Register. Once the 8
bits of the Configuration Register have been sent, the
master needs to issue an acknowledge, unless it is the
last byte to be read, in which case the master issues a
not acknowledge. If desired, the master may stop the
communication transfer at this point by issuing the
STOP condition after the not acknowledge. However, if
the value of the three registers is needed again, the
transfer can continue by clocking the 8 bits of the
Potentiometer 0 value as described above.
Reading Pot Values
As shown in Figure 1, the DS1881 provides one read
command operation. This operation allows the user to
read both Potentiometer Wiper Setting Registers and
the Configuration Register. To initiate a read operation,
the R/W bit of the slave address byte is set to 1.
Communication to read the DS1881 begins with a
START condition, which is issued by the master device.
The slave address byte sent from the master device fol-
lows the START condition. Once a matching slave
address byte has been received by the DS1881, the
DS1881 responds with an acknowledge. The master
can then begin to receive data. The value of the wiper
READ PROTOCOL
COMMAND
BYTE
COMMAND
BYTE
COMMAND
BYTE
SLAVE ADDRESS
BYTE
MSB
0
LSB
MSB
0
LSB
MSB
0
LSB
MSB
1
LSB
CONFIG
REG
A
2
A
1
A
0
1
0
1
1
0
POT-0
1
POT-1
0
R/W = 1
DATA BYTES ARE READ IN THE ORDER SHOWN ABOVE.
Figure 1. Read Protocol
12
____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Writing Command Byte Values
An example of writing to the DS1881 is shown in Figure 2.
The DS1881 has one write command that is used to
change the Potentiometer Wiper Setting registers and the
Configuration Register. All write operations begin with a
START from the master, followed by a slave address
byte. The R/W bit should be written to 0, which initiates
a write command. Once the slave address byte has
been issued and the master receives the acknowledge
from the DS1881, potentiometer wiper data is transmit-
ted to the DS1881 by the master device.
I2C Definitions
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
If the potentiometer has been configured to be written
in nonvolatile memory (see the Configuration Register
section), then the acknowledge needs to be followed
with a STOP command. This command is required from
the master at the end of data transmission to initiate the
EEPROM write. The STOP command is also accepted if
the user has configured the pot values to be written in
volatile memory, but no EEPROM is written to.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
2
I C Serial Interface Descriptions
I2C interface supports a bidirectional data transmission
protocol with device addressing. A device that sends
data on the bus is defined as a transmitter, and a
device receiving data as a receiver. The device that
controls the message is called a master. The devices
that are controlled by the master are slaves. The bus
must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The
DS1881 operates as a slave on the I2C bus. Connections
to the bus are made by the open-drain I/O lines, SDA
and SCL. The following I/O terminals control the I2C
serial port: CE, SDA, SCL, A0, A1, and A2. A data
transfer protocol and a timing diagram are provided in
Figures 3 and 4. The following terminology is commonly
used to describe I2C data transfers.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS
are commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition. See the timing diagram for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 4). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
WRITE PROTOCOL
COMMAND
BYTE
COMMAND
BYTE
COMMAND
BYTE
SLAVE ADDRESS
BYTE
MSB
0
LSB
MSB
0
LSB
MSB
0
LSB
MSB
1
LSB
CONFIG
REG
A
2
A
1
A
0
1
0
1
0
0
POT-0
1
POT-1
0
R/W = 0
DATA BYTES CAN BE WRITTEN IN ANY ORDER.
Figure 2. Write Protocol
____________________________________________________________________ 13
Dual NV Audio Taper Digital Potentiometer
setup time (see Figure 4) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
(Figure 4) for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERRED
CONDITION
Figure 3. Data Transfer Protocol
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:DAT
SU:STO
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 4. I C Timing Diagram
14
____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
desired number of data bytes and generates a STOP
condition. The DS1881 is capable of writing both poten-
tiometer wiper settings and the Configuration Register
with a single write transaction.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave will return control of SDA to
the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave addressing byte sent immediately
following a START condition. The slave address byte
(Figure 5) contains the slave address in the most signif-
icant 7 bits and the R/W bit in the least significant bit.
Acknowledge Polling: Any time an EEPROM location
is written, the DS1881 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the byte of data to EEPROM. During the EEPROM write
time, the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS1881, which allows the next page to be written as
soon as the DS1881 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of t to elapse before attempting to write
W
again to the device.
EEPROM Write Cycles: When EEPROM writes occur to
the memory, the DS1881 will write to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte repeat-
edly. The DS1881’s EEPROM write cycles are specified in
the NV Memory Characteristics table. The specification
shown is at the worst-case temperature. If zero-crossing
detection is enabled, EEPROM write cycles cannot begin
until after the zero-crossing detection is complete.
The DS1881’s slave address is 0101 A2 A1 A0 (binary),
where A2, A1, and A0 are the values of the address
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W = 0, the master indi-
cates it will write data to the slave. If R/W = 1, the mas-
ter will read data from the slave. If an incorrect slave
address is written, the DS1881 will assume the master is
communicating with another I2C device and ignore the
communications until the next START condition is sent.
Reading a Single Byte from a Slave: To read a single
byte from the slave, the master generates a START con-
dition, writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition. When a single
byte is read, it will always be the Potentiometer 0 value.
I2C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte, it NACKs to indicate the end of
the transfer and generates a STOP condition. The first
byte read will be the Potentiometer 0 Wiper Setting. The
next byte will be the Potentiometer 1 Wiper Setting. The
third byte is the Configuration Register byte. If an ACK
is issued by the master following the Configuration
Register byte, then the DS1881 will send the
Potentiometer 0 Wiper Setting again. This round robin
reading will occur as long as each byte read is followed
by an ACK from the master.
DETERMINES
READ OR WRITE
7-BIT SLAVE
ADDRESS
FUNCTION
0
1
0
1
A1
A0
R/W
LSB
A2
MSB
A2, A1, AND A0
PIN VALUES
Figure 5. DS1881’s Slave Address Byte
____________________________________________________________________ 15
Dual NV Audio Taper Digital Potentiometer
SDA and SCL Pullup Resistors
Applications Information
SDA is an open-collector output on the DS1881 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be uti-
lized for SCL. Pullup resistor values should be chosen
to ensure that the rise and fall times listed in the AC
Electrical Characteristics table are within specification.
Power-Supply Decoupling
To achieve best results, it is recommended that the
power supplies are decoupled with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as pos-
sible to the voltage supplies and GND pins to minimize
lead inductance.
Typical Operating Circuit
5V (V
)
5V (V )
CC
DD
V
V
CC
DD
DECOUPLING
CAPACITOR
DECOUPLING
CAPACITOR
4.7kΩ
4.7kΩ
GND
SDA
HOST
µC
SCL
CE
DS1881
H1
W1
L1
A2
A1
A0
AUDIO
OUT
H0
W0
L0
5V (V
)
CC
AUDIO IN
(AC + V / 2)
20kΩ
CC
V
/ 2 = 2.5V
CC
20kΩ
Chip Topology
Package Information
For the latest package outline information, go to
TRANSISTOR COUNT: 52,353
www.maxim-ic.com/DallasPackInfo.
SUBSTRATE CONNECTED TO GROUND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney
DS1881Z-050+T&R CAD模型
引脚图
封装焊盘图
DS1881Z-050+T&R 相关器件
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| DS1882Z-050+ | MAXIM | Dual Log Audio Digital Potentiometer | 获取价格 |
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| DS1882Z-050+T&R | MAXIM | Dual Log Audio Digital Potentiometer | 获取价格 |
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| DS1884T+ | MAXIM | Power Supply Support Circuit, Fixed, 1 Channel, 4 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, TQFN-24 | 获取价格 |
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