DS1921G-F5N# [MAXIM]
Analog Circuit, 1 Func, CAN-2;
| 型号： | DS1921G-F5N# |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, CAN-2 |
| 文件： | 总42页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5101; Rev 3; 4/10
Thermochron iButton
DS921G
General Description
Features
®
®
♦ Digital Thermometer Measures Temperature in
The DS1921G Thermochron iButton is a rugged, self-
sufficient system that measures temperature and records
the result in a protected memory section. The recording
is done at a user-defined rate, both as a direct storage of
temperature values as well as in the form of a histogram.
Up to 2048 temperature values taken at equidistant inter-
vals ranging from 1 to 255min can be stored. The his-
togram provides 63 data bins with a resolution of 2.0°C.
If the temperature leaves a user-programmable range,
the DS1921G also records when this happened, for how
long the temperature stayed outside the permitted range,
and if the temperature was too high or too low. An addi-
tional 512 bytes of read/write nonvolatile (NV) memory
allows storing information pertaining to the object to
which the DS1921G is associated. Data is transferred
0.5°C Increments
♦ Accuracy ±±°C ꢀrom ꢁ-0°C to ꢂ+0°C ꢃ(ee the
Electrical Characteristics ꢀor Accuracy
(peciꢀication)
♦ BuiltꢁIn RealꢁTime Clock ꢃRTC) and Timer Has
Accuracy oꢀ ±ꢄ Minutes per Month ꢀrom 0°C to ꢂꢅ5°C
♦ Water Resistant or Waterprooꢀ iꢀ Placed Inside
D(9±0+ iButton Capsule ꢃExceeds Water
Resistant - ATM Requirements)
♦ Automatically Wakes Up and Measures Temperature
at UserꢁProgrammable Intervals ꢀrom ± Minute to
ꢄ55 Minutes
♦ Logs Up to ꢄ0ꢅ8 Consecutive Temperature
Measurements in Protected NV RAM
®
serially through the 1-Wire protocol, which requires only
♦ Records a LongꢁTerm Temperature Histogram
a single data lead and a ground return. Every DS1921G
is factory lasered with a guaranteed unique, electrically
readable, 64-bit registration number that allows for abso-
lute traceability. The durable stainless steel package is
highly resistant to environmental hazards such as dirt,
moisture, and shock. Accessories permit the DS1921G
to be mounted on almost any object including contain-
ers, pallets, and bags.
with ꢄ.0°C Resolution
♦ Programmable Temperature High and
Temperature Low Alarm Trip Points
♦ Records Up to ꢄꢅ Timestamps and Durations
When Temperature Leaves the Range (peciꢀied
by the Trip Points
♦ 5±ꢄ Bytes oꢀ GeneralꢁPurpose Read/Write NV RAM
♦ Communicates to Host with a (ingle Digital (ignal
at ±5.ꢅkbps or ±ꢄ5kbps Using ±ꢁWire Protocol
Applications
Common iButton Features
Temperature Logging in Cold Chain, Food Safety,
Pharmaceutical, and Medical Products
♦ Digital Identiꢀication and Inꢀormation by
Momentary Contact
Ordering Information
♦ Unique, FactoryꢁLasered, and Tested 6ꢅꢁBit
Registration Number ꢃ8ꢁBit Family Code ꢂ ꢅ8ꢁBit
(erial Number ꢂ 8ꢁBit CRC Tester) Assures
Absolute Traceability Because No Two Parts are
Alike
PART
TEMP RANGE
PIN-PACKAGE
DS1921G-F5#
-40°C to +85°C
F5 iButton
#Denotes a RoHS-compliant device that may include lead(Pb)
that is exempt under the RoHS requirements.
♦ Multidrop Controller ꢀor ±ꢁWire Net
♦ ChipꢁBased Data Carrier Compactly (tores Inꢀormation
♦ Data Can Be Accessed While Aꢀꢀixed to Object
Examples of Accessories
♦ Button (hape is (elꢀꢁAligning with Cupꢁ(haped
PART
DS9096P
DS9101
ACCESSORY
Probes
Self-Stick Adhesive Pad
♦ Durable (tainlessꢁ(teel Case Engraved with
Registration Number Withstands Harsh
Environments
♦ Easily Aꢀꢀixed with (elꢀꢁ(tick Adhesive Backing,
Latched by Its Flange, or Locked with a Ring
Pressed Onto Its Rim
Multipurpose Clip
Mounting Lock Ring
Snap-In Fob
DS9093RA
DS9093A
DS9092
iButton Probe
♦ Presence Detector Acknowledges When Reader
First Applies Voltage
Pin Conꢀiguration appears at end oꢀ data sheet.
♦ Meets UL 9±- ꢃꢅth Edit.); Intrinsically (aꢀe
Apparatus: Approved Under Entity Concept ꢀor Use
in Class I, Division ±, Group A, B, C and D Locations
Thermochron, iButton, and 1-Wire are registered trademarks of
Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering inꢀormation, please contact Maxim Direct at ±ꢁ888ꢁ6ꢄ9ꢁꢅ6ꢅꢄ,
or visit Maxim’s website at www.maximꢁic.com.
Thermochron iButton
AB(OLUTE MAXIMUM RATING(
IO Voltage Range Relative to GND ..........................-0.5V to +6V
IO Sink Current....................................................................20mA
Operating Temperature Range..........................-40°C to +85°C*
Storage Temperature Range..............................-40°C to +50°C*
*Storage or operation above +50°C significantly reduces battery life.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS921G
ELECTRICAL CHARACTERI(TIC(
(V
PUP
= +2.8V to +5.25V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Resistance
Input Capacitance
R
(Notes 1, 2)
(Notes 3, 4)
2.2
800
10
kꢀ
pF
μA
PUP
C
100
IO
L
Input Load Current
I
IO pin at V
(Note 5)
PUP
V
> 4.5V
PUP
1.14
0.71
2.70
2.70
0.30
2.70
2.70
0.4
High-to-Low Switching Threshold
(Notes 4, 6, 7, 8)
V
V
V
V
V
TL
Input Low Voltage
V
(Notes 1, 6, 9)
> 4.5V
IL
V
1.00
0.66
Low-to-High Switching Threshold
(Notes 4, 6, 7, 10)
PUP
V
TH
OL
Output Low Voltage at 4mA
V
(Notes 6, 11)
Standard speed, R
= 2.2kꢀ
5
2
PUP
Overdrive speed, R
= 2.2kꢀ
PUP
Recovery Time (Notes 1, 4)
t
μs
μs
REC
Overdrive speed, directly prior to reset
pulse; R = 2.2kꢀ
5
PUP
Standard speed
Overdrive speed
65
8
Time-Slot Duration (Notes 1, 12)
t
SLOT
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed, V
> 4.5V
480
540
48
640
640
80
PUP
Standard speed
Reset Low Time (Notes 1,12)
t
μs
RSTL
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
> 4.5V
PUP
58
80
15
60
Presence-Detect High
Time (Note 12)
t
μs
μs
μs
PDH
1.1
60
6
270
24
Presence-Detect Low
Time (Note 12)
t
> 4.5V
7.5
7.5
60
PDL
PUP
32
75
Presence-Detect
Sample Time (Notes 1, 4)
t
MSP
6
8.6
ꢄ
_______________________________________________________________________________________
Thermochron iButton
DS921G
ELECTRICAL CHARACTERI(TIC( ꢃcontinued)
(V
PUP
= +2.8V to +5.25V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Standard speed
60
6
120
15
Write-Zero Low Time
(Notes 1, 12)
t
μs
μs
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
> 4.5V
W0L
PUP
8.5
5
15
15 - ꢁ
2 - ꢁ
Write-One Low Time
(Notes 1, 13)
t
W1L
1
IO PIN: 1-Wire READ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
15 - ꢂ
2 - ꢂ
15
Read Low Time (Notes 1, 14)
t
μs
μs
RL
t
t
+ ꢂ
Read Sample Time
(Notes 1, 14)
RL
RL
t
MSR
+ ꢂ
2
REAL-TIME CLOCK
Frequency Deviation
ꢃ
F
-5°C to +46°C
-48
+46
ppm
TEMPERATURE CONVERTER
Tempcore Operating Range
Conversion Time
T
-40
19
+85
90
°C
TC
t
ms
CONV
Thermal Response Time
Constant
ꢄ
(Note 15)
130
s
RESP
-40°C to < -30°C
-30°C to +70°C
> +70°C to +85°C
-1.3
-1.0
-1.3
+1.3
+1.0
+1.3
Conversion Error
(Notes 16, 17)
ꢃꢅ
°C
—
(See the accuracy
graphs.)
Number of Conversions
N
(Notes 4, 18)
CONV
Note ±: System requirement.
Note ꢄ: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For
more heavily loaded systems, an active pullup such as that found in the DS2480B may be required.
Note -: Capacitance on IO could be 800pF when power is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs
after V
has been applied, the parasite capacitor does not affect normal communication.
PUP
Note ꢅ: These values are derived from simulation across process, voltage, and temperature and are not production tested.
Note 5: Input load is to ground.
Note 6: All voltages are referenced to ground.
Note +:
Note 8: Voltage below which, during a falling edge of IO, a logic 0 is detected.
Note 9: The voltage on IO must be less than or equal to V whenever the master drives the line low.
V , V are a function of the internal supply voltage.
TL TH
ILMAX
Note ±0: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note ±±: The I-V characteristic is linear for voltages less than 1V.
Note ±ꢄ: Numbers in bold are not in compliance with the published iButton standards. See the Comparison Table.
Note ±-: ε in Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from V to V
.
TH
IL
Note ±ꢅ: δ in Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from V to the input
IL
high threshold of the bus master.
Note ±5: This number was derived from a test conducted by Cemagref in Antony, France, in July 2000.
http://www.cemagref.fr/English/index.htm Test Report No. E42
Note ±6: Total accuracy is Δϑ plus 0.25°C quantization due to the 0.5°C digital resolution of the device.
_______________________________________________________________________________________
-
Thermochron iButton
ELECTRICAL CHARACTERI(TIC( ꢃcontinued)
(V
PUP
= +2.8V to +5.25V, T = -40°C to +85°C.)
A
Note ±+: WARNING: Not for use as the sole method of measuring or tracking temperature in products and articles that could affect
the health or safety of persons, plants, animals, or other living organisms, including but not limited to foods, beverages,
pharmaceuticals, medications, blood and blood products, organs, flammable, and combustible products. User shall
assure that redundant (or other primary) methods of testing and determining the handling methods, quality, and fitness of
the articles and products should be implemented. Temperature tracking with this product, where the health or safety of the
aforementioned persons or things could be adversely affected, is only recommended when supplemental or redundant
information sources are used. Data-logger products are 100% tested and calibrated at time of manufacture by Maxim to
ensure that they meet all data sheet parameters, including temperature accuracy. User shall be responsible for proper use
and storage of this product. As with any sensor-based product, user shall also be responsible for occasionally rechecking
the temperature accuracy of the product to ensure it is still operating properly.
DS921G
Note ±8: The number of temperature conversions (= samples) possible with the built-in energy source depends on the operating and
storage temperature of the device. When not in use for a mission, the RTC oscillator should be turned off and the device
should be stored at a temperature not exceeding +25°C. Under this condition the shelf life time is 10 years minimum.
COMPARI(ON TABLE
LEGACY VALUES
DS1921G VALUES
PARAMETER
STANDARD SPEED (μs) OVERDRIVE SPEED (μs) STANDARD SPEED (μs) OVERDRIVE SPEED (μs)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
(including
SLOT
61
(undefined)
7
(undefined)
65*
(undefined)
8*
(undefined)
)
REC
t
t
t
t
480
15
(undefined)
48
2
80
6
540
15
640
60
58
1.1
7.5
8.5
80
6
RSTL
PDH
PDL
60
60
240
120
8
24
16
60
270
120
32
15
60
6
60
W0L
*Intentional change; longer recovery time between time slots.
Note: Numbers in bold are not in compliance with the published iButton standards.
iButton CAN PHY(ICAL (PECIFICATION
SIZE
See the Package Information section.
WEIGHT
Ca. 3.3g
Meets UL 913 (4th Edit.); Intrinsically Safe Apparatus, approval under Entity Concept for use in Class I, Division 1,
Group A, B, C, and D Locations.
SAFETY
ꢅ
_______________________________________________________________________________________
Thermochron iButton
DS921G
RTC Deviation vs. Temperature
4
2
UPPER LIMIT
LOWER LIMIT
0
-2
-4
-6
-8
-10
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Minimum Product Lifetime vs. Temperature at Different Sample Rates
11.00
10.00
9.00
8.00
7.00
6.00
5.00
4.00
EVERY MINUTE
NO SAMPLES
EVERY 3 MINUTES
OSCILLATOR OFF
EVERY 10 MINUTES
3.00
2.00
1.00
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Thermochron iButton
Minimum Product Lifetime vs. Sample Rate at Different Temperatures
11.00
+15°C
10.00
-20°C
9.00
-40°C
8.00
+40°C
DS921G
7.00
+45°C
6.00
+50°C
5.00
+55°C
4.00
+60°C
3.00
2.00
+70°C
1.00
+85°C
0.00
1
10
100
1000
MINUTES BETWEEN SAMPLES
Accuracy Limits
2.0
1.5
UPPER LIMIT
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
LOWER LIMIT
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Thermochron iButton
DS921G
the Thermochron in the DS9107 iButton capsule. The
DS9107 provides a watertight enclosure that has been
rated to IP68 (refer to Application Note 4126:
Understanding the IP (Ingress Protection) Ratings of
iButton Data Loggers and Capsule).
Detailed Description
The DS1921G Thermochron iButton is an ideal device
to monitor the temperature of any object it is attached
to or shipped with, such as perishable goods or con-
tainers of temperature-sensitive chemicals. The
read/write NV memory can store an electronic copy of
shipping information, date of manufacture and other
important data written as clear as well as encrypted
files. Note that the initial sealing level of the DS1921G
achieves IP56. Aging and use conditions can degrade
the integrity of the seal over time, therefore, for applica-
tions with significant exposure to liquids, sprays, or
other similar environments, it is recommended to place
Overview
Figure 1 shows the relationships between the major
control and memory sections of the DS1921G. The
device has seven main data components: 64-bit
lasered ROM; 256-bit scratchpad; 4096-bit general-
purpose SRAM; 256-bit register page of timekeeping,
control, and counter registers; 96 bytes of alarm time-
stamp and duration logging memory; 126 bytes of
ROM
FUNCTION
CONTROL
64-BIT
PARASITE-POWERED
LASERED
1-Wire PORT
IO
CIRCUITRY
ROM
256-BIT
SCRATCHPAD
MEMORY
FUNCTION
CONTROL
DS1921G
GENERAL-PURPOSE
SRAM
INTERNAL
32.768kHz
TIMEKEEPING,
CONTROL REGISTERS,
AND COUNTERS
OSCILLATOR
REGISTER PAGE
ALARM TIMESTAMP AND
DURATION LOGGING
MEMORY
TEMPERATURE
CORE
HISTOGRAM
MEMORY
CONTROL
LOGIC
DATA-LOG MEMORY
3V LITHIUM
Figure 1. Block Diagram
_______________________________________________________________________________________
+
Thermochron iButton
histogram memory; and 2048 bytes of data-logging
memory. Except for the ROM and the scratchpad, all
other memory is arranged in a single linear address
space. All memory reserved for logging purposes,
including counter registers and several other regis-
ters, is read-only for the user. The timekeeping and
control registers are write protected while the device
is programmed for a mission.
available commands. The protocol for these memory
function commands is described in Figure 10. All data
is read and written least signiꢀicant bit ꢀirst.
Parasite Power
Figure 1 shows the parasite-powered circuitry. This cir-
cuitry “steals” power whenever the IO input is high. IO
provides sufficient power as long as the specified tim-
ing and voltage requirements are met. The advantages
of parasite power are two-fold: 1) By parasiting off this
input, battery power is not consumed for 1-Wire ROM
function commands, and 2) if the battery is exhausted
for any reason, the ROM may still be read normally. The
remaining circuitry of the DS1921G is solely operated
by battery energy.
The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide
one of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Conditional Search ROM,
Skip ROM, Overdrive-Skip ROM, or Overdrive-Match
ROM. Upon completion of an Overdrive ROM com-
mand byte executed at standard speed, the device
enters overdrive mode, where all subsequent communi-
cation occurs at a higher speed. The protocol required
for these ROM function commands is described in
Figure 13. After a ROM function command is success-
fully executed, the memory functions become accessi-
ble and the master can provide any one of the seven
DS921G
64-Bit Lasered ROM
Each DS1921G contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits
(see Figure 3 for details). The 1-Wire CRC is generated
1-Wire NET
BUS
MASTER
OTHER DEVICES
DS1921G
COMMAND LEVEL:
AVAILABLE COMMANDS:
COMMAND CODES:
DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
CONDITIONAL SEARCH ROM
33h
55h
F0h
CCh
3Ch
69h
ECh
64-BIT ROM
64-BIT ROM
64-BIT ROM
N/A
1-Wire ROM
FUNCTION COMMANDS
OD-FLAG
64-BIT ROM, OD-FLAG
64-BIT ROM, CONDITIONAL SEARCH
SETTINGS, DEVICE STATUS
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
READ MEMORY WTH CRC
CLEAR MEMORY
0Fh
AAh
55h
F0h
A5h
3Ch
256-BIT SCRATCHPAD, FLAGS
256-BIT SCRATCHPAD
4096-BIT SRAM, REGISTERS, FLAGS
ALL MEMORY
DS1921G-SPECIFIC
MEMORY/CONTROL
FUNCTION COMMANDS
ALL MEMORY
MISSION TIMESTAMP, MISSION SAMPLES COUNTER,
START DELAY, SAMPLE RATE, ALARM TIMESTAMPS
AND DURATIONS, HISTOGRAM MEMORY
MEMORY ADDRESS 211h
CONVERT TEMPERATURE
44h
Figure 2. Hierarchical Structure for 1-Wire Protocol
8
_______________________________________________________________________________________
Thermochron iButton
DS921G
MSB
MSB
LSB
8-BIT
CRC CODE
8-BIT FAMILY CODE
48-BIT SERIAL NUMBER
(21h)
LSB MSB
LSB MSB
LSB
Figure 3. 64-Bit Lasered ROM
8
5
4
POLYNOMIAL = X + X + X + 1
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
8TH
STAGE
0
1
2
3
4
5
6
7
8
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 4. 1-Wire CRC Generator
using a polynomial generator consisting of a shift regis-
ter and XOR gates as shown in Figure 4. The polynomi-
al is X + X + X + 1. Additional information about the
1-Wire CRC is available in Application Note 27:
Understanding and Using Cyclic Redundancy Checks
with Maxim iButton Products.
Memory
Figure 5 shows the DS1921G memory map. The 4096-
bit general-purpose SRAM makes up pages 0 to 15.
The timekeeping, control, and counter registers fill
page 16, called register page (see Figure 6). Pages 17,
18, and 19 are assigned to storing the alarm time-
stamps and durations. The temperature histogram bins
begin at page 64 and use up to four pages. The tem-
perature-logging memory covers pages 128 to 191.
Memory pages 20 to 63, 68 to 127, and 192 to 255 are
reserved for future extensions. The scratchpad is an
additional page that acts as a buffer when writing to the
SRAM memory or the register page. The memory
pages 17 and higher are read only for the user. They
are written to or erased solely under the supervision of
the on-chip control logic.
8
5
4
The Shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is then entered.
After the 48th bit of the serial number has been
entered, the Shift register contains the CRC value.
Shifting in the 8 bits of CRC returns the Shift register to
all zeros.
_______________________________________________________________________________________
9
Thermochron iButton
32-BYTE INTERMEDIATE STORAGE SCRATCHPAD
ADDRESS
0000h to 01FFh
0200h to 021Fh
0220h to 027Fh
0280h to 07FFh
0800h to 087Fh
0880h to 0FFFh
1000h to 17FFh
1800h to 1FFFh
GENERAL-PURPOSE SRAM (16 PAGES)
32-BYTE REGISTER PAGE
PAGES 0 to 15
PAGE 16
ALARM TIMESTAMPS AND DURATIONS
(RESERVED FOR FUTURE EXTENSIONS)
TEMPERATURE HISTOGRAM MEMORY
(RESERVED FOR FUTURE EXTENSIONS)
DATA-LOG MEMORY (64 PAGES)
PAGES 17 to 19
PAGES 20 to 63
PAGES 64 to 67
PAGES 68 to 127
PAGES128 to 191
PAGES 192 to 255
DS921G
(RESERVED FOR FUTURE EXTENSIONS)
Figure 5. Memory Map
ADDRESS BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
ACCESS*
0200h
0201h
0
0
10 Seconds
10 Minutes
Single Seconds
Single Minutes
20 Hour
AM/PM
0202h
0
12/24
10 Hour
0
Single Hours
RTC
Registers
R/W R/W**
0203h
0204h
0
0
0
0
0
0
Day of Week
10 Date
Single Date
10
Months
0205h
CENT
0
0
Single Months
0206h
0207h
0208h
10 Years
Single Years
MS
10 Seconds Alarm
10 Minutes Alarm
20 Hour
Single Seconds Alarm
Single Minutes Alarm
MM
RTC Alarm
Registers
R/W R/W**
R/W R/W**
10 Hour
Alarm
0209h
MH
MD
12/24
AM/PM
Alarm
Single Hours Alarm
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0
0
0
0
Day of Week Alarm
Temperature Low Alarm Threshold
Temperature High Alarm Threshold
Temperature
Alarms
Number of Minutes Between Temperature Conversions
EMCLR EM RO TLS THS
(No function, reads 00h)
Sample Rate R/W
R**
R/W R/W**
R**
EOSC
0
TAS
Control
—
R
*The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while a
mission is in progress.
**While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only
ones), however, ends the mission and overwrites selected writable registers.
Figure 6. Register Pages Map
±0 ______________________________________________________________________________________
Thermochron iButton
DS921G
ADDRESS BIT 7
0210h
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
—
ACCESS*
(No function, reads 00h)
R
R
R**
R**
0211h
Temperature Read-Out (Forced Conversion)
Temperature
0212h
Low Byte
High Byte
Mission Start
Delay
R/W R/W**
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
TCB
MEMCLR
MIP
SIP
Minutes
0
TLF
THF
TAF
Status
R/W
R/W
Hours
Date
Mission
Timestamp
R
R
Month
Year
Low Byte
Center Byte
High Byte
Low Byte
Mission
Samples
Counter
R
R
R
R
Device
Samples
Counter
Center Byte
High Byte
*The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while a
mission is in progress.
**While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only
ones), however, ends the mission and overwrites selected writable registers.
Figure 6. Register Pages Map (continued)
To distinguish between the days of the week, the
DS1921G includes a counter with a range from 1 to 7.
Detailed Register Descriptions
Timekeeping
The RTC/alarm and calendar information is accessed
by reading/writing the appropriate bytes in the register
page, address 0200h to 0206h. Note that some bits are
set to 0. These bits always read 0 regardless of how
they are written. The contents of the time, calendar, and
alarm registers are in the binary-coded decimal (BCD)
format.
The assignment of a counter value to the day of week is
arbitrary. Typically, the number 1 is assigned to a
Sunday (U.S. standard) or to a Monday (European stan-
dard).
The calendar logic is designed to automatically com-
pensate for leap years. For every year value that is
either 00 or a multiple of four, the device adds a 29th of
February. This works correctly up to (but not including)
the year 2100.
RTC/Calendar
The RTC of the DS1921G can run in either 12hr or 24hr
mode. Bit 6 of the Hours register (address 0202h) is
defined as the 12hr or 24hr mode select bit. When high,
the 12hr mode is selected. In the 12hr mode, bit 5 is the
AM/PM bit with logic 1 being PM. In the 24hr mode, bit
5 is the 20hr bit (20hr to 23hr).
The DS1921G is Y2K compliant. Bit 7 (CENT) of the
Months register at address 0205h serves as a century
flag. When the Year register rolls over from 99 to 00, the
century flag toggles. It is recommended to write the
century bit to a 1 when setting the RTC to a time/date
between the years 2000 and 2099.
______________________________________________________________________________________ ±±
Thermochron iButton
RTC and RTC Alarm Registers Map
ADDRESS
0200h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
10 Seconds
10 Minutes
Single Seconds
0201h
Single Minutes
Single Hours
20 Hour
AM/PM
0202h
0
12/24
10 Hour
0
0203h
0204h
0205h
0206h
0207h
0208h
0
0
0
0
0
0
0
Day of Week
DS921G
10 Date
Single Date
Single Months
CENT
0
10 Months
10 Years
Single Years
MS
10 Seconds Alarm
10 Minutes Alarm
Single Seconds Alarm
Single Minutes Alarm
MM
20 Hour
AM/PM
Alarm
10 Hour
Alarm
0209h
020Ah
MH
MD
12/24
0
Single Hours Alarm
0
0
0
Day of Week Alarm
RTC Alarm Control
ALARM REGISTER MASK BITS
(BIT 7 OF 0207h TO 20Ah)
FUNCTION
MS
1
MM
1
MH
1
MD
1
Alarm once per second.
Alarm when seconds match (once per minute).
0
1
1
1
0
0
1
1
Alarm when minutes and seconds match (once every hour).
0
0
0
1
Alarm when hours, minutes, and seconds match (once every day).
Alarm when day, hours, minutes, and seconds match (once every week).
0
0
0
0
the values stored in the RTC Alarm registers. Any alarm
sets the timer alarm flag (TAF) in the device’s Status
register (address 214h). The bus master can set the
search conditions in the Control register (address
20Eh) to identify devices with timer alarms by means of
the conditional search function (see the ROM Function
Commands section).
RTC Alarms
The DS1921G also contains an RTC alarm function. The
RTC Alarm registers are located in registers 0207h to
020Ah. The most significant bit of each of the alarm
registers is a mask bit. When all the mask bits are logic
0, an alarm occurs once per week when the values
stored in timekeeping registers 0200h to 0203h match
±ꢄ ______________________________________________________________________________________
Thermochron iButton
DS921G
Temperature Alarm Register Map
ADDRESS
020Bh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Temperature Low Alarm Threshold
Temperature High Alarm Threshold
020Ch
Sample Rate Register Map
ADDRRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
020Dh
Sample Rate
To specify the temperature alarm thresholds, this equa-
tion needs to be resolved to
Temperature Conversion
The DS1921G measures temperatures with a resolution
of 0.5°C. Temperature values are represented in a sin-
gle byte as an unsigned binary number, which trans-
lates into a theoretical range of 128°C. The range,
however, has been limited to values from 0000 0000
(00h) through 1111 1010 (FAh). The codes 01h to F9h
are considered valid temperature readings.
T[7…0] = 2 x ϑ(°C) + 80.0
A value of 23°C, for example, thus translates into 126
decimal or 7Eh. This corresponds to the binary patterns
0111 1110, which could be written to a Temperature
Alarm register (address 020Bh and 020Ch, respectively).
If a temperature conversion yields a temperature that is
out of range, it is recorded as 00h (if too low) or FAh (if
too high). Since out-of-range results are accumulated in
histogram bins 0 and 62 (see the Temperature Logging
and Histogram section), the data in these bins is of lim-
ited value. For this reason the specified temperature
range of the DS1921G is considered to begin at code
04h and end at code F7h, which corresponds to his-
togram bins 1 to 61.
Sample Rate
The content of the Sample Rate register (address
020Dh) determines how many minutes the temperature
conversions are apart from each other during a mission.
The sample rate can be any value from 1 to 255, coded
as an unsigned 8-bit binary number. If the memory has
been cleared (Status register bit MEMCLR = 1) and a
mission is enabled (Control register bit EM = 0), writing
a nonzero value to the Sample Rate register starts a mis-
sion. For a full description of the correct sequence of
steps to start a temperature-logging mission, see the
Missioning or Mission Example: Prepare and Start a
New Mission sections.
With T[7…0] representing the decimal equivalent of a tem-
perature reading, the temperature value is calculated as
ϑ(°C) = T[7…0]/2 - 40.0
This equation is valid for converting temperature read-
ings stored in the data-log memory as well as for data
read from the Forced Temperature Conversion Readout
register (address 0211h).
______________________________________________________________________________________ ±-
Thermochron iButton
Control Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
020Eh
EOSC
EMCLR
0
EM
RO
TLS
THS
TAS
and no further temperature values are stored in the
temperature logging memory once it is filled with data.
This does not stop the mission. The device continues
measuring temperatures and updating the histogram
and alarm timestamps and durations.
Control Register
The DS1921G is set up for its operation by writing
appropriate data to its special function registers that
are located in the register page. Several functions that
are controlled by a single bit only are combined into a
single byte called the Control register (address 020Eh).
This register can be read and written. If the device is
programmed for a mission, writing to the Control regis-
ter ends the mission and changes the register contents.
DS921G
Bit ꢄ: Temperature Low Alarm (earch ꢃTL(). If this
bit is 1, the device responds to a Conditional Search
ROM command if, during a mission, the temperature
has reached or is lower than the Low Temperature
Threshold stored at address 020Bh.
The functional assignments of the individual bits are
explained below. Bit 5 has no function. It always reads
0 and cannot be written to 1.
Bit ±: Temperature High Alarm (earch ꢃTH(). If this
bit is 1, the device responds to a Conditional Search
ROM command if, during a mission, the temperature
has reached or is higher than the High Temperature
Threshold stored at address 020Ch.
Bit +: Enable Oscillator ꢃEOSC). This bit controls the
crystal oscillator of the RTC. When set to logic 0, the
oscillator starts operation. When written to logic 1, the
oscillator stops and the device is in a low-power data-
retention mode. This bit must be 0 ꢀor normal operaꢁ
tion. The RTC must have advanced at least 1 second
before a Mission Start is accepted.
Bit 0: Timer Alarm (earch ꢃTA(). If this bit is 1, the
device responds to a Conditional Search ROM com-
mand if, during a mission, a timer alarm has occurred.
Since a timer alarm cannot be disabled, the TAF flag
usually reads 1 during a mission. Therefore, it is advis-
able to set the TAS bit to a 0, in most cases.
Bit 6: Memory Clear Enable ꢃEMCLR). This bit needs
to be set to logic 1 to enable the Clear Memory func-
tion, which is invoked as a memory function command.
The timestamp, histogram memory as well as the
Mission Timestamp, Mission Samples Counter, Mission
Start Delay, and Sample Rate are cleared only if the
Clear Memory command is issued with the next
access to the device. The EMCLR bit returns to 0 as
the next memory function command is executed.
Mission Start Delay Counter
The content of the Mission Start Delay Counter register
determines how many minutes the device waits before
starting the logging process. The Mission Start Delay
value is stored as an unsigned 16-bit integer number at
addresses 0212h (low byte) and 0213h (high byte). The
maximum delay is 65,535 minutes, equivalent to 45
days, 12 hours, and 15 minutes.
Bit ꢅ: Enable Mission ꢃEM). This bit controls whether
the DS1921G begins a mission as soon as the sample
rate is written. To enable the device for a mission, this
bit must be 0.
For a typical mission, the Mission Start Delay is 0. If a
mission is too long for a single DS1921G to store all
temperature readings at the selected sample rate, one
can use several devices, staggering the Mission Start
Delay to record the full period. In this case, the rollover
enable (RO) bit in the Control register (address 020Eh)
must be set to 0 to prevent overwriting of the recorded
temperature log after the data-log memory is full. See
the Mission Start and Logging Process section and
Figure 11 for details.
Bit -: Rollover Enable/Disable ꢃRO). This bit controls
whether the temperature logging memory is overwritten
with new data or whether data logging is stopped once
the memory is filled with data during a mission. Setting
this bit to a 1 enables the rollover and data logging
continues at the beginning, overwriting previously col-
lected data. Clearing this bit to 0 disables the rollover
±ꢅ ______________________________________________________________________________________
Thermochron iButton
DS921G
Status Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0214h
TCB
MEMCLR
MIP
SIP
0
TLF
THF
TAF
the address range of 200h to 213h. Alternatively, a mis-
sion can be ended by directly writing to the Status reg-
ister and setting the MIP bit to 0. The MIP bit cannot be
set to 1 by writing to the Status register.
Status Register
The Status register holds device status information
and alarm flags. The register is located at address
0214h. Writing to this register does not necessarily
end a mission.
BIT ꢅ: (ample in Progress ꢃ(IP). If this bit reads 1, the
DS1921G is currently performing a temperature conver-
sion as part of a mission in progress. The mission sam-
ples occur on the seconds rollover from 59 to 00. The
SIP bit changes from 0 to 1 approximately 250ms
before the actual temperature conversion begins allow-
ing the circuitry of the chip to wake up. A temperature
conversion including a wake-up phase takes maximum
875ms. During this time, read accesses to the memory
pages 17 and higher are permissible but can reveal
invalid data.
The functional assignments of the individual bits are
explained below. The bits MIP, TLF, THF, and TAF can
only be written to 0. All other bits are read-only. Bit 3
has no function.
Bit +: Temperature Core Busy ꢃTCB). If this bit reads
0, the DS1921G is currently performing a temperature
conversion. This temperature conversion is either self-
initiated because of a mission being in progress or initi-
ated by a command when a mission is not in progress.
The TCB bit goes low just before a conversion starts
and returns to high just after the result is latched into
the Read-Out register at address 0211h.
Bit ꢄ: Temperature Low Flag ꢃTLF). Logic 1 in the
temperature low flag bit indicates that a temperature
measurement during a mission revealed a temperature
equal to or lower than the value in the Temperature Low
Threshold register. The temperature low flag can be
cleared at any time by writing this bit to 0. This flag
must be cleared before starting a new mission.
Bit 6: Memory Cleared ꢃMEMCLR). If this bit reads 1,
the memory pages 17 and higher (alarm timestamps/
durations, temperature histogram, excluding data-log
memory), as well as the Mission Timestamp, Mission
Samples Counter, Mission Start Delay, and Sample
Rate have been cleared to 0 from executing a Clear
Memory function command. The MEMCLR bit returns to
0 as soon as writing a nonzero value to the Sample
Rate register starts a new mission, provided that the EM
bit is also 0. The memory has to be cleared in order
ꢀor a mission to start.
Bit ±: Temperature High Flag ꢃTHF). Logic 1 in the
temperature high flag bit indicates that a temperature
measurement during a mission revealed a temperature
equal to or higher than the value in the Temperature
High Threshold register. The temperature high flag can
be cleared at any time by writing this bit to 0. This flag
must be cleared before starting a new mission.
Bit 5: Mission in Progress ꢃMIP). If this bit reads 1, the
DS1921G has been set up for a mission and this mis-
sion is still in progress. A mission is started if the EM bit
of the Control register (address 20Eh) is 0 and a nonze-
ro value is written to the Sample Rate register, address
20Dh. The MIP bit returns from logic 1 to logic 0 when a
mission is ended. A mission ends with the first write
attempt (Copy Scratchpad command) to any register in
Bit 0: Timer Alarm Flag ꢃTAF). If this bit reads 1, a
RTC alarm has occurred (see the Timekeeping section
for details). The timer alarm flag can be cleared at any
time by writing this bit to logic 0. Since the timer alarm
cannot be disabled, the TAF flag usually reads 1 during
a mission. This flag should be cleared before starting a
new mission.
______________________________________________________________________________________ ±5
Thermochron iButton
Mission Timestamp Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0215h
0
10 Minutes
Single Minutes
20 Hour
AM/PM
0216h
0
12/24
10 Hour
Single Hours
0217h
0218h
0219h
0
0
0
0
10 Date
Single Date
Single Months
Single Years
0
10 Months
DS921G
10 Years
Mission Samples Counter Register Map
ADDRESS
021Ah
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Low Byte
021Bh
Center Byte
High Byte
021Ch
Device Samples Counter Register Map
ADDRESS
021Dh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Low Byte
021Eh
Center Byte
High Byte
021Fh
Mission Timestamp
Temperature Logging and Histogram
Once set up for a mission, the DS1921G logs the tem-
perature measurements simultaneously byte after byte
in the data-log memory as well as in histogram form in
the histogram memory. The data-log memory is able to
store 2,048 temperature values measured at equidis-
tant time points. The first temperature value of a mission
is written to address location 1000h of the data-log
memory, the second value to address location 1001h
and so on. Knowing the starting time point (Mission
Timestamp register), the interval between temperature
measurements, the Mission Samples Counter register,
and the rollover setting, one can reconstruct the time
and date of each measurement stored in the data log.
The Mission Timestamp register indicates the time and
date of the first temperature conversion of a mission.
Subsequent temperature conversions take place as
many minutes apart from each other as specified by the
value in the Sample Rate register. Mission samples
occur on minute boundaries.
Mission Samples Counter
The Mission Samples Counter register indicates how
many temperature measurements have taken place
during the current mission in progress (if MIP = 1) or
during the latest mission (if MIP = 0). The value is
stored as an unsigned 24-bit integer number. This
counter is reset through the Clear Memory command.
There are two alternatives to the way the DS1921G
behaves after the 2048 bytes of data-log memory is
filled with data. With rollover disabled (RO = 0), the
device fills the data-log memory with the first 2048 mis-
sion samples. Additional mission samples are not
logged in the data-log, but the histogram and tempera-
ture alarm RAM continue to update. With rollover
enabled (RO = 1), the data log wraps around and over-
writes previous data starting at 1000h for the every
2049th mission sample. In this mode, the device stores
the last 2048 mission samples.
Device Samples Counter
The Device Samples Counter register indicates how
many temperature measurements have taken place
since the device was assembled at the factory. The
value is stored as an unsigned, 24-bit integer number.
The maximum number that can be represented in this
format is 16,777,215, which is higher than the expected
lifetime of the DS1921G iButton. This counter cannot be
reset under software control.
±6 ______________________________________________________________________________________
Thermochron iButton
DS921G
TEMPERATURE
EQUIVALENT IN °C
TEMPERATURE READING
HISTOGRAM BIN NUMBER HISTOGRAM BIN ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
…
-40.0 or lower
-39.5
0
0
800h to 801h
800h to 801h
800h to 801h
800h to 801h
802h to 803h
802h to 803h
802h to 803h
802h to 803h
804h to 805h
…
-39.0
0
-38.5
0
-38.0
1
-37.5
1
-37.0
1
-36.5
1
-36.0
2
…
…
60
61
61
61
61
62
62
62
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
+81.5
+82.0
+82.5
+83.0
+83.5
+84.0
+84.5
+85.0 or higher
878h to 879h
87Ah to 87Bh
87Ah to 87Bh
87Ah to 87Bh
87Ah to 87Bh
87Ch to 87Dh
87Ch to 87Dh
87Ch to 87Dh
Figure 7. Histogram Bin and Temperature Cross-Reference
For the temperature histogram, the DS1921G provides
63 bins that begin at memory address 0800h. Each bin
consists of a 16-bit, nonrolling-over binary counter that
is incremented each time a temperature value acquired
during a mission falls into the range of the bin. The least
significant byte of each bin is stored at the lower
address. Bin 0 begins at memory address 0800h, bin 1
at 0802h, and so on up to 087Ch for bin 62, as shown
in Figure 7. The number of the bin to be updated after a
temperature conversion is determined by cutting off the
two least significant bits of the binary temperature
value. Out-of-range values are range locked and count-
ed as 00h or FAh.
Temperature Alarm Logging
For some applications it is essential to not only record
temperature over time and the temperature histogram,
but also record when exactly the temperature exceed-
ed a predefined tolerance band and for how long the
temperature stayed outside the desirable range. The
DS1921G can log high and low durations. The toler-
ance band is specified by means of the Temperature
Alarm Threshold registers, addresses 20Bh and 20Ch
in the register page. One can set a high temperature
and low temperature threshold. See the Temperature
Conversion section for the data format the temperature
has to be written in. As long as the temperature values
stay within the tolerance band (i.e., are higher than the
low threshold and lower than the high threshold), the
DS1921G does not record any temperature alarm. If the
temperature during a mission reaches or exceeds
either threshold, the DS1921G generates an alarm and
sets either the temperature high flag (THF) or the tem-
perature low flag (TLF) in the Status register (address
Since each data bin is 2 bytes, it can increment up to
65,535 times. Additional measurements for a bin that
has already reached its maximum value are not count-
ed; the bin counter remains at its maximum value. With
the fastest sample rate of one sample every minute, a
2-byte bin is sufficient for up to 45 days if all tempera-
ture readings fall into the same bin.
______________________________________________________________________________________ ±+
Thermochron iButton
ADDRESS
DESCRIPTION
ALARM EVENT
0220h
0221h
Mission Samples Counter, Low Byte
Mission Samples Counter, Center Byte
Mission Samples Counter, High Byte
Alarm Duration Counter
Low Alarm 1
0222h
0223h
0224h to 0227h
0228h to 024Fh
0250h
Alarm Timestamp and Duration
Alarm Timestamp and Durations
Mission Samples Counter, Low Byte
Mission Samples Counter, Center Byte
Mission Samples Counter, High Byte
Alarm Duration Counter
Low Alarm 2
DS921G
Low Alarms 3 to 12
0251h
High Alarm 1
0252h
0253h
0254h to 0257h
0258h to 027Fh
Alarm Timestamp and Duration
Alarm Timestamp and Durations
High Alarm 2
High Alarms 3 to 12
Figure 8. Alarm Timestamps and Durations Address Map
214h). This way, if the search conditions (address
20Eh) are set accordingly, the master can quickly iden-
tify devices with temperature alarms by means of the
conditional search function (see the ROM Function
Commands section). The device also generates a time-
stamp of when the alarm occurred and begins record-
ing the duration of the alarming temperature.
tion counter of the particular timestamp does not incre-
ment any further. Should the temperature again cross
this threshold, it is recorded at the next available alarm
location. This algorithm is implemented for the low tem-
perature thresholds as well as for the high temperature
threshold.
Missioning
Timestamps and durations where the temperature
leaves the tolerance band are stored in the address
range 0220h to 027Fh, as shown in Figure 8. This allo-
cation allows recording 24 individual alarm events and
periods (12 periods for too hot and 12 for too cold). The
date and time of each of these periods can be deter-
mined from the Mission Timestamp register and the
time distance between each temperature reading.
The typical task of the DS1921G iButton is recording
the temperature of a temperature-sensitive object.
Before the device can perform this function, it needs to
be configured. This procedure is called missioning.
First, the DS1921G must have its RTC set to a valid time
and date. This reference time can be UTC (also called
GMT, Greenwich Mean Time) or any other time stan-
dard that was chosen for the application. The clock
must be running (EOSC = 0) for at least one second.
Setting an RTC alarm is optional. The memory assigned
to store the alarm timestamps and durations, tempera-
ture histogram, Mission Timestamp, Mission Samples
Counter, Mission Start Delay, and Sample Rate must be
cleared using the Clear Memory command. In case
there were temperature alarms in the previous mission,
the TLF and THF flags need to be cleared manually. To
enable the device for a mission, the EM flag must be
set to 0. These are general settings that have to be
made regardless of the type of object to be monitored
and the duration of the mission.
The alarm timestamp is a copy of the Mission Samples
Counter register when the alarm first occurred. The
least significant byte is stored at the lower address.
One address higher than the timestamp, the DS1921G
maintains a 1-byte duration counter that stores the
number of samples the temperature was found to be
beyond the threshold. If this counter has reached its
limit after 255 consecutive temperature readings and
the temperature has not yet returned to within the toler-
ance band, the device issues another timestamp at the
next higher alarm location and opens another counter
to record the duration. If the temperature returns to nor-
mal before the counter has reached its limit, the dura-
±8 ______________________________________________________________________________________
Thermochron iButton
DS921G
Next, the low temperature and high temperature thresh-
olds that specify the temperature tolerance band must
be defined. The Temperature Conversion section
describes how to convert a temperature value into the
binary code to be written to the threshold registers.
Address Registers and
Transfer Status
Because of the serial data transfer, the DS1921G
employs three address registers, called TA1, TA2, and
E/S (Figure 9). Registers TA1 and TA2 must be loaded
with the target address to which the data is written or
from which data is sent to the master upon a read com-
mand. Register E/S acts like a byte counter and transfer
status register. It is used to verify data integrity with
write commands. Therefore, the master has only read
access to this register. The lower 5 bits of the E/S regis-
ter indicate the address of the last byte that has been
written to the scratchpad. This address is called Ending
Offset. Bit 5 of the E/S register, called PF or partial byte
flag, is set if the number of data bits sent by the master
is not an integer multiple of 8. Bit 6 is always a 0. Note
that the lowest 5 bits of the target address also deter-
mine the address within the scratchpad where interme-
diate storage of data begins. This address is called
byte offset. If the target address for a write command is
13Ch, for example, then the scratchpad stores incom-
ing data beginning at the byte offset 1Ch and is full
after only 4 bytes. The corresponding ending offset in
this example is 1Fh. For the best economy of speed
and efficiency, the target address for writing should
point to the beginning of a new page, i.e., the byte off-
set is 0. Thus, the full 32-byte capacity of the scratch-
pad is available, resulting also in the ending offset of
1Fh. However, it is possible to write one or several con-
tiguous bytes somewhere within a page. The ending
offset together with the partial and overflow flag are a
means to support the master checking the data integri-
ty after a write command. The highest valued bit of the
E/S register, called authorization accepted (AA), indi-
cates that a valid copy command for the scratchpad
has been received and executed. Writing data to the
scratchpad clears this flag.
The state of the search condition bits in the Control
register does not affect the mission. If multiple devices
are connected to form a 1-Wire net, the setting of the
search condition enables these devices to participate
in the conditional search if certain events, such as
timer or temperature alarms, have occurred. Details
on the search conditions are found in the ROM
Function Commands section and in the Control regis-
ter description.
The setting of the rollover-enable bit (RO) and sample
rate depends on the duration of the mission and the
monitoring requirements. If the most recent temperature
history is important, the rollover should be enabled
(RO = 1). Otherwise, one should estimate the duration
of the mission in minutes and divide the number by
2048 to calculate the value of the sample rate (number
of minutes between temperature conversions). For
example, if the estimated duration of a mission is 10
days (14,400min), then the 2048-byte capacity of the
data-log memory would be sufficient to store a new
value every 7min. If the DS1921G’s data-log memory is
not large enough to store all temperature readings, one
can use several devices and set the Mission Start Delay
to values that make the second device start recording
as soon as the memory of the first device is full and so
on. The RO bit needs to be set to 0 to disable rollover
that would otherwise overwrite the recorded tempera-
ture log.
After the RO bit and the Mission Start Delay are set, the
Sample Rate register is the last element of data that is
written. The sample rate can be any value from 1 to
255, coded as an unsigned 8-bit binary number. As
soon as the sample rate is written, the DS1921G sets
the MIP flag and clears the MEMCLR flag. After as
many minutes as specified by the Mission Start Delay
are over, the device waits for the next minute boundary,
then wakes up, copies the current time and date to the
Mission Timestamp register, and makes the first tem-
perature conversion of the mission. This increments
both the Mission Samples Counter and Device Samples
Counter. All subsequent temperature measurements
are taken on minute boundaries specified by the value
in the Sample Rate register. One can read the memory
of the DS1921G to watch the mission as it progresses.
Care should be taken to avoid memory access con-
flicts. See the Memory Access Conflicts section for
details.
Writing with Verification
To write data to the DS1921G, the scratchpad must be
used as intermediate storage. First, the master issues
the Write Scratchpad command to specify the desired
target address, followed by the data to be written to the
scratchpad. In the next step, the master sends the
Read Scratchpad command to read the scratchpad
and to verify data integrity. As preamble to the scratch-
pad data, the DS1921G sends the requested target
address TA1 and TA2 and the contents of the E/S regis-
ter. If the PF flag is set, data did not arrive correctly in
the scratchpad. The master does not need to continue
reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag indicates that the
______________________________________________________________________________________ ±9
Thermochron iButton
BIT NUMBER
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
TARGET ADDRESS (TA2)
T15
AA
T14
0
T13
PF
T12
E4
T11
E3
T10
E2
T9
E1
T8
E0
DS921G
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ-ONLY)
Figure 9. Address Registers
write command was not recognized by the device. If
everything went correctly, both flags are cleared and
the ending offset indicates the address of the last byte
written to the scratchpad. Now the master can continue
verifying every data bit. After the master has verified the
data, it has to send the Copy Scratchpad command.
This command must be followed exactly by the data of
the three address registers TA1, TA2, and E/S as the
master has read them verifying the scratchpad. As
soon as the DS1921G has received these bytes, it
copies the data to the requested location beginning at
the target address.
Write Scratchpad [0Fh]
After issuing the Write Scratchpad command, the mas-
ter must first provide the 2-byte target address, fol-
lowed by the data to be written to the scratchpad. The
data is written to the scratchpad starting at the byte off-
set T[4:0]. The ending offset E[4:0] is the byte offset at
which the master stops writing data. Only full data
bytes are accepted. If the last data byte is incomplete,
its content is ignored and the partial byte flag (PF) is
set.
When executing the Write Scratchpad command, the
CRC generator inside the DS1921G (see Figure 16) cal-
culates a CRC of the entire data stream, starting at the
command code and ending at the last data byte sent
by the master. This CRC is generated using the CRC-
16 polynomial by first clearing the CRC generator and
then shifting in the command code (0Fh) of the Write
Scratchpad command, the target addresses TA1 and
TA2 as supplied by the master, and all the data bytes.
The master can end the Write Scratchpad command at
any time. However, if the ending offset is 11111b, the
master can send 16 read time slots and receive an
inverted CRC-16 generated by the DS1921G.
Memory/Control Function
Commands
The Memory/Control Function Flowchart (Figure 10)
describes the protocols necessary for accessing the
memory and the special function registers of the
DS1921G. An example on how to use these and other
functions to set up the DS1921G for a mission is includ-
ed in the Mission Example: Prepare and Start a New
Mission section. The communication between master
and DS1921G takes place either at standard speed
(default, OD = 0) or at overdrive speed (OD = 1). If not
explicitly set into the overdrive mode, the DS1921G
assumes standard speed. Internal memory access dur-
ing a mission has priority over external access through
the 1-Wire interface. This affects the read memory com-
mands described below. See the Memory Access
Conflicts section for details.
Note: The range 200h to 213h of the register page is
protected during a mission. See Figure 6 for the
access type of the individual registers between and
during missions.
ꢄ0 ______________________________________________________________________________________
Thermochron iButton
DS921G
The data to be copied is determined by the three
address registers. The scratchpad data from the begin-
ning offset through the ending offset is copied, starting
at the target address. Anywhere from 1 to 32 bytes can
be copied to memory with this command. The AA flag
remains at logic 1 until it is cleared by the next Write
Scratchpad command. Note that the Copy Scratchpad
command, when applied to the address range 200h to
213h during a mission, ends the mission.
Read Scratchpad [AAh]
This command is used to verify scratchpad data and
target addresses. After issuing the Read Scratchpad
command, the master begins reading. The first 2 bytes
are the target address. The next byte is the ending off-
set/data status byte (E/S) followed by the scratchpad
data beginning at the byte offset T[4:0], as shown in
Figure 9. Regardless of the actual ending offset, the
master can read data until the end of the scratchpad
after which it receives an inverted CRC-16 of the com-
mand code, target addresses TA1 and TA2, the E/S
byte, and the scratchpad data starting at the target
address. After the CRC is read, the bus master reads
logical “1”s from the DS1921G until a reset pulse is
issued.
Read Memory [F0h]
The Read Memory command can be used to read the
entire memory. After issuing the command, the master
must provide the 2-byte target address. After the 2
bytes, the master reads data beginning from the target
address and can continue until the end of memory, at
which point logic “0”s are read. It is important to realize
that the target address registers contain the address
provided. The ending offset/data status byte is unaf-
fected.
Copy Scratchpad [55h]
This command is used to copy data from the scratch-
pad to the writable memory sections. Applying a Copy
Scratchpad command to the Sample Rate register can
start a mission provided that several preconditions are
met. See the Mission Start and Logging Process sec-
tion and the flowchart in Figure 11 for details. After issu-
ing the Copy Scratchpad command, the master must
provide a 3-byte authorization pattern, which can be
obtained by reading the scratchpad for verification.
This pattern must exactly match the data contained in
the three address registers (TA1, TA2, E/S, in that
order). If the pattern matches, the AA flag is set and the
copy begins. A pattern of alternating “1”s and “0”s is
transmitted after the data has been copied until the
master issues a reset pulse. While the copy is in
progress, any attempt to reset the part is ignored. Copy
typically takes 2µs per byte.
The hardware of the DS1921G provides a means to
accomplish error-free writing to the memory section. To
safeguard data in the 1-Wire environment when read-
ing and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets of
the size of one memory page each. Such a packet
would typically store a 16-bit CRC with each page of
data to ensure rapid, error-free data transfers that elim-
inate having to read a page multiple times to verify if
the received data is correct (refer to Application Note
114: 1-Wire File Structure for the recommended file
structure).
______________________________________________________________________________________ ꢄ±
Thermochron iButton
MASTER Tx MEMORY OR
CONTROL FUNCTION COMMAND
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 13)
TO FIGURE 10b
0Fh
AAh
55h
N
N
N
WRITE SCRATCHPAD?
READ SCRATCHPAD?
COPY SCRATCHPAD
Y
Y
Y
DS921G
DS1921G SETS
EMCLR = 0
DS1921G SETS
EMCLR = 0
DS1921G SETS
EMCLR = 0
MASTER Tx
MASTER Rx
MASTER Tx
TA1 [T7:T0], TA2 [T15:T8]
TA1 [T7:T0], TA2 [T15:T8]
TA1 [T7:T0], TA2 [T15:T8]
DS1921G SETS
SCRATCHPAD OFFSET = [T4:T0]
AND CLEARS (PF, AA)
MASTER Rx ENDING OFFSET
WITH DATA STATUS
(E/S)
MASTER Tx
E/S BYTE
N
AUTHORIZATION
CODE MATCH?
MASTER Tx DATA BYTE
TO SCRATCHPAD OFFSET
DS1921G SETS
SCRATCHPAD OFFSET = [T4:T0]
Y
DS1921G
INCREMENTS
SCRATCHPAD
OFFSET
DS1921G SETS [E4:E0] =
SCRATCHPAD OFFSET
DS1921G
INCREMENTS
SCRATCHPAD
OFFSET
MASTER Rx DATA BYTE FROM
SCRATCHPAD OFFSET
AA = 1
DS1921G COPIES SCRATCHPAD
DATA TO MEMORY
Y
Y
MASTER Tx RESET?
N
MASTER Tx RESET?
N
MASTER Rx "1"s
MASTER Rx "1"s
N
COPYING
FINISHED
N
Y
SCRATCHPAD
OFFSET = 11111b?
N
SCRATCHPAD
OFFSET = 11111b?
N
Y
MASTER Tx RESET?
Y
PARTIAL
BYTE WRITTEN?
Y
Y
Y
DS1921G Tx "0"
MASTER Rx CRC-16 OF
COMMAND, ADDRESS, DATA,
E/S BYTE, AND DATA STARTING
AT THE TARGET ADDRESS
N
MASTER Tx RESET?
N
Y
MASTER Tx RESET?
PF = 1
MASTER Rx CRC-16 OF
COMMAND, ADDRESS, DATA
N
Y
MASTER Tx RESET?
DS1921G Tx "1"
N
Y
MASTER Tx RESET?
MASTER Rx "1"s
N
MASTER Tx RESET?
Y
N
MASTER Rx "1"s
FROM FIGURE 10b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 13)
Figure 10a. Memory/Control Function Flowchart
ꢄꢄ ______________________________________________________________________________________
Thermochron iButton
DS921G
A5h
FROM FIGURE 10a
TO FIGURE 10c
F0h
3Ch
N
N
N
N
READ MEMORY
WITH CRC
READ MEMORY?
CLEAR MEMORY
Y
Y
Y
DS1921G SETS
EMCLR = 0
DS1921G SETS
EMCLR = 0
EMCLR = 1?
Y
DECISION MADE
BY DS1921G
MASTER Rx
MASTER Tx
TA1 [T7:T0], TA2 [T15:T8]
TA1 [T7:T0], TA2 [T15:T8]
DS1921G CLEARS MISSION
TIMESTAMP, MISSION
SAMPLES COUNTER, MISSION
START DELAY, SAMPLE RATE
REGISTER
DS1921G SETS
MEMORY ADDRESS = [T15:T0]
DS1921G SETS MEMORY
ADDRESS = [T15:T0]
DECISION MADE
BY MASTER
DS1921G
INCREMENTS
ADDRESS
MASTER Rx DATA BYTE FROM
MEMORY ADDRESS
DS1921G CLEARS ALARM
TIMESTAMPS AND DURATIONS
Y
END OF
MEMORY?
COUNTER
N
DS1921G CLEARS HISTOGRAM
MEMORY
Y
MASTER Tx RESET?
N
MASTER Rx
00 BYTE
MASTER Rx DATA BYTE
FROM MEMORY ADDRESS
DS1921G SETS
MEMCLR = 1
DS1921G
INCREMENTS
ADDRESS
N
END OF
MEMORY?
Y
MASTER Tx RESET?
N
COUNTER
DS1921G SETS
EMCLR = 0
Y
MASTER Rx "0"
N
END OF PAGE?
Y
N
MASTER Tx RESET?
Y
MASTER Rx CRC-16 OF
COMMAND, ADDRESS, DATA
(1ST PASS); CRC-16 OF DATA
(SUBSEQUENT PASSES)
Y
CRC OK?
N
MASTER Tx
RESET
TO FIGURE 10a
FROM FIGURE 10c
Figure 10b. Memory/Control Function Flowchart
______________________________________________________________________________________ ꢄ-
Thermochron iButton
FROM FIGURE 10b
44h CONVERT
N
TEMPERATURE?
Y
DS921G
TEMPERATURE
CONVERSION PROCESS
DS1921G SETS
EMCLR = 0
DS1921G SETS
TCB = 0
Y
MISSION IN
PROGRESS?
N
DS1921G PERFORMS A
TEMPERATURE CONVERSION
DS1921G STARTS TEMPERATURE
CONVERSION PROCESS
DS1921G COPIES RESULT TO
ADDRESS 0211h
DS1921G SETS
TCB = 1
N
MASTER
Tx RESET?
Y
END OF PROCESS
N
MASTER
Tx RESET?
Y
TO FIGURE 10b
Figure 10c. Memory/Control Function Flowchart
ꢄꢅ ______________________________________________________________________________________
Thermochron iButton
DS921G
When the command is completed the MEMCLR bit in
the Status register reads 1 and the EMCLR bit is 0.
Read Memory with CRC [A5h]
The Read Memory with CRC command is used to read
memory data that cannot be packetized, such as the
register page and the data recorded by the device dur-
ing a mission. The command works the same way as
the simple Read Memory command, except for the 16-
bit CRC that the DS1921G generates and transmits fol-
lowing the last data byte of a memory page.
Convert Temperature [44h]
If a mission is not in progress (MIP = 0), the Convert
Temperature command can be issued to measure the
current temperature of the device. The result of the tem-
perature conversion can be found at memory address
211h in the register page. This command takes maxi-
mum 90ms to complete. During this time the device
remains fully accessible for memory/control and ROM
function commands.
After having sent the command code of the Read
Memory with CRC command, the bus master sends a
2-byte address (TA1 = T[7:0], TA2 = T[15:8]) that indi-
cates a starting byte location. With the subsequent
read-data time slots, the master receives data from the
DS1921G starting at the initial address and continues
until the end of a 32-byte page is reached. At that point
the bus master sends 16 additional read-data time slots
and receives an inverted 16-bit CRC. With subsequent
read-data time slots the master receives data starting at
the beginning of the next page followed again by the
inverted CRC for that page. This sequence continues
until the bus master resets the device.
Mission Start and Logging Process
The DS1921G does not use a special command to start
a mission. Instead, a mission is started by writing a
nonzero value to the Sample Rate register using the
Copy Scratchpad command. As shown in Figure 11, a
new mission can only be started if the previous mission
has been stopped (MIP = 0), the memory is cleared
(MEMCLR = 1), and the mission is enabled (EM = 0). If
the new sample rate is different from zero, the value is
copied to the Sample Rate register. At the same time
the MIP bit is set and the MEMCLR bit is cleared to indi-
cate that the device is on a mission. Next, the Mission
Start Delay Counter starts decrementing every minute
until it is down to 0. Now the DS1921G waits until the
next minute boundary and starts the logging process,
which as its first action copies the applicable RTC reg-
isters to the Mission Timestamp register.
With the initial pass through the Read Memory with
CRC command flow, the 16-bit CRC value is the result
of shifting the command byte into the cleared CRC gen-
erator followed by the two address bytes and the con-
tents of the data memory. Subsequent passes through
the Read Memory with CRC command flow generate a
16-bit CRC that is the result of clearing the CRC gener-
ator and then shifting in the contents of the data memo-
ry page. After the 16-bit CRC of the last page is read,
the bus master receives logical “0”s from the DS1921G
and inverted CRC-16s at page boundaries until a reset
pulse is issued. The Read Memory with CRC command
sequence can be ended at any point by issuing a reset
pulse.
Stop Mission
The DS1921G does not have a special command to
stop a mission. A mission can be stopped at any time
by writing to any address in the range of 0200h to
0213h or by writing the MIP bit of the Status register at
address 0214h to 0. Either approach involves the use of
the Copy Scratchpad command. There is no need for
the Mission Start Delay to expire before a mission can
be stopped (see Figure 11).
Clear Memory [3Ch]
The Clear Memory command is used to clear the
Sample Rate, Mission Start Delay, Mission Timestamp,
and Mission Samples Counter in the register page and
the temperature alarm memory and the temperature
histogram memory. These memory areas must be
cleared for the device to be set up for another mission.
The Clear Memory command does not clear the data-
log memory or the temperature and timer alarm flags in
the Status register. The RTC oscillator must be on and
have counted at least 1s before issuing the command.
For the Clear Memory command to function, the
EMCLR bit in the Control register must be set to 1, and
the Clear Memory command must be issued with the
very next access to the device’s memory functions.
Issuing any other memory function command resets the
EMCLR bit. The Clear Memory process takes 500µs.
Memory Access Conflicts
While a mission is in progress, a temperature sample is
periodically taken and stored in the data-log, his-
togram, and potential alarm memory. This “internal
activity” has priority over a Read Memory command’s
or Read Memory with CRC command’s access to these
pages. If a conflict occurs, the data read may be
invalid, even if the CRC value matches the data. To
ensure that the data read is valid, it is recommended to
first read the SIP bit of the Status register. If the SIP bit
is set, delay reading the data-log, histogram, and alarm
memory until SIP is 0. The interference is more likely to
be seen with a high sample rate (one sample every
______________________________________________________________________________________ ꢄ5
Thermochron iButton
MISSION START PROCESS
LOGGING PROCESS
DS1921G COPIES RTC TO
MISSION TIMESTAMP
Y
MIP = 1?
N
DS1921G SETS MIP = 0
DS1921G SETS DATA-LOG
ADDRESS = 1000h
DS921G
N
EM = 0?
DS1921G MEASURES
TEMPERATURE
Y
N
MEMCLR = 1?
DS1921G UPDATES HISTOGRAM,
DEVICE SAMPLES COUNTER,
MISSION SAMPLES COUNTER
AND ALARM, IF APPLICABLE
Y
Y
NEW SAMPLE
RATE = 0?
N
Y
RO = 1?
N
DS1921G COPIES NEW SAMPLE
RATE FROM SCRATCHPAD TO
SAMPLE RATE REGISTER
DATA-LOG
ADDRESS = 1800h?
Y
N
DS1921G SETS MIP = 1;
MEMCLR = 0
DS1921G STORES TEMPERATURE
AT DATA-LOG ADDRESS
DS1921G STORES TEMPERATURE
AT DATA-LOG ADDRESS
DS1921G INCREMENTS
DATA-LOG ADDRESS
DS1921G INCREMENTS LOWER
11 BITS OF DATA-LOG ADDRESS
Y
START DELAY
COUNTER = 0?
N
DS1921G WAITS
UNTIL NEXT MINUTE
BOUNDARY
N
DS1921G WAITS
Y
MIP = 1?
Y
ONE SAMPLE
PERIOD
MIP = 1?
N
DS1921G
LOGGING
PROCESS
DS1921G WAITS UNTIL NEXT
MINUTE BOUNDARY
END OF PROCESS
DS1921G DECREMENTS
START DELAY COUNTER
END OF PROCESS
NOTE: THE MISSION START PROCESS IS INVOKED WHEN THE COPY SCRATCHPAD COMMAND IS USED TO SET A NEW SAMPLE RATE BY WRITING TO THE SAMPLE RATE
REGISTER AT ADDRESS 020Dh. ONE MINUTE AFTER THE START DELAY COUNTDOWN IS OVER, THE LOGGING PROCESS BEGINS AND THE MISSION START PROCESS ENDS.
Figure 11. Mission Start and Logging Process
ꢄ6 ______________________________________________________________________________________
Thermochron iButton
DS921G
minute). Since all mission samples occur on the sec-
onds rollover (59 to 00), memory conflicts can be avoid-
ed by first reading the RTC seconds counter. For
example, if it takes 2s to read the data log, then avoid
starting the memory read if the seconds counter is 58,
59, or 00. Alternatively, one can read the affected mem-
ory section twice and accept the data only if both read-
ings match. In any case, when writing driver software, it
is important to know about the possibility of interference
and to take measures to work around it.
a maximum data rate of 16.3kbps. The speed can be
boosted to 142kbps by activating the overdrive mode.
The DS1921G is not guaranteed to be fully compliant to
the iButton standard. Its maximum data rate in standard
speed is 15.4kbps and 125kbps in overdrive. The value
of the pullup resistor primarily depends on the network
size and load conditions. The DS1921G requires a
pullup resistor of maximum 2.2kΩ at any speed.
The idle state for the 1-Wire bus is high. If for any rea-
son a transaction needs to be suspended, the bus
must be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 16µs (overdrive speed) or more than 120µs
(standard speed), one or more devices on the bus may
be reset. Note that the DS1921G does not quite meet
the full 16µs maximum low time of the normal 1-Wire
bus overdrive timing. With the DS1921G the bus must
be left low for no longer than 15µs at overdrive speed to
ensure that no DS1921G on the 1-Wire bus performs a
reset. The DS1921G communicates properly when
used in conjunction with a DS2480B or DS2490 1-Wire
driver and adapters that are based on these driver
chips.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS1921G
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, trans-
action sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transac-
tions in terms of the bus state during specific time slots
that are initiated on the falling edge of sync pulses from
the bus master.
Hardware Configuration
Transaction Sequence
The protocol for accessing the DS1921G through the
1-Wire port is as follows:
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS1921G is
open drain with an internal circuit equivalent to that
shown in Figure 12.
• Initialization
• ROM Function Command
• Memory/Control Function Command
• Transaction/Data
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. At standard speed the 1-Wire bus has
V
PUP
BUS MASTER
DS1921G 1-Wire PORT
R
PUP
DATA
Rx
Tx
Rx
I
L
Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
100Ω MOSFET
Figure 12. Hardware Configuration
______________________________________________________________________________________ ꢄ+
Thermochron iButton
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participat-
ing in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states
of the bit. By choosing which state to write, the bus
master branches in the ROM code tree. After one com-
plete pass, the bus master knows the registration num-
ber of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to
Application Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
Initialization
All transactions on the 1-Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master, followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS1921G is on the bus and is ready to operate. For
more details, see the 1-Wire Signaling section.
DS921G
ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands. All
ROM function commands are 8 bits long. A list of these
commands follows (see the flowchart in Figure 13).
Conditional Search ROM [ECh]
The Conditional Search ROM command operates simi-
larly to the Search ROM command except that only
devices fulfilling the specified condition participate in
the search. The condition is specified by the bit func-
tions TAS, THS, and TLS in the Control register,
address 20Eh. The Conditional Search ROM provides
an efficient means for the bus master to determine
devices on a multidrop system that have to signal an
important event, such as a temperature leaving the tol-
erance band. After each pass of the conditional search
that successfully determined the 64-bit ROM code for a
specific device on the multidrop bus, that particular
device can be individually accessed as if a Match ROM
command had been issued, since all other devices
have dropped out of the search process and are wait-
ing for a reset pulse.
Read ROM [33h]
This command allows the bus master to read the
DS1921G’s 8-bit family code, unique 48-bit serial num-
ber and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The resultant fami-
ly code and 48-bit serial number result in a mismatch of
the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS1921G on a multidrop bus. Only the DS1921G that
exactly matches the 64-bit ROM sequence responds to
the memory function command. All other slaves wait for
a reset pulse. This command can be used with a single
device or multiple devices on the bus.
For the conditional search, one can select any combi-
nation of the three search conditions by writing the
associated bit to a logical 1. These bits correspond
directly to the flags in the Status register of the device.
If the flag in the Status register reads 1 and the corre-
sponding bit in the Control register is a logical 1 too,
the device responds to the Conditional Search ROM
command. If more than one bit search condition is
selected, the first event that occurs makes the device
respond to the Conditional Search ROM command.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the regis-
tration number, starting with the least significant bit, the
bus master issues a triplet of time slots. On the first slot,
each slave device participating in the search outputs
the true value of its registration number bit. On the sec-
ond slot, each slave device participating in the search
outputs the complemented value of its registration num-
ber bit. On the third slot, the master writes the true
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. If
more than one slave is present on the bus and, for
example, a read command is issued following the Skip
ROM command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
ꢄ8 ______________________________________________________________________________________
Thermochron iButton
DS921G
MASTER Tx
RESET PULSE
FROM FIGURE 13b
FROM MEMORY/CONTROL
FUNCTIONS FLOWCHART (FIGURE 10)
SHORT
RESET PULSE?
N
OD = 0
Y
*
MASTER Tx ROM
FUNCTION COMMAND
DS1921G Tx
PRESENCE PULSE
**
33h
READ ROM
COMMAND?
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
ECh
TO FIGURE 13b
N
N
N
N
CONDITIONAL SEARCH
COMMAND?
Y
Y
Y
Y
N
N
N
CONDITION
MET?
Y
DS1921G Tx BIT 0
DS1921G Tx BIT 0
MASTER Tx BIT 0
DS1921G Tx BIT 0
DS1921G Tx BIT 0
MASTER Tx BIT 0
*
*
*
*
*
*
DS1921G Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
BIT 0 MATCH?
*
*
N
N
BIT 0 MATCH?
Y
BIT 0 MATCH?
Y
Y
DS1921G Tx BIT 1
DS1921G Tx BIT 1
MASTER Tx BIT 1
DS1921G Tx BIT 1
DS1921G Tx BIT 1
MASTER Tx BIT 1
*
*
*
*
*
*
DS1921G Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
*
N
N
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
DS1921G Tx BIT 63
DS1921G Tx BIT 63
MASTER Tx BIT 63
DS1921G Tx BIT 63
DS1921G Tx BIT 63
MASTER Tx BIT 63
*
*
*
*
*
*
DS1921G Tx
CRC BYTE
MASTER Tx BIT 63
*
N
N
N
BIT 63 MATCH?
Y
BIT 63 MATCH?
Y
BIT 63 MATCH?
Y
TO FIGURE 13b
FROM FIGURE 13b
*TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD = 1.
** PRESENCE PULSE IS SHORT IF OD = 1.
TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 10)
Figure 13a. ROM Functions Flowchart
______________________________________________________________________________________ ꢄ9
Thermochron iButton
TO FIGURE 13a
DS921G
CCh
SKIP ROM
COMMAND?
3Ch
OVERDRIVE-
SKIP ROM?
69h
OVERDRIVE-
MATCH ROM?
FROM FIGURE 13a
N
N
N
Y
Y
Y
OD = 1
OD = 1
MASTER
Tx RESET
PULSE?
Y
MASTER Tx BIT 0
***
N
N
N
N
BIT 0 MATCH?
Y
MASTER Tx BIT 1
***
BIT 1 MATCH?
Y
MASTER Tx BIT 63
***
BIT 63 MATCH?
Y
FROM FIGURE 13a
TO FIGURE 13a
***ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED.
Figure 13b. ROM Functions Flowchart
-0 ______________________________________________________________________________________
Thermochron iButton
DS921G
standard speed at the next reset pulse of minimum
480µs duration. The Overdrive-Match ROM command
can be used with a single or multiple devices on the
bus.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory/control
functions without providing the 64-bit ROM code. Unlike
the normal Skip ROM command, the Overdrive-Skip
ROM command sets the DS1921G in the overdrive
mode (OD = 1). All communication following this com-
mand must occur at overdrive speed until a reset pulse
of minimum 480µs duration resets all devices on the
bus to standard speed (OD = 0).
1-Wire Signaling
The DS1921G requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and pres-
ence pulse, write-zero, write-one, and read-data. Except
for the presence pulse, the bus master initiates all these
signals. The DS1921G can communicate at two different
speeds: standard speed and overdrive speed. If not
explicitly set into the overdrive mode, the DS1921G
communicates at standard speed. While in overdrive
mode, the fast timing applies to all waveforms.
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be
issued followed by a Match ROM or Search ROM com-
mand sequence. This speeds up the time for the
search process. If more than one slave supporting
overdrive is present on the bus and the Overdrive-Skip
ROM command is followed by a read command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
below the threshold V . To get
TL
PUP
from active to idle, the voltage needs to rise from
past the threshold V . The time it takes for the
V
ILMAX
TH
voltage to make this rise is seen in Figure 14 as “ε” and
its duration depends on the pullup resistor (R ) used
PUP
and the capacitance of the 1-Wire network attached.
The voltage V is relevant for the DS1921G when
determining a logical level, but not for triggering any
events.
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-
bit ROM sequence transmitted at overdrive speed
allows the bus master to address a specific DS1921G
on a multidrop bus and to simultaneously set it in over-
drive mode. Only the DS1921G that exactly matches
the 64-bit ROM sequence responds to the subsequent
memory/control function command. Slaves already in
overdrive mode from a previous Overdrive-Skip or suc-
cessful Overdrive-Match ROM command remain in
overdrive mode. All overdrive-capable slaves return to
ILMAX
The initialization sequence required to begin any com-
munication with the DS1921G is shown in Figure 14. A
reset pulse followed by a presence pulse indicates the
DS1921G is ready to receive data, given the correct
ROM and memory function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for t
+ t to compensate for the edge.
F
RSTL
MASTER Tx "RESET PULSE"
MASTER Rx "PRESENCE PULSE"
ε
t
MSP
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
PDH
t
t
t
REC
RSTL
PDL
t
F
t
RSTH
RESISTOR
MASTER
DS1921G
Figure 14. Intitialization Procedure: Reset and Presence Pulses
______________________________________________________________________________________ -±
Thermochron iButton
A t
duration of 480µs or longer exits the overdrive
The sum of t + δ (rise time) on one side and the inter-
RSTL
RL
mode, returning the device to standard speed. If the
nal timing generator of the DS1921G on the other side
DS1921G is in overdrive mode and t
than 80µs, the device remains in overdrive mode.
is no longer
define the master sampling window (t
MSRMAX
the data line. For most reliable communication, t
to
RSTL
MSRMIN
t
) in which the master must perform a read from
RL
After the bus master has released the line, it goes into
receive mode (Rx). Now the 1-Wire bus is pulled to
should be as short as permissible and the master
should read close to but no later than t . After
MSRMAX
V
through the pullup resistor or, in case of a
PUP
reading from the data line, the master must wait until
DS2480B driver, through active circuitry. When the
threshold V is crossed, the DS1921G waits for t
t
is expired. This guarantees sufficient recovery
REC
SLOT
time t
DS921G
TH
PDH
for the DS1921G to get ready for the next
and then transmits a presence pulse by pulling the line
low for t . To detect a presence pulse, the master
must test the logical state of the 1-Wire line at t
time slot.
PDL
.
MSP
CRC Generation
The t
window must be at least the sum of t
,
RSTH
PDHMAX
There are two different types of CRCs with the
DS1921G. One CRC is an 8-bit type and is stored in the
most significant byte of the 64-bit ROM. The bus master
can compute a CRC value from the first 56 bits of the
64-bit ROM and compare it to the value stored within
the DS1921G to determine if the ROM data has been
received error-free. The equivalent polynomial function
t
, and t
. Immediately after t
is
RSTH
PDLMAX
RECMIN
expired, the DS1921G is ready for data communication.
In a mixed population network, t should be extend-
RSTH
ed to minimum 480µs at standard speed and 48µs at
overdrive speed to accommodate other 1-Wire devices.
Read/Write Time Slots
Data communication with the DS1921G takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. The definitions of the
write and read time slots are illustrated in Figure 15.
8
5
4
of this CRC is X + X + X + 1. This 8-bit CRC is
received in the true (noninverted) form. It is computed
at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to
16
the standardized CRC-16 polynomial function X
+
15
2
X
+ X + 1. This CRC is used for error detection when
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V , the DS1921G starts its internal
TL
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
reading data memory using the Read Memory with
CRC command and for fast verification of a data trans-
fer when writing to or reading from the scratchpad. In
contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC-generator
inside the DS1921G chip (Figure 16) calculates a new
16-bit CRC as shown in the command flowchart of
Figure 10. The bus master compares the CRC value
read from the device to the one it calculates from the
data and decides whether to continue with an operation
or to reread the portion of the data with the CRC error.
With the initial pass through the Read Memory with
CRC flowchart, the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC gener-
ator, followed by the 2 address bytes and the data
bytes. Subsequent passes through the Read Memory
with CRC flowchart generate a 16-bit CRC that is the
result of clearing the CRC generator and then shifting in
the data bytes.
Masterꢁtoꢁ(lave
For a writeꢁone time slot, the voltage on the data line
must have crossed the V threshold after the write-one
TH
low time t
is expired. For a writeꢁzero time slot,
W1LMAX
the voltage on the data line must stay below the V
TH
threshold until the write-zero low time t
is expired.
W0LMIN
The voltage on the data line should not exceed V
ILMAX
during the entire t
or t
window. After the V
W1L TH
W0L
threshold has been crossed, the DS1921G needs a
recovery time t
before it is ready for the next time slot.
REC
(laveꢁtoꢁMaster
A readꢁdata time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
RL
With the Write Scratchpad command, the CRC is gener-
ated by first clearing the CRC generator and then shift-
ing in the command code, the target addresses TA1
and TA2, and all the data bytes. The DS1921G transmits
this CRC only if the data bytes written to the scratchpad
include scratchpad ending offset 11111b. The data can
start at any location within the scratchpad.
until the read low time t
is expired. During the t
RL
window, when responding with a 0, the DS1921G starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS1921G does not hold the data line low at all, and the
voltage starts rising as soon as t is over.
RL
-ꢄ ______________________________________________________________________________________
Thermochron iButton
DS921G
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
SLOT
RESISTOR
MASTER
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
REC
t
SLOT
RESISTOR
MASTER
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER
SAMPLING
WINDOW
V
TL
V
ILMAX
0V
δ
t
t
REC
F
t
SLOT
RESISTOR
MASTER
DS1921G
Figure 15. Read/Write Timing Diagram
______________________________________________________________________________________ --
Thermochron iButton
With the Read Scratchpad command, the CRC is gen-
erated by first clearing the CRC generator and then
shifting in the command code, the target addresses
TA1 and TA2, the E/S byte, and the scratchpad data
starting at the target address. The DS1921G transmits
this CRC only if the reading continues through the end
of the scratchpad, regardless of the actual ending off-
set. For more information on generating CRC values
refer to Application Note 27: Understanding and Using
Cyclic Redundancy Checks with Maxim iButton
Products.
DS921G
16
15
2
POLYNOMIAL = X + X + X + 1
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
0
1
2
3
4
5
6
7
X
X
X
X
X
X
X
X
9TH
STAGE
10TH
STAGE
11TH
STAGE
12TH
STAGE
13TH
STAGE
14TH
STAGE
15TH
STAGE
16TH
STAGE
8
9
10
11
12
13
14
15
16
CRC OUTPUT
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 16. CRC-16 Hardware Description and Polynomial
Command-Specific 1-Wire Communication Protocol—Legend
SYMBOL
DESCRIPTION
1-Wire reset pulse generated by master
RST
PD
1-Wire presence pulse generated by slave
Select
Command and data to satisfy the ROM function protocol (Skip ROM, Search ROM, etc.)
Command: “Write Scratchpad”
WS
RS
Command: “Read Scratchpad”
CPS
RM
Command: “Copy Scratchpad”
Command: “Read Memory”
RMC
Command: “Read Memory with CRC”
CM
Command: “Clear Memory”
CT
Command: “Convert Temperature”
TA
Target Address TA1, TA2
TA-E/S
Target Address TA1, TA2 with E/S byte
<data to EOS>
<data to EOP>
<data to EOM>
Transfer of as many data bytes as are needed to reach the scratchpad offset 1Fh
Transfer of as many data bytes as are needed to reach the end of a memory page
Transfer of as many data bytes as are needed to reach the end of the data-log memory
-ꢅ ______________________________________________________________________________________
Thermochron iButton
DS921G
Command-Specific 1-Wire Communication Protocol—Legend
(continued)
SYMBOL
<00 to EOP>
<32 bytes>
<data>
DESCRIPTION
Transfer of as many 00h bytes as are needed to reach a memory page boundary
Transfer of 32 bytes
Transfer of an undetermined amount of data
Transfer of an inverted CRC-16
CRC-16
FF loop
Indefinite loop where the master reads FFh bytes
Indefinite loop where the master reads AAh bytes
Indefinite loop where the master reads 00h bytes
AA loop
00 loop
Command-Specific 1-Wire Communication Protocol—Color Codes
Master-to-Slave Slave-to-Master
1-Wire Communication Examples
Write (cratchpad, Reaching the End oꢀ the (cratchpad
RST PD Select WS TA <data to EOS> CRC-16 FF loop
Write (cratchpad, Not Reaching the End oꢀ the (cratchpad
RST PD Select WS TA <data> RST PD
Read (cratchpad
RST PD Select RS TA-E/S <data to EOS> CRC-16 FF loop
Copy (cratchpad ꢃ(uccess)
RST PD Select CPS TA-E/S AA loop
Copy (cratchpad ꢃInvalid TAꢁE/()
RST PD Select CPS TA-E/S FF loop
Read Memory ꢃ(uccess)
RST PD Select RM TA <data to EOM> 00 loop
Read Memory ꢃInvalid Address)
RST PD Select RM TA 00 loop
Reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond data-log memory)
results in 00h bytes.
______________________________________________________________________________________ -5
Thermochron iButton
1-Wire Communication Examples (continued)
Read Memory with CRC ꢃ(uccess)
RST PD Select RMC TA <data to EOP> CRC-16
<32 bytes>
Loop
CRC-16
DS921G
The “32 bytes” are either valid page data or 00h bytes when reading reserved pages 20 through 63 or 68
through 127 or pages 192 and higher (beyond data-log memory).
Read Memory with CRC ꢃInvalid Address)
RST PD Select RMC TA
<00 to EOP> CRC-16
<32 bytes>
Loop
CRC-16
The “32 bytes” are all 00h.
Clear Memory
RST PD Select CM FF loop
To verify success, read the Status register at address 0214h. If MEMCLR is 1, the command was executed
successfully.
Convert Temperature
RST PD Select CT FF loop
To read the result and to verify success, read the addresses 0211h (result) and the Device Samples Counter
at address 021Dh to 021Fh. If the count has incremented, the command was executed successfully.
Step 1: Set the RTC (if it needs to be adjusted).
Mission Example: Prepare and
Step 2: Clear the data of the previous mission.
Start a New Mission
Step 3: Set the search condition and Mission Start
Assumption: The previous mission has ended. To end
Delay and clear the alarm flags.
an ongoing mission write the MIP bit in the Status regis-
ter to 0.
Step 4: Set the temperature alarms and write the
Sample Rate to start the mission.
The preparation of a DS1921G for a mission including
the start of the mission requires up to four steps:
-6 ______________________________________________________________________________________
Thermochron iButton
DS921G
(tep ±: (et the RTC
Let the actual time be 15:30:00 hours on Monday, the 1st of April in 2002. This results in the following data to be writ-
ten to the RTC registers:
ADDRESS
DATA
200h
00h
201h
30h
202h
15h
203h
01h
204h
81h
205h
04h
206h
02h
With only a single DS1921G connected to the bus master, the communication of step 1 is as follows:
MASTER MODE
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
COMMENTS
Reset pulse (480μs to 960μs)
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Presence pulse
Issue Skip ROM command
Issue Write Scratchpad command
TA1, beginning offset = 00h
TA2, address = 0200h
0Fh
00h
02h
<7 data bytes>
(Reset)
(Presence)
CCh
Write 7 bytes of data to scratchpad
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Read Scratchpad command
Read TA1, beginning offset = 00h
Read TA2, address = 0200h
Read E/S, ending offset = 6h, flags = 0h
Read scratchpad data and verify
Reset pulse
AAh
00h
02h
06h
<7 data bytes>
(Reset)
(Presence)
CCh
Presence pulse
Issue Skip ROM command
Issue Copy Scratchpad command
TA1
55h
00h
(AUTHORIZATION CODE)
02h
TA2
06h
E/S
(Reset)
(Presence)
Reset pulse
Presence pulse
______________________________________________________________________________________ -+
Thermochron iButton
(tep ꢄ: Clear the data oꢀ the previous mission
Set the EMCLR bit to 1, enable the RTC, and then execute the Clear Memory command. The RTC oscillator must be
stable before the Clear Memory command is issued. Wait 500µs after issuing the Clear Memory command before
proceeding to step 3. This results in the following data to be written to the Status register:
ADDRESS
DATA
20Eh
40h
DS921G
With only a single DS1921G connected to the bus master, the communication of step 2 is as follows:
MASTER MODE
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
COMMENTS
Reset pulse (480μs to 960μs)
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Tx
Tx
Rx
Presence pulse
Issue Skip ROM command
Issue Write Scratchpad command
TA1, beginning offset = 0Eh
TA2, address = 020Eh
0Fh
0Eh
02h
40h
Write status byte to scratchpad
Reset pulse
(Reset)
(Presence)
CCh
Presence pulse
Issue Skip ROM command
Issue Read Scratchpad command
Read TA1, beginning offset = 0Eh
Read TA2, address = 020Eh
Read E/S, ending offset = 0Eh, flags = 0h
Read scratchpad data and verify
Reset pulse
AAh
0Eh
02h
0Eh
40h
(Reset)
(Presence)
CCh
Presence pulse
Issue Skip ROM command
Issue Copy Scratchpad command
TA1
55h
0Eh
(AUTHORIZATION CODE)
02h
TA2
0Eh
E/S
(Reset)
(Presence)
CCh
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Clear Memory command
Reset pulse
3Ch
(Reset)
(Presence)
Presence pulse
-8 ______________________________________________________________________________________
Thermochron iButton
DS921G
(tep -: (et the search condition and Mission (tart Delay and clear the alarm ꢀlags
In this example, the rollover is disabled and the search condition is set for a high temperature only. The mission is
to start with a delay of 90min (005Ah) and the alarm flags TLF, THF, and TAF are cleared. This results in the follow-
ing data to be written to the special function registers:
ADDRESS
DATA
20Eh
02h
20Fh
00h*
210h
00h*
211h
00h*
212h
5Ah
213h
00h
214h
00h
*Writing through address locations 20Fh to 211h is faster than accessing the Mission Start Delay register in a separate cycle. The
write attempt has no effect on the contents of these registers.
With only a single DS1921G connected to the bus master, the communication of step 3 is as follows:
MASTER MODE
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
COMMENTS
Reset Pulse (480μs to 960μs)
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Presence pulse
Issue Skip ROM command
Issue Write Scratchpad command
TA1, beginning offset = 0Eh
TA2, address = 020Eh
0Fh
0Eh
02h
<7 data bytes>
(Reset)
(Presence)
CCh
Write 7 bytes of data to scratchpad
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Read Scratchpad command
Read TA1, beginning offset = 0Eh
Read TA2, address = 020Eh
Read E/S, ending offset = 14h, flags = 0h
Read scratchpad data and verify
Reset pulse
AAh
0Eh
02h
14h
<7 data bytes>
(Reset)
(Presence)
CCh
Presence pulse
Issue Skip ROM command
Issue Copy Scratchpad command
TA1
55h
0Eh
(AUTHORIZATION CODE)
02h
TA2
13h
E/S
(Reset)
(Presence)
Reset pulse
Presence pulse
______________________________________________________________________________________ -9
Thermochron iButton
(tep ꢅ: (et the temperature alarms and write the (ample Rate to start the mission
In this example, the temperature alarms are set to -5°C for the low temperature threshold and 0°C for the high tem-
perature threshold. The sample rate is once every 10min, allowing the mission to last up to 14 days. This results in
the following data to be written to the special function registers:
ADDRESS
DATA
20Bh
46h
20Ch
50h
20Dh
0Ah
DS921G
With only a single DS1921G connected to the bus master, the communication of step 4 is as follows:
MASTER MODE
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
COMMENTS
Reset pulse (480μs to 960μs)
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Tx
Rx
Presence pulse
Issue Skip ROM command
Issue Write Scratchpad command
TA1, beginning offset = 0Bh
TA2, address = 020Bh
0Fh
0Bh
02h
<3 data bytes>
(Reset)
(Presence)
CCh
Write 3 bytes of data to scratchpad
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Read Scratchpad command
Read TA1, beginning offset = 0Bh
Read TA2, address = 020Bh
Read E/S, ending offset = 0Dh, flags = 0h
Read scratchpad data and verify
Reset pulse
AAh
0Bh
02h
0Dh
<3 data bytes>
(Reset)
(Presence)
CCh
Presence pulse
Issue Skip ROM command
Issue Copy Scratchpad command
TA1
55h
0Bh
(AUTHORIZATION CODE)
02h
TA2
0Dh
E/S
(Reset)
(Presence)
Reset pulse
Presence pulse
If step 4 is successful, the MIP bit in the Status register is 1, the MEMCLR bit is 0, and the Mission Start Delay
counts down.
ꢅ0 ______________________________________________________________________________________
Thermochron iButton
DS921G
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maximꢁic.com/packages.
5.89mm
0.51mm
BRANDING
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
F5 iButton
IB-5CP
ꢄ±ꢁ0ꢄ66
16.25mm
89
000000FB®C522B1
®
1-Wire
®
Thermochrom
17.35mm
IO
GND
______________________________________________________________________________________ ꢅ±
Thermochron iButton
Revision History
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
Added bullet “Water resistant or waterproof if placed inside DS9107 iButton capsule (Exceeds
Water Resistant 3 ATM requirements)”.
Deleted “application pending” from UL bullet and safety statement.
1, 2
DS921G
120407
Added text to Detailed Description section: Note that the initial sealing level of DS1921G
achieves IP56. Aging and use conditions can degrade the integrity of the seal over time, so for
applications with significant exposure to liquids, sprays, or other similar environments, it is
recommended to place the Thermochron in the DS9107 iButton capsule. The DS9107 provides a
watertight enclosure that has been rated to IP68 (See www.maxim-ic.com/AN4126).
4/09
4/10
Created newer template-style data sheet.
All
Overdrive specifications for t
values for the full range.
, t
, and t
split into range V
> 4.5V and full range. New
PUP
RSTL PDL
W0L
2–4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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