DS2070W-100# [MAXIM]
Non-Volatile SRAM, 2MX8, 100ns, CMOS, PBGA256, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, BGA-256;
| 型号： | DS2070W-100# |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Non-Volatile SRAM, 2MX8, 100ns, CMOS, PBGA256, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, BGA-256 静态存储器 |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 8/06
3.3V Single-Piece 16Mb
Nonvolatile SRAM
General Description
Features
ꢀ Single-Piece, Reflowable, (27mm)2 PBGA Package
The DS2070W is a 16Mb reflowable nonvolatile (NV)
SRAM, which consists of a static RAM (SRAM), an NV
controller, and an internal rechargeable manganese
lithium (ML) battery. These components are encased in
a surface-mount module with a 256-ball BGA footprint.
Footprint
ꢀ Internal ML Battery and Charger
ꢀ Unconditionally Write-Protects SRAM when V
CC
is Out-of-Tolerance
Whenever V
is applied to the module, it recharges the
CC
ꢀ Automatically Switches to Battery Supply when
Power Failures Occur
ML battery, powers the SRAM from the external power
source, and allows the contents of the SRAM to be mod-
V
CC
ified. When V
is powered down or out-of-tolerance,
CC
ꢀ Internal Power-Supply Monitor Detects Power Fail
Below Nominal V (3.3V)
the controller write-protects the SRAM’s contents and
powers the SRAM from the battery. The DS2070W also
contains a power-supply monitor output, RST, which can
be used as a CPU supervisor for a microprocessor.
CC
ꢀ Reset Output can be Used as a CPU Supervisor
for a Microprocessor
ꢀ Industrial Temperature Range (-40 C to +85 C)
ꢀ UL Recognized
Applications
RAID Systems and Servers
Industrial Controllers
Data-Acquisition Systems
Gaming
POS Terminals
Routers/Switches
Fire Alarms
PLC
Pin Configuration appears at end of data sheet.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
SPEED (ns)
SUPPLY TOLERANCE
2
DS2070W-100#
256 Ball (27mm) BGA Module
100
3.3V 0.3V
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements.
Typical Operating Circuit
(CE)
(WR)
(RD)
CE
WE
OE
DS2070W
2048k x 8
NV SRAM
MICROPROCESSOR
OR DSP
8 BITS
DQ0–DQ7
DATA
21 BITS
ADDRESS
(INT)
A0–A20
RST
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.3V Single-Piece 16Mb
Nonvolatile SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.3V to +4.6V
Storage Temperature Range...............................-40°C to +85°C
Operating Temperature Range ...........................-40°C to +85°C
Soldering Temperature .....................See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40 C to +85 C.)
A
PARAMETER
Supply Voltage
Input Logic 1
SYMBOL
CONDITIONS
MIN
3.0
2.2
0
TYP
MAX
UNITS
V
3.3
3.6
V
V
V
CC
V
V
CC
IH
Input Logic 0
V
0.4
IL
DC ELECTRICAL CHARACTERISTICS
(V
= 3.3V 0.3Vꢀ T = -40 C to +85 C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
-1.0
-1.0
-1.0
2.0
TYP
MAX
+1.0
+1.0
UNITS
µA
Input Leakage Current
I/O Leakage Current
Output-Current High
Output-Current Low
Output-Current Low RST
I
IL
I
CE = V
At 2.4V
At 0.4V
µA
IO
CC
I
mA
OH
I
mA
OL
I
RST
At 0.4V (Note 1)
10.0
mA
OL
I
I
CE = 2.2V
0.5
0.2
7
5
CCS1
CCS2
Standby Current
mA
CE = V - 0.2V
CC
Operating Current
I
t
= 200nsꢀ outputs open
50
3.0
mA
V
CCO1
RC
Write-Protection Voltage
V
2.8
2.9
TP
CAPACITANCE
(T = +25 C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
7
MAX
UNITS
pF
Input Capacitance
C
Not tested
Not tested
IN
Input/Output Capacitance
C
7
pF
OUT
AC ELECTRICAL CHARACTERISTICS
(V
= 3.3V 0.3Vꢀ T = -40 C to +85 C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
100
MAX
UNITS
ns
t
Read Cycle Time
Access Time
RC
t
100
50
ns
ACC
t
OE to Output Valid
CE to Output Valid
ns
OE
t
100
ns
CO
2
_____________________________________________________________________
3.3V Single-Piece 16Mb
Nonvolatile SRAM
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V 0.3Vꢀ T = -40 C to +85 C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
t
OE or CE to Output Active
(Note 2)
(Note 2)
5
ns
COE
Output High Impedance from
Deselection
t
35
ns
OD
OH
t
t
Output Hold from Address Change
Write Cycle Time
5
100
75
0
ns
ns
ns
ns
WC
t
Write Pulse Width
(Note 3)
WP
AW
t
Address Setup Time
t
t
(Note 4)
(Note 5)
(Note 2)
(Note 2)
(Note 6)
(Note 4)
(Note 5)
5
WR1
WR2
Write Recovery Time
ns
20
t
Output High Impedance from WE
Output Active from WE
Data Setup Time
35
ns
ns
ns
ODW
t
5
40
0
OEW
t
DS
t
DH1
DH2
Data Hold Time
ns
t
20
POWER-DOWN/POWER-UP TIMING
(T = -40 C to +85 C.)
A
SYMBOL
PARAMETER
Fail Detect to CE and WE Inactive
CONDITIONS
(Note 7)
MIN
TYP
MAX
UNITS
µs
V
V
V
V
V
V
V
t
1.5
CC
CC
CC
CC
CC
CC
CC
PD
Slew from V to 0V
t
150
150
µs
TP
F
Slew from 0V to V
t
R
µs
TP
Valid to CE and WE Inactive
Valid to End of Write Protection
Fail Detect to RST Active
Valid to RST Inactive
t
2
ms
ms
µs
PU
t
t
t
125
3.0
525
REC
RPD
RPU
(Note 1)
(Note 1)
225
350
ms
DATA RETENTION
(T = +25 C.)
A
SYMBOL
PARAMETER
CONDITIONS
(Note 8)
MIN
TYP
MAX
UNITS
Expected Data-Retention Time (Per Charge)
t
2
3
years
DR
AC TEST CONDITIONS
Input Pulse Levels:
V
= 0.0Vꢀ V = 3.0V
IH
IL
Input Pulse Rise and Fall Times:
5ns
Input and Output Timing Reference Level: 1.5V
Output Load: 1 TTL Gate + C (100pF) including scope and jig
L
_____________________________________________________________________
3
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Read Cycle
t
RC
V
V
V
V
IH
IH
IH
ADDRESSES
V
V
IL
IL
IL
t
t
OH
OD
t
ACC
V
IH
V
IH
t
CE
OE
CO
V
IL
V
t
OE
IH
V
IH
V
IL
t
t
OD
COE
t
COE
V
V
V
OH
OH
OUTPUT
DATA VALID
D
OUT
V
OL
OL
(SEE NOTE 9.)
4
_____________________________________________________________________
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Write Cycle 1
t
WC
V
V
V
V
IH
IL
IH
IH
ADDRESSES
V
IL
V
IL
t
AW
CE
V
IL
V
IL
t
t
WP
WR1
WE
V
IH
V
IH
V
IL
V
IL
t
OEW
t
ODW
HIGH
IMPEDANCE
D
OUT
t
DS
t
DH1
V
IH
V
IH
D
IN
DATA IN STABLE
V
IL
V
IL
(SEE NOTES 2, 3, 4, 6, 10–13.)
Write Cycle 2
t
WC
V
IH
V
V
V
V
IL
IH
IH
ADDRESSES
CE
V
IL
IL
t
t
AW
t
WP
WR2
V
V
IH
IH
V
V
V
IL
IL
V
IL
WE
V
IL
IL
t
t
ODW
COE
D
OUT
t
t
DS
DH2
V
IH
V
IH
D
IN
DATA IN STABLE
V
IL
V
IL
(SEE NOTES 2, 3, 5, 6, 10–13.)
_____________________________________________________________________
5
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Power-Down/Power-Up Condition
V
CC
V
TP
t
DR
~2.5V
t
F
t
R
t
REC
t
t
PU
PD
SLEWS WITH
V
CC
CE,
WE
V
IH
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
t
t
RPU
RPD
RST
V
V
OL
OL
(SEE NOTES 1, 7.)
Note 1: RST is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to real-
ize a logic-high level.
Note 2: These parameters are sampled with a 5pF load and are not 100% tested.
Note 3:
t
is specified as the logical AND of CE and WE. t
is measured from the latter of CE or WE going low to the earlier of
WP
WP
CE or WE going high.
Note 4:
Note 5:
Note 6:
t
t
t
and t
and t
are measured from WE going high.
are measured from CE going high.
WR1
WR2
DH1
DH2
is measured from the earlier of CE or WE going high.
DS
Note 7: In a power-down conditionꢀ the voltage on any pin cannot exceed the voltage on V
.
CC
Note 8: The expected t is defined as accumulative time in the absence of V
starting from the time power is first applied by the
DR
CC
user. Minimum expected data-retention time is based on a maximum of two +230°C convection solder reflow exposuresꢀ
followed by a fully charged cell. Full charge occurs with the initial application of V for a minimum of 96 hours. This para-
CC
meter is assured by component selectionꢀ process controlꢀ and design. It is not measured directly in production testing.
Note 9: WE is high for a read cycle.
Note 10: OE = V or V . If OE = V during write cycleꢀ the output buffers remain in a high-impedance state.
IH
IL
IH
Note 11: If the CE low transition occurs simultaneously with or later than the WE low transitionꢀ the output buffers remain in a high-
impedance state during this period.
Note 12: If the CE high transition occurs prior to or simultaneously with the WE high transitionꢀ the output buffers remain in a high-
impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transitionꢀ the output buffers remain
in a high-impedance state during this period.
Note 14: DS2070W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
6
_____________________________________________________________________
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Typical Operating Characteristics
(V
= +3.3Vꢀ T = +25 Cꢀ unless otherwise noted.)
A
CC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. OPERATING FREQUENCY
BATTERY CHARGER CURRENT
vs. BATTERY VOLTAGE
8
7
6
5
4
3
2
1
0
12
10
8
1000
900
800
700
600
500
V
V
= CE = 3.3V,
T
= +25 C
V
= CE = 3.3V
CC
CC
A
= V
,
BAT
CHARGE
OSC = ON
5MHz CE-ACTIVATED
50% DUTY CYCLE
1MHz CE-ACTIVATED
50% DUTY CYCLE
6
5MHz ADDRESS-
ACTIVATED
100% DUTY CYCLE
1MHz ADDRESS-
ACTIVATED
100% DUTY CYCLE
4
2
V
CHARGE
0
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
85
5
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
0
0.2
DELTA V BELOW V
CHARGE
0.4
0.6
0.8
(V)
1.0
V
V
CC
CC
V
PERCENT CHANGE
vs. TEMPERATURE
CHARGE
V
TP
vs. TEMPERATURE
DQ V vs. DQ I
OH OH
1.0
0.5
0
3.00
2.95
2.90
2.85
2.80
3.5
3.3
3.1
2.9
2.7
2.5
V
V
= 3.3V,
CC
V
= 3.3V
CC
= V
BAT
CHARGE
-0.5
-1.0
-40
-15
10
35
60
-40
-15
10
35
60
85
-5
-4
-3
-2
(mA)
-1
0
TEMPERATURE ( C)
TEMPERATURE ( C)
I
OH
RST OUTPUT-VOLTAGE LOW
vs. OUTPUT-CURRENT LOW
RST VOLTAGE
vs. V DURING POWER-UP
DQ V vs. DQ I
CC
OL
OL
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
T
= +25 C
V
= 2.8V
A
V
= 3.3V
CC
CC
0
5
10
15
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
POWER-UP (V)
0
1
2
I
3
4
I
(mA)
V
CC
(mA)
OL
OL
_____________________________________________________________________
7
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Pin Description
BALLS
A1ꢀ A2ꢀ A3ꢀ A4
NAME
GND
N.C.
A15
DESCRIPTION
Ground
BALLS
NAME
A5
DESCRIPTION
Address Input 5
Address Input 4
Address Input 3
Address Input 2
Address Input 1
Address Input 0
Ground
N17ꢀ N18ꢀ N19ꢀ N20
P17ꢀ P18ꢀ P19ꢀ P20
R17ꢀ R18ꢀ R19ꢀ R20
T17ꢀ T18ꢀ T19ꢀ T20
U17ꢀ U18ꢀ U19ꢀ U20
V17ꢀ V18ꢀ V19ꢀ V20
W17ꢀ W18ꢀ W19ꢀ W20
Y17ꢀ Y18ꢀ Y19ꢀ Y20
A5ꢀ B5ꢀ C5ꢀ D5
B1ꢀ B2ꢀ B3ꢀ B4
No Connection
A4
C1ꢀ C2ꢀ C3ꢀ C4
D1ꢀ D2ꢀ D3ꢀ D4
E1ꢀ E2ꢀ E3ꢀ E4
Address Input 15
Address Input 16
Open-Drain Reset Output
Supply Voltage
A3
A16
A2
RST
A1
F1ꢀ F2ꢀ F3ꢀ F4
V
A0
CC
G1ꢀ G2ꢀ G3ꢀ G4
H1ꢀ H2ꢀ H3ꢀ H4
J1ꢀ J2ꢀ J3ꢀ J4
WE
OE
Write-Enable Input
Output-Enable Input
Chip-Enable Input
Data Input/Output 7
Data Input/Output 6
Data Input/Output 5
Data Input/Output 4
Data Input/Output 3
Data Input/Output 2
Data Input/Output 1
Data Input/Output 0
Ground
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A19
A20
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Ground
CE
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Address Input 19
Address Input 20
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
K1ꢀ K2ꢀ K3ꢀ K4
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND
GND
GND
A18
A17
A14
A13
A12
A11
A10
A9
A6ꢀ B6ꢀ C6ꢀ D6
L1ꢀ L2ꢀ L3ꢀ L4
A7ꢀ B7ꢀ C7ꢀ D7
M1ꢀ M2ꢀ M3ꢀ M4
N1ꢀ N2ꢀ N3ꢀ N4
P1ꢀ P2ꢀ P3ꢀ P4
A8ꢀ B8ꢀ C8ꢀ D8
A9ꢀ B9ꢀ C9ꢀ D9
A10ꢀ B10ꢀ C10ꢀ D10
A11ꢀ B11ꢀ C11ꢀ D11
A12ꢀ B12ꢀ C12ꢀ D12
A13ꢀ B13ꢀ C13ꢀ D13
A14ꢀ B14ꢀ C14ꢀ D14
A15ꢀ B15ꢀ C15ꢀ D15
A16ꢀ B16ꢀ C16ꢀ D16
U5ꢀ V5ꢀ W5ꢀ Y5
R1ꢀ R2ꢀ R3ꢀ R4
T1ꢀ T2ꢀ T3ꢀ T4
U1ꢀ U2ꢀ U3ꢀ U4
V1ꢀ V2ꢀ V3ꢀ V4
W1ꢀ W2ꢀ W3ꢀ W4
Y1ꢀ Y2ꢀ Y3ꢀ Y4
Ground
Ground
A17ꢀ A18ꢀ A19ꢀ A20
B17ꢀ B18ꢀ B19ꢀ B20
C17ꢀ C18ꢀ C19ꢀ C20
D17ꢀ D18ꢀ D19ꢀ D20
E17ꢀ E18ꢀ E19ꢀ E20
F17ꢀ F18ꢀ F19ꢀ F20
G17ꢀ G18ꢀ G19ꢀ G20
H17ꢀ H18ꢀ H19ꢀ H20
J17ꢀ J18ꢀ J19ꢀ J20
K17ꢀ K18ꢀ K19ꢀ K20
L17ꢀ L18ꢀ L19ꢀ L20
M17ꢀ M18ꢀ M19ꢀ M20
Ground
Address Input 18
Address Input 17
Address Input 14
Address Input 13
Address Input 12
Address Input 11
Address Input 10
Address Input 9
Address Input 8
Address Input 7
Address Input 6
U6ꢀ V6ꢀ W6ꢀ Y6
U7ꢀ V7ꢀ W7ꢀ Y7
U8ꢀ V8ꢀ W8ꢀ Y8
U9ꢀ V9ꢀ W9ꢀ Y9
U10ꢀ V10ꢀ W10ꢀ Y10
U11ꢀ V11ꢀ W11ꢀ Y11
U12ꢀ V12ꢀ W12ꢀ Y12
U13ꢀ V13ꢀ W13ꢀ Y13
U14ꢀ V14ꢀ W14ꢀ Y14
U15ꢀ V15ꢀ W15ꢀ Y15
U16ꢀ V16ꢀ W16ꢀ Y16
A8
A7
A6
8
_____________________________________________________________________
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Functional Diagram
CE
RST
DELAY TIMING
CIRCUITRY
V
REF
TP
UNINTERRUPTED
POWER SUPPLY
FOR THE SRAM
CHARGER
CURRENT-LIMITING
RESISTOR
V
CC
V
CC
CE
OE
WE
SRAM
DQ0–DQ7
V
SW
REF
REDUNDANT LOGIC
REDUNDANT
SERIES FET
CURRENT-LIMITING
ML
RESISTOR
BATTERY-CHARGING/SHORTING
PROTECTION CIRCUITRY (UL RECOGNIZED)
GND
OE
WE
DS2070W
A0–A20
The DS2070W assembly consists of a low-power SRAMꢀ
an ML batteryꢀ and an NV controller with a battery charg-
Detailed Description
The DS2070W is a 16Mb (2048kb x 8 bits) fully staticꢀ NV
memory similar in function and organization to the
DS1270W NV SRAMꢀ but containing a rechargeable ML
battery. The DS2070W NV SRAM constantly monitors
2
erꢀ integrated on a standard 256-ballꢀ (27mm) BGA sub-
strate. Unlike other surface-mount NV memory modules
that require the battery to be removable for solderingꢀ the
internal ML battery can tolerate exposure to convection
reflow soldering temperatures allowing this single-piece
component to be handled with standard BGA assembly
techniques.
V
CC
for an out-of-tolerance condition. When such a con-
dition occursꢀ the lithium energy source is automatically
switched on and write protection is unconditionally
enabled to prevent data corruption. There is no limit to
the number of write cycles that can be executed and no
additional support circuitry is required for microprocessor
interfacing. This device can be used in place of SRAMꢀ
EEPROMꢀ or flash components.
The DS2070W also contains a power-supply monitor
outputꢀ RSTꢀ which can be used as a CPU supervisor
for a microprocessor.
_____________________________________________________________________
9
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Memory Operation Truth Table
WE
CE
0
OE
0
MODE
Read
I
OUTPUTS
Active
CC
1
Active
Active
1
0
1
Read
High Impedance
High Impedance
High Impedance
0
0
X
Write
Active
X
1
X
Standby
Standby
X = Don’t care.
energy source to the RAM to retain data. During power-
upꢀ when V rises above V ꢀ the power-switching
Read Mode
The DS2070W executes a read cycle whenever WE (write
enable) is inactive (high) and CE (chip enable) is active
(low). The unique address specified by the 21 address
inputs (A0 to A20) defines which of the 2ꢀ097ꢀ152 bytes of
data is to be accessed. Valid data will be available to the
SW
CC
circuit connects external V
to the RAM and discon-
CC
nects the lithium energy source. Normal RAM operation
can resume after V exceeds V for a minimum
CC
TP
duration of t
.
REC
eight data output drivers within t
(access time) after
ACC
Battery Charging
is greater than V ꢀ an internal regulator
the last address input signal is stableꢀ providing that CE
and OE (output enable) access times are also satisfied. If
CE and OE access times are not satisfiedꢀ then data
access must be measured from the later-occurring signal
When V
CC
TP
charges the battery. The UL-approved charger circuit
includes short-circuit protection and a temperature-sta-
bilized voltage reference for on-demand charging of
the internal battery. Typical data-retention expectations
of 3 years per charge cycle are achievable.
(CE or OE) and the limiting parameter is either t
for CE
CO
or t for OE, rather than address access.
OE
Write Mode
A maximum of 96 hours of charging time is required to
fully charge a depleted battery.
The DS2070W executes a write cycle whenever the CE
and WE signals are active (low) after address inputs
are stable. The later-occurring falling edge of CE or WE
will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
System Power Monitoring
When the external V
supply falls below the selected
CC
out-of-tolerance trip pointꢀ the output RST is forced
active (low). Once activeꢀ the RST is held active until
the V
supply has fallen below that of the internal bat-
CC
minimum recovery time (t ) before another cycle can
WR
tery. On power-upꢀ the RST output is held active until
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
Howeverꢀ if the output drivers have been enabled (CE
the external supply is greater than the selected trip
point and one reset timeout period (t
This is sufficiently longer than t
SRAM is ready for access by the microprocessor.
) has elapsed.
RPU
to ensure that the
REC
and OE active) then WE will disable the outputs in t
ODW
from its falling edge.
Freshness Seal and Shipping
The DS2070W is shipped from Dallas Semiconductor
with the lithium battery electrically disconnectedꢀ guar-
anteeing that no battery capacity has been consumed
during transit or storage. As shippedꢀ the lithium battery
is ~60% chargedꢀ and no preassembly charging oper-
ations should be attempted.
Data-Retention Mode
The DS2070W provides full functional capability for V
CC
greater than 3.0V and write-protects by 2.8V. Data is
maintained in the absence of V without additional
CC
support circuitry. The NV static RAM constantly moni-
tors V . Should the supply voltage decayꢀ the NV
CC
SRAM automatically write-protects itself. All inputs
When V
is first applied at a level greater than V
ꢀ
CC
TP
become “don’t care”ꢀ and all data outputs become high
the lithium battery is enabled for backup operation. A
96-hour initial battery charge time is recommended for
new system installations.
impedance. As V
SW
falls below approximately 2.5V
CC
(V )ꢀ the power-switching circuit connects the lithium
10
____________________________________________________________________
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Applications Information
Recommended Reflow Temperature Profile
Power-Supply Decoupling
To achieve the best results when using the DS2070Wꢀ
decouple the power supply with a 0.1µF capacitor. Use
a high-qualityꢀ ceramic surface-mount capacitor if pos-
sible. Surface-mount components minimize lead induc-
tanceꢀ which improves performanceꢀ while ceramic
capacitors have adequately high frequency response
for decoupling applications.
Sn-Pb EUTECTIC
PROFILE FEATURE
ASSEMBLY
Average ramp-up rate
3 C/second max
(T to T )
L
P
Preheat
- Temperature min (T
- Temperature max (T
)
+100 C
+150 C
Smin
)
Smax
- Time (min to max) (t )
60 to 120 seconds
S
Using the Open-Drain RST Output
The RST output is open drainꢀ and therefore requires a
pullup resistor to realize a high logic output level. Pullup
resistor values between 1k and 10k are typical.
T
Smax
to T
L
- Ramp-up rate
Time maintained above:
Battery Charging/Lifetime
The DS2070W charges an ML battery to maximum
capacity in approximately 96 hours of operation when
Temperature (T )
+183 C
60 to 150 seconds
-
L
- Time (t )
L
Peak temperature (T )
+225 +0/-5 C
P
V
is greater than V . Once the battery is chargedꢀ
TP
CC
Time within 5 C of actual peak
temperature (T )
P
its lifetime depends primarily on the V
duty cycle.
CC
10 to 30 seconds
The DS2070W can maintain data from a singleꢀ initial
charge for up to 3 years. Once rechargedꢀ this deep-
discharge cycle can be repeated up to 20 timesꢀ pro-
ducing a worst-case service life of 60 years. More
typical duty cycles are of shorter durationꢀ enabling the
DS2070W to be charged hundreds of timesꢀ therefore
extending the service life well beyond 60 years.
Ramp-down rate
6 C/second max
6 minutes max
Time +25 C to peak temperature
Note: All temperatures refer to top side of the package, mea-
sured on the package body surface.
Recommended Cleaning Procedures
The DS2070W may be cleaned using aqueous-based
cleaning solutions. No special precautions are needed
when cleaning boards containing a DS2070W module.
Removal of the topside label violates the environmen-
tal integrity of the package and voids the warranty of
the product.
____________________________________________________________________ 11
3.3V Single-Piece 16Mb
Nonvolatile SRAM
Pin Configuration
TOP VIEW
1
2
6
11
15
16
17 18 19
3
4
5
7
9
10
13
14
20
8
12
GND
A18
A17
A14
A13
A12
A11
A10
A9
GND
A
B
A
B
N.C.
A15
A16
RST
C
D
E
C
D
E
V
CC
F
F
WE
OE
G
H
G
H
CE
J
J
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND
GND
A8
A7
K
L
K
L
DS2070W
A6
M
N
P
M
N
P
A5
A4
A3
R
T
R
T
A2
A1
U
V
U
V
A0
W
Y
W
Y
GND
GND
1
10
11
12
14
15
16
18
20
3
4
6
7
8
9
13
17
19
2
5
Package Information
For the latest package outline informationꢀ go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Productsꢀ Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Springer
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