DS21448LN_技术文档

DS21448

3.3V E1/T1/J1 Quad Line Interface

www.maxim-ic.com

GENERAL DESCRIPTION

FEATURES

The DS21448 is a quad-port E1 or T1 line interface

unit (LIU) for short-haul and long-haul applications. It

incorporates four independent transmitters and four

independent receivers in a single 144-pin PBGA or

128-pin LQFP package. The transmit drivers

generate the necessary G.703 E1 waveshapes in

75Ω or 120Ω applications and the DSX-1 or CSU line

build-outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1

applications.

ꢀ

Four Complete E1, T1, or J1 LIUs

Supports Long- and Short-Haul Trunks

Internal Software-Selectable Receive-Side

Termination for 75Ω/100Ω/120Ω

ꢀ

3.3V Power Supply

32-Bit or 128-Bit Crystal-Less Jitter Attenuator

Requires Only a 2.048MHz Master Clock for E1

and T1, with the Option to Use 1.544MHz for T1

Generates the Appropriate Line Build-Outs With

and Without Return Loss for E1, and DSX-1 and

CSU Line Build-Outs for T1

ꢀ

APPLICATIONS

Integrated Multiservice Access Platforms

T1/E1 Cross-Connects, Multiplexers, and Channel

Banks

ꢀ

AMI, HDB3, and B8ZS Encoding/Decoding

16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz

Clock Output Synthesized to Recovered Clock

Programmable Monitor Mode for Receiver

Loopbacks and PRBS Pattern Generation/

Detection with Output for Received Errors

Generates/Detects In-Band Loop Codes, 1 to 16

Bits, Including CSU Loop Codes

Central-Office Switches and PBX Interfaces

T1/E1 LAN/WAN Routers

ꢀ

Wireless Base Stations

ꢀ

ORDERING INFORMATION

8-Bit Parallel or Serial Interface with Optional

Hardware Mode

PART*

TEMP RANGE

PIN-PACKAGE

DS21448

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

144 TE-PBGA

128 LQFP

Muxed and Nonmuxed Parallel Bus Supports

Intel or Motorola

DS21448+

DS21448N

DS21448N+

DS21448L

DS21448L+

DS21448LN

DS21448LN+

ꢀ

Detects/Generates Blue (AIS) Alarms

NRZ/Bipolar Interface for Tx/Rx Data I/O

Transmit Open-Circuit Detection

128 LQFP

Receive Carrier Loss (RCL) Indication (G.775)

High-Z State for TTIP and TRING

128 LQFP

50mA_RMSTransmit Current Limiter

+ Denotes lead-free/RoHS-compliant package.

JTAG Boundary Scan Test Port per IEEE 1149.1

Meets Latest E1 and T1 Specifications Including

ANSI.403-1999, ANSI T1.408, AT&T TR 62411,

ITU G.703, G.704, G.706, G.736, G.775, G.823,

I.431, O.151, O.161, ETSI ETS 300 166,

JTG.703, JTI.431, TBR12, TBR13, and CTR4

*All devices rated at 3.3V.

Pin Configurations appear in Section 11.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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DS21448 3.3V T1/E1/J1 Quad Line Interface

TABLE OF CONTENTS

1.

2.

3.

BLOCK DIAGRAMS ........................................................................................................................5

PIN DESCRIPTION ..........................................................................................................................7

DETAILED DESCRIPTION ............................................................................................................13

3.1 DS21448 AND DS21Q348 DIFFERENCES......................................................................................13

PORT OPERATION .......................................................................................................................14

4.1 HARDWARE MODE.........................................................................................................................14

4.2 SERIAL PORT OPERATION..............................................................................................................15

4.3 PARALLEL PORT OPERATION .........................................................................................................18

4.

4.3.1

4.3.2

4.3.3

Device Power-Up and Reset................................................................................................................ 18

Register Map........................................................................................................................................ 18

Control Registers ................................................................................................................................. 19

5.

6.

STATUS REGISTERS....................................................................................................................23

DIAGNOSTICS ..............................................................................................................................28

6.1 IN-BAND LOOP-CODE GENERATION AND DETECTION......................................................................28

6.2 LOOPBACKS ..................................................................................................................................31

6.2.1

6.2.2

6.2.3

6.2.4

Remote Loopback (RLB) ..................................................................................................................... 31

Local Loopback (LLB).......................................................................................................................... 31

Analog Loopback (LLB) ....................................................................................................................... 31

Dual Loopback (DLB)........................................................................................................................... 31

6.3 PRBS GENERATION AND DETECTION ............................................................................................31

6.4 ERROR COUNTER..........................................................................................................................31

6.5 ERROR COUNTER UPDATE ............................................................................................................32

6.6 ERROR INSERTION ........................................................................................................................32

ANALOG INTERFACE...................................................................................................................33

7.1 RECEIVER .....................................................................................................................................33

7.2 TRANSMITTER ...............................................................................................................................33

7.3 JITTER ATTENUATOR .....................................................................................................................34

7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................34

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT..................................43

8.1 JTAG TAP CONTROLLER STATE MACHINE ....................................................................................43

8.2 INSTRUCTION REGISTER................................................................................................................45

8.3 TEST REGISTERS ..........................................................................................................................46

OPERATING PARAMETERS ........................................................................................................48

7.

8.

9.

10. AC TIMING PARAMETERS AND DIAGRAMS..............................................................................49

11. PIN CONFIGURATIONS................................................................................................................56

11.1

11.2

144-PIN BGA ............................................................................................................................56

128-PIN LQFP...........................................................................................................................57

12. PACKAGE INFORMATION ...........................................................................................................58

12.1

12.2

144-BALL TE-PBGA (56-G6020-001) .......................................................................................58

128-PIN LQFP (56-G4011-001)................................................................................................59

13. THERMAL INFORMATION............................................................................................................60

14. REVISION HISTORY......................................................................................................................60

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DS21448 3.3V T1/E1/J1 Quad Line Interface

LIST OF FIGURES

Figure 1-1. Block Diagram..........................................................................................................................5

Figure 1-2. Receive Logic Detail ................................................................................................................6

Figure 1-3. Transmit Logic Detail ...............................................................................................................6

Figure 4-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................16

Figure 4-2. Serial Port Operation for Read Access (R = 1) Mode 2 .........................................................16

Figure 4-3. Serial Port Operation for Read Access (R = 1) Mode 3 .........................................................16

Figure 4-4. Serial Port Operation for Read Access (R = 1) Mode 4 .........................................................17

Figure 4-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................17

Figure 4-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................17

Figure 7-1. Basic Interface .......................................................................................................................36

Figure 7-2. Protected Interface Using Internal Receive Termination........................................................37

Figure 7-3. Protected Interface Using External Receive Termination.......................................................38

Figure 7-4. Dual Connector-Protected Interface Using Receive Termination...........................................39

Figure 7-5. E1 Transmit Pulse Template..................................................................................................40

Figure 7-6. T1 Transmit Pulse Template..................................................................................................41

Figure 7-7. Jitter Tolerance ......................................................................................................................42

Figure 7-8. Jitter Attenuation ....................................................................................................................42

Figure 8-1. JTAG Block Diagram..............................................................................................................43

Figure 8-2. TAP Controller State Diagram................................................................................................44

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS0 = 0).......................................................................49

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS0 = 0) .......................................................................50

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS0 = 0)..........................................................................50

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS0 = 1).......................................................................51

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS0 = 1) .......................................................................52

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS0 = 1)................................................................52

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS0 = 1) ................................................................52

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................53

Figure 10-9. Receive-Side Timing............................................................................................................54

Figure 10-10. Transmit-Side Timing.........................................................................................................55

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DS21448 3.3V T1/E1/J1 Quad Line Interface

LIST OF TABLES

Table 2-A. Bus Interface Selection.............................................................................................................7

Table 2-B. Pin Assignments .......................................................................................................................7

Table 2-C. Parallel Interface Mode Pin Description....................................................................................9

Table 2-D. Serial Interface Mode Pin Description ....................................................................................10

Table 2-E. Hardware Interface Mode Pin Description ..............................................................................11

Table 3-A. DS21448 vs. DS21Q348 Pin Differences ...............................................................................13

Table 4-A. Loopback Control in Hardware Mode .....................................................................................14

Table 4-B. Transmit Data Control in Hardware Mode...............................................................................14

Table 4-C. Receive Sensitivity Settings in Hardware Mode .....................................................................14

Table 4-D. Monitor Gain Settings in Hardware Mode...............................................................................14

Table 4-E. Internal Rx Termination Select in Hardware Mode .................................................................14

Table 4-F. MCLK Selection in Hardware Mode ........................................................................................15

Table 4-G. Parallel Port Mode Selection ..................................................................................................18

Table 4-H. Register Map ..........................................................................................................................18

Table 4-I. Receive Sensitivity Settings .....................................................................................................22

Table 4-J. Backplane Clock Select...........................................................................................................22

Table 4-K. Monitor Gain Settings .............................................................................................................22

Table 4-L. Internal Rx Termination Select................................................................................................22

Table 5-A. Received Alarm Criteria..........................................................................................................25

Table 5-B. Receive Level Indication.........................................................................................................27

Table 6-A. Transmit Code Length ............................................................................................................29

Table 6-B. Receive Code Length .............................................................................................................29

Table 6-C. Definition of Received Errors..................................................................................................32

Table 6-D. Function of ECRS Bits and RNEG Pin....................................................................................32

Table 7-A. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) ......................................................34

Table 7-B. Line Build-Out Select for T1 in Register CCR4 (ETS = 1) ......................................................34

Table 7-C. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) Using Alternate Transformer

Configuration......................................................................................................................................35

Table 7-D. Transformer Specifications (3.3V Operation)..........................................................................35

Table 8-A. Instruction Codes for IEEE 1149.1 Architecture .....................................................................45

Table 8-B. ID Code Structure ...................................................................................................................46

Table 8-C. Device ID Codes.....................................................................................................................46

Table 8-D. Boundary Scan Control Bits....................................................................................................47

Table 10-A. AC Characteristics—Multiplexed Parallel Port (BIS0 = 0).....................................................49

Table 10-B. AC Characteristics—Nonmultiplexed Parallel Port (BIS0 = 1)..............................................51

Table 10-C. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)...........................................................53

Table 10-D. AC Characteristics—Receive Side .......................................................................................54

Table 10-E. AC Characteristics—Transmit Side ......................................................................................55

Table 13-A. Thermal Characteristics—BGA.............................................................................................60

Table 13-B. Theta-JA (θ_JA) vs. Airflow—BGA...........................................................................................60

Table 13-C. Thermal Characteristics—LQFP...........................................................................................60

Table 13-D. Theta-JA (θ_JA) vs. Airflow—LQFP.........................................................................................60

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DS21448 3.3V T1/E1/J1 Quad Line Interface

1. BLOCK DIAGRAMS

Figure 1-1. Block Diagram

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

TYPICAL OF ALL FOUR CHANNELS

2

JACLK

POWER

2.048MHz TO

1.544MHz PLL

16.384MHz OR

8.192MHz OR

4.096MHz OR

2.048MHz

CONNECTIONS

VCO/PLL

BPCLK

SYNTHESIZER

n

RPOS

RCLK

RNEG

RRING

RTIP

See Figure 1-2

PBEO

UNFRAMED

ALL-ONES

INSERTION

MUX

RCL/LOTC

TRING

TTIP

TPOS

TCLK

TNEG

See Figure 1-3

HRST

CONTROL AND TEST

PORT (ROUTED TO

ALL BLOCKS)

MUX (THE SERIAL, PARALLEL, AND HARDWARE INTERFACES

SHARE DEVICE PINS)

BIS0

TXDIS/TEST

CONTROL AND

(ROUTED TO

ALL BLOCKS)

SERIAL

PARALLEL INTERFACE

5

JTAG PORT

INTERFACE

8

Dallas

Semiconductor

DS21448

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DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 1-2. Receive Logic Detail

RCLK

CLOCK

INVERT

FROM

REMOTE

LOOPBACK

ROUTED TO

ALL BLOCKS

CCR2.0

RPOS

MUX

NRZ DATA

B8ZS/HDB3

DECODER

RNEG

BPV/CV/EXZ

CCR1.6

ALL-ONES

DETECTOR

LOOP CODE

DETECTOR

PRBS

PBEO

DETECTOR

CCR2.3

4 OR 8 ZERO DETECT

16 ZERO DETECT

CCR6.2/ RIR1.5

CCR6.0

MUX

CCR6.0/

SR.4 RIR1.3

SR.6 SR.7

SR.0

CCR6.1

16-BIT ERROR

COUNTER (ECR)

CCR1.4

RIR1.7

RIR1.6

Figure 1-3. Transmit Logic Detail

CCR3.4

CCR3.3

CCR1.6

CCR2.2

PRBS

GENERATOR

CCR3.0

OR

GATE

CCR3.1

LOOP CODE

GENERATOR

MUX

B8ZS/

HDB3

1

0

LOGIC

ERROR

INSERT

TPOS

CODER

OR

GATE

BPV

INSERT

TNEG

MUX

TO REMOTE

LOOPBACK

0

1

0

1

CLOCK

INVERT

TCLK

MUX

RCLK

MUX

JACLK

(FROM MCLK)

CCR1.1

CCR2.1

ROUTED TO

ALL BLOCKS

OR

AND

LOSS-OF-TRANSMIT

CLOCK DETECT

GATE

SR.5

TO LOTC OUTPUT PIN

CCR1.2

CCR1.0

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DS21448 3.3V T1/E1/J1 Quad Line Interface

2. PIN DESCRIPTION

The DS21448 can be controlled in parallel port mode, serial port mode, or hardware mode. The bus interface select

bits 0 and 1 (BIS0, BIS1) determine the device mode and pin assignments (Table 2-A).

Table 2-A. Bus Interface Selection

BIS1

BIS0

BUS INTERFACE TYPE

Parallel Port Mode (multiplexed)

Parallel Port Mode (nonmultiplexed)

Serial Port Mode

0

1

0

1

0

1

Hardware Mode

Table 2-B. Pin Assignments

I/O

PARALLEL PORT MODE

SERIAL PORT MODE

HARDWARE MODE

BGA

J3

D3

D10

K10

J2

H1

K2

J1

K3

K1

L1

LQFP

18

I

EGL1

EGL2

EGL3

EGL4

ETS

CS1

CS2

CS3

CS1

CS2

CS3

57

84

I

114

91

I

CS4

I

N/A

RD (DS)

WR (R/W)

ALE (AS)

N/A

92

I

N/A

NRZE

SCLKE

L2

95

I

N/A

35

I

SCLK

SDI

36

I

N/A

L1

62

I/O

I

A4

SDO

L0

63

A3

ICES

DJA

H11

H12

G12

J10

H10

G11

J9

64

I

A2

OCES

N/A

JAMUX

JAS

65

I

A1

66

I

A0

N/A

HBE

75

I/O

I

D7/AD7

D6/AD6

D5/AD5

D4/AD4

D3/AD3

D2/AD2

D1/AD1

D0/AD0

VSM

N/A

CES

76

N/A

TPD

77

N/A

TX0

78

N/A

TX1

E3

D4

F3

79

N/A

LOOP0

LOOP1

MM0

80

N/A

81

N/A

D5

—

82

N/A

MM1

VSM

3

VSM

L5

115–117

19–21

49–51

85–87

118–120

22–24

52–54

88–90

97

—

I/O

O

I

VDD1

VDD2

VDD3

VDD4

VSS1

VSS2

VSS3

VSS4

INT

VDD1

VDD2

VDD3

VDD4

VSS1

VSS2

VSS3

VSS4

RT1

E4

D8

J8

VDD2

VDD3

VDD4

M4

F4

VSS1

VSS2

D9

H9

K9

K5

G3

E10

K8

L6

VSS3

VSS4

INT

110

111

121

123

126

128

1

PBEO1

PBEO2

PBEO3

PBEO4

RCL1/LOTC1

RCL2/LOTC2

RCL3/LOTC3

RCL4/LOTC4

TXDIS/TEST

RTIP1

RTIP2

RTIP3

RTIP4

RRING1

RRING2

PBEO1

PBEO2

PBEO3

PBEO4

RCL1/LOTC1

RCL2/LOTC2

RCL3/LOTC3

RCL4/LOTC4

TXDIS/TEST

RTIP1

RTIP2

RTIP3

RTIP4

RRING1

RRING2

PBEO1

PBEO2

PBEO3

PBEO4

RCL1

RCL2

RCL3

RCL4

TXDIS/TEST

RTIP1

RTIP2

RTIP3

RTIP4

RRING1

RRING2

D7

F9

J7

2

K7

A1

98

124

28

I

A4

I

A7

60

I

A10

B2

B5

93

I

125

29

I

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DS21448 3.3V T1/E1/J1 Quad Line Interface

I/O

PARALLEL PORT MODE

SERIAL PORT MODE

HARDWARE MODE

BGA

B8

LQFP

61

94

106

109

122

47

56

112

107

68

6

38

71

102

7

39

72

103

8

I

RRING3

RRING4

HRST

RRING3

RRING4

HRST

RRING3

RRING4

HRST

B11

L9

I

J6

I

MCLK

H4

O

I

BPCLK1

BPCLK2

BPCLK3

BPCLK4

BIS0

BPCLK1

BPCLK2

BPCLK3

BPCLK4

BIS0

BPCLK1

BPCLK2

BPCLK3

BPCLK4

BIS0

D6

F10

L8

L7

M8

A2

I

BIS1

O

—

O

I

TTIP1

A5

TTIP2

A8

TTIP3

A11

J4

TTIP4

TVSS1

TVSS2

TVSS3

TVSS4

TVDD1

TVDD2

TVDD3

TVDD4

TRING1

TRING2

TRING3

TRING4

RPOS1

RPOS2

RPOS3

RPOS4

RNEG1

RNEG2

RNEG3

RNEG4

RCLK1

RCLK2

RCLK3

RCLK4

TPOS1

TPOS2

TPOS3

TPOS4

TNEG1

TNEG2

TNEG3

TNEG4

TCLK1

TCLK2

TCLK3

TCLK4

PBTS

TVSS1

TVSS2

TVSS3

TVSS4

TVDD1

TVDD2

TVDD3

TVDD4

TRING1

TRING2

TRING3

TRING4

RPOS1

RPOS2

RPOS3

RPOS4

RNEG1

RNEG2

RNEG3

RNEG4

RCLK1

RCLK2

RCLK3

RCLK4

TPOS1

TPOS2

TPOS3

TPOS4

TNEG1

TNEG2

TNEG3

TNEG4

TCLK1

TCLK2

TCLK3

TCLK4

N/A

TVSS1

TVSS2

TVSS3

TVSS4

TVDD1

TVDD2

TVDD3

TVDD4

TRING1

TRING2

TRING3

TRING4

RPOS1

RPOS2

RPOS3

RPOS4

RNEG1

RNEG2

RNEG3

RNEG4

RCLK1

RCLK2

RCLK3

RCLK4

TPOS1

TPOS2

TPOS3

TPOS4

TNEG1

TNEG2

TNEG3

TNEG4

TCLK1

TCLK2

TCLK3

TCLK4

RT0

D1

E9

L10

J5

D2

40

73

104

9

G9

M9

B3

B6

41

74

105

10

12

14

16

11

13

15

25

127

31

58

96

26

30

33

55

27

32

34

59

17

43

83

113

108

42

48

44

45

46

B9

B12

K4

E1

D11

K11

G2

E2

F11

M10

H3

F1

E11

L11

G1

F2

I

E12

M11

H2

M1

D12

K12

M2

L2

F12

L12

M12

L3

M3

M5

M6

M7

I

JTRST

JTMS

JTRST

JTMS

JTRST

JTMS

I

JTCLK

JTDI

JTCLK

JTDI

JTCLK

JTDI

I

O

JTDO

Note 1: The VSM signal is not available with the BGA package option.

Note 2: The LQFP no-connect pin numbers are 4, 5, 37, 67, 69, 70, and 99–101.

Note 3: The BGA no-connect pin numbers are A3, A6, A9, A12, B1, B4, B7, B10, C1–C12, E5–E8, F5–F8, G4–G8, G10, H5–H8, J11, J12, K6,

and L4.

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DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 2-C. Parallel Interface Mode Pin Description

I/O

FUNCTION

Read Input (Data Strobe). RD and DS are active-low signals. DS is active low when in

I

RD (DS)

nonmultiplexed, Motorola mode. See the bus timing diagrams in Section 10.

WR (R/W)

I

Write Input (Read/Write). WR is an active-low signal. See the bus timing diagrams in Section 10.

Address Latch Enable (Address Strobe). When using multiplexed bus mode (BIS0 = 0), this pin

serves to demultiplex the bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),

ALE should be wired low.

ALE (AS)

Address Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the address bus.

A4–A0

I

In multiplexed bus operation (BIS0 = 0), these pins are not used and should be wired low.

Data Bus/Address/Data Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the

data bus. In multiplexed bus operation (BIS0 = 0), these pins serve as an 8-bit multiplexed

address/data bus.

D7/AD7–D0/AD0

INT

I/O

Interrupt (INT). The interrupt flags the host controller during conditions and change of conditions

defined in the status register. It is an active-low, open-drain output.

Tri-State Control, Multifunctional. Set this pin high, with all CS1–CS4 inputs inactive, to tri-state

TTIP1–TTIP4 and TRING1–TRING4. Set this pin high with any of the CS1–CS4 inputs active to

tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.

Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zeros

default state.

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This

clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1

1.544MHz clock source is optional (Note 1).

O

I

TXDIS/TEST

HRST

I

MCLK

BIS0/BIS1

PBTS

I

Bus Interface Select Bit 0 and 1. Used to select bus interface option. See Table 2-A for details.

Parallel Bus Type Select. When using the parallel port, set PBTS high to select Motorola bus

timing; set low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS),

and WR (R/W) pins.

Chip Select 1. Must be low to read or write to channel 1 of the device. CS1 is an active-low

signal.

Chip Select 2. Must be low to read or write to channel 2 of the device. CS2 is an active-low

signal.

I

CS1–CS4

Chip Select 3. Must be low to read or write to channel 3 of the device. CS3 is an active-low

signal.

Chip Select 4. Must be low to read or write to channel 4 of the device. CS4 is an active-low

signal.

PRBS Bit-Error Output. The receiver constantly searches for a 2¹⁵- 1 (E1) or a QRSS (T1)

PRBS, depending on the ETS bit setting (CCR1.7). It remains high if it is out of synchronization

with the PRBS pattern. It goes low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization cause a positive-going pulse (with same period as E1 or

T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to logic 1.

PBEO1–PBEO4

O

Receive Carrier Loss/Loss-of-Transmit Clock. An output that toggles high during a receive carrier

loss (CCR2.7 = 0) or toggles high if the TCLK pin has not been toggled for 5µs ± 2µs (CCR2.7 =

1). CCR2.7 defaults to logic 0 when in hardware mode.

RCL1/LOTC1–

RCL4/LOTC4

RTIP1–RTIP4

RRING1–RRING4

I

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a

1:1 transformer to the line. See Section 7 for details.

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is

referenced to RCLK selectable through CCR5.7 and CCR5.6.

BPCLK1–BPCLK4

O

TTIP1–TTIP4

TRING1–TRING4

O

Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up

transformer to the line. See Section 7 for details.

Receive Positive Data. These bits are updated on the rising edge (CCR2.0 = 0) or the falling

edge (CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1

for NRZ applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or

EXZ) causes a positive-going pulse synchronous with RCLK at RNEG.

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 =

1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ

applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ)

causes a positive-going pulse synchronous with RCLK at RNEG.

RPOS1–RPOS4

RNEG1–RNEG4

O

9 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

I/O

FUNCTION

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of

RCLK1–RCLK4

O

signal at RTIP and RRING.

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge

TPOS1–TPOS4

TNEG1–TNEG4

I

(CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge

(CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. It is used to clock data through the

TCLK1–TCLK4

I

transmit-side formatter. It can be sourced internally by MCLK or RCLK. See Common Control

Register 1 and Figure 1-3.

JTRST

JTMS

I

JTAG Reset

JTAG Mode Select

JTCLK

I

JTAG Clock

JTDI

I

JTAG Data In

JTDO

O

I

JTAG Data Out

VSM

Voltage Supply Mode (LQFP only). Should be wired low for correct operation.

3.3V, ±5% Transmitter Positive Supply

3.3V, ±5% Positive Supply

TVDD1–TVDD4

VDD1–VDD4

TVSS1–TVSS4

VSS1–VSS4

—

Transmitter Signal Ground

Signal Ground

Table 2-D. Serial Interface Mode Pin Description

I/O

FUNCTION

Interrupt (INT). Flags host controller during conditions and change of conditions defined in the

status register. Active-low, open-drain output.

I/O

INT

Tri-State Control, Multifunctional. Set this pin high with all CS1–CS4 inputs inactive to tri-state

TTIP1–TTIP4 and TRING1–TRING4. Set this pin high with any of the CS1–CS4 inputs active to

tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.

Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zeros

default state.

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This

clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz

clock source is optional (Note 1).

TXDIS/TEST

HRST

I

MCLK

BIS0/BIS1

I

Bus Interface Select Bit 0 and 1. Used to select bus interface option. See Table 2-A for details.

Chip Select 1. Must be low to read or write to channel 1 of the device. CS1 is an active-low

CS1

signal.

Chip Select 2. Must be low to read or write to channel 2 of the device. CS2 is an active-low

signal.

I

CS2

CS3

Chip Select 3. Must be low to read or write to channel 3 of the device. CS3 is an active-low

signal.

Chip Select 4. Must be low to read or write to channel 4 of the device. CS4 is an active-low

signal.

CS4

Input Clock-Edge Select. Selects whether the serial interface data input (SDI) is sampled on the

rising (ICES = 0) or falling edge (ICES = 1) of SCLK.

Output Clock-Edge Select. Selects whether the serial interface data output (SDO) changes on

the rising (OCES = 1) or falling edge (OCES = 0) of SCLK.

Serial Clock. Serial interface clock.

ICES

OCES

SCLK

SDI

SDO

I

O

Serial Data Input. Serial interface data input.

Serial Data Output. Serial interface data output.

PRBS Bit-Error Output. The receiver constantly searches for a 2¹⁵- 1 (E1) or a QRSS (T1)

PRBS, depending on the ETS bit setting (CCR1.7). It remains high if it is out of synchronization

with the PRBS pattern. It goes low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization cause a positive-going pulse (with same period as E1 or

T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to logic 1.

PBEO1–PBEO4

O

Receive Carrier Loss/Loss-of-Transmit Clock. An output that toggles high during a receive carrier

loss (CCR2.7 = 0) or toggles high if the TCLK pin has not been toggled for 5µs ± 2µs

(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a

1:1 transformer to the line. See Section 7 for details.

RCL1/LOTC1–

RCL4/LOTC4

O

I

RTIP1–RTIP4

RRING1–RRING4

10 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

I/O

FUNCTION

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is

referenced to RCLK selectable through CCR5.7 and CCR5.6.

BPCLK1–BPCLK4

O

TTIP1–TTIP4

TRING–TRING4

O

Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up

transformer to the line. See Section 7 for details.

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1)

of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ applications.

In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ) causes a

positive-going pulse synchronous with RCLK at RNEG.

RPOS1–RPOS4

RNEG1–RNEG4

O

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 =

1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ

applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ)

causes a positive-going pulse synchronous with RCLK at RNEG.

O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of

signal at RTIP and RRING.

RCLK1–RCLK4

TPOS1–TPOS4

TNEG1–TNEG4

O

I

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =

1) of TCLK for data to be transmitted out onto the line.

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =

I

1) of TCLK for data to be transmitted out onto the line.

Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit

TCLK1–TCLK4

I

side formatter. They can be sourced internally by MCLK or RCLK. See Common Control Register

1 and Figure 1-3.

JTRST

JTMS

I

JTAG Reset

JTAG Mode Select

JTCLK

I

JTAG Clock

JTDI

I

JTAG Data In

JTDO

O

I

JTAG Data Out

VSM

Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.

3.3V, ±5% Transmitter Positive Supply

3.3V, ±5% Positive Supply

TVDD1–TVDD4

VDD1–VDD4

TVSS1–TVSS4

VSS1–VSS4

—

Transmitter Signal Ground for Transmitter Outputs

Signal Ground

Table 2-E. Hardware Interface Mode Pin Description

I/O

FUNCTION

E1/T1 Select

0 = E1

ETS

I

1 = T1

NRZ Enable

0 = bipolar data at RPOS/RNEG and TPOS/TNEG

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when the

device receives a BPV, CV, or EXZ.

NRZE

I

Receive and Transmit Synchronization Clock Enable. SCLKE combines RSCLKE (CCR5.3) and

TSCLKE (CCR5.2).

SCLKE

0 = disable 2.048MHz synchronization transmit and receive mode

1 = enable 2.048MHz synchronization transmit and receive mode

Disable Jitter Attenuator

DJA

JAMUX

JAS

I

0 = jitter attenuator enabled

1 = jitter attenuator disabled

Jitter Attenuator Clock Mux. Controls the source for JACLK.

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK).

1 = JACLK sourced from internal PLL (2.048 MHz at MCLK).

Jitter Attenuator Path Select

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Receive and Transmit HDB3/B8ZS Enable. HBE combines RHBE (CCR2.3) and THBE

(CCR2.2).

HBE

I

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Line Build-Out Select Bits 0,1, and 2. These pins set the transmitter build-out; see (Table 7-A

(E1) and Table 7-B (T1).

L0/L1/L2

11 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

I/O

FUNCTION

Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and

which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES.

0 = update RPOS/RNEG on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK

1 = update RPOS/RNEG on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK

Transmit Power-Down

CES

I

TPD

I

0 = normal transmitter operation

1 = powers down the transmitter and tri-states TTIP and TRING pins

Transmit Data Source Select Bits 0 and 1. These inputs determine the source of the transmit

data (Table 4-B).

TX0/TX1

LOOP0/LOOP1

MM0/MM1

I

Loopback Select Bits 0 and 1. These inputs determine the active loopback mode (Table 4-A).

Monitor Mode Select Bits 0 and 1. These inputs determine if the receive equalizer is in a monitor

mode (Table 4-D).

Receive LIU Termination Select Bits 0 and 1. These inputs determine the receive termination

(Table 4-E).

RT1/RT0

TEST

I

Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port).

Set low for normal operation. Useful in board-level testing.

Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zero

default state.

HRST

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This

clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz

clock source is optional (Note 1). See Table 4-F for details.

MCLK

I

BIS0/BIS1

I

Bus Interface Select Bit 0 and 1. Used to select bus interface option (Table 2-A).

Receive Equalizer Gain-Limit Select. These bits control the sensitivity of the receive equalizers

(Table 4-C).

EGL1–EGL4

PRBS Bit-Error Output. The receiver constantly searches for a 2¹⁵- 1 PRBS (ETS = 0) or a

QRSS PRBS (ETS = 1). The pattern is chosen automatically by the value of the ETS pin. It

remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized

to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-

going pulse (with same period as E1 or T1 clock) synchronous with RCLK.

PBEO1–PBEO4

O

RCL1–RCL4

RTIP1–RTIP4

O

I

Receive Carrier Loss. An output that toggles high during a receive carrier loss.

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a

1:1 transformer to the line. See Section 7 for details.

RRING1–RRING4

BPCLK1–BPCLK4

TTIP1–TTIP4

I

O

Backplane Clock. A 16.384MHz clock output that is referenced to RCLK.

Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up

transformer to the line. See Section 7 for details.

O

TRING1–TRING4

Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of

RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on

RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with

RCLK at RNEG.

RPOS1–RPOS4

O

Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of

RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on

RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with

RCLK at RNEG.

RNEG1–RNEG4

RCLK1–RCLK4

O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of

signal at RTIP and RRING.

Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of

TCLK for data to be transmitted out onto the line.

TPOS1–TPOS4

TNEG1–TNEG4

I

Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of

TCLK for data to be transmitted out onto the line.

Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit

TCLK1–TCLK4

I

side formatter. It can be sourced internally by MCLK or RCLK. See Common Control Register 1

and Figure 1-3.

JTRST

JTMS

I

JTAG Reset

JTAG Mode Select

JTCLK

I

JTAG Clock

JTDI

I

JTAG Data In

JTDO

O

I

JTAG Data Out

VSM

Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.

3.3V, ±5% Transmitter Positive Supply

3.3V, ±5% Positive Supply

TVDD1–TVDD4

VDD1–VDD4

–

—

12 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

I/O

—

FUNCTION

Transmitter Signal Ground for Transmitter Outputs

Signal Ground

TVSS1–TVSS4

VSS1–VSS4

Note 1: G.703 requires an accuracy of ±50ppm for T1 and E1. TR62411 and ANSI specs require ±32ppm accuracy for T1 interfaces.

3. DETAILED DESCRIPTION

The DS21448 has a usable receiver sensitivity of 0 to -43dB for E1 applications and 0 to -36dB for T1 that allows it

to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6000ft (T1) in length. The user has the option to use

internal receive termination, software selectable for 75Ω, 100Ω, and 120Ω applications, or external termination.

The on-board crystal-less jitter attenuator can be placed in either the transmit or the receive data path, and requires

only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1

applications).

The DS21448 has diagnostic capabilities such as loopbacks and PRBS pattern generation and detection. 16-bit

loop-up and loop-down codes can be generated and detected. A single input pin can power down all transmitters to

allow the implementation of hitless protection switching (HPS) for 1+1 redundancy without the use of relays. The

device can be controlled through an 8-bit parallel port (muxed or nonmuxed) or a serial port, and it can be used in

hardware mode. A standard boundary scan interface supports board-level testing.

The DS21448 contains four independent LIUs that share a common interface for configuration and status. The user

can choose between three different means of accessing the device: a parallel microprocessor interface, a serial

interface, and a hardwired mode, which configures the device by setting levels on the device’s pins. The

DS21448’s four chip selects (CS1, CS2, CS3, and CS4) determine which LIU is accessed when using the parallel

or serial interface modes. Four sets of identical register maps exist, one for each channel. Using the appropriate

chip select accesses a channel’s register map.

The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off the T1 line is transformer-coupled

into the RTIP and RRING pins of the DS21448. The user has the option to use internal termination, software

selectable for 75Ω/100Ω/120Ω applications, or external termination. The device recovers clock and data from the

analog signal and passes it through the jitter attenuation mux, outputting the received line clock at RCLK and

bipolar or NRZ data at RPOS and RNEG. The DS21448 contains an active filter that reconstructs the analog-

received signal for the nonlinear losses that occur in transmission. The receive circuitry is also configurable for

various monitor applications. The device has a usable receive sensitivity of 0 to -43dB for E1 and 0 to -36dB for T1

that allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data

input at TPOS and TNEG is sent through the jitter attenuation mux to the waveshaping circuitry and line driver. The

DS21448 drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The line driver

can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.

3.1 DS21448 and DS21Q348 Differences

The DS21448 BGA is a monolithic quad-port LIU that is a replacement for the DS21Q348. The additional features

of JTAG, transmit driver disable, and the serial interface in the DS21448 have changed the function of several pins,

as shown in Table 3-A.

Table 3-A. DS21448 vs. DS21Q348 Pin Differences

G4

J1

DS21Q348

VSM

VSS

DS21448

N.C.

SCLK

K1

K3

K7

L3

A4

A4/SDO

SDI

VSS

TEST

N.C.

TXDIS/TEST

JTRST*

JTMS*

JTCLK

JTDI*

M3

M5

M6

M7

N.C.

JTDO

*DS21448 pin is internally pulled up.

13 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

4. PORT OPERATION

4.1 Hardware Mode

The DS21448 supports a hardware configuration mode that allows the user to configure the device by setting levels

on the device’s pins. This mode allows the DS21448 configuration without the use of a microprocessor, simplifying

designs. Not all of the device features are supported in the hardware mode.

In hardware mode (BIS0 = 1, BIS1 = 1) several pins have been redefined so they can be used for initializing the

DS21448. Refer to Table 2-B and Table 2-E for pin assignment and definition. Because of limited pin count, several

functions have been combined and affect all four channels in the device and/or treat the receive and transmit paths

as one block. Restrictions when using the hardware mode include the following:

•

BPCLK pins only output a 16.384MHz signal.

The RCL/LOTC pins are designated to RCL.

The RHBE and THBE control bits are combined and controlled by HBE.

RSCLKE and TSCLKE bits are combined and controlled by SCLKE.

TCES and RCES are combined and controlled by CES.

The transmitter functions are combined and controlled by TX1 and TX0.

Loopback functions are controlled by LOOP1 and LOOP0.

JABDS defaults to 128-bit buffer depth.

All other control bits default to logic 0.

Table 4-A. Loopback Control in Hardware Mode

LOOPBACK

Remote Loopback

Local Loopback

Analog Loopback

No Loopback

SYMBOL

RLB

LOOP1

LOOP0

1

0

1

0

1

0

LLB

ALB

—

Table 4-B. Transmit Data Control in Hardware Mode

TRANSMIT DATA

Unframed All Ones

Alternating Ones and Zeros

PRBS

SYMBOL

TUA1

TAOZ

TPRBSE

—

TX1

1

TX0

1

0

1

0

TPOS and TNEG

Table 4-C. Receive Sensitivity Settings in Hardware Mode

EGL

ETS

RECEIVE SENSITIVITY (dB)

-12 (short haul)

0

1

0

0 (E1)

1 (T1)

-43 (long haul)

-30 (limited long haul)

-36 (long haul)

Table 4-D. Monitor Gain Settings in Hardware Mode

MM1

MM0

INTERNAL LINEAR GAIN BOOST (dB)

0

1

0

1

0

1

Normal operation (no boost)

20

26

32

Table 4-E. Internal Rx Termination Select in Hardware Mode

INTERNAL RECEIVE

RT1

RT0

TERMINATION CONFIGURATION

Internal receive-side termination disabled

Internal receive-side 120Ω enabled

Internal receive-side 100Ω enabled

Internal receive-side 75Ω enabled

0

1

0

1

0

1

14 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 4-F. MCLK Selection in Hardware Mode

MCLK (MHz)

2.048

JAMUX

ETS

0

1

0

1

2.048

1.544

4.2 Serial Port Operation

Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21448 (Table 2-A). Serial port read/write

timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.

See Section 10 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 4-1,

Figure 4-2, Figure 4-3, Figure 4-4, Figure 4-5, and Figure 4-6 for additional details.

A serial bus access requires the use of four signals: serial clock (SCLK), one of the four chip selects (CS), serial

data input (SDI), and serial data output (SDO). The DS21448 uses SCLK to sample data that is present on SDI and

output data onto SDO. Input clock-edge select (ICES) allows the user to choose which SCLK edge input data is

sampled on. Output clock-edge select (OCES) allows the user to choose which SCLK edge output data changes

on. When ICES is low, input data is latched on the rising edge of SCLK, and when ICES is high, input data is

latched on the falling edge of SCLK. When OCES is low, data is output on the falling edge of SCLK, and when

OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling or rising edge of SCLK.

All data transfers are initiated by driving the appropriate port’s CS input low and ends with CS going inactive. CS

must go inactive between data transfers. See the serial bus timing information in Section 10 for details. All data

transfers are terminated if the port’s CS input transitions high. Port control logic is disabled, and SDO is tri-stated

when all CS pins are inactive.

Reading from or writing to the internal registers requires writing one address/command byte prior to the transferring

register data. Two types of serial bus transfers exist, standard and burst. The standard serial bus access always

consists of two bytes, an address/command byte that is always supplied by the user on SDI, and a data byte that

can either be written to the DS21448 using SDI (write operation) or output by the DS21448 on SDO (read

operation). The burst serial bus access consists of a single address/command byte followed either by 22 read or 22

write data bytes.

The first bit written (LSB) of the address/command byte specifies whether the access is to be a read (1) or a write

(0). The next 5 bits identify the register address. Valid register addresses are 00h through 15h. Bit 7 is reserved

and must be set to 0 for proper operation. Bit 8, the last bit (MSB) of the address/command byte, is the burst mode-

enable bit. When the burst bit is enabled (set to 0) and a READ operation is performed, the DS21448 automatically

outputs the contents of registers 00h through 15h sequentially, starting with register address 00h. When the burst

bit is enabled and a WRITE operation is performed, data supplied on SDI is sequentially written into the DS21448’s

register space starting at address 00h. Burst operation is stopped once address 15h is read or CS goes inactive.

For both burst read and burst write transfers, the address/command byte’s register address bits must be set to 0.

The user can broadcast register write accesses to multiple ports simultaneously by enabling the desired channels’

chip selects at the same time. However, only one port can be read at a time. Any attempt to read multiple ports

simultaneously results in invalid data being returned on SDO.

15 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 4-1. Serial Port Operation for Read Access (R = 1) Mode 1

ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)

OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

A1

A2

A3

A4

A5

0

B

1

(MSB)

(LSB)

READ ACCESS ENABLED

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(MSB)

(LSB)

Figure 4-2. Serial Port Operation for Read Access (R = 1) Mode 2

ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)

OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

A1

A2

A3

A4

A5

0

B

1

(MSB)

(LSB)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(MSB)

(LSB)

Figure 4-3. Serial Port Operation for Read Access (R = 1) Mode 3

ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)

OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

A1

A2

A3

A4

A5

0

B

1

(MSB)

(LSB)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(MSB)

(LSB)

16 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 4-4. Serial Port Operation for Read Access (R = 1) Mode 4

ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)

OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

A1

A2

A3

A4

A5

B

0

1

(LSB)

(MSB)

SDO

D0

D1

D2

D3

D4

D5

D6

D7

(MSB)

(LSB)

Figure 4-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2

ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SDI

DO

D6

A1

A2

A3

A4

A5

0

B

D1

D2

D3

D4

D5

D7

0

(LSB)

(MSB)

(LSB)

WRITE ACCESS ENABLED

SDO

Figure 4-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4

ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)

SCLK

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SDI

DO

D6

A1

A2

A3

A4

A5

0

B

D1

D2

D3

D4

D5

D7

(MSB)

0

(LSB)

(MSB)

(LSB)

WRITE ACCESS ENABLED

SDO

17 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

4.3 Parallel Port Operation

The option for either multiplexed bus operation (BIS0 = 0) or nonmultiplexed bus operation (BIS0 = 1) is available

when using the parallel interface. The DS21448 can operate with either Intel or Motorola bus timing configurations.

If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus

signals are listed in parentheses (). Four sets of identical register maps exist, one for each channel. See Table 4-H

for register names and addresses. Use the appropriate chip select (CS1, CS2, CS3, or CS4) to access a channel’s

register map. See the timing diagrams in Section 10 for more details. Hardware and serial port modes are not

supported when using parallel port operation.

4.3.1 Device Power-Up and Reset

The DS21448 resets itself upon power-up, setting all writeable registers to 00h and clearing the status and

information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power

supplies have settled, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2). The

DS21448 can at any time be reset to the default settings by bringing HRST low (level triggered) or by powering

down and powering up again.

Table 4-G. Parallel Port Mode Selection

PBTS

BIS0

PROCESSOR

Intel

BUS INTERFACE TYPE

Parallel Port Mode (Multiplexed)

Parallel Port Mode (Nonmultiplexed)

Parallel Port Mode (Multiplexed)

Parallel Port Mode (Nonmultiplexed)

0

1

0

1

0

1

Intel

Motorola

4.3.2 Register Map

Table 4-H shows the typical register map for all four ports. Use the appropriate chip select (CS1, CS2, CS3, or CS4)

to access a channel’s register map.

Table 4-H. Register Map

NAME

CCR1

CCR2

CCR3

CCR4

CCR5

CCR6

SR

R/W

R

ADDRESS

00h

FUNCTION

Common Control Register 1

Common Control Register 2

Common Control Register 3

Common Control Register 4

Common Control Register 5

Common Control Register 6

Status Register

01h

02h

03h

04h

05h

06h

IMR

R/W

R

07h

Interrupt Mask Register

RIR1

08h

Receive Information Register 1

Receive Information Register 2

In-Band Code Control Register

Transmit Code Definition Register 1

Transmit Code Definition Register 2

Receive-Up Code Definition Register 1

Receive-Up Code Definition Register 2

Receive-Down Code Definition Register 1

Receive-Down Code Definition Register 2

Error Count Register 1

RIR2

R

09h

IBCC

R/W

R

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

TCD1

TCD2

RUPCD1

RUPCD2

RDNCD1

RDNCD2

ECR1

ECR2

TEST1

TEST2

—

10h

11h

R

12h

Error Count Register 2

R/W

—

13h

Test 1

14h

Test 2

15h

(Note 1)

Test 3

—

Note 1: Register addresses 16h–1Fh do not exist.

18 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

4.3.3 Control Registers

CCR1 (00H): Common Control Register 1

(MSB)

(LSB)

ETS

NAME

ETS

NRZE

POSITION

CCR1.7

RCLA

ECUE

JAMUX

FUNCTION

TTOJ

TTOR

LOTCMC

E1/T1 Select

0 = E1

1 = T1

NRZ Enable

0 = bipolar data at RPOS/RNEG and TPOS/TNEG

NRZE

RCLA

ECUE

CCR1.6

CCR1.5

CCR1.4

1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when the

device receives a BPV, CV, or EXZ

Receive-Carrier-Loss Alternate Criteria

0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros

1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive zeros

Error Counter Update Enable. A 0-to-1 transition forces the next receive clock cycle to load the

error counter registers with the latest counts and reset the counters. The user must wait a

minimum of two clock cycles (976ns for E1 and 1296ns for T1) before reading the error count

registers to allow for a proper update. See Section 6 for details.

Jitter Attenuator Clock Mux. Controls the source for JACLK (Figure 1-1).

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)

1 = JACLK sourced from internal PLL (2.048MHz at MCLK)

TCLK to JACLK. Internally connects TCLK to JACLK (Figure 1-3).

0 = disabled

JAMUX

TTOJ

CCR1.3

CCR1.2

CCR1.1

1 = enabled

TCLK to RCLK. Internally connects TCLK to RCLK (Figure 1-3).

0 = disabled

TTOR

1 = enabled

Loss-of-Transmit Clock Mux Control. Determines whether the transmit logic should switch to

JACLK if the TCLK input should fail to transition (Figure 1-3).

0 = do not switch to JACLK if TCLK stops

LOTCMC

CCR1.0

1 = switch to JACLK if TCLK stops

19 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

CCR2 (01H): Common Control Register 2

(MSB)

(LSB)

RLPIN

NAME

RLPIN

—

SCLD

CLDS

RHBE

THBE

TCES

RCES

POSITION

CCR2.7

FUNCTION

RCL/LOTC Pin Function Select. Forced to logic 0 in hardware mode.

0 = toggles high during a receive-carrier loss condition

1 = toggles high if TCLK does not transition for at least 5µs

—

CCR2.6

CCR2.5

Not Assigned. Should be set to 0 when written to.

Short Circuit-Limit Disable (ETS = 0). Controls the 50mA (RMS) current limiter.

SCLD

0 = enable 50mA current limiter

1 = disable 50mA current limiter

Custom Line-Driver Select. Setting this bit to 1 redefines the operation of the transmit line

driver. When this bit is set to 1 and CCR4.5 = CCR4.6 = CCR4.7 = 0, the device generates a

square wave at the TTIP and TRING outputs instead of a normal waveform. When this bit is

set to 1 and CCR4.5 = CCR4.6 = CCR4.7 ≠ 0, the device forces TTIP and TRING outputs to

become open-drain drivers instead of their normal push-pull operation. This bit should be set

to 0 for normal operation of the device. Contact the factory for more details about how to use

this bit.

CLDS

CCR2.4

Receive HDB3/B8ZS Enable

RHBE

THBE

TCES

RCES

CCR2.3

CCR2.2

CCR2.1

CCR2.0

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit HDB3/B8ZS Enable

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit Clock-Edge Select. Selects which TCLK edge to sample TPOS and TNEG.

0 = sample TPOS and TNEG on falling edge of TCLK

1 = sample TPOS and TNEG on rising edge of TCLK

Receive Clock-Edge Select. Selects which RCLK edge to update RPOS and RNEG.

0 = update RPOS and RNEG on rising edge of RCLK

1 = update RPOS and RNEG on falling edge of RCLK

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DS21448 3.3V T1/E1/J1 Quad Line Interface

CCR3 (02H): Common Control Register 3

(MSB)

(LSB)

TUA1

ATUA1

TAOZ

TPRBSE

TLCE

FUNCTION

LIRST

IBPV

IBE

NAME

POSITION

Transmit Unframed All Ones. The polarity of this bit is set such that the device transmits an all-

ones pattern on power-up or device reset. This bit must be set to 1 to allow the device to transmit

TUA1

CCR3.7

CCR3.6

data. The transmission of this data pattern is always timed off JACLK (Figure 1-1).

0 = transmit all ones at TTIP and TRING

1 = transmit data normally

Automatic Transmit Unframed All Ones. Automatically transmit an unframed all-ones pattern at

TTIP and TRING during an RCL condition.

ATUA1

0 = disabled

1 = enabled

Transmit Alternate Ones and Zeros. Transmit a …101010… pattern at TTIP and TRING. The

transmission of this data pattern is always timed off TCLK.

TAOZ

CCR3.5

CCR3.4

0 = disabled

1 = enabled

Transmit PRBS Enable. Transmit a 2¹⁵- 1 (E1) or a QRSS (T1) PRBS at TTIP and TRING.

TPRBSE

0 = disabled

1 = enabled

Transmit Loop-Code Enable. Enables the transmit side to transmit the loop-up code in the transmit

code definition registers (TCD1 and TCD2). See Section 6 for details.

0 = disabled

TLCE

LIRST

IBPV

IBE

CCR3.3

CCR3.2

CCR3.1

CCR3.0

1 = enabled

Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset that resets the clock

recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on

power-up. It must be cleared and set again for a subsequent reset.

Insert Bipolar Violation (BPV). A 0-to-1 transition on this bit causes a single bipolar violation to be

inserted into the transmit data stream. Once this bit has been toggled from 0 to 1, the device waits

for the next occurrence of three consecutive 1s to insert the BPV. This bit must be cleared and set

again for a subsequent error to be inserted (Figure 1-3).

Insert Bit Error. A 0-to-1 transition on this bit causes a single logic error to be inserted into the

transmit data stream. This bit must be cleared and set again for a subsequent error to be inserted

(Figure 1-3).

CCR4 (03H): Common Control Register 4

(MSB)

(LSB)

L2

L1

L0

EGL

JAS

JABDS

DJA

TPD

NAME

L2

POSITION

CCR4.7

CCR4.6

CCR4.5

FUNCTION

Line Build-Out Select Bit 2. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

Line Build Out Select Bit 1. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

Line Build Out Select Bit 0. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

L1

L0

EGL

CCR4.4

Receive Equalizer Gain Limit. This bit controls the sensitivity of the receive equalizer (Table 4-I).

Jitter Attenuator Path Select

JAS

CCR4.3

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Jitter Attenuator Buffer Depth Select

0 = 128 bits

JABDS

DJA

CCR4.2

CCR4.1

CCR4.0

1 = 32 bits (use for delay-sensitive applications)

Disable Jitter Attenuator

0 = jitter attenuator enabled

1 = jitter attenuator disabled

Transmit Power-Down

TPD

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP and TRING pins

21 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 4-I. Receive Sensitivity Settings

EGL

ETS

(CCR1.7)

0 (E1)

RECEIVE SENSITIVITY

(dB)

(CCR4.4)

0

1

0

-12 (short haul)

-43 (long haul)

-30 (limited long haul)

-36 (long haul)

0 (E1)

1 (T1)

CCR5 (04H): Common Control Register 5

(MSB)

(LSB)

BPCS1

BPCS0

MM1

MM0

RSCLKE

TSCLKE

RT1

RT0

NAME

BPCS1

BPCS0

MM1

POSITION

CCR5.7

CCR5.6

CCR5.5

CCR5.4

FUNCTION

Backplane Clock Frequency Select 1. See Table 4-J for details.

Backplane Clock Frequency Select 0. See Table 4-J for details.

Monitor Mode Gain Select 1 (Table 4-K. )

MM0

Monitor Mode Gain Select 0. See (Table 4-K.

Receive Synchronization Clock Enable

RSCLKE

CCR5.3

0 = disable 2.048MHz synchronization receive mode

1 = enable 2.048MHz synchronization receive mode

Transmit Synchronization Clock Enable

TSCLKE

CCR5.2

0 = disable 2.048MHz transmit synchronization clock

1 = enable 2.048MHz transmit synchronization clock

Receive Termination Select 1. See Table 4-L for details.

RT1

RT0

CCR5.1

CCR5.0

Receive Termination Select 0. See Table 4-L for details.

Table 4-J. Backplane Clock Select

BPCS1

BPCS0

BPCLK FREQUENCY (MHz)

(CCR5.7)

(CCR5.6)

0

1

0

1

0

1

16.384

8.192

4.096

2.048

Table 4-K. Monitor Gain Settings

MM1

MM0

INTERNAL LINEAR GAIN

(CCR5.5)

(CCR5.4)

BOOST (dB)

0

1

0

1

0

1

Normal operation (no boost)

20

26

32

Table 4-L. Internal Rx Termination Select

RT1

RT0

INTERNAL RECEIVE

(CCR5.1)

(CCR5.0)

TERMINATION CONFIGURATION

Internal receive-side termination disabled

0

1

0

1

0

1

Internal receive-side 120Ω enabled

Internal receive-side 100Ω enabled

Internal receive-side 75Ω enabled

22 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

CCR6 (05H): Common Control Register 6

(MSB)

(LSB)

LLB

RLB

ARLBE

ALB

RJAB

ECRS2

FUNCTION

ECRS1

ECRS0

NAME

POSITION

Local Loopback. In local loopback, transmit data is looped back to the receive path, passing

through the jitter attenuator if it is enabled. Data in the transmit path acts as normal. See

Section 6.2 for details.

LLB

RLB

CCR6.7

CCR6.6

0 = loopback disabled

1 = loopback enabled

Remote Loopback. In remote loopback, data output from the clock/data recovery circuitry is

looped back to the transmit path, passing through the jitter attenuator if it is enabled. Data in

the receive path acts as normal, while data presented at TPOS and TNEG is ignored. See

Section 6.2 for details.

0 = loopback disabled

1 = loopback enabled

Automatic Remote Loopback Enable and Reset. When this bit is set high, the device

automatically goes into remote loopback when it detects loop-up code programmed into the

receive loop-up code definition registers (RUPCD1 and RUPCD2) for a minimum of 5

seconds; it also sets the RIR2.1 status bit. Once it is in an RLB state, the bit remains in this

state until it has detected the loop code programmed into the receive loop-down code

definition registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds, at which point it

forces the device out of RLB and clears RIR2.1. Toggling this bit from 1 to 0 resets the

automatic RLB circuitry. The action of the automatic remote loopback circuitry is logically

ORed with the RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).

Analog Loopback. In analog loopback, signals at TTIP and TRING are internally connected to

RTIP and RRING. The incoming line signals at RTIP and RRING are ignored. The signals at

TTIP and TRING are transmitted as normal. See Section 6.2 for more details.

0 = loopback disabled

ARLBE

CCR6.5

ALB

CCR6.4

CCR6.3

1 = loopback enabled

RCLK Jitter Attenuator Bypass. This control bit allows the receive-recovered clock and data to

bypass the jitter attenuation, while still allowing the BPCLK output to use the jitter attenuator.

See Section 7.3 for details.

RJAB

0 = disabled

1 = enabled

ECRS2

ECRS1

ECRS0

CCR6.2

CCR6.1

CCR6.0

Error Count Register Select 2. See Section 6.4 for details.

Error Count Register Select 1. See Section 6.4 for details.

Error Count Register Select 0. See Section 6.4 for details.

5. STATUS REGISTERS

The three registers that contain information about the device’s real-time status are the status register (SR) and

receive information registers 1 and 2 (RIR1/RIR2). When a particular event has occurred (or is occurring), the

appropriate bit in one of these registers is set to 1. Some bits in SR, RIR1, and RIR2 are latched bits and some are

real-time bits (denoted in the following register descriptions). For latched status bits, when an event or an alarm

occurs, the bit is set to 1 and remains set until the user reads that bit. The bit is cleared when it is read, and it is not

set until the event has occurred again. Two of the latched status bits (RUA1 and RCL) remain set after reading if

the alarm is still present.

The user always precedes a read of any of the three status registers with a write. The byte written to the register

informs the DS21448 which bits the user wishes to read and have cleared. The user writes a byte to one of these

registers with a 1 in the bit positions to be read and a 0 in the other bit positions. When a 1 is written to a bit

location, that location is updated with the latest information. When a 0 is written to a bit position, that bit position is

not updated, and the previous value is held. A write to the status and information registers is immediately followed

by a read of the same register. The read result should be logically ANDed with the mask byte that was just written,

and this value should be written back into the same register to ensure that bit does indeed clear. This second write

step is necessary because the alarms and events in the status registers occur asynchronously with respect to their

access through the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor

to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the

DS21448 with higher-order software languages.

23 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

The bits in the SR register have the unique ability to initiate a hardware interrupt through the INT output pin. Each

of the alarms and events in the SR can be either masked or unmasked from the interrupt pin through the interrupt

mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in the SR act differently than the

interrupts caused by the other status bits in the SR. The RCL, RUA1, and LOTC bits forces the INT pin low

whenever they change state (i.e., go active or inactive). The INT pin is allowed to return high (if no other interrupts

are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.

The other status bits in the SR can force the INT pin low when they are set. The INT pin is allowed to return high (if

no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.

The host can quickly determine which of the four LIU channels is generating an interrupt by reading one of the

unused addresses in the 16h–1Fh range in any LIU channel. See the following LIU channel interrupt status

description for additional information.

LIU Channel Interrupt Status

(MSB)

(LSB)

—

LIU4

FUNCTION

LIU3

LIU2

LIU1

NAME

N/A

POSITION

7

6

5

4

Not Assigned. Could be any value when read.

N/A

LIU4 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 4 is

asserting an interrupt.

LIU4

LIU3

LIU2

LIU1

3

2

1

0

LIU3 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 3 is

asserting an interrupt.

LIU2 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 2 is

asserting an interrupt.

LIU1 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 1 is

asserting an interrupt.

SR (06H): Status Register

(MSB)

(LSB)

LUP

LDN

LOTC

RUA1

RCL

FUNCTION

TCLE

TOCD

PRBSD

NAME

LUP

POSITION

Loop-Up Code Detected. This bit is set when the loop-up code defined in registers RUPCD1 and

RUPCD2 is being received. See Section 6.1 for details.

SR.7

(Latched)

LDN

Loop-Down Code Detected. This bit is set when the loop-down code defined in registers

RDNCD1 and RDNCD2 is being received. See Section 6.1 for details.

Loss-of-Transmit Clock. This bit is set when the TCLK pin has not transitioned for 5µs (±2µs),

forcing the LOTC pin high.

SR.6

SR.5

SR.4

SR.3

SR.2

SR.1

(Latched)

LOTC

(Real Time)

RUA1

Receive Unframed All Ones. This bit is set when an unframed all-ones code is received at RRING

and RTIP (Table 5-A).

(Latched)

RCL

Receive Carrier Loss. This bit is set when an RCL condition exists at RRING and RTIP. See

(Table 5-A) for details.

(Latched)

TCLE

Transmit Current-Limit Exceeded. This bit is set when the 50mA (RMS) current limiter is activated

whether or not the current limiter is enabled.

(Real Time)

TOCD

Transmit Open-Circuit Detect. This bit is set when the device detects that the TTIP and TRING

outputs are open circuited.

(Real Time)

PRBSD

PRBS Detect. This bit is set when the receive side detects a 2¹⁵- 1 (E1) or a QRSS (T1)

pseudorandom bit sequence (PRBS).

SR.0

(Real Time)

24 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 5-A. Received Alarm Criteria

ALARM

E1/T1

SET CRITERIA

CLEAR CRITERIA

RUA1

E1

Fewer than two 0s in two frames (512 bits)

Over a 3ms window, five or fewer 0s are

received.

255 (or 2048) consecutive 0s received

(G.775) (Note 2)

More than two 0s in two frames (512 bits)

Over a 3ms window, six or more 0s are

received.

RUA1

T1

RCL

In 255-bit times, at least 32 1s are

received.

E1

(Note 1)

14 or more 1s out of 112 possible bit

positions are received, starting with the

first 1 received.

RCL

192 (or 1544) consecutive 0s are received

(Note 2)

T1

(Note 1)

Note 1: RCL is also known as a loss of signal (LOS) or Red Alarm in T1.

Note 2: See CCR1.5 for details.

IMR (07H): Interrupt Mask Register

(MSB)

(LSB)

LUP

NAME

LUP

LDN

POSITION

IMR.7

LOTC

RUA1

RCL

TCLE

FUNCTION

TOCD

PRBSD

Loop-Up Code Detected

0 = interrupt masked

1 = interrupt enabled

Loop-Down Code Detected

0 = interrupt masked

1 = interrupt enabled

Loss-of-Transmit Clock

0 = interrupt masked

1 = interrupt enabled

Receive Unframed All Ones

0 = interrupt masked

1 = interrupt enabled

Receive Carrier Loss

0 = interrupt masked

1 = interrupt enabled

Transmit Current-Limiter Exceeded

0 = interrupt masked

1 = interrupt enabled

Transmit Open-Circuit Detect

0 = interrupt masked

1 = interrupt enabled

PRBS Detection

LDN

LOTC

RUA1

RCL

IMR.6

IMR.5

IMR.4

IMR.3

IMR.2

IMR.1

IMR.0

TCLE

TOCD

PRBSD

0 = interrupt masked

1 = interrupt enabled

25 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

RIR1 (08H): Receive Information Register 1

(MSB)

(LSB)

ZD

16ZD

HBD

RCLC

RUA1C

JALT

—

NAME

POSITION

RIR1.7

FUNCTION

Zero Detect. This bit is set when a string of at least four (ETS = 0) or eight (ETS = 1)

ZD

consecutive 0s (regardless of the length of the string) have been received. This bit is cleared

when read.

16 Zero Detect. This is set when at least 16 consecutive 0s (regardless of the length of the

string) have been received. This bit is cleared when read.

(Latched)

16ZD

RIR1.6

RIR1.5

(latched)

HDB3/B8ZS Word Detect. This is set when an HDB3 (ETS = 0) or B8ZS (ETS = 1) codeword

is detected independently of the receive HDB3/B8ZS mode (CCR4.6) being enabled. This bit

is cleared when read. It is useful for automatically setting the line coding.

RCL Clear. Set when the RCL alarm has met the clear criteria defined in Table 5-A. This bit

is cleared when read.

HBD

(Latched)

RCLC

RIR1.4

RIR1.3

(Latched)

RUA1C

Receive Unframed All-Ones Clear. This bit is set when the unframed all-ones signal is no

longer detected. This bit is cleared when read (Table 5-A).

(Latched)

Jitter Attenuator Limit Trip. This bit is set when the jitter attenuator FIFO reaches within 4 bits

of its useful limit. This bit is cleared when read and is useful for debugging jitter attenuation

operation.

JALT

RIR1.2

(Latched)

N/A

RIR1.1

RIR1.0

Not Assigned. Could be any value when read.

RIR2 (09H): Receive Information Register 2

(MSB)

(LSB)

RL3

RL2

RL1

RL0

—

ARLB

SEC

NAME

POSITION

FUNCTION

RL3

(Real Time)

RL2

RIR2.7

Receive Level Bit 3 (Table 5-B)

Receive Level Bit 2 (Table 5-B)

Receive Level Bit 1 (Table 5-B)

Receive Level Bit 0 (Table 5-B)

RIR2.6

RIR2.5

RIR2.4

(Real Time)

RL1

(Real Time)

RL0

(Real Time)

N/A

RIR2.3

RIR2.2

Not Assigned. Could be any value when read.

N/A

Automatic Remote Loopback Detected. This bit is set to 1 when the automatic remote

loopback circuitry has detected the presence of a loop-up code for 5 seconds. It remains set

until the automatic RLB circuitry has detected the loop-down code for 5 seconds. See

Section 11 for more details. This bit is forced low when the automatic RLB circuitry is

disabled (CCR6.5 = 0).

One-Second Timer. This bit is set to 1 on one-second boundaries as timed by the device,

based on the RCLK. It is cleared when read.

ARLB

RIR2.1

RIR2.0

(Real Time)

SEC

(Latched)

26 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 5-B. Receive Level Indication

RL3

0

RL2

0

RL1

0

RL0

0

RECEIVE LEVEL (dB)

Greater than -2.5

-2.5 to -5.0

0

1

0

1

0

-5.0 to -7.5

0

1

-7.5 to -10.0

0

1

0

-10.0 to -12.5

-12.5 to -15.0

-15.0 to -17.5

-17.5 to -20.0

-20.0 to -22.5

-22.5 to -25.0

-25.0 to -27.5

-27.5 to -30.0

-30.0 to -32.5

-32.5 to -35.0

-35.0 to -37.5

-37.5 to -40.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

27 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

6. DIAGNOSTICS

6.1 In-Band Loop-Code Generation and Detection

The DS21448 can generate and detect a repeating bit pattern from 1 to 8 or 16 bits in length. To transmit a pattern,

the user loads the pattern into the transmit code definition (TCD1 and TCD2) registers and selects the proper

length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register. When generating

a 1-, 2-, 4-, 8-, or 16-bit pattern, the transmit code registers (TCD1 and TCD2) must be filled with the proper code.

Generation of a 1-, 3-, 5-, or 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern is

transmitted, as long as the TLCE control bit (CCR3.3) is enabled. For example, if the user wished to transmit the

standard loop-up code for CSUs, which is a repeating pattern of ...10000100001..., then 80h would be loaded into

TCD1, and the length would set using TC1 and TC0 in the IBCC register to 5 bits.

The DS21448 can detect two separate repeating patterns to allow for a loop-up code and a loop-down code to be

detected. The user programs the codes in the receive-up code definition (RUPCD1 and RUPCD2) registers and the

receive-down code definition (RDNCD1 and RDNCD2) registers; the length of each pattern is selected through the

IBCC register. The DS21448 detects repeating pattern codes with bit-error rates as high as 1 x 10^-2. The code

detector has a nominal integration period of 48ms, so after approximately 48ms of receiving either code, the proper

status bit (LUP at SR.7 and LDN at SR.6) is set to 1. Normally codes are sent for a period of 5 seconds. It is

recommended that the software poll the DS21448 every 100ms to 1000ms until 5 seconds has elapsed to ensure

the code is continuously present.

IBCC (0AH): In-Band Code Control Register

(MSB)

(LSB)

TC1

TC0

RUP2

RUP1

RUP0

RDN2

RDN1

RDN0

NAME

POSITION

FUNCTION

TC1

IBCC.7

IBCC.6

IBCC.5

IBCC.4

IBCC.3

IBCC.2

IBCC.1

IBCC.0

Transmit Code Length Definition Bit 1 (Table 6-A)

Transmit Code Length Definition Bit 0. (Table 6-A)

TC0

RUP2

RUP1

RUP0

RDN2

RDN1

RDN0

Receive Up Code Length Definition Bit 2 (Table 6-B)

D0

Receive-Up Code Length Definition Bit 1 (Table 6-B)

Receive-Up Code Length Definition Bit 0 (Table 6-B)

Receive-Down Code Length Definition Bit 2 (Table 6-B)

Receive-Down Code Length Definition Bit 1 (Table 6-B)

Receive-Down Code Length Definition Bit 0 (Table 6-B)

28 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 6-A. Transmit Code Length

LENGTH SELECTED

TC1

TC0

(BITS)

0

1

0

1

0

1

5

6/3

7

16/8/4/2/1

Table 6-B. Receive Code Length

LENGTH SELECTED

RUP2/RDN2

RUP1/RDN1

RUP0/RDN0

(BITS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

16/8

TCD1 (0BH): Transmit Code Definition Register 1

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

NAME

C7

POSITION

TCD1.7

TCD1.6

TCD1.5

TCD1.4

TCD1.3

TCD1.2

TCD1.1

TCD1.0

FUNCTION

Transmit Code Definition Bit 7. First bit of the repeating pattern.

Transmit Code Definition Bit 6

C6

C5

Transmit Code Definition Bit 5

C4

Transmit Code Definition Bit 4

Transmit Code Definition Bit 3

C3

C2

Transmit Code Definition Bit 2. A don’t care if a 5-bit length is selected.

Transmit Code Definition Bit 1. A don’t care if a 5-bit or 6-bit length is selected.

Transmit Code Definition Bit 0. A don’t care if a 5-, 6-, or 7-bit length is selected.

C1

C0

TCD2 (0CH): Transmit Code Definition Register 2

(MSB)

(LSB)

C15

C14

C13

C12

C11

FUNCTION

C10

C9

C8

NAME

C15

C14

C13

C12

C11

C10

C9

POSITION

TCD2.7

TCD2.6

TCD2.5

TCD2.4

TCD2.3

TCD2.2

TCD2.1

TCD2.0

Transmit Code Definition Bit 15

Transmit Code Definition Bit 14

Transmit Code Definition Bit 13

Transmit Code Definition Bit 12

Transmit Code Definition Bit 11

Transmit Code Definition Bit 10

Transmit Code Definition Bit 9

Transmit Code Definition Bit 8

C8

29 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

RUPCD1 (0DH): Receive-Up Code Definition Register 1

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

NAME

C7

POSITION

RUPCD1.7

RUPCD1.6

RUPCD1.5

RUPCD1.4

RUPCD1.3

RUPCD1.2

RUPCD1.1

RUPCD1.0

FUNCTION

Receive-Up Code Definition Bit 7. First bit of the repeating pattern.

C6

Receive-Up Code Definition Bit 6. A don’t care if a 1-bit length is selected.

Receive-Up Code Definition Bit 5. A don’t care if a 1-bit or 2-bit length is selected.

Receive-Up Code Definition Bit 4. A don’t care if a 1-bit to 3-bit length is selected.

Receive-Up Code Definition Bit 3. A don’t care if a 1-bit to 4-bit length is selected.

Receive-Up Code Definition Bit 2. A don’t care if a 1-bit to 5-bit length is selected.

Receive-Up Code Definition Bit 1. A don’t care if a 1-bit to 6-bit length is selected.

Receive-Up Code Definition Bit 0. A don’t care if a 1-bit to 7-bit length is selected.

C5

C4

C3

C2

C1

C0

RUPCD2 (0EH): Receive-Up Code Definition Register 2

(MSB)

(LSB)

C15

C14

C13

C12

C11

FUNCTION

C10

C9

C8

NAME

C15

C14

C13

C12

C11

C10

C9

POSITION

RUPCD2.7

RUPCD2.6

RUPCD2.5

RUPCD2.4

RUPCD2.3

RUPCD2.2

RUPCD2.1

RUPCD2.0

Receive-Up Code Definition Bit 15

Receive-Up Code Definition Bit 14

Receive-Up Code Definition Bit 13

Receive-Up Code Definition Bit 12

Receive-Up Code Definition Bit 11

Receive-Up Code Definition Bit 10

Receive-Up Code Definition Bit 9

Receive-Up Code Definition Bit 8

C8

RDNCD1 (0FH): Receive-Down Code Definition Register 1

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

NAME

C7

POSITION

RDNCD1.7

RDNCD1.6

RDNCD1.5

RDNCD1.4

RDNCD1.3

RDNCD1.2

RDNCD1.1

RDNCD1.0

FUNCTION

Receive-Down Code Definition Bit 7. First bit of the repeating pattern.

C6

Receive-Down Code Definition Bit 6. A don’t care if a 1-bit length is selected.

Receive-Down Code Definition Bit 5. A don’t care if a 1-bit or 2-bit length is selected.

Receive-Down Code Definition Bit 4. A don’t care if a 1-bit to 3-bit length is selected.

Receive-Down Code Definition Bit 3. A don’t care if a 1-bit to 4-bit length is selected.

Receive-Down Code Definition Bit 2. A don’t care if a 1-bit to 5-bit length is selected.

Receive-Down Code Definition Bit 1. A don’t care if a 1-bit to 6-bit length is selected.

Receive-Down Code Definition Bit 0. A don’t care if a 1-bit to 7-bit length is selected.

C5

C4

C3

C2

C1

C0

RDNCD2 (10H): Receive-Down Code Definition Register 2

(MSB)

(LSB)

C15

C14

C13

C12

C11

FUNCTION

C10

C9

C8

NAME

C15

C14

C13

C12

C11

C10

C9

POSITION

RDNCD2.7

RDNCD2.6

RDNCD2.5

RDNCD2.4

RDNCD2.3

RDNCD2.2

RDNCD2.1

RDNCD2.0

Receive-Down Code Definition Bit 15

Receive-Down Code Definition Bit 14

Receive-Down Code Definition Bit 13

Receive-Down Code Definition Bit 12

Receive-Down Code Definition Bit 11

Receive-Down Code Definition Bit 10

Receive-Down Code Definition Bit 9

Receive-Down Code Definition Bit 8

C8

30 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

6.2 Loopbacks

6.2.1 Remote Loopback (RLB)

When RLB (CCR6.6) is enabled, the DS21448 is placed into remote loopback. In this loopback, data from the

clock/data recovery state machine is looped back to the transmit path, passing through the jitter attenuator if it is

enabled. The data at the RPOS and RNEG pins is valid, while data presented at TPOS and TNEG is ignored. See

Figure 1-1 for more details.

If the automatic RLB enable (CCR6.5) is set to 1, the DS21448 automatically goes into remote loopback when it

detects the loop-up code programmed in the receive-up code definition registers (RUPCD1 and RUPCD2) for a

minimum of 5 seconds. When the DS21448 detects the loop-down code programmed in the receive loop-down

code definition registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds, the DS21448 comes out of remote

loopback. Setting ARLBE to 0 can also disable the ARLB.

6.2.2 Local Loopback (LLB)

When LLB (CCR6.7) is set to 1, the DS21448 is placed into local loopback. In this loopback, data on the transmit

side is transmitted as normal. TCLK and TPOS/TNEG pass through the jitter attenuator (if enabled) and are output

at RCLK and RPOS/RNEG. Incoming data from the line at RTIP and RRING is ignored. If transmit unframed all

ones (CCR3.7) is set to 1 while in LLB, TTIP and TRING transmit all ones while TCLK and TPOS/TNEG are looped

back to RCLK and RPOS/RNEG. See Figure 1-1 for more details.

6.2.3 Analog Loopback (LLB)

Setting ALB (CCR6.4) to 1 puts the DS21448 in analog loopback. Signals at TTIP and TRING are internally

connected to RTIP and RRING. The incoming signals at RTIP and RRING are ignored. The signals at TTIP and

TRING are transmitted as normal. See Figure 1-1 for more details.

6.2.4 Dual Loopback (DLB)

Setting CCR6.7 and CCR6.6 (LLB and RLB, respectively) to 1 puts the DS21448 into dual loopback operation. The

TCLK and TPOS/TNEG signals are looped back through the jitter attenuator (if enabled) and output at RCLK and

RPOS/RNEG. Clock and data recovered from RTIP and RRING are looped back to the transmit side and output at

TTIP and TRING. This mode of operation is not available when implementing hardware operation. See Figure 1-1

more details.

6.3 PRBS Generation and Detection

Setting TPRBSE (CCR3.4) = 1 enables the DS21448 to transmit a 2¹⁵- 1 (E1) or a QRSS (T1) PRBS, depending

on the ETS bit setting in CCR1.7. The DS21448’s receive side always searches for these PRBS patterns

independently of CCR3.4. The PRBS bit-error output (PBEO) remains high until the receiver has synchronized to

one of the two patterns (64 bits received without an error), at which time PBEO goes low, and the PRBSD bit in the

SR is set. Once synchronized, any bit errors received cause a positive-going pulse at PBEO, synchronous with

RCLK. This output can be used with external circuitry track bit-error rates during the PRBS testing. Setting CCR6.2

(ECRS2) = 1 allows the PRBS errors to be accumulated in the 16-bit counter in registers ECR1 and ECR2. The

PRBS synchronizer remains in sync until it experiences six bit errors or more within a 64-bit span. Both PRBS

patterns comply with the ITU-T O.151 specifications.

6.4 Error Counter

Error count register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a user-

selectable 16-bit counter that records incoming errors, including BPVs, code violations (CVs), excessive zero

violations (EXZs), and/or PRBS errors. See Table 6-C, Table 6-D, and Figure 1-2 for details.

31 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 6-C. Definition of Received Errors

ERROR

E1 OR T1

DEFINITION OF RECEIVED ERRORS

Two consecutive marks with the same polarity. Ignores BPVs because of HDB3 and B8ZS zero

suppression when CCR2.3 = 0. Typically used with AMI coding (CCR2.3 = 1). ITU-T O.161.

When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two consecutive BPVs with the same

polarity. ITU-T O.161.

BPV

E1/T1

CV

E1

EXZ

When four or more consecutive zeros are detected.

When receiving AMI-coded signals (CCR2.3 = 1), detection of 16 or more 0s or a BPV. ANSI T1.403

1999.

EXZ

T1

When receiving B8ZS-coded signals (CCR2.3 = 0), detection of eight or more 0s or a BPV. ANSI

T1.403 1999.

PRBS

E1/T1

A bit error in a received PRBS pattern. See Section 6.3 for details. ITU-T O.151.

Table 6-D. Function of ECRS Bits and RNEG Pin

E1 or T1

ECRS2

ECRS1

ECRS0

RHBE

FUNCTION OF ECR COUNTERS/RNEG

(CCR1.7)

(CCR6.2)

(CCR6.1)

(CCR6.0)

(CCR2.3)

(Note 1)

CVs

0

1

X

0

1

0

1

0

1

0

1

0

1

X

0

BPVs (HDB3 codewords not counted)

CVs + EXZs

1

BPVs + EXZs

X

BPVs (B8ZS codewords not counted)

BPVs + 8 EXZs

0

1

BPVs

1

BPVs + 16 EXZs

X

PRBS Errors (Note 2)

Note 1: RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).

Note 2: PRBS errors are always output at PBEO, independent of ECR control bits and NRZ mode, and are not present at RNEG.

6.5 Error Counter Update

A 0-to-1 transition of the ECUE (CCR1.4) control bit updates the ECR registers with the current values and resets

the counters. ECUE must be set back to 0 and another 0-to-1 transition must occur for subsequent reads/resets of

the ECR registers. Note that the DS21448 can report errors at RNEG when in NRZ mode (CCR1.6 = 1) by

outputting a pulse for each error occurrence. The counter saturates at 65,535 and does not roll over.

ECR1 (11H): Upper Error Count Register 1/ECR2 (12H): Lower Error Count Register 2

(MSB)

E15

(LSB)

E8

E0

E14

E6

E13

E5

E12

E4

E11

E3

E10

E2

E9

E1

ECR1

ECR2

E7

NAME

E15

E0

POSITION

ECR1.7

ECR2.0

FUNCTION

MSB of the 16-bit error count.

LSB of the 16-bit error count.

6.6 Error Insertion

When IBPV (CCR3.1) is transitioned from 0 to 1, the device waits for the next occurrence of three consecutive 1s

to insert a BPV. IBPV must be cleared and set again for another BPV error insertion. See Figure 1-3 for details on

the insertion of the BPV into the data stream.

When IBE (CCR3.0) is transitioned from 0 to 1, the device inserts a logic error. IBE must be cleared and set again

for another logic error insertion. See Figure 1-2 and Figure 1-3 for details about the logic error insertion into the

data steam.

32 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

7. ANALOG INTERFACE

7.1 Receiver

The DS21448 contains a digital clock recovery system. The DS21448 couples to the receive E1 or T1 twisted pair

(or coaxial cable in 75Ω E1 applications) through a 1:1 transformer. See Table 7-C for transformer details.

Figure 7-1, Figure 7-2, Figure 7-3, and Table 4-L show the receive termination requirements. The DS21448 has the

option of using internal termination resistors.

The DS21448 is designed to be fully software selectable for E1 and T1 without the need to change any external

resistors for the receive side. The receive side allows user configuration for 75Ω, 100Ω, or 120Ω receive

termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When using the internal termination feature, the

R_rresistors should be 60Ω each. See Figure 7-1 for details. If external termination is required, RT1 and RT0 should

be set to 0, and both R_rresistors (Figure 7-1) should be 37.5Ω, 50Ω, or 60Ω each, depending on the line

impedance.

The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in Figure 1-1) is internally multiplied by 16

through another internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from

the PLL circuit to form a 16-times oversampler used to recover the clock and data. This oversampling technique

offers outstanding performance to meet jitter tolerance specifications, as shown in Figure 7-7.

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS

waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and RRING, an RCL

condition occurs, and the RCLK is derived from the JACLK source. See Figure 1-1 for more details. If the jitter

attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK

to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the

RCLK output can exhibit slightly shorter high cycles of the clock. This is because of the highly oversampled digital

clock recovery circuitry. See the receive-side AC timing characteristics in Section 10 for more details.

The receive-side circuitry also contains a clock synthesizer that outputs a user-configurable clock (up to

16.384MHz) synthesized from RCLK at BPCLK (pin 31). See Table 4-J for details about output clock frequencies at

BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.

The DS21448 has a bypass mode for the receive-side clock and data. This allows the BPCLK to be derived from

RCLK after the jitter attenuator, while the clock and data presented at RCLK, RPOS, and RNEG go unaltered. This

is intended for applications where the receive-side jitter attenuation is done after the LIU. Setting RJAB (CCR6.3) to

logic 1 enables the bypass. Ensure the jitter attenuator is in the receive path (CCR4.3 = 0). See Figure 1-1 for more

details.

The DS21448 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in the

receive information register 2. This feature is helpful when troubleshooting line performance problems (Table 5-B).

E1 and T1 monitor applications require various flat-gain settings for the receive-side circuitry. The DS21448 can be

programmed to support these applications through the monitor mode control bits MM1 and MM0. When the monitor

modes are enabled, the receiver tolerates normal line loss up to -6dB (Table 4-K).

7.2 Transmitter

The DS21448 uses a set of laser-trimmed delay lines with a precision digital-to-analog converter (DAC) to create

the waveforms that are transmitted onto the E1 or T1 line. The waveforms meet the latest ETSI, ITU, ANSI, and

AT&T specifications. The user selects which waveform to generate by setting the ETS bit (CCR1.7) for E1 or T1

operation, then programming the L2/L1/L0 bits in common control register 4 for the appropriate application. See

Table 7-A and Table 7-B for the proper L2/L1/L0 settings.

A 2.048MHz or 1.544MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG. ITU

specification G.703 requires ±50ppm accuracy for T1 and E1. TR62411 and ANSI specs require ±32ppm accuracy

for T1 interfaces. The clock can be sourced internally by RCLK or JACLK. See CCR1.2, CCR1.1, CCR1.0, and

Figure 1-3 for details. Because of the transmitter’s design, very little jitter (less than 0.005UI_P-Pbroadband from

33 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms created are independent of the duty

cycle of TCLK. The transmitter couples to the E1 or T1 transmit-twisted pair (or coaxial cable in some E1

applications) through a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer

used must meet the specifications listed in Table 7-C.

The DS21448 has an automatic short-circuit limiter that limits the source current to 50mA (RMS) into a 1Ω load.

This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is activated, TCLE

(SR.2) is set even if the short-circuit limiter is disabled. The TPD bit (CCR4.0) powers down the transmit-line driver

and tri-states the TTIP and TRING pins. The DS21448 can also detect when the TTIP or TRING outputs are open

circuited. When an open circuit is detected, TOCD (SR.1) is set.

7.3 Jitter Attenuator

The DS21448 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the

JABDS bit (CCR4.2). The 128-bit mode is used in applications where large excursions of wander are expected.

The 32-bit mode is used in delay-sensitive applications. Figure 7-8 shows the attenuation characteristics. The jitter

attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS

bit (CCR4.3). Also, setting the DJA bit (CCR4.1) can disable the jitter attenuator (in effect, remove it). For the jitter

attenuator to operate properly, a 2.048MHz or 1.544MHz clock must be applied at MCLK. ITU specification G.703

requires ±50ppm accuracy for T1 and E1. TR62411 and ANSI specs require ±32ppm accuracy for T1 interfaces.

An on-board PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate for T1 applications.

Setting JAMUX (CCR1.3) to logic 0 bypasses this PLL. On-board circuitry adjusts either the recovered clock from

the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used

to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if

the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UI_P-P(buffer depth is 128

bits) or 28UI_P-P(buffer depth is 32 bits), the DS21448 divides the internal nominal 32.768MHz (E1) or 24.704MHz

(T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides

by either 15 or 17, it also sets the JALT bit in the receive information register 1 (RIR1).

7.4 G.703 Synchronization Signal

The DS21448 can receive a 2.048MHz square-wave synchronization clock, as specified in Section 10 of ITU

G.703. To use the DS21448 in this mode, set the receive-synchronization-clock enable (CCR5.3) = 1. The

DS21448 can also transmit the 2.048MHz square-wave synchronization clock, as specified in Section 10 of G.703.

To transmit the 2.048MHz clock, set the transmit-synchronization-clock enable (CCR5.2) = 1.

Table 7-A. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)

L2

0

L1

0

L0

0

APPLICATION

75Ω normal

N

RETURN LOSS

N.M.

R_t(Ω)

0

1:2

0

1

N.M.

0

120Ω normal

1

0

1

21dB

6.2

11.6

75Ω with high return loss

120Ω with high return loss

Table 7-B. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)

L2

0

L1

0

L0

0

APPLICATION

DSX-1 (0 to 133ft)/0dB CSU

DSX-1 (133 to 266f)

DSX-1 (266 to 399ft)

DSX-1 (399 to 533ft)

DSX-1 (533 to 655ft)

-7.5dB CSU

N

RETURN LOSS

N.M.

R_t(Ω)

1:2

0

1

N.M.

0

1

0

N.M.

0

1

N.M.

1

0

N.M.

1

0

1

N.M.

1

0

-15dB CSU

N.M.

1

-22.5dB CSU

N.M.

Note: See Figure 7-1, Figure 7-2, and Figure 7-3.

N.M. = Not meaningful.

34 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 7-C. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) Using Alternate

Transformer Configuration

L2

0

L1

0

L0

0

APPLICATION

75Ω normal

N

RETURN LOSS

N.M.

R_t(Ω)

0

0.8:1:1CT

0

1

N.M.

0

120Ω normal

1

0

1

21dB

11.6

75Ω with high return loss

120Ω with high return loss

Note: See Figure 7-4.

Table 7-D. Transformer Specifications (3.3V Operation)

SPECIFICATION

RECOMMENDED VALUE

1:1 (receive) and 1:2 (transmit) ±2%

600µH (min)

Turns Ratio

Primary Inductance

Leakage Inductance

1.0µH (max)

Interwinding Capacitance

40pF (max)

TRANSMIT TRANSFORMER DC RESISTANCE

1.0Ω (max)

1.5Ω (max)

Primary (Device Side)

Secondary

RECEIVE TRANSFORMER DC RESISTANCE

Primary (Device Side)

Secondary

1.2Ω (max)

35 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-1. Basic Interface

V_DD

R

0.1µF

t

TTIP

V_DD

TRANSMIT LINE

1.0µF

(NONPOLARIZED)

+

TRING

V_SS

68µF

0.01µF

R

2:1

(LARGER WINDING

TOWARD THE NETWORK)

t

Dallas

Semiconductor

DS21448

V_DD

V_SS

0.1µF

10µF

RTIP

RECEIVE LINE

RRING

1:1

R

r

2.048MHz

(THIS CAN ALSO BE 1.544MHz

FOR T1 ONLY OPERATION)

MCLK

0.1µF

NOTE 1: ALL RESISTOR VALUES ARE ±1%.

NOTE 2: IN E1 APPLICATIONS, THE R_TRESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS

(Table 7-A). NO RETURN LOSS IS REQUIRED FOR T1 APPLICATIONS.

NOTE 3: THE RR RESISTORS SHOULD EACH BE SET TO 60Ω IF THE INTERNAL RECEIVE-SIDE TERMINATION FEATURE IS ENABLED. WHEN THIS

FEATURE IS DISABLED, R_R= 37.5Ω FOR 75Ω OR 60Ω FOR 120Ω E1 SYSTEMS, OR 50Ω FOR 100Ω T1 LINES.

NOTE 4: SEE Table 7-A AND Table 7-B FOR THE APPROPRIATE TRANSMIT TRANSFORMER TURNS RATIO (N).

36 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-2. Protected Interface Using Internal Receive Termination

V_DD

R

FUSE

0.1µF

t

TTIP

V_DD

V_SS

S

TRANSMIT

LINE

1.0µF

S

(NONPOLARIZED)

+

TRING

68µF

0.01µF

R

2:1

t

Dallas

Semiconductor

(LARGER WINDING TOWARD

THE NETWORK)

DS21448

V_DD

0.1µF

10µF

V_SS

FUSE

RTIP

S

RECEIVE

LINE

S

RRING

1:1

60

2.048MHz

MCLK

(THIS CAN ALSO BE 1.544MHz

FOR T1 ONLY OPERATION)

0.1µF

NOTE 1: ALL RESISTOR VALUES ARE ±1%.

NOTE 2: S IS A SIDACTOR.

NOTE 3: THE FUSES ARE OPTIONAL TO PREVENT AC POWER LINE CROSSES FROM COMPROMISING THE TRANSFORMERS.

NOTE 4: THE R_TRESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS (Table 7-A). NO RETURN LOSS IS REQUIRED

FOR T1 APPLICATIONS.

NOTE 5: THE 68µF IS USED TO KEEP THE LOCAL POWER PLANE POTENTIAL WITHIN TOLERANCE DURING A SURGE.

NOTE 6: REFER TO APPLICATION NOTE 324 FOR SIDACTOR AND FUSE DETAILS.

37 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-3. Protected Interface Using External Receive Termination

V_DD

R

0.1µF

FUSE

t

TTIP

V_DD

V_SS

S

TRANSMIT

LINE

1.0µF

S

(NONPOLARIZED)

+

TRING

68µF

0.01µF

FUSE

R

2:1

t

Dallas

(LARGER WINDING TOWARD

THE NETWORK)

Semiconductor

DS21448

V_DD

0.1µF

10µF

470

V_SS

FUSE

RTIP

S

RECEIVE

LINE

S

RRING

1:1

R

r

2.048MHz

MCLK

(THIS CAN ALSO BE 1.544MHz

FOR T1 ONLY OPERATION)

0.1µF

NOTE 1: ALL RESISTOR VALUES ARE ±1%.

NOTE 2: S IS A SIDACTOR.

NOTE 3: THE FUSES ARE OPTIONAL TO PREVENT AC POWER LINE CROSSES FROM COMPROMISING THE TRANSFORMERS.

NOTE 4: R_r= 37.5Ω FOR 75Ω OR 60Ω FOR 120Ω E1 SYSTEMS, OR 50Ω FOR 100Ω T1 LINES.

NOTE 5: THE R_TRESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS (Table 7-A). NO RETURN LOSS IS REQUIRED FOR

T1 APPLICATIONS.

NOTE 6: THE 68µF IS USED TO KEEP THE LOCAL POWER PLANE POTENTIAL WITHIN TOLERANCE DURING A SURGE.

NOTE 7: REFER TO APPLICATION NOTE 324 FOR SIDACTOR AND FUSE DETAILS.

38 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-4. Dual Connector-Protected Interface Using Receive Termination

0.8:1:1CT

0.22µF

FUSE

UNBALANCED

LINE (75

1.6:1

S

)

Ω

V_DD

TTIP

0.1

µ

F

R

t

1.0

F

µ

L1

V_DD

0.22

F

µ

FUSE

S

2:1

S

V_SS

BALANCED LINE

(100 /120

+

TRING

RTIP

)

Ω

0.01µF

68

F

µ

FUSE

R

t

0.1

F

10 F

µ

V_DD

0.8:1:1CT

0.22

F

µ

UNBALANCED

LINE (75

V_SS

0.8:1

S

)

Ω

Dallas

Semiconductor

51.1

DS21448

S

L1

0.22

F

µ

FUSE

2.048MHz (THIS CAN ALSO

BE 1.544MHz FOR T1 ONLY

OPERATION)

MCLK

S

BALANCED LINE

(100 /120

S

1:1

)

Ω

RRING

FUSE

60

0.1

F

µ

NOTE 1: REFER TO APPLICATION NOTE 384 FOR A COMPLETE DISCUSSION OF THIS CIRCUIT.

NOTE 2: ALL RESISTOR VALUES ARE ±1%.

NOTE 3: THE FUSES ARE OPTIONAL TO PREVENT AC POWER LINE CROSSES FROM COMPROMISING THE TRANSFORMERS.

NOTE 4: S IS A SIDACTOR.

NOTE 5: THE R_TRESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS (Table 7-C). NO RETURN LOSS IS REQUIRED

FOR T1 APPLICATIONS.

NOTE 6: THE 68µF IS USED TO KEEP THE LOCAL POWER PLANE POTENTIAL WITHIN TOLERANCE DURING A SURGE.

39 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-5. E1 Transmit Pulse Template

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

269ns

G.703

TEMPLATE

194ns

219ns

-0.1

-0.2

-250

-200

-150

-100

-50

0

50

100

150

200

250

TIME (ns)

40 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-6. T1 Transmit Pulse Template

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

MAXIMUM CURVE

UI Time Amp.

MINIMUM CURVE

UI Time Amp.

-0.77 -500 0.05

-0.39 -255 0.05

-0.27 -175 0.80

-0.27 -175 1.15

-0.77 -500 -0.05

-0.23 -150 -0.05

-0.23 -150 0.50

-0.15 -100 0.95

-0.12 -75

1.15

1.05

-0.07

0.05

0.00

0

0.95

0.00

0

0.15 100

0.23 150

0.46 300

0.66 430

0.93 600

1.16 750

0.90

0.27 175

0.35 225

0.93 600

1.16 750

0.50

-0.45

-0.20

-0.05

-0.1

T1.102/87, T1.403,

CB 119 (OCT ‘79), AND

I.431 TEMPLATE

-0.2

-0.3

-0.4

-0.5

-500 -400 -300 -200 -100

0

100 200 300 400 500 600 700

TIME (ns)

41 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 7-7. Jitter Tolerance

1k

100

TR 62411 (DEC ‘90)

ITU-T G.823

DS21448 TOLERANCE

10

1

0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 7-8. Jitter Attenuation

0

ITU G.7XX

PROHIBITED AREA

TBR12

PROHIBITED

AREA

-20

-40

CURVE A

E1

T1

TR 62411 (DEC 90)

PROHIBITED AREA

CURVE B

-60

1

10

100

1k

10k

100k

FREQUENCY (Hz)

42 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Table 8-A). The DS21448

contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port

(TAP) and Boundary Scan Architecture:

Test Access Port

TAP Controller

Bypass Register

Boundary Scan Register

Device Identification Register

Instruction Register

The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in

Section 1 for details. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE

1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

Figure 8-1. JTAG Block Diagram

BOUNDRY SCAN

REGISTER

IDENTIFICATION

REGISTER

MUX

BYPASS

REGISTER

INSTRUCTION

REGISTER

TEST ACCESS PORT

SELECT

CONTROLLER

OUTPUT ENABLE

V_DD

10kΩ

JTDI

JTMS

JTCLK

JTRST

JTDO

8.1 JTAG TAP Controller State Machine

This section covers the operation of the TAP controller state machine. See Figure 8-2 for details on each of the

states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the

rising edge of JTCLK (Table 8-B).

Test-Logic-Reset. Upon power-up, the TAP controller is in test-logic-reset state. The instruction register contains

the IDCODE instruction. All system logic of the device operates normally.

Run-Test-Idle. The run-test-idle is used between scan operations or during specific tests. The instruction register

and test registers remain idle.

Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the

controller into the capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK

moves the controller to the select-IR-scan state.

43 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 8-2. TAP Controller State Diagram

Test Logic

1

Reset

0

1

Run Test/

Select

0

Idle

DR-Scan

0

IR-Scan

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

0

1

Exit DR

Exit IR

0

Pause DR

Pause IR

0

1

0

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Capture-DR. Data can be parallel-loaded into the test data registers selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register

remains at its current value. On the rising edge of JTCLK, the controller goes to the shift-DR state if JTMS is LOW,

or it goes to the exit1-DR state if JTMS is HIGH.

Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO, and

shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current

instruction is not placed in the serial path, it maintains its previous state.

Exit1-DR. While in this state, a rising edge on JTCLK puts the controller in the update-DR state, which terminates

the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the pause-

DR state.

Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current

instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising edge on

JTCLK with JTMS HIGH puts the controller in the exit2-DR state.

Exit2-DR. A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the update-DR state

and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the shift-DR state.

Update-DR. A falling edge on JTCLK while in the update-DR state latches the data from the shift register path of

the test registers into the data output latches. This prevents changes at the parallel output due to changes in the

shift register.

44 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this

state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and initiates a scan

sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the

test-logic-reset state.

Capture-IR. The capture-IR state is used to load the shift register in the instruction register with a fixed value. This

value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the

exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the shift-IR state.

Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts

data one stage for every rising edge of JTCLK toward the serial output. The parallel register and all test registers

remain at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the exit1-IR state.

A rising edge on JTCLK with JTMS LOW keeps the controller in the shift-IR state while moving data one stage

through the instruction shift register.

Exit1-IR. A rising edge on JTCLK with JTMS LOW puts the controller in the pause-IR state. If JTMS is HIGH on the

rising edge of JTCLK, the controller enters the update-IR state and terminates the scanning process.

Pause-IR. Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK

puts the controller in the exit2-IR state. The controller remains in the pause-IR state if JTMS is LOW during a rising

edge on JTCLK.

Exit2-IR. A rising edge on JTCLK with JTMS HIGH puts the controller in the update-IR state. The controller loops

back to shift-IR if JTMS is LOW during a rising edge of JTCLK in this state.

Update-IR. The instruction code shifted into the instruction shift register is latched into the parallel output on the

falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current

instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the run-test-idle state. With JTMS HIGH,

the controller enters the select-DR-scan state.

8.2 Instruction Register

The instruction register contains a shift register, as well as a latched parallel output, and is 3 bits in length. When

the TAP controller enters the shift-IR state, the instruction shift register is connected between JTDI and JTDO.

While in the shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial

output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH moves the

controller to the update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift

register to the instruction parallel output. Table 8-A shows the instructions supported by the DS21448 and its

respective operational binary codes.

Table 8-A. Instruction Codes for IEEE 1149.1 Architecture

INSTRUCTION

SAMPLE/PRELOAD

BYPASS

SELECTED REGISTER

Boundary Scan

Bypass

INSTRUCTION CODES

010

111

000

011

100

001

EXTEST

Boundary Scan

Bypass

CLAMP

HIGHZ

Bypass

Device Identification

IDCODE

SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions.

The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal

operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into

the boundary scan register through JTDI using the shift-DR state.

BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO

through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s

normal operation.

45 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

EXTEST. This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the

instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of

all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The capture-

DR samples all digital inputs into the boundary scan register.

CLAMP. All digital outputs of the device are output data from the boundary scan parallel output while connecting

the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.

HIGHZ. All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected

between JTDI and JTDO.

IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test

register is selected. The device identification code is loaded into the identification register on the rising edge of

JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially

through JTDO. During test-logic-reset, the identification code is forced into the instruction register’s parallel output.

The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and

number of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 8-B. Table 8-C lists

the device ID code for the SCT devices.

Table 8-B. ID Code Structure

MSB

LSB

Version

Device ID

16 bits

JEDEC

1

(Contact Factory)

4 bits

00010100001

Table 8-C. Device ID Codes

DEVICE

16-BIT ID

DS21448

0018

8.3 Test Registers

IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An

optional test register, the identification register, has been included with the DS21448 design. It is used with the

IDCODE instruction and the test-logic-reset state of the TAP controller.

Bypass Register

The bypass register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that

provides a short path between JTDI and JTDO.

Identification Register

The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is

selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state. See Table 8-B

and Table 8-C for more information about bit usage.

Boundary Scan Register

The boundary scan register contains a shift register path and a latched parallel output for all control cells and digital

I/O cells, and is n bits in length. See Table 8-D for all cell bit locations and definitions.

46 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 8-D. Boundary Scan Control Bits

BIT

NAME

I/O

BIT

NAME

I/O

BGA

LQFP

BGA

LQFP

54

—

64

48

46

67

22

—

44

15

3

A1

124

RTIP1

TTIP1

RTIP2

TTIP2

RTIP3

TTIP3

RTIP4

TTIP4

RRING1

TRING1

RRING2

TRING2

RRING3

TRING3

RRING4

TRING4

TVSS2

TVDD2

CS2

I

O

I

O

I

O

I

O

I

O

I

O

I

O

I

O

—

I

—

BUScntl

—

(Note 1)

A2

A4

A5

A7

A8

A10

A11

B2

B3

B5

B6

B8

B9

B11

B12

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

E1

E2

E3

E4

E9

E10

E11

E12

F1

F2

F3

6

28

38

60

71

56

42

8

23

26

—

52

58

57

2

43

11

—

33

20

—

50

53

60

41

1

G12

H1

H2

H3

H4

H9

H10

H11

H12

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

K1

K2

K3

K4

K5

K7

K8

66

92

27

127

122

88–90

76

64

65

35

91

18

7

8

109

2

85–87

78

75

62

95

A0

WR (R/W)

TNEG1

RCLK1

BPCLK1

VSS4

D6/AD6

A2

A1

I

O

—

I/O

I

—

I

O

—

I/O

I

O

I

93

102

125

9

29

41

61

74

94

105

39

SCLK

RD (DS)

CS1

TVSS1

TVDD1

MCLK

RCL/LOTC4

VDD4

D4/AD4

D7/AD7

A4

ALE (AS)

SDI

40

57

80

82

D2/AD2

D0/AD0

BPCLK2

RCL/LOTC2

VDD3

I/O

O

—

I

47

128

49–51

52–54

84

14

34

12

13

79

19–21

72

121

58

33

31

30

81

22–24

1

56

15

36

10

110

98

123

19

32

37

25

RPOS1

PBEO1

TXDIS/TEST

PBEO4

VSS3

CS3

RPOS3

TNEG3

RPOS2

RNEG2

D3/AD3

VDD2

TVSS3

PBEO3

RCLK3

TPOS3

RCLK2

TPOS2

D1/AD1

VSS2

RCL/LOTC3

BPCLK3

RNEG3

TCLK3

TPOS1

RNEG1

PBEO2

TVDD3

D5/AD5

O

I

O

39

—

INTcntl

17

16

49

—

27

63

4

O

I/O

—

O

I

(Note 2)

38

28

13

62

59

0

—

24

35

30

36

—

40

29

5

K9

K10

K11

K12

L1

L2

L3

L5

L6

97

114

16

59

63

I/O

I

O

I

INT

CS4

RPOS4

TNEG4

A3

TCLK2

JTRST

VDD1

RCL/LOTC1

BIS0

BPCLK4

HRST

43

42

I

115–117

126

107

112

106

103

96

—

O

I

O

I

—

O

I

—

I

6

7

O

I

L7

L8

L9

47

—

21

65

14

45

9

I/O

—

O

I

F4

F9

L10

L11

L12

M1

M2

M3

M4

M5

TVSS4

RCLK4

TCLK4

TNEG2

TCLK1

JTMS

F10

F11

F12

G1

G2

G3

G9

G11

113

32

17

83

26

I

12

—

18

31

—

51

11

111

73

O

—

I/O

48

118–120

44

VSS1

JTCLK

77

47 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

BIT

NAME

I/O

BIT

NAME

I/O

BGA

LQFP

BGA

LQFP

—

55

—

M6

45

JTDI

JTDO

BIS1

I

O

I

10

61

66

34

M10

25

RNEG4

ADRScntl

TPOS4

PBTS

O

—

I

M7

M8

M9

46

68

104

—

M11

M12

—

55

108

TVDD4

—

I

Note 1: 0 = Dn/ADn are inputs; 1 = Dn/ADn are outputs.

Note 2: 0 = INT is an input; 1 = INT is an output.

9. OPERATING PARAMETERS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground

Operating Temperature Range for DS21448TN

Storage Temperature Range

-1.0V to +6.0V

-40°C to +85°C

-55°C to +125°C

Soldering Temperature

See IPC/JEDEC J-STD-020 Specification

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is

not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(T_A= -40°C to +85°C)

PARAMETER

SYMBOL

V_IH

CONDITIONS

MIN

2.2

TYP

MAX

5.5

UNITS

Logic 1

V

Logic 0

V_IL

-0.3

+0.8

3.465

Supply for 3.3V Operation

V_DD

(Note 1)

3.135

3.3

CAPACITANCE

(T_A= +25°C)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

C_IN

CONDITIONS

MIN

TYP

5

MAX

UNITS

pF

C_OUT

7

pF

DC CHARACTERISTICS

(V_DD= 3.3V ±5%, T_A= -40°C to +85°C.)

PARAMETER

SYMBOL

MIN

TYP

MAX

+1.0

UNITS

µA

Input Leakage

I_IL

I_LO

(Note 2)

-1.0

Output Leakage

(Note 3)

µA

Output Current (2.4V)

Output Current (0.4V)

Supply Current at 3.3V

Power Dissipation at 3.3V

I_OH

I_OL

-1.0

mA

W

+4.0

I_DD

P_DD

(Notes 4, 5)

320

400

1.06

1.32

Note 1: Applies to V_DD

.

Note 2: 0.0V < V_IN< V_DD

.

Note 3: Applied to INT when tri-stated.

Note 4: TCLK = MCLK = 2.048MHz.

Note 5: Power dissipation with all ports active, TTIP and TRING driving a 30Ω load, for an all-ones data density.

48 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

10. AC TIMING PARAMETERS AND DIAGRAMS

Table 10-A. AC Characteristics—Multiplexed Parallel Port (BIS0 = 0)

(V_DD= 3.3V ±5%, T_A= -40°C to +85°C.) (Figure 10-1, Figure 10-2, and Figure 10-3)

PARAMETER

SYMBOL

CONDITIONS

MIN

200

100

TYP

MAX UNITS

Cycle Time

t_CYC

ns

PW_EL

PW_EH

t_R, t_F

t_RWH

t_RWS

t_CS

Pulse Width, DS Low or RD High

Pulse Width, DS High or RD Low

Input Rise/Fall Times

20

50

ns

10

50

20

0

R/W Hold Time

R/W Setup Time Before DS High

CS Setup Time Before DS, WR, or RD Active

CS Hold Time

t_CH

Read Data Hold Time

t_DHR

10

5

Write Data Hold Time

t_DHW

Muxed Address Valid to AS or ALE Fall

Muxed Address Hold Time

t_ASL

15

10

20

30

10

20

50

t_AHL

t_ASD

Delay Time DS, WR, or RD to AS or ALE Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to DS, WR, or RD

Output Data Delay Time from DS or RD

Data Setup Time

PW_ASH

t_ASED

t_DDR

80

t_DSW

Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS0 = 0)

t

CYC

ALE

PW

ASH

t

ASD

WR

RD

t

ASED

t

ASD

PW

EH

t

CH

PW

CS

EL

CS

t

ASL

t

DHR

DDR

AD0–AD7

t

AHL

49 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS0 = 0)

t

CYC

ALE

PW

ASH

t

ASD

RD

WR

t

ASED

ASD

PW

EH

t

CH

PW

EL

CS

t

ASL

DHW

AD0–AD7

t

AHL

DSW

Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS0 = 0)

PW

ASH

AS

PW

EH

t

ASED

ASD

DS

PW

EL

t

CYC

t

RWS

RWH

R/W

t

DDR

t

ASL

DHR

AD0–AD7

(READ)

t

AHL

t

CH

CS

t

DSW

t

ASL

t

AD0–AD7

(WRITE)

t

DHW

AHL

50 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 10-B. AC Characteristics—Nonmultiplexed Parallel Port (BIS0 = 1)

(V_DD= 3.3V ±5%, T_A= -40°C to +85°C.) (Figure 10-4, Figure 10-5, Figure 10-6, and Figure 10-7)

PARAMETER

Setup Time for A0 to A4, Valid to CS

Active

SYMBOL

CONDITIONS

MIN

0

TYP

MAX UNITS

t1

ns

Setup Time for CS Active to Either RD,

WR, or DS Active

t2

t3

t4

t5

t6

t7

t8

t9

0

ns

Delay Time from Either RD or DS Active

to Data Valid

75

20

ns

Hold Time from Either RD, WR, or DS

Inactive to CS Inactive

0

Hold Time from CS Inactive to Data Bus

Tri-State

5.0

75

10

Wait Time from Either WR or DS Active to

Latch Data

Data Setup Time to Either WR or DS

Inactive

Data Hold Time from Either WR or DS

Inactive

Address Hold from Either WR or DS

Inactive

Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS0 = 1)

ADDRESS VALID

A0–A4

DATA VALID

D0–D7

t5

5ns (MIN) / 20ns (MAX)

WR

CS

RD

t1

0ns (MIN)

t2

t3

t4

0ns (MIN)

75ns (MAX)

51 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS0 = 1)

ADDRESS VALID

A0–A4

D0–D7

RD

t7

t8

10ns

(MIN)

10ns

(MIN)

t1

0ns (MIN)

t2

CS

t6

t4

0ns (MIN)

75ns (MIN)

WR

Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS0 = 1)

ADDRESS VALID

A0–A4

D0–D7

R/W

DATA VALID

5ns (MIN) / 20ns (MAX)

t5

t1

0ns (MIN)

t2

CS

t3

t4

0ns (MIN)

75ns (MAX)

DS

Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS0 = 1)

ADDRESS VALID

A0–A4

D0–D7

R/W

10ns

(MIN)

10ns

(MIN)

t8

t7

t1

0ns (MIN)

t2

CS

t6

t4

0ns (MIN)

75ns (MIN)

DS

52 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 10-C. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)

(V_DD= 3.3V ±5%, T_A= -40°C to +85°C.) (Figure 10-8)

PARAMETER

Setup Time CS to SCLK

Setup Time SDI to SCLK

Hold Time SCLK to SDI

SCLK High/Low Time

SCLK Rise/Fall Time

SCLK to CS Inactive

SYMBOL

CONDITIONS

MIN

50

TYP

MAX

UNITS

ns

t_CSS

t_SSS

50

ns

t_SSH

50

ns

t_SLH

200

ns

t_SRF

50

ns

t_LSC

50

250

ns

t_CM

ns

CS Inactive Time

SCLK to SDO Valid

t_SSV

ns

SCLK to SDO Tri-State

CS Inactive to SDO Tri-State

t_SST

100

ns

t_CSH

ns

Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)

t_CM

CS

t_LSC

t_SRF

t_SLH

t_CSS

SCLK

(Note 1)

SCLK

t_SSS

LSB

t_SSH

(Note 2)

t_CSH

MSB

LSB

MSB

t_SST

SDI

t_SSV

HIGH-Z

MSB

HIGH-Z

SDO

NOTE 1: OCES =1 AND ICES = 0.

NOTE 2: OCES = 0 AND ICES = 1.

53 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 10-D. AC Characteristics—Receive Side

(V_DD= 3.3V ± 5%, T_A=-40°C to +85°C.) (Figure 10-9)

PARAMETER

SYMBOL

CONDITIONS

(Note 1)

(Note 2)

MIN

TYP

488

648

MAX

UNITS

RCLK Period

t_CP

ns

t_CH

t_CL

t_CH

t_CL

RCLK Pulse Width

(Note 3)

200

150

ns

(Note 4)

Delay RCLK to RPOS, RNEG,

PBEO, RBPV Valid

t_DD

50.0

Note 1: E1 mode.

Note 2: T1 or J1 mode.

Note 3: Jitter attenuator enabled in the receive path.

Note 4: Jitter attenuator disabled or enabled in the transmit path.

Figure 10-9. Receive-Side Timing

RCLK

(Note 1)

t

CL

CH

RCLK

(Note 2)

t

CP

t

DD

RPOS, RNEG

PBEO

BIT

ERROR

PRBS DETECTOR OUT OF SYNC

t

DD

BPV/

EXZ/

CV

BPV/

EXZ/

CV

RNEG

(Note 3)

NOTE 1: RCES = 1 (CCR2.0) OR CES = 1.

NOTE 2: RCES = 0 (CCR2.0) OR CES = 0.

NOTE 3: RNEG IS IN NRZ MODE (CCR1.6 = 1).

54 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 10-E. AC Characteristics—Transmit Side

(V_DD= 3.3V ±5%, T_A= -40°C to +85°C.) (Figure 10-10)

PARAMETER

SYMBOL

CONDITIONS

(Note 5)

(Note 6)

MIN

TYP

488

648

MAX

UNITS

TCLK Period

t_CP

ns

t_CH

t_CL

75

TCLK Pulse Width

ns

TPOS/TNEG Setup to TCLK

Falling or Rising

t_SU

20

TPOS/TNEG Hold from TCLK

t_HD

ns

Falling or Rising

TCLK Rise and Fall Times

t_R, t_F

25

Note 5: E1 mode.

Note 6: T1 or J1 mode.

Figure 10-10. Transmit-Side Timing

t

CP

t

CL

CH

t

R

F

TCLK

(Note 1)

TCLK

(Note 2)

t

SU

t

TPOS, TNEG

HD

NOTE 1: TCES = 0 (CCR2.1) OR CES = 0.

NOTE 2: TCES = 1 (CCR2.1) OR CES = 1.

55 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

11. PIN CONFIGURATIONS

11.1 144-Pin TE-PBGA

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

RTIP1

TTIP1

N.C.

RTIP2

TTIP2

N.C.

RTIP3

TTIP3

N.C.

RTIP4

TTIP4

N.C.

N.C. RRING1 TRING1

N.C. RRING2 TRING2

N.C. RRING3 TRING3

N.C. RRING4 TRING4

N.C.

BPCLK2

N.C.

VDD3

N.C.

D2/

D0/

RCL/

TVSS2 TVDD2

RPOS2 RNEG2

RCLK2 TPOS2

VSS3

RPOS3 TNEG3

CS2

CS3

AD2

AD0

LOTC2

D3/

VDD2

VSS2

N.C.

TVSS3 PEBO3 RCLK3 TPOS3

AD3

D1/

RCL/

N.C.

BPCLK3 RNEG3 TCLK3

LOTC3

AD1

D5/

G

H

J

TPOS1 RNEG1 PEBO2

N.C.

TVDD3

VSS4

N.C.

A0

A1

AD5

WR

(R/W)

D6/

A2/

TNEG1 RCLK1 BPCLK1 N.C.

N.C.

AD6

OCES

RD

(DS)

RCL/

D4/

D7/

SCLK

TVSS1 TVDD1 MCLK

VDD4

PEBO4

N.C.

CS1

LOTC4

AD4

AD7

A4/

ALE

(AS)

TXDIS/

TEST

K

L

SDI

RPOS1 PEBO1

N.C.

RPOS4 TNEG4

INT

CS4

SDO

A3/

RCL/

TCLK2 JTRST

N.C.

VDD1

BIS0 BPCLK4

TVSS4 RCLK4 TCLK4

HRST

ICES

LOTC1

M

TNEG2 TCLK1 JTMS

VSS1

JTCLK

JTDI

JTDO

BIS1

TVDD4 RNEG4 TPOS4 PBTS

56 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

11.2 128-Pin LQFP

(

TVSS4

TVDD4

TRING4

HRST

BIS0

PBTS/RT0

MCLK

100

90

80

70

A2/OCES/JAMUX

A3/ICES/DJA

A4/SD0/L0

RRING3

60

50

40

RTIP3

TNEG4

RCLK3

PBEO1

PBEO2

BPCLK4

TCLK4

/EGL2

CS2

110

BPCLK3

TPOS4

VSS3

/EGL4

CS4

VSS3

Dallas Semiconductor

VDD1

VSS3

DS21448

VDD3

VDD1

VDD3

VSS1

VDD3

VSS1

JTMS

VSS1

BPCLK2

JTDO

120

PBEO3

BPCLK1

PBEO4

JTDI

JTCLK

TCLK2

JTRST

TRING2

TVDD2

TVSS2

RTIP1

RRING1

RCL1/LOTC1

RCLK1

RCL2/LOTC2

1

10

20

30

57 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

12. PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for

each package is a link to the latest package outline information.)

12.1 144-Ball TE-PBGA (56-G6020-001)

58 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

12.2 128-Pin LQFP (56-G4011-001)

59 of 60

DS21448 3.3V T1/E1/J1 Quad Line Interface

13. THERMAL INFORMATION

Table 13-A. Thermal Characteristics—BGA

PARAMETER

MIN

TYP

MAX

+85

UNITS

°C

Ambient Temperature (Note 1)

Junction Temperature

-40

+125

°C

°C/W

+24

Theta-JA (θ_JA) in Still Air (Note 2)

Table 13-B. Theta-JA (θ ) vs. Airflow—BGA

JA

FORCED AIR (m/s)

THETA-JA (θ_JA)

24°C/W

0

1

21°C/W

2.5

19°C/W

Table 13-C. Thermal Characteristics—LQFP

PARAMETER

MIN

TYP

MAX

+85

UNITS

°C

Ambient Temperature (Note 1)

Junction Temperature

-40

+125

°C

°C/W

+27.8

+0.1

Theta-JA (θ_JA) in Still Air (Note 2)

Theta-JC (θ_JC) in Still Air (Note 3)

Table 13-D. Theta-JA (θ ) vs. Airflow—LQFP

JA

FORCED AIR (m/s)

THETA-JA (θ_JA)

27.8°C/W

0

1

23.5°C/W

2.5

21.6°C/W

Note 1: The package is mounted on a four-layer JEDEC-standard test board.

Note 2: Theta-JA (θ_JA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC-standard test board.

Note 3: While Theta-JC (θ_JC) is commonly used as the thermal parameter that provides a correlation between the junction temperature (Tj) and

the average temperature on top center of the LQFP package (TC), the proper term is Psi-JT. It is defined by: (Tj - TC) / overall package

power.

Note 4: The method of measurement for the thermal parameters is defined in the EIA/JEDEC-standard document EIA-JESD51-2.

14. REVISION HISTORY

REVISION

DESCRIPTION

042303

New product release.

Table 5-B. Receive Level Indication: Changed “-12.5 to -5.0” to “-12.5 to -15.0”. Adjusted steps

after -17.5 dB to be in -2.5dB decrements.

Section 9, Operating Parameters: Updated supply current and power dissipation values in the DC

Characteristics table to reflect latest characterization data. Updated Note 5 to show that values are for all ports

active.

012104

In the Absolute Maximum Ratings section, added range for storage temperature and changed

113004

011206

soldering temperature from IPC JEDEC J-STD-020A to J-STD-020.

Added lead-free packages to Ordering Information table.

60 of 60

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.


型号：	DS21448LN
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	3.3V E1/T1/J1 Quad Line Interface PC 电信电信集成电路
文件：	总60页 (文件大小：837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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