DS2172T+ [MAXIM]
Telecom Circuit, 1-Func, PQFP32, TQFP-32;型号: | DS2172T+ |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Telecom Circuit, 1-Func, PQFP32, TQFP-32 电信 电信集成电路 |
文件: | 总22页 (文件大小:181K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS2172
Bit Error Rate Tester (BERT)
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Generates/Detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
ꢀ Operates at speeds from DC to 52 MHz
ꢀ Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 26-1, 29-1, 211-1, 215-1, 220-1, 223-1,
and 232-1
ꢀ Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
32 31 30 29 28 27 26 25
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
1
2
3
4
5
6
7
8
24
23
22
21
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE(AS)
DS2172
32-PIN TQFP 20
19
18
17
9 10 11 12 13 14 15 16
ꢀ Large 32-bit error count and bit count
registers
ꢀ Software programmable bit error insertion
ꢀ Fully independent transmit and receive
sections
ORDERING INFORMATION
DS2172T (00 C to 700 C)
ꢀ 8-bit parallel control port
ꢀ Detects test patterns with bit error rates up to
DS2172TN (-400 C to + 850 C)
10-2
DESCRIPTION
The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates
ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns
required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the
loopback, run the test, check for errors, and finally deactivate the loopback.
The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up
to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,
Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS2172 can insert single or 10-1 to 10-7 bit errors to verify equipment operation and connectivity.
1 of 23
101000
DS2172
1.0 GENERAL OPERATION
1.1 PATTERN GENERATION
The DS2172 is programmed to generate a particular test pattern by programming the following registers:
-
-
-
-
-
Pattern Set Registers (PSR)
Pattern Length Register (PLR)
Polynomial Tap Register (PTR)
Pattern Control Register (PCR)
Error Insertion Register (EIR)
Please see Tables 4 and 5 for examples of how to program these registers in order to generate some
standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit
Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin
appearing at the TDATA pin.
1.2 PATTERN SYNCHRONIZATION
The DS2172 expects to receive the same pattern that it transmitted. The synchronizer examines the data at
RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard
synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.
In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined
in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an
all-0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by
using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are
received without error, where n is the exponent in the polynomial from table 4. Once in synchronization
(SR0. = 1) any deviation from this pattern will be counted by the Bit Error Count Register.
In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.
Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in
the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an
explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this
pattern will be counted by the Bit Error Count Register.
1.3 BER CALCULATION
Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the
bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count
Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over
the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration
period.
1.4 GENERATING ERRORS
Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the
transmitted data stream. Injecting errors allows users to stress communication links and to check the
functionality of error monitoring equipment along the path.
1.5 POWER-UP SEQUENCE
On power-up, the registers in the DS2172 will be in a random state. The user must program all the
internal registers to a known state before proper operation can be insured.
2 of 22
DS2172
DS2172 FUNCTIONAL BLOCK DIAGRAM Figure 1
RLOS
DS2172 PATTERN GENERATION BLOCK DIAGRAM Figure 2
NOTES:
1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern.
2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.
3 of 22
DS2172
DETAILED PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1
TL
I
Transmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to VSS if not used. See Figure 8 for timing information.
2
3
4
AD0
AD1
I/O
I/O
I
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
TEST
Test. Set high to 3-state all output pins ( INT , ADx, TDATA, RLOS).
Should be tied to VSS to enable all outputs.
5
6
VSS
AD2
AD3
AD4
AD5
AD6
AD7
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Signal Ground. 0.0V. Should be tied to local ground plane.
Positive Supply. 5.0V.
I/O
I/O
I/O
I/O
I/O
I/O
-
7
8
9
10
11
12
13
14
VDD
BTS
-
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
15
16
17
I
I
I
Read Input (Data Strobe).
RD (DS)
CS
Chip Select. Must be low to read or write the port.
ALE(AS)
Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.
18
19
I
Write Input (Read/Write).
WR (R/ W )
INT
O
Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.
20
21
22
VDD
VSS
LC
-
-
I
Positive Supply. 5.0V.
Signal Ground. 0.0V. Should be tied to local ground plane.
Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to VSS if not used.
23
RLOS
O
Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
4 of 22
DS2172
PIN SYMBOL TYPE DESCRIPTION
24
RL
I
Receive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to VSS if not used.
25
26
RDATA
RDIS
I
I
Receive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.
Receive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to VSS if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.
27
RCLK
I
Receive Clock. Input clock from transmission link. 0 to 52 MHz. Can be
a gapped clock. Fully independent from TCLK.
28
29
30
VDD
VSS
-
-
I
Positive Supply. 5.0V.
Signal Ground. 0.0V. Should be tied to local ground plane.
TCLK
Transmit Clock. Transmit demand clock. 0 to 52 MHz. Can be a gapped
clock. Fully independent of RCLK.
31
TDIS
I
Transmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to VSS if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.
32
TDATA
O
Transmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.
DS2172 REGISTER MAP Table 2
ADDRESS R/W
REGISTER NAME
ADDRESS R/W
REGISTER NAME
Bit Error Counter Register 3.
Bit Error Counter Register 2.
Bit Error Counter Register 1.
Bit Error Counter Register 0.
Pattern Receive Register 3.
Pattern Receive Register 2.
Pattern Receive Register 1.
Pattern Receive Register 0.
Status Register.
00
01
02
03
04
05
06
07
08
09
0A
0B
R/W Pattern Set Register 3.
R/W Pattern Set Register 2.
R/W Pattern Set Register 1.
R/W Pattern Set Register 0.
R/W Pattern Length Register.
R/W Polynomial Tap Register.
R/W Pattern Control Register.
R/W Error Insert Register.
0C
0D
0E
0F
10
11
12
13
14
15
1C
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Counter Register 3.
Bit Counter Register 2.
Bit Counter Register 1.
Bit Counter Register 0.
R/W Interrupt Mask Register.
R/W Test Register (see note 1)
NOTE:
1. The Test Register must be set to 00 hex to insure proper operation of the DS2172.
5 of 22
DS2172
2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical
Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the address
information and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or WR pulses. In a read cycle, the DS2172 outputs a byte of data during the latter
portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can
also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update counters and
load transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these
port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB)
(LSB)
PS31
PS30
PS22
PS14
PS6
PS29
PS21
PS13
PS5
PS28
PS20
PS12
PS4
PS27
PS19
PS11
PS3
PS26
PS18
PS10
PS2
PS25
PS17
PS9
PS24
PSR3 (addr.=00 Hex)
PSR2 (addr.=01 Hex)
PSR1 (addr.=02 Hex)
PSR0 (addr.=03 Hex)
PS23
PS15
PS7
PS16
PS8
PS1
PS0
4.0 PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
PLR: PATTERN LENGTH REGISTER (Address=04 Hex)
(MSB)
(LSB)
-
-
-
LB4
LB3
LB2
LB1
LB0
6 of 22
DS2172
SYMBOL
POSITION NAME AND DESCRIPTION
-
-
-
PLR1.7
PLR1.6
PLR1.5
PLR1.4
PLR1.3
PLR1.2
PLR1.1
PLR1.0
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Length Bit 4.
Length Bit 3.
Length Bit 2.
Length Bit 1.
Length Bit 0.
LB4
LB3
LB2
LB1
LB0
5.0 POLYNOMIAL TAP REGISTER
Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input of
the pattern generator. Feedback Tap B provides one of two feedback paths within the pattern generator.
Please refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for register
programming examples.
PTR: POLYNOMIAL TAP REGISTER (Address=05 Hex)
(MSB)
(LSB)
-
-
-
PT4
PT3
PT2
PT1
PT0
SYMBOL
POSITION NAME AND DESCRIPTION
-
-
-
PTR.7
PTR.6
PTR.5
PTR.4
PTR.3
PTR.2
PTR.1
PTR.0
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Polynomial Tap Bit 4.
Polynomial Tap Bit 3.
Polynomial Tap Bit 2.
PT4
PT3
PT2
PT1
PT0
Polynomial Tap Bit 1.
Polynomial Tap Bit 0.
7 of 22
DS2172
6.0 PATTERN CONTROL REGISTER
The Pattern Control Register (PCR) is used to configure the operating parameters of the DS2172 and to
control the patterns being generated and received. Also the PCR is used to control the pattern
synchronizer and the error and bit counters.
PCR: PATTERN CONTROL REGISTER (Address=06 Hex)
(MSB)
(LSB)
TL
QRSS
PS
LC
RL
SYNCE
RESYNC
LPBK
SYMBOL POSITION NAME AND DESCRIPTION
TL
PCR.7
Transmit Load. A low to high transition loads the pattern generator with
the contents of the Pattern Set Registers. PCR.7 is logically OR’ed with the
input pin TL. Must be cleared and set again for subsequent loads.
Zero Suppression Select. Forces a 1 into the pattern whenever the next 14
bit positions are all 0s. Should only be set when using the QRSS pattern.
0 = Zero suppression disabled
QRSS
PCR.6
1 = Zero suppression enabled
PS
PCR.5
PCR.4
Pattern Select.
0 = Repetitive Pattern
1 = Pseudorandom Pattern
LC
Latch Count Registers. A low to high transition latches the bit and error
counts into the user accessible registers BCR and BECR and clears the
internal register count. PCR.4 is logically OR’ed with input pin LC. Must
be cleared and set again for subsequent loads.
RL
PCR.3
Receive Data Load. A transition from low to high loads the previous
32 bits of data received at RDATA into the Pattern Receive Registers
(PRR). PCR.3 is logically OR’ed with input pin RL. Must be cleared and
set again for subsequent latches.
SYNCE
RESYNC
LPBK
PCR.2
PCR.1
PCR.0
SYNC Enable.
0 = auto resync is enabled.
1 = auto resync is disabled.
Initiate Manual Resync Process. A low to high transition will force the
DS2172 to resynchronize to the incoming pattern at RDATA. Must be
cleared and set again for a subsequent resync.
Transmit/Receive Loopback Select. When enabled, the RDATA input is
disabled; TDATA continues to output data as normal. See Figure 1.
0 = loopback disabled
1 = loopback enabled
8 of 22
DS2172
7.0 ERROR INSERT REGISTER
The Error Insertion Register (EIR) controls circuitry within the DS2172 that allows the generated pattern
to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly
programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under microcontroller
control) via the EIR.3 bit.
EIR: ERROR INSERT REGISTER (Address=07 Hex)
(MSB)
(LSB)
-
-
TINV
RINV
SBE
EIR2
EIR1
EIR0
SYMBOL POSITION NAME AND DESCRIPTION
-
-
EIR.7
EIR.6
EIR.5
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Transmit Data Inversion Select.
TINV
0 = do not invert data to be transmitted at TDATA
1 = invert data to be transmitted at TDATA
Receive Data Inversion Select.
0 = do not invert data received at RDATA
1 = invert data received at RDATA
Single Bit Error Insert. A low to high transition will create a single bit
error. Must be cleared and set again for a subsequent bit error to be
inserted. Can be used to accomplish rates not addressed in Table 3 (e.g.,
BER of less than 10-7).
RINV
SBE
EIR.4
EIR.3
EIB2
EIB1
EIB0
EIR.2
EIR.1
EIR.0
Error Insert Bit 2. See Table 3.
Error Insert Bit 1. See Table 3.
Error Insert Bit 0. See Table 3.
ERROR BIT INSERTION Table 3
EIB2
EIB1
EIB0
ERROR RATE INSERTED
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no errors automatically inserted
10-1
10-2
10-3
10-4
10-5
10-6
10-7
9 of 22
DS2172
PSEUDORANDOM PATTERN GENERATION (PCR.5=1) Table 4
PATTERN TYPE
PTR PLR PSR3 PSR2 PSR1 PSR0 TINV RINV
23 - 1
24 - 1
25 - 1
26 - 1
27 - 1
27 - 1
27 - 1
00
00
01
04
00
03
03
04
02
08
0D
02
06
02
10
01
00
11
02
02
01
02
10
02
03
04
05
06
06
06
08
09
0A
0E
10
11
13
13
14
15
16
18
1B
1C
1E
1F
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Fractional T1 LB Activate
Fractional T1 LB Deactivate
O.153 (511 type)
29 - 1
210 - 1
211 - 1
215 - 1
217 - 1
218 - 1
220 - 1
220 - 1
221 - 1
222 - 1
223 - 1
225 - 1
228 - 1
229 - 1
231 - 1
232 - 1
O.152 and O.153 (2047 type)
O.151
O.153
O.151 QRSS (PCR.6=1)
O.151
(see note below)
REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5
PATTERN TYPE
PTR PLR PSR3 PSR2 PSR1 PSR0 TINV RINV
all 1s
00
00
00
00
00
00
00
00
00
00
00
00
01
03
17
0F
07
03
04
02
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
20
FF
FF
FF
FF
FF
FF
FF
FF
FF
00
00
FF
FF
FF
FF
FF
FE
FE
FC
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
all 0s
alternating 1s and 0s
double alternating 1s and 0s
3 in 24
1 in 16
01
1 in 8
01
1 in 4
F1
F0
FC
D4 Line Loopback Activate
D4 Line Loopback Deactivate
10 of 22
DS2172
NOTES FOR TABLES 4 AND 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 232 -1 pattern, the random pattern actually repeats every (4093 x 220) + 1046529 bits instead of
232 - 1.
8.0 BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS2172 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
BIT COUNT REGISTERS
(MSB)
(LSB)
BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24
BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
BC15 BC14 BC13 BC12 BC11 BC10
BC7 BC6 BC5 BC4 BC3 BC2
BC9
BC1
BC8
BC0
9.0 BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS2172 latches the bit error count
into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input
pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by an
external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
(MSB)
(LSB)
BECR3 (addr.=0C Hex)
BECR2 (addr.=0D Hex)
BECR1 (addr.=0E Hex)
BECR0 (addr.=0F Hex)
BEC31 BEC30 BEC29 BEC28 BEC27 BEC26 BEC25 BEC24
BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16
BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9
BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1
BEC8
BEC0
11 of 22
DS2172
10.0 PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
PATTERN RECEIVE REGISTERS
(MSB)
(LSB)
PR31
PR30
PR22
PR14
PR6
PR29
PR21
PR13
PR5
PR28
PR20
PR12
PR4
PR27
PR19
PR11
PR3
PR26
PR18
PR10
PR2
PR25
PR17
PR9
PR24
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
PR23
PR15
PR7
PR16
PR8
PR0
PR1
11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS2172. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the INT pin. Each of the alarms
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
12 of 22
DS2172
SR: STATUS REGISTER (Address=14 Hex)
(MSB)
(LSB)
SYNC
-
RA1
RA0
RLOS
BED
BCOF
BECOF
SYMBOL POSITION NAME AND DESCRIPTION
-
SR.7
SR.6
Not Assigned. Could be any value when read.
Receive All Ones. Set when 32 consecutive 1s are received; allowed to be
cleared when a 0 is received.
RA1
RA0
SR.5
SR.4
Receive All Zeros. Set when 32 consecutive 0s are received; allowed to be
cleared when a 1 is received.
Receive Loss Of Sync. Set when the device is searching for
synchronization. Once sync is achieved, will remain set until read.
Bit Error Detection. Set when bit errors are detected.
Bit Counter Overflow. Set when the 32-bit BCR overflows.
Bit Error Count Overflow. Set when the 32-bit BECR overflows.
Sync. Real time status of the synchronizer (this bit is not latched). Will be
set when synchronization is declared. Will be cleared when 6 or more bits
out of 64 are received in error (if PCR.2 = 0).
RLOS
BED
BCOF
BECOF
SYNC
SR.3
SR.2
SR.1
SR.0
13 of 22
DS2172
IMR: INTERRUPT MASK REGISTER (Address=15 Hex)
(MSB)
(LSB)
SYNC
-
RA1
RA0
RLOS
BED
BCOF
BECOF
SYMBOL POSITION NAME AND DESCRIPTION
-
IMR.7
IMR.6
Not Assigned. Should be set to 0 when written to.
Receive All 1s.
RA1
0 = interrupt masked
1 = interrupt enabled
Receive All 0s.
RA0
RLOS
BED
IMR.5
IMR.4
IMR.3
IMR.2
IMR.1
IMR.0
0 = interrupt masked
1 = interrupt enabled
Receive Loss Of Sync.
0 = interrupt masked
1 = interrupt enabled
Bit Error Detection.
0 = interrupt masked
1 = interrupt enabled
Bit Counter Overflow.
0 = interrupt masked
1 = interrupt enabled
Bit Error Count Overflow.
0 = interrupt masked
1 = interrupt enabled
Sync.
BCOF
BECOF
SYNC
0 = interrupt masked
1 = interrupt enabled
14 of 22
DS2172
12.0 AC TIMING AND DC OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature for DS2172TN
Storage Temperature
-1.0V to +7.0V
-40°C to +85°C
-55°C to +125°C
Soldering Temperature
See J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(00C to 700C for DS2172T)
-400C to +850C for DS2172TN)
PARAMETER
Logic 1
SYMBOL MIN
TYP
MAX
VDD+0.3
+0.8
UNITS NOTES
VIH
VIL
2.0
-0.3
4.50
V
V
V
Logic 0
Supply
VDD
5.50
CAPACITANCE
PARAMETER
(tA=250C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
Input Capacitance
Output Capacitance
CIN
5
7
pF
pF
COUT
DC CHARACTERISTICS
(00C to 700C for DS2172T; VDD=5V±10%)
-400C to +850C for DS2172TN; VDD=5V±10%)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Supply Current @ 5V
Input Leakage
IDD
10
mA
µA
µA
mA
mA
1
2
3
IIL
ILO
IOH
IOL
-1.0
+1.0
1.0
Output Leakage
Output Current @ 2.4V
Output Current @ 0.4V
-1.0
+4.0
NOTES:
1. TCLK = RCLK = 1.544 MHz; outputs open circuited.
2. 0.0V < VIN < VDD.
3. Applies to INT when tri-stated.
15 of 22
DS2172
AC CHARACTERISTICS - PARALLEL PORT
(00C to 700C for DS2172T; VDD=5V 10%)
-400C to +850C for DS2172TN; VDD=5V 10%)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Cycle Time
tCYC
PWEL
PWEH
tR, tF
tRWH
tRWS
200
100
100
ns
ns
ns
ns
ns
ns
ns
Pulse Width, DS Low or RD High
Pulse Width, DS High or RD Low
Input Rise/Fall Times
20
10
50
20
R/ W Hold Times
R/ W Setup Time Before DS High
tCS
CS Setup Time Before DS, WR or RD
Active
tCH
tDHR
tDHW
tASL
0
5
ns
ns
ns
ns
CS Hold Time
Read Data Hold Time
Write Data Hold Time
50
0
Mux'ed Address Valid to AS or ALE
Fall
15
Mux'ed Address Hold Time
tAHL
tASD
10
20
ns
ns
Delay Time DS, WR or RD to AS or
ALE Rise
Pulse Width AS or ALE High
PWASH
tASED
30
10
ns
ns
Delay Time, AS or ALE to DS, WR or
RD
Output Data Delay Time from DS or
RD
tDDR
tDSW
5
50
ns
ns
Data Setup Time
50
16 of 22
DS2172
INTEL BUS READ AC TIMING (BTS=0) Figure 3
tCYC
ALE
WR
PWASH
tASD
tASD
tASED
PWEH
RD
CS
PWEL
tCS
tCH
tDHR
tASL
tDDR
AD0-AD7
tAHL
17 of 22
DS2172
INTEL BUS WRITE AC TIMING (BTS=0) Figure 4
tCYC
ALE
RD
PWASH
tASD
tASD
tASED
PWEH
WR
CS
PWEL
tCS
tCH
tDHW
tASL
AD0-AD7
tDSW
tAHL
18 of 22
DS2172
MOTOROLA BUS AC TIMING (BTS=1) Figure 5
PWASH
AS
tASD
PWEH
tASED
DS
PWEL
tCYC
tRWH
tRWS
R/W
tASL
tDHR
tDDR
AD0-AD7
(READ)
tAHL
tCH
tCS
CS
tASL
tDSW
AD0-AD7
(WRITE)
tAHL
tDHW
19 of 22
DS2172
AC CHARACTERISTICS - RECEIVE SIDE
(00C TO 700C FOR DS2172T; VDD=5V 10%)
-400C to +850C for DS2172TN; VDD=5V 10%)
PARAMETER
RCLK Period
SYMBOL MIN
TYP
MAX
UNITS NOTES
tCP
tCH
19
8
ns
ns
ns
ns
ns
ns
ns
ns
RCLK Pulse Width
tCL
8
RDATA Set Up to RCLK Rising
RDATA Hold from RCLK Rising
RDIS Set Up to RCLK Rising
RDIS Hold from RCLK Rising
RL and LC Pulse Width
tSU1
tHD1
tSU2
tHD2
tWRL
tR, tF
4
0
4
0
25
RCLK Rise and Fall Times
10
ns
1
AC CHARACTERISTICS - TRANSMIT SIDE
(00C to 700C for DS2172T; VDD=5V 10%)
-400C to +850C for DS2172TN; VDD=5V 10%)
PARAMETER
TCLK Period
SYMBOL MIN
TYP
MAX
UNITS NOTES
tCP
tCH
19
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK Pulse Width
tCL
8
TDATA Delay from TCLK Rising
TDIS Set Up to TCLK Rising
TDIS Hold from TCLK Rising
TL Pulse Width
tDD
9
tSU
4
0
tHD
tWTL
tSTL
tHTL
tR, tF
15
4
TL Set Up to TCLK Rising
TL Hold Off from TCLK Rising
TCLK Rise and Fall Time
0
10
ns
1
NOTE:
1. The maximum rise and fall time is either 10 ns or 10% of tCP whichever is less.
20 of 22
DS2172
RECEIVE AC TIMING Figure 6
TRANSMIT AC TIMING Figure 7
NOTE: When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the previous valve until TDIS is low
about the rising edge of TCLK.
TRANSMIT AC TIMING FOR THE TL INPUT Figure 8
NOTE: The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the new pattern (the shaded one) will
appear after two TCLK periods.
21 of 22
DS2172
DS2172 32-PIN TQFP
DIM
A
MIN
-
MAX
1.20
0.15
1.05
9.20
A1
A2
D
0.05
0.95
8.80
D1
E
7.00 BSC
8.80
0.45
9.20
E1
L
7.00 BSC
0.75
e
0.80 BSC
B
0.30
0.09
0.45
0.20
C
22 of 22
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