DS2188SN/T&R [MAXIM]
PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16;
| 型号： | DS2188SN/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16 衰减器 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总10页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2188
T1/CEPT Jitter Attenuator
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Attenuates clock and data jitter present in T1
or CEPT lines
DJA
RPOS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RRPOS
RRNEG
RRCLK
RST
ꢀ Meets the jitter attenuation templates
outlined in TR62411, TR-TSY-000170,
G.735, and G.742
ꢀ Only one external component required; either
a 6.176 MHz (T1) or 8.192 MHz (CEPT)
crystal
ꢀ Selectable buffer size of 128 or 32 bits
ꢀ Jitter attenuation is easily disabled
ꢀ Single +5V supply; low-power CMOS
technology
ꢀ Available in 16-pin DIP and 16-pin SOIC
(DS2188S)
RNEG
RCLK
BDS
TEST
BL
XTAL OUT
VSS
XTAL2
XTAL1
ORDERING INFORMATION
DS2188
DS2188S
DS2188N
16 Pin dip
16 Pin SOIC (0º-+70ºC)
16 Pin dip (-40ºC-+85ºC)
(0ºC-F70ºC)
ꢀ Companion to the DS2186 Transmit Line
and DS2187 Receive Line Interface
DS2188SN 16 Pin SOIC (-40ºC-+85-ºC)
DESCRIPTION
The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an
external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A
CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network
Interface Unit.
OVERVIEW
The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency
of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.
If the incoming jitter has excursions greater than 120 UIpp, then the crystal is adjusted to track the short-
term frequency variations of the incoming signal so that there is no loss of data. This adjustment is
accomplished by dividing the 4X crystal by either 3 ½ or 4 ½ instead of 4. When the incoming jitter is
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DS2188
greater than 120 UIpp, the BL pin will transition high. When the incoming jitter returns to less than
120 UIpp, the BL pin will return low.
The jitter attenuator in the DS2188 can be disabled by tying the DJA pin high. When the jitter attenuator
is disabled, the FIFO is bypassed and jitter received at RCLK, RPOS and RNEG is passed through the
DS2188 to RRCLK, RRPOS, and RRNEG. In this situation, the BL pin has no significance and XTAL
OUT will not be coherent with RRCLK.
How to use the DS2188 with Dallas Semiconductor’s other T1 and CEPT line interface parts is illustrated
in Figures 3 through 5. Figure 3 illustrates how to use the DS2188 in the receive path along with a
DS2187 Receive Line Interface. Figure 4 illustrates how to use the DS2188 in the transmit path with the
DS2186 Transmit Line Interface.
BUFFER DEPTH SELECT
The buffer size on the DS2188 can be configured to either 128 or 32 bits via the BDS pin. If BDS is tied
low, then the buffer depth will be 128 bits and hence can handle input jitter up to 120 UIpp without losing
its full attenuation capabilities as is described above in the Over-view. If BDS is tied high, then the
buffer depth is shortened to 32 bits. In this configuration, the DS2188 can handle input jitter up to
28 UIpp without losing its full jitter attenuation capabilities. The user may wish to limit the buffer size to
32 bits in applications where through-put delay is critical or into existing applications that al-ready have
32 bits of buffer space.
RESET
The buffer on the DS2188 is automatically centered on power-up. The user can recenter the 128-bit (or
32-bit) buffer on demand via the RST pin. The RST pin on the DS2188 is negative-edge triggered. When
this pin transitions from high-to-low, the buffer is recentered. The RST pin can be held either high or low
during operation of the DS2188; only a negative going signal will initiate a recentering. In most cases, a
reset of the DS2188 will corrupt data that is currently passing through the buffer.
DS2188 TI JITTER ATTENUATION PERFORMANCE Figure 1
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DS2188
DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure 2
DS2188 IN THE RECEIVE PATH Figure 3
DS2188 IN THE TRANSMIT PATH Figure 4
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DS2188
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1
2
3
DJA
RPOS
RNEG
I
I
I
Disable Jitter Attenuation. When high, jittered data and clock at RPOS,
RNEG, and RCLK are passed directly to RRPOS, RRNEG, and RRCLK.
Receive Positive Data Input. Jittered data input. Sampled on the falling
edge of RCLK.
Receive Negative Data Input. Jittered data input. Sampled on the falling
edge of RCLK.
4
5
RCLK
BDS
I
I
Receive Clock Input. Jittered input 1.544 MHz or 2.048 MHz clock.
Buffer Depth Select.
0 = 128 bits
1 = 32 bits
6
7
TEST
I
Test Input. In normal applications, this pin should be tied low.
When tied high, used to verify free running frequency of XTAL.
Crystal Frequency Output. Buffered output of the 4X crystal connected
to XTAL1 and XTAL2.
XTAL
OUT
O
8
9
10
VSS
-
I
O
Ground. 0.0V
XTAL1
XTAL2
Crystal Connections. In T1 environments, connect a 6.176 MHz crystal
to these pins. In CEPT environments, connect an 8.192 MHz crystal to
these pins.
11
12
BL
O
I
Buffer Limit. Transitions high when the buffer fills or empties to within
either 4 bits (BDS=0) or 2 bits (BDS=1) of its capacity. Indicates that the
jitter at RCLK is greater than 120 UIpp (BDS=0) or 28 UIpp (BDS=1).
Reset. Negative-edge triggered; a high-low transition will recenter the
RST
buffer. Activation of this pin may corrupt data through the DS2188.
13
14
RRCLK
RRNEG
O
O
Receive Reference Clock. Dejittered 1.544 MHz or 2.048 MHz clock.
Receive Reference Negative Data Output. Dejittered data output.
Updated on the rising edge of RRCLK.
Receive Reference Positive Data Output. Dejittered data output.
Updated on the rising edge of RRCLK.
15
16
RRPOS
VDD
O
-
Positive Supply. 5.0V
CRYSTAL REQUIREMENTS
The DS2188 must have a crystal connected to the XTAL1 and XTAL2 pins. For T1 environments, the
frequency of this crystal should be 6.176 MHz. For CEPT environments, the frequency of this crystal
should be 8.192 MHz. Table 2 lists some suggested crystal manufacturers that are recommended for use
with the DS2188. Also, see DS2188 Application Note, “Operation at Speeds Greater than E1” for
additional information.
CRYSTAL MANUFACTURERS Table 2
MANUFACTURER
PART #
FREQUENCY
6.176 MHz
JAN Crystal
6323-00, JC6A14
6323-00, JC8A14
8.192 MHz
M-TRON
4575-002
4575-001
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6.176 MHz
8.192 MHz
DS2188
CRYSTAL SELECTION GUIDELINES FOR THE DS2188
PARAMETER
Parallel resonant frequency
Mode
SPECIFICATION
6.176 MHz (T1) or 8.192 MHz (CEPT)
Fundamental
Load capacitance
Tolerance
14 to 20 pF (16 pF preferred)
±50 ppm over 0 to 70°C
CL = 10 pF, delta_f = +175 to +250 ppm
CL = 45 pF, delta_f = -175 to -250 ppm
40 ohms maximum for 6.176 MHz
30 ohms maximum for 8.192 MHz
Pullability
Effective series resistance
Crystal cut
AT
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DS2188
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.1V to +7.0V
0° to 70°C
Storage Temperature
Soldering Temperature
-55°C to +125°C
See J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Commercial (0°C to 70°C)
Industrial (-40ºC to 85ºC)
PARAMETER
Input Logic 1
Input Logic 0
Supply
SYMBOL
VIH
MIN
2.0
TYP
MAX
VCC+0.3
+0.8
UNITS NOTES
V
V
V
1
1
VIL
-0.3
4.50
VDD
5.50
NOTE:
1. Does not apply to XTAL1.
CAPACITANCE
(tA=25°C)
PARAMETER
SYMBOL
CIN
MIN
TYP
5
MAX
UNITS NOTES
Input Capacitance
Output
pF
pF
COUT
10
DC ELECTRICAL CHARACTERISTICS
Commercial (0°C to 70°C; VDD = 5.0V ± 10%)
Industrial (-40ºC to 85ºC)
PARAMETER
Supply Current
SYMBOL
MIN
TYP
MAX
UNITS NOTES
IDD
IL
IOH
IOL
7
12
mA
µA
1
2, 3
3
Input Leakage
-1.0
-1.0
+4.0
+1.0
Output Current (2.4V)
Output Current (0.4V)
mA
mA
3
NOTES:
1. RCLK = 1.544 MHz; VDD = 5.50; outputs open.
2. VSS < VIN < VDD: XTAL1 = XTAL2 = VDD.
3. Does not apply to XTAL1 or XTAL2.
6 of 10
DS2188
AC ELECTRICAL CHARACTERISTICS
Commercial (0°C to 70°C; VDD = 5.0V ± 0%)
Industrial (-40ºC to 85ºC)
PARAMETER
SYMBOL
MIN
-200
100
TYP
MAX
UNITS NOTES
RCLK Period
+200
ppm
ns
1
RCLK Pulse Width
RCLK Rise and Fall Times
RPOS, RNEG Setup to RCLK
50
ns
50
50
ns
RPOS, RNEG Hold for
RCLK
ns
Propagation delay from
RRCLK to RPOS, RRNEG
Valid
50
50
ns
Propagation delay from
XTAL OUT to RRCLK
ns
2
1
µA
RST Pulse Width
NOTES:
1. The average period of RCLK must be within Ù200 ppm of the fundamental frequency of the crystal
divided by four.
2. Only valid when the incoming jitter is less than 120 Ulpp (BDS=0) or 28 Ulpp (BDS=1).
7 of 10
DS2188
AC TIMING DIAGRAM Figure 5
NOTE:
1. The phase relationship between XTAL OUT and RRCLK can be of either form.
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DS2188
DS1288 T1/CEPT JITTER ATTENTUATOR 16-PIN DIP
PKG
DIM
AIN
MM
B IN
MM
C IN
MM
D IN
MM
E IN
MM
F IN
MM
G IN
MM
H IN
MM
J IN
16-PIN
MAX
0.780
MIN
0.740
18.80
0.240
6.10
19.81
0.260
6.60
0.120
3.05
0.140
3.56
0.300
7.62
0.325
8.26
0.015
0.38
0.040
1.02
0.120
3.04
0.140
1.02
0.090
2.29
0.110
2.79
0.320
8.13
0.370
9.40
0.008
0.20
0.012
0.30
MM
K IN
MM
0.015
0.38
0.021
0.53
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DS2188
DS1288S T1/CEPT JITTER ATTENTUATOR 16-PIN SOIC
PKG
DIM
AIN
MM
B IN
MM
C IN
MM
E IN
MM
F IN
MM
G IN
MM
H IN
MM
J IN
MM
K IN
MM
L IN
MM
phi
16-PIN
MIN
MAX
0.412
10.46
0.300
7.65
0.402
10.21
0.290
7.37
0.089
2.26
0.095
2.41
0.004
0.102
0.094
2.38
0.012
0.30
0.105
2.68
0.050 BSC
1.27 BSC
0.398
0.416
10.57
0.013
0.33
0.019
0.48
0.40
1.02
8Û
10.11
0.009
0.229
0.013
0.33
0.016
0.40
0Û
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