DS21Q44TN+_技术文档

DS21Q44

Enhanced Quad E1 Framer

www.maxim-ic.com

FEATURES

FUNCTIONAL DIAGRAM

CꢀFour E1 (CEPT or PCM-30)/ISDN-PRI

framing transceivers

Elastic

Store

Receive

Framer

CꢀAll four framers are fully independent;

transmit and receive sections of each framer

are fully independent

Elastic

Store

Transmit

Formatter

CꢀFrames to FAS, CAS, CCS, and CRC4 formats

CꢀEach of the four framers contain dual two-

frame elastic store slip buffers that can

connect to asynchronous backplanes up to

8.192MHz

FRAMER #0

FRAMER #1

FRAMER #2

FRAMER #3

Control Port

Cꢀ8-bit parallel control port that can be used

directly on either multiplexed or

nonmultiplexed buses (Intel or Motorola)

CꢀEasy access to Si and Sa bits

CꢀExtracts and inserts CAS signaling

CꢀLarge counters for bipolar and code

violations, CRC4 code word errors, FAS

word errors, and E-bits

ACTUAL SIZE

QUAD

E1

FRAMER

CꢀProgrammable output clocks for Fractional

E1, per channel loopback, H0 and H12

applications

ORDERING INFORMATION

CꢀIntegral HDLC controller with 64-byte buffers

configurable for Sa bits or DS0 operation

CꢀDetects and generates AIS, remote alarm,

and remote multiframe alarms

DS21Q44T

0°C to +70°C

-40°C to +85°C

DS21Q44TN

CꢀPin compatible with DS21Q42 enhanced

quad T1 framer

Cꢀ3.3V supply with 5V tolerant I/O; low-power

CMOS

CꢀAvailable in 128-pin TQFP package

CꢀIEEE 1149.1 support

DESCRIPTION

The DS21Q44 E1 is an enhanced version of the DS21Q43 quad E1 framer. The DS21Q44 contains four

framers that are configured and read through a common microprocessor-compatible parallel port. Each

framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All

four framers in the DS21Q44 are totally independent; they do not share a common framing synchronizer.

The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic

stores contained in each of the four framers can be independently enabled and disabled as required. The

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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062602

DS21Q44

device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and

I.431 as well as ETS 300 011 and ETS 300 233.

1. INTRODUCTION

The DS21Q44 is a superset version of the popular DS21Q43 quad E1 framer offering the new features

listed below. All of the original features of the DS21Q43 have been retained and software created for the

original device is transferable to the DS21Q44.

NEW FEATURES

C Additional hardware signaling capability including:

– receive signaling reinsertion to a backplane multiframe sync

– availability of signaling in a separate PCM data stream

– signaling freezing

– interrupt generated on change of signaling data

C Per–channel code insertion in both transmit and receive paths

C Full HDLC controller with 64-byte buffers in both transmit and receive paths. Configurable for Sa

bits or DS0 access

C RCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state

C 8.192MHz clock synthesizer

C Ability to monitor one DS0 channel in both the transmit and receive paths

C Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233

C Automatic RAI generation to ETS 300 011 specifications

C IEEE 1149.1 support

FUNCTIONAL DESCRIPTION

The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as

detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If

needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered E1 data stream and an asynchronous backplane clock which is

provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz

clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.

The transmit side in each framer is totally independent from the receive side in both the clock

requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic

store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for

E1 transmission.

READER’S NOTE:

This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us

frame, there are 32 8–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first.

These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is

identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made

up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is

the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:

FAS

CAS

MF

Si

Frame Alignment Signal

Channel Associated Signaling

Multiframe

CRC4

CCS

Sa

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

International bits

E-bit

CRC4 Error Bits

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DS21Q44

Figure 1-1. DS21Q44 ENHANCED QUAD E1 FRAMER

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DS21Q44

TABLE OF CONTENTS

1. INTRODUCTION ..............................................................................................................................2

2. DS21Q44 PIN DESCRIPTION .........................................................................................................7

3. DS21Q44 PIN FUNCTION DESCRIPTION .................................................................................13

4. DS21Q44 REGISTER MAP .............................................................................................................20

5. PARALLEL PORT ...........................................................................................................................24

6. CONTROL, ID, AND TEST REGISTERS.....................................................................................24

7. STATUS AND INFORMATION REGISTERS .............................................................................35

8. ERROR COUNT REGISTERS........................................................................................................41

9. DS0 MONITORING FUNCTION ...................................................................................................44

10. SIGNALING OPERATION ............................................................................................................46

10.1 PROCESSOR-BASED SIGNALING ........................................................................................46

10.2 HARDWARE-BASED SIGNALING........................................................................................49

11. PER–CHANNEL CODE GENERATION AND LOOPBACK ....................................................50

11.1 TRANSMIT SIDE CODE GENERATION ...............................................................................50

11.1.1 Simple Idle Code Insertion and Per-Channel Loopback...................................................50

11.1.2 Per-Channel Code Insertion..............................................................................................51

11.2 RECEIVE SIDE CODE GENERATION...................................................................................52

12. CLOCK BLOCKING REGISTERS................................................................................................53

13. ELASTIC STORES OPERATION .................................................................................................54

13.1 RECEIVE SIDE..........................................................................................................................55

13.2 TRANSMIT SIDE......................................................................................................................55

14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION.....................................55

14.1 HARDWARE SCHEME............................................................................................................55

14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME......................................56

14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................58

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DS21Q44

15. HDLC CONTROLLER FOR THE SA BITS OR DS0..................................................................60

15.1 GENERAL OVERVIEW ...........................................................................................................60

15.2 HDLC STATUS REGISTERS...................................................................................................61

15.3 BASIC OPERATION DETAILS ...............................................................................................62

15.4 HDLC REGISTER DESCRIPTION ..........................................................................................63

16. INTERLEAVED PCM BUS OPERATION....................................................................................70

17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...........................73

17.1 DESCRIPTION ..........................................................................................................................73

17.2 TAP CONTROLLER STATE MACHINE ................................................................................74

17.3 INSTRUCTION REGISTER AND INSTRUCTIONS..............................................................76

17.4 TEST REGISTERS ....................................................................................................................78

18. TIMING DIAGRAMS.......................................................................................................................82

19. OPERATING PARAMETERS .......................................................................................................92

20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................105

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DS21Q44

DOCUMENT REVISION HISTORY

REVISION NOTES:

DATE

NOTES

122298

052300

062602

Initial Release

C Changed explanation on JTRST test access port pin.

C All instances of JTRST* changed to JTRST.

C Corrected errors in the JTAG portion of data sheet.

C Updated device characterization data

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DS21Q44

2. DS21Q44 PIN DESCRIPTION

Table 2-1. PIN DESCRIPTION SORTED BY PIN NUMBER

SYMBOL

TCHBLK0

TPOS0

TYPE

DESCRIPTION

1

2

3

4

5

6

7

8

9

O

I

Transmit Channel Block from Framer 0

Transmit Bipolar Data from Framer 0

Receive Link Data from Framer 0

Receive Link Clock from Framer 0

Receive Clock for Framer 0

Receive Bipolar Data for Framer 0

Receive Signaling Output from Framer 0

[Receive Channel Clock from Framer 0]

Receive Channel Block from Framer 0

Receive System Clock for Elastic Store in Framer 0

Receive Sync for Framer 0

Receive Serial Data from Framer 0

Signal Ground

Positive Supply Voltage

TNEG0

RLINK0

RLCLK0

RCLK0

RNEG0

RPOS0

I

RSIG0

O

[O]

O

I

[RCHCLK0]

RCHBLK0

RSYSCLK0

RSYNC0

RSER0

10

11

12

13

14

15

16

I/O

O

—

[O]

O

I

VSS

VDD

SPARE1

[RMSYNC0]

RFSYNC0

JTRST

Reserved. Must be left unconnected for normal operation

[Receive Multiframe Sync from Framer 0]

Receive Frame Sync from Framer 0

JTAG Reset

17

18

[RLOS/LOTC0]

TCLK0

TLCLK0

TSYNC0

TLINK0

A0

[O]

I

[Receive Loss of Sync/Loss of Transmit clock from Framer 0]

Transmit Clock for Framer 0

19

20

21

22

23

24

25

26

27

28

29

O

I/O

I

Transmit Link Clock from Framer 0

Transmit Sync for Framer 0

Transmit Link Data for Framer 0

Address Bus Bit 0; LSB

I

A1

I

Address Bus Bit 1

A2

I

Address Bus Bit 2

A3

I

Address Bus Bit 3

A4

I

Address Bus Bit 4

A5

I

Address Bus Bit 5

A6/ALE (AS)

I

Address Bus Bit 6; MSB or Address Latch Enable (Address

Strobe)

30

31

32

33

34

INT*

TSYSCLK1

TSER1

O

I

Receive Alarm Interrupt for all Four Framers

Transmit System Clock for Elastic Store in Framer 1

Transmit Serial Data for Framer 1

Transmit Sync for Elastic Store in Framer 1

Transmit Signaling Input for Framer 1

[Transmit Channel Clock from Framer 1]

Transmit Channel Block from Framer 1

Transmit Bipolar Data from Framer 1

Receive Link Data from Framer 1

I

TSSYNC1

TSIG1

I

[TCHCLK1]

TCHBLK1

TPOS1

[O]

O

35

36

37

38

TNEG1

RLINK1

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DS21Q44

SYMBOL

TYPE

DESCRIPTION

Receive Link Clock from Framer 1

Receive Clock for Framer 1

Receive Bipolar Data for Framer 1

Receive Signaling output from Framer 1

[Receive Channel Clock from Framer 1]

Receive Channel Block from Framer 1

Receive System Clock for Elastic Store in Framer 1

Address Bus Bit 7

39

40

41

42

43

RLCLK1

O

RCLK1

I

RNEG1

RPOS1

I

RSIG1

O

[O]

O

I

[RCHCLK1]

RCHBLK1

RSYSCLK1

A7

44

45

46

47

48

49

50

I

FMS

Framer Mode Select

RSYNC1

RSER1

I/O

O

I

Receive Sync for Framer 1

Receive Serial Data from Framer 1

JTAG Test Mode Select

JTMS

[RMSYNC1]

RFSYNC1

JTCLK

[O]

O

I

[Receive Multiframe Sync from Framer 1]

Receive Frame Sync from Framer 1

JTAG Test Clock

51

52

[RLOS/LOTC1]

TCLK1

[O]

I

[Receive Loss of Sync/Loss of Transmit clock from Framer 1]

Transmit Clock for Framer 1

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

TLCLK1

TSYNC1

TLINK1

TEST

O

I/O

I

Transmit Link Clock from Framer 1

Transmit Sync for Framer 1

Transmit Link Data for Framer 1

Tri-state Control for all Output and I/O Pins

Framer Select 0 for Parallel Control Port

Framer Select 1 for Parallel Control Port

Chip Select

I

FS0

I

FS1

I

CS*

I

BTS

I

Bus Type Select for Parallel Control Port

Read Input (Data Strobe)

Write Input (Read/Write)

RD*/(DS*)

WR*/(R/W*)

MUX

I

Nonmultiplexed or Multiplexed Bus Select

Transmit System Clock for Elastic Store in Framer 2

Transmit Serial Data for Framer 2

Transmit Sync for Elastic Store in Framer 2

Transmit Signaling Input for Framer 2

[Transmit Channel Clock from Framer 2]

Transmit Channel Block from Framer 2

Transmit Bipolar Data from Framer 2

Receive Link Data from Framer 2

Receive Link Clock from Framer 2

Receive Clock for Framer 2

TSYSCLK2

TSER2

I

TSSYNC2

TSIG2

I

[TCHCLK2]

TCHBLK2

TPOS2

[O]

O

I

69

70

71

72

73

74

75

76

77

TNEG2

RLINK2

RLCLK2

RCLK2

RNEG2

RPOS2

I

Receive Bipolar Data for Framer 2

Receive Signaling Output from Framer 2

[Receive Channel Clock from Framer 2]

Signal Ground

Positive Supply Voltage

Receive Channel Block from Framer 2

RSIG2

O

[O]

—

O

[RCHCLK2]

VSS

78

79

80

VDD

RCHBLK2

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DS21Q44

SYMBOL

TYPE

DESCRIPTION

81

82

83

84

RSYSCLK2

RSYNC2

RSER2

I

I/O

O

I

Receive System Clock for Elastic Store in Framer 2

Receive Sync for Framer 2

Receive Serial Data from Framer 2

JTAG Test Data Input

JTDI

[RMSYNC2]

RFSYNC2

JTDO

[O]

O

[O]

I

[Receive Multiframe Sync from Framer 2]

Receive Frame Sync from Framer 2

JTAG Test Data Output

85

86

[RLOS/LOTC2]

TCLK2

[Receive Loss of Sync/Loss of Transmit clock from Framer 2]

Transmit Clock for Framer 2

87

88

89

90

91

92

93

94

TLCLK2

TSYNC2

TLINK2

O

I/O

I

Transmit Link Clock from Framer 2

Transmit Sync for Framer 2

Transmit Link Data for Framer 2

Transmit System Clock for Elastic Store in Framer 3

Transmit Serial Data for Framer 3

Transmit Sync for Elastic Store in Framer 3

Transmit Signaling Input for Framer 3

[Transmit Channel Clock from Framer 3]

Transmit Channel Block from Framer 3

Transmit Bipolar Data from Framer 3

Receive Link Data from Framer 3

Receive Link Clock from Framer 3

Receive Clock for Framer 3

TSYSCLK3

TSER3

I

TSSYNC3

TSIG3

I

[TCHCLK3]

TCHBLK3

TPOS3

95

96

O

97

TNEG3

O

98

RLINK3

RLCLK3

RCLK3

O

99

O

100

101

102

103

I

RNEG3

I

Receive Bipolar Data for Framer 3

Receive Signaling Output from Framer 3

[Receive Channel Clock from Framer 3]

Receive Channel Block from Framer 3

Receive System Clock for Elastic Store in Framer 3

Receive Sync for Framer 3

RPOS3

I

RSIG3

O

[RCHCLK3]

RCHBLK3

RSYSCLK3

RSYNC3

RSER3

[O]

O

104

105

106

107

108

I

I/O

O

Receive Serial Data from Framer 3

8MHz Clock

8MCLK

O

[RMSYNC3]

RFSYNC3

VSS

[O]

O

[Receive Multiframe Sync from Framer 3]

Receive Frame Sync from Framer 3

Signal Ground

109

110

111

112

—

I

VDD

CLKSI

Positive Supply Voltage

8MCLK Clock Reference Input

[RLOS/LOTC3]

TCLK3

[O]

I

[Receive Loss of Sync/Loss of Transmit clock from Framer 3]

Transmit Clock for Framer 3

113

114

115

116

117

118

119

120

121

TLCLK3

TSYNC3

TLINK3

O

Transmit Link Clock from Framer 3

Transmit Sync for Framer 3

I/O

I

Transmit Link Data for Framer 3

Data Bus Bit or Address/Data Bit 0; LSB

Data Bus Bit or Address/Data Bit 1

Data Bus Bit or Address/Data Bit 2

Data Bus Bit or Address/Data Bit 3

Data Bus Bit or Address/Data Bit 4

D0 or AD0

D1 or AD1

D2 or AD2

D3 or AD3

D4 or AD4

I/O

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DS21Q44

SYMBOL

TYPE

DESCRIPTION

122

123

124

125

126

127

128

D5 or AD5

D6 or AD6

D7 or AD7

TSYSCLK0

TSER0

I/O

I

Data Bus Bit or Address/Data Bit 5

Data Bus Bit or Address/Data Bit 6

Data Bus Bit or Address/Data Bit 7; MSB

Transmit System Clock for Elastic Store in Framer 0

Transmit Serial Data for Framer 0

I

TSSYNC0

TSIG0

I

Transmit Sync for Elastic Store in Framer 0

Transmit Signaling Input for Framer 0

[Transmit Channel Clock from Framer 0]

I

[TCHCLK0]

[O]

NOTES:

1) Brackets [ ] indicate pin function when the DS21Q44 is configured for emulation of the DS21Q43,

(FMS = 1).

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DS21Q44

Table 2-2. PIN DESCRIPTION SORTED BY PIN FUNCTION, FMS = 0

SYMBOL

TYPE

DESCRIPTION

108

23

24

25

26

27

28

29

8MCLK

O

8MHz Clock

A0

I

Address Bus Bit 0; LSB

Address Bus Bit 1

Address Bus Bit 2

Address Bus Bit 3

Address Bus Bit 4

Address Bus Bit 5

A1

I

A2

I

A3

A4

I

A5

I

A6/ALE (AS)

I

Address Bus Bit 6; MSB or Address Latch Enable (Address

Strobe)

46

61

112

60

A7

I

Address Bus Bit 7

BTS

Bus Type Select for Parallel Control Port

8MCLK Clock Reference Input

Chip Select

CLKSI

I

CS*

I

117

118

119

120

121

122

123

124

47

D0 or AD0

D1 or AD1

D2 or AD2

D3 or AD3

D4 or AD4

D5 or AD5

D6 or AD6

D7 or AD7

FMS

I/O

I

Data Bus Bit or Address/Data Bit 0; LSB

Data Bus Bit or Address/Data Bit 1

Data Bus Bit or Address/Data Bit 2

Data Bus Bit or Address/Data Bit 3

Data Bus Bit or Address/Data Bit 4

Data Bus Bit or Address/Data Bit 5

Data Bus Bit or Address/Data Bit 6

Data Bus Bit or Address/Data Bit 7; MSB

Framer Mode Select

58

FS0

I

Framer Select 0 for Parallel Control Port

Framer Select 1 for Parallel Control Port

Receive Alarm Interrupt for all Four Framers

JTAG Test Clock

59

FS1

I

30

INT*

O

I

52

JTCLK

84

JTDI

I

JTAG Test Data Input

86

JTDO

O

I

JTAG Test Data Output

50

JTMS

JTAG Test Mode Select

18

JTRST

I

JTAG Reset

64

MUX

Nonmultiplexed or Multiplexed Bus Select

Receive Channel Block from Framer 0

Receive Channel Block from Framer 1

Receive Channel Block from Framer 2

Receive Channel Block from Framer 3

Receive Clock for Framer 0

10

RCHBLK0

RCHBLK1

RCHBLK2

RCHBLK3

RCLK0

RCLK1

RCLK2

RCLK3

RD*/(DS*)

RFSYNC0

RFSYNC1

RFSYNC2

RFSYNC3

O

I

44

80

104

6

40

I

Receive Clock for Framer 1

74

I

Receive Clock for Framer 2

100

62

I

Receive Clock for Framer 3

I

Read Input (Data Strobe)

17

O

Receive Frame Sync from Framer 0

Receive Frame Sync from Framer 1

Receive Frame Sync from Framer 2

Receive Frame Sync from Framer 3

51

85

109

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DS21Q44

SYMBOL

TYPE

DESCRIPTION

Receive Link Clock from Framer 0

5

39

73

99

4

38

72

98

7

41

75

101

8

42

76

102

13

49

83

107

9

43

77

103

12

48

82

106

11

45

81

105

16

1

35

69

95

19

53

87

113

57

20

54

88

114

RLCLK0

RLCLK1

RLCLK2

RLCLK3

RLINK0

RLINK1

RLINK2

RLINK3

RNEG0

O

I

Receive Link Clock from Framer 1

Receive Link Clock from Framer 2

Receive Link Clock from Framer 3

Receive Link Data from Framer 0

Receive Link Data from Framer 1

Receive Link Data from Framer 2

Receive Link Data from Framer 3

Receive Bipolar Data for Framer 0

Receive Bipolar Data for Framer 1

Receive Bipolar Data for Framer 2

Receive Bipolar Data for Framer 3

Receive Bipolar Data for Framer 0

Receive Bipolar Data for Framer 1

Receive Bipolar Data for Framer 2

Receive Bipolar Data for Framer 3

Receive Serial Data from Framer 0

Receive Serial Data from Framer 1

Receive Serial Data from Framer 2

Receive Serial Data from Framer 3

Receive Signaling Output from Framer 0

Receive Signaling output from Framer 1

Receive Signaling Output from Framer 2

Receive Signaling Output from Framer 3

Receive Sync for Framer 0

RNEG1

I

RNEG2

I

RNEG3

I

RPOS0

I

RPOS1

I

RPOS2

I

RPOS3

I

RSER0

O

I/O

I

RSER1

RSER2

RSER3

RSIG0

RSIG1

RSIG2

RSIG3

RSYNC0

RSYNC1

RSYNC2

RSYNC3

RSYSCLK0

RSYSCLK1

RSYSCLK2

RSYSCLK3

SPARE1

TCHBLK0

TCHBLK1

TCHBLK2

TCHBLK3

TCLK0

Receive Sync for Framer 1

Receive Sync for Framer 2

Receive Sync for Framer 3

Receive System Clock for Elastic Store in Framer 0

Receive System Clock for Elastic Store in Framer 1

Receive System Clock for Elastic Store in Framer 2

Receive System Clock for Elastic Store in Framer 3

Reserved. Must be left unconnected for normal operation

Transmit Channel Block from Framer 0

Transmit Channel Block from Framer 1

Transmit Channel Block from Framer 2

Transmit Channel Block from Framer 3

Transmit Clock for Framer 0

I

—

O

I

TCLK1

I

Transmit Clock for Framer 1

TCLK2

I

Transmit Clock for Framer 2

TCLK3

I

Transmit Clock for Framer 3

TEST

I

Tri-state Control for all Output and I/O Pins

Transmit Link Clock from Framer 0

Transmit Link Clock from Framer 1

Transmit Link Clock from Framer 2

Transmit Link Clock from Framer 3

TLCLK0

TLCLK1

TLCLK2

TLCLK3

O

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DS21Q44

SYMBOL

TYPE

DESCRIPTION

Transmit Link Data for Framer 0

22

56

90

116

3

37

71

97

2

TLINK0

TLINK1

TLINK2

TLINK3

TNEG0

TNEG1

TNEG2

TNEG3

TPOS0

I

Transmit Link Data for Framer 1

Transmit Link Data for Framer 2

Transmit Link Data for Framer 3

Transmit Bipolar Data from Framer 0

Transmit Bipolar Data from Framer 1

Transmit Bipolar Data from Framer 2

Transmit Bipolar Data from Framer 3

Transmit Bipolar Data from Framer 0

Transmit Bipolar Data from Framer 1

Transmit Bipolar Data from Framer 2

Transmit Bipolar Data from Framer 3

Transmit Serial Data for Framer 0

Transmit Serial Data for Framer 1

Transmit Serial Data for Framer 2

Transmit Serial Data for Framer 3

Transmit Signaling Input for Framer 0

Transmit Signaling Input for Framer 1

Transmit Signaling Input for Framer 2

Transmit Signaling Input for Framer 3

Transmit Sync for Elastic Store in Framer 0

Transmit Sync for Elastic Store in Framer 1

Transmit Sync for Elastic Store in Framer 2

Transmit Sync for Elastic Store in Framer 3

Transmit Sync for Framer 0

I

O

I

36

70

96

126

32

66

92

128

34

68

94

127

33

67

93

21

55

89

115

125

31

65

91

15

79

111

14

78

110

63

TPOS1

TPOS2

TPOS3

TSER0

TSER1

I

TSER2

I

TSER3

I

TSIG0

I

TSIG1

I

TSIG2

I

TSIG3

I

TSSYNC0

TSSYNC1

TSSYNC2

TSSYNC3

TSYNC0

TSYNC1

TSYNC2

TSYNC3

TSYSCLK0

TSYSCLK1

TSYSCLK2

TSYSCLK3

VDD

I

I/O

I

Transmit Sync for Framer 1

Transmit Sync for Framer 2

Transmit Sync for Framer 3

Transmit System Clock for Elastic Store in Framer 0

Transmit System Clock for Elastic Store in Framer 1

Transmit System Clock for Elastic Store in Framer 2

Transmit System Clock for Elastic Store in Framer 3

Positive Supply Voltage

I

—

I

VDD

Positive Supply Voltage

VDD

Positive Supply Voltage

VSS

Signal Ground

VSS

Signal Ground

VSS

Signal Ground

WR*/(R/W*)

Write Input (Read/Write)

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DS21Q44

3. DS21Q44 PIN FUNCTION DESCRIPTION

TRANSMIT SIDE PINS

Signal Name:

TCLK

Signal Description:

Signal Type:

Transmit Clock

Input

A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.

Signal Name:

TSER

Signal Description:

Signal Type:

Transmit Serial Data

Input

Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is

disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.

Signal Name:

TCHCLK

Signal Description:

Signal Type:

Transmit Channel Clock

Output

A 256-kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the

transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store

is enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS

= 1 (DS21Q43 emulation).

Signal Name:

TCHBLK

Signal Description:

Signal Type:

Transmit Channel Block

Output

A user programmable output that can be forced high or low during any of the 32 E1 channels.

Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK

when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD

controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps (H0),

768 kbps, 1920 bps (H12) or ISDN–PRI . Also useful for locating individual channels in drop–and–insert

applications, for external per–channel loopback, and for per–channel conditioning. See Section 12 for

details.

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DS21Q44

Signal Name:

TSYSCLK

Signal Description:

Signal Type:

Transmit System Clock

Input

1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.

Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up

to 8.192 MHz.

Signal Name:

TLCLK

Signal Description:

Signal Type:

Transmit Link Clock

Output

4 kHz to 20 kHz demand clock for the TLINK input. See Section 14 for details.

Signal Name:

TLINK

Signal Description:

Signal Type:

Transmit Link Data

Input

If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination

of the Sa bit positions (Sa4 to Sa8). See Section 14 for details.

Signal Name:

TSYNC

Signal Description:

Signal Type:

Transmit Sync

Input /Output

A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This pin can

also be programmed to output either a frame or multiframe pulse. Always synchronous with TCLK.

Signal Name:

TSSYNC

Signal Description:

Signal Type:

Transmit System Sync

Input

Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or

multiframe boundaries for the transmit side. Should be tied low in applications that do not use the

transmit side elastic store. Always synchronous with TSYSCLK.

Signal Name:

TSIG

Signal Description:

Signal Type:

Transmit Signaling Input

Input

When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream.

Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the

falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when

FMS = 0.

Signal Name:

TPOS

Signal Description:

Signal Type:

Transmit Positive Data Output

Output

Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be

programmed to source NRZ data via the Output Data Format (TCR1.7) control bit.

Signal Name:

TNEG

Signal Description:

Signal Type:

Transmit Negative Data Output

Output

Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.

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DS21Q44

RECEIVE SIDE PINS

Signal Name:

RLINK

Signal Description:

Signal Type:

Receive Link Data

Output

Updated with full recovered E1 data stream on the rising edge of RCLK.

Signal Name:

RLCLK

Signal Description:

Signal Type:

Receive Link Clock

Output

A 4 kHz to 20-kHz clock for the RLINK output. Used for sampling Sa bits.

Signal Name:

RCLK

Signal Description:

Signal Type:

Receive Clock Input

Input

2.048 MHz clock that is used to clock data through the receive side framer.

Signal Name:

RCHCLK

Signal Description:

Signal Type:

Receive Channel Clock

Output

A 256-kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the

receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is

enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS =

1 (DS21Q43 emulation).

Signal Name:

RCHBLK

Signal Description:

Signal Type:

Receive Channel Block

Output

A user programmable output that can be forced high or low during any of the 32 E1 channels.

Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK

when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD

controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps service,

768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for

external per–channel loopback, and for per–channel conditioning. See Section 12 for details.

Signal Name:

RSER

Signal Description:

Signal Type:

Receive Serial Data

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RSYNC

Signal Description:

Signal Type:

Receive Sync

Input /Output

An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC

multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an

input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.

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DS21Q44

Signal Name:

RFSYNC

Signal Description:

Signal Type:

Receive Frame Sync

Output

An extracted 8-kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.

Signal Name:

RMSYNC

Signal Description:

Signal Type:

Receive Multiframe Sync

Output

An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If

the receive side elastic store is disabled, then this output will output multiframe boundaries associated

with RCLK. This function is available when FMS = 1 (DS21Q43 emulation).

Signal Name:

RSYSCLK

Signal Description:

Signal Type:

Receive System Clock

Input

1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied

low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.

Signal Name:

RSIG

Signal Description:

Signal Type:

Receive Signaling Output

Output

Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic

store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is

enabled. This function is available when FMS = 0.

Signal Name:

RLOS/LOTC

Signal Description:

Signal Type:

Receive Loss of Sync / Loss of Transmit Clock

Output

A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either

toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the

TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q43

emulation).

Signal Name:

CLKSI

Signal Description:

Signal Type:

8 MHz Clock Reference

Input

A 2.048 MHz reference clock used in the generation of 8MCLK. This function is available when

FMS = 0.

Signal Name:

8MCLK

Signal Description:

Signal Type:

8 MHz Clock

Output

A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is

available when FMS = 0.

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DS21Q44

Signal Name:

RPOS

Signal Description:

Signal Type:

Receive Positive Data Input

Input

Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and

RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar

violation monitoring circuitry.

Signal Name:

RNEG

Signal Description:

Signal Type:

Receive Negative Data Input

Input

Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and

RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar

violation monitoring circuitry.

PARALLEL CONTROL PORT PINS

Signal Name:

INT*

Signal Description:

Signal Type:

Interrupt

Output

Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2

and the FDL Status Register. Active low, open drain output.

Signal Name:

FMS

Signal Description:

Signal Type:

Framer Mode Select

Input

Set low to select DS21Q44 feature set. Set high to select DS21Q43 emulation.

Signal Name:

MUX

Signal Description:

Signal Type:

Bus Operation

Input

Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.

Signal Name:

D0 TO D7 / AD0 TO AD7

Data Bus or Address/Data Bus

Input /Output

Signal Description:

Signal Type:

In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation

(MUX = 1), serves as a 8–bit multiplexed address / data bus.

Signal Name:

A0 TO A5, A7

Address Bus

Input

Signal Description:

Signal Type:

In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation

(MUX = 1), these pins are not used and should be tied low.

Signal Name:

ALE (AS) / A6

Signal Description:

Signal Type:

Address Latch Enable (Address Strobe) or A6

Input

In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation

(MUX = 1), serves to demultiplex the bus on a positive–going edge.

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DS21Q44

Signal Name:

BTS

Signal Description:

Signal Type:

Bus Type Select

Input

Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the

function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the

function listed in parenthesis ().

Signal Name:

RD* (DS*)

Signal Description:

Signal Type:

Read Input (Data Strobe)

Input

RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing

diagrams in section 19 .

Signal Name:

FS0 AND FS1

Framer Selects

Input

Signal Description:

Signal Type:

Selects which of the four framers to be accessed.

Signal Name:

CS*

Signal Description:

Signal Type:

Chip Select

Input

Must be low to read or write to the device. CS* is an active low signal.

Signal Name:

WR* (R/W*)

Signal Description:

Signal Type:

Write Input (Read/Write)

Input

WR* is an active low signal.

TEST ACCESS PORT PINS

Signal Name:

TEST

Signal Description:

Signal Type:

3–State Control

Input

Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal

operation. Useful in board level testing.

Signal Name:

JTRST

Signal Description:

Signal Type:

IEEE 1149.1 Test Reset

Input

If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally.

If FMS = 0: JTAG functionality is available and JTRST is pulled up internally by a 10=kilo ohm resistor.

If FMS = 0, and boundary scan is not used this pin should be held low. This signal is used to

asynchronously reset the test access port controller. The device enters the DEVICE ID MODE when

JTRST is pulled high. The device enters the DEVICE ID MODE when JTRST is pulled high. The

device operates as a T1/E1 transceiver if JTRST is pulled low.

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DS21Q44

Signal Name:

JTMS

Signal Description:

Signal Type:

IEEE 1149.1 Test Mode Select

Input

This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined

IEEE 1149.1 states. If not used, this pin should be pulled high. This function is available when FMS = 0.

Signal Name:

JTCLK

Signal Description:

Signal Type:

IEEE 1149.1 Test Clock Signal

Input

This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not

used, this pin should be tied to VSS. This function is available when FMS = 0.

Signal Name:

JTDI

Signal Description:

Signal Type:

IEEE 1149.1 Test Data Input

Input

Test instructions and data are clocked into this pin on the rising edge of JTCLK. If not used, this pin

should be pulled high. This function is available when FMS = 0.

Signal Name:

JTDO

Signal Description:

Signal Type:

IEEE 1149.1 Test Data Output

Output

Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin

should be left unconnected. This function is available when FMS = 0.

SUPPLY PINS

Signal Name:

VDD

Signal Description:

Signal Type:

Positive Supply

Supply

2.97 to 3.63 volts.

Signal Name:

Signal Description:

Signal Type:

0.0 volts.

VSS

Signal Ground

Supply

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DS21Q44

4. DS21Q44 REGISTER MAP

Table 4-1. REGISTER MAP SORTED BY ADDRESS

REGISTER

ADDRESS

R/W

REGISTER NAME

ABBREVIATION

VCR1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

R

BPV or Code Violation Count 1

BPV or Code Violation Count 2

CRC4 Error Count 1 / FAS Error Count 1

CRC4 Error Count 2

E-Bit Count 1 / FAS Error Count 2

E-Bit Count 2

R

VCR2

R

CRCCR1

CRCCR2

EBCR1

EBCR2

SR1

R

R/W

—

Status 1

Status 2

SR2

RIR

Receive Information

Test 2

TEST2 (set to 00h)

(set to 00H)

IDR

Not used

—

Not used

—

Not used

—

Not used

—

Not used

R

Device ID

R/W

—

Receive Control 1

Receive Control 2

Transmit Control 1

Transmit Control 2

Common Control 1

Test 1

Interrupt Mask 1

Interrupt Mask 2

Not used

RCR1

RCR2

TCR1

TCR2

CCR1

TEST1 (set to 00h)

IMR1

IMR2

(set to 00H)

CCR2

—

Not used

R/W

R

Common Control 2

Common Control 3

Transmit Sa Bit Control

Common Control 6

Synchronizer Status

Receive Nonalign Frame

Transmit Align Frame

Transmit Non-Align Frame

Transmit Channel Blocking 1

Transmit Channel Blocking 2

Transmit Channel Blocking 3

Transmit Channel Blocking 4

Transmit Idle 1

CCR3

TSaCR

CCR6

SSR

R

RNAF

R/W

TAF

TNAF

TCBR1

TCBR2

TCBR3

TCBR4

TIR1

Transmit Idle 2

Transmit Idle 3

TIR2

TIR3

Transmit Idle 4

TIR4

21 of 105

DS21Q44

REGISTER

ADDRESS

R/W

REGISTER NAME

Transmit Idle Definition

ABBREVIATION

TIDR

RCBR1

RCBR2

RCBR3

RCBR4

RAF

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

R/W

R

Receive Channel Blocking 1

Receive Channel Blocking 2

Receive Channel Blocking 3

Receive Channel Blocking 4

Receive Align Frame

Receive Signaling 1

R

RS1

R

Receive Signaling 2

RS2

R

Receive Signaling 3

RS3

R

Receive Signaling 4

RS4

R

Receive Signaling 5

RS5

R

Receive Signaling 6

RS6

R

Receive Signaling 7

RS7

R

Receive Signaling 8

RS8

R

Receive Signaling 9

RS9

R

Receive Signaling 10

Receive Signaling 11

Receive Signaling 12

Receive Signaling 13

Receive Signaling 14

Receive Signaling 15

Receive Signaling 16

Transmit Signaling 1

Transmit Signaling 2

Transmit Signaling 3

Transmit Signaling 4

Transmit Signaling 5

Transmit Signaling 6

Transmit Signaling 7

Transmit Signaling 8

Transmit Signaling 9

Transmit Signaling 10

Transmit Signaling 11

Transmit Signaling 12

Transmit Signaling 13

Transmit Signaling 14

Transmit Signaling 15

Transmit Signaling 16

Transmit Si Bits Align Frame

Transmit Si Bits Nonalign Frame

Transmit Remote Alarm Bits

Transmit Sa4 Bits

RS10

RS11

RS12

RS13

RS14

RS15

RS16

TS1

R

R/W

TS2

TS3

TS4

TS5

TS6

TS7

TS8

TS9

TS10

TS11

TS12

TS13

TS14

TS15

TS16

TSiAF

TSiNAF

TRA

TSa4

TSa5

TSa6

TSa7

Transmit Sa5 Bits

Transmit Sa6 Bits

Transmit Sa7 Bits

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DS21Q44

REGISTER

ADDRESS

R/W

REGISTER NAME

Transmit Sa8 Bits

ABBREVIATION

TSa8

RSiAF

RSiNAF

RRA

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

R/W

R

Receive Si bits Align Frame

Receive Si bits Nonalign Frame

Receive Remote Alarm Bits

Receive Sa4 Bits

R

RSa4

RSa5

RSa6

RSa7

RSa8

TC1

R

Receive Sa5 Bits

R

Receive Sa6 Bits

R

Receive Sa7 Bits

R

Receive Sa8 Bits

R/W

Transmit Channel 1

Transmit Channel 2

Transmit Channel 3

Transmit Channel 4

Transmit Channel 5

Transmit Channel 6

Transmit Channel 7

Transmit Channel 8

Transmit Channel 9

Transmit Channel 10

Transmit Channel 11

Transmit Channel 12

Transmit Channel 13

Transmit Channel 14

Transmit Channel 15

Transmit Channel 16

Transmit Channel 17

Transmit Channel 18

Transmit Channel 19

Transmit Channel 20

Transmit Channel 21

Transmit Channel 22

Transmit Channel 23

Transmit Channel 24

Transmit Channel 25

Transmit Channel 26

Transmit Channel 27

Transmit Channel 28

Transmit Channel 29

Transmit Channel 30

Transmit Channel 31

Transmit Channel 32

Receive Channel 1

Receive Channel 2

Receive Channel 3

Receive Channel 4

TC2

TC3

TC4

TC5

TC6

TC7

TC8

TC9

TC10

TC11

TC12

TC13

TC14

TC15

TC16

TC17

TC18

TC19

TC20

TC21

TC22

TC23

TC24

TC25

TC26

TC27

TC28

TC29

TC30

TC31

TC32

RC1

RC2

RC3

RC4

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DS21Q44

REGISTER

ADDRESS

R/W

REGISTER NAME

Receive Channel 5

ABBREVIATION

RC5

84

85

R/W

R

Receive Channel 6

Receive Channel 7

Receive Channel 8

Receive Channel 9

Receive Channel 10

Receive Channel 11

Receive Channel 12

Receive Channel 13

Receive Channel 14

Receive Channel 15

Receive Channel 16

Receive Channel 17

Receive Channel 18

Receive Channel 19

Receive Channel 20

Receive Channel 21

Receive Channel 22

Receive Channel 23

Receive Channel 24

Receive Channel 25

Receive Channel 26

Receive Channel 27

Receive Channel 28

Receive Channel 29

Receive Channel 30

Receive Channel 31

Receive Channel 32

Transmit Channel Control 1

Transmit Channel Control 2

Transmit Channel Control 3

Transmit Channel Control 4

Receive Channel Control 1

Receive Channel Control 2

Receive Channel Control 3

Receive Channel Control 4

Common Control 4

Transmit DS0 Monitor

Common Control 5

Receive DS0 Monitor

Test 3

RC6

86

RC7

87

RC8

88

RC9

89

RC10

8A

8B

8C

8D

8E

8F

90

RC11

RC12

RC13

RC14

RC15

RC16

RC17

91

RC18

92

RC19

93

RC20

94

RC21

95

RC22

96

RC23

97

RC24

98

RC25

99

RC26

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

RC27

RC28

RC29

RC30

RC31

RC32

TCC1

TCC2

TCC3

TCC4

RCC1

RCC2

RCC3

RCC4

CCR4

TDS0M

CCR5

RDS0M

TEST3 (set to 00H)

(set to 00H)

HCR

R/W

R

R/W

—

Not used

—

Not used

—

Not used

R/W

HDLC Control Register

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DS21Q44

REGISTER

ADDRESS

R/W

REGISTER NAME

HDLC Status Register

ABBREVIATION

HSR

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

R/W

–

HDLC Interrupt Mask Register

Receive HDLC Information Register

Receive HDLC FIFO Register

Interleave Bus Operation Register

Transmit HDLC Information Register

Transmit HDLC FIFO Register

Receive HDLC DS0 Control Register 1

Receive HDLC DS0 Control Register 2

Transmit HDLC DS0 Control Register 1

Transmit HDLC DS0 Control Register 2

Not used

HIMR

RHIR

RHFR

IBO

THIR

THFR

RDC1

RDC2

TDC1

TDC2

(set to 00H)

–

Not used

–

Not used

–

Not used

NOTES:

1) Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all 0’s)

on power-up initialization to ensure proper operation.

2) Register banks CxH, DxH, ExH, and FxH are not accessible.

5. PARALLEL PORT

The DS21Q44 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by

an external microcontroller or microprocessor. The DS21Q44 can operate with either Intel or Motorola

bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola

timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in

the A.C. Electrical Characteristics in Section 19 for more details.

6. CONTROL, ID, AND TEST REGISTERS

The operation of each framer within the DS21Q44 is configured via a set of ten control registers.

Typically, the control registers are only accessed when the system is first powered up. Once a channel in

the DS21Q44 has been initialized, the control registers will only need to be accessed when there is a

change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two

Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).

Each of the ten registers are described in this section.

There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is

fixed to a one indicating that the DS21Q44 is present. The T1 pin–for–pin compatible version of the

DS21Q44 is the DS21Q42 and it also has an ID register at address 0Fh and the user can read the MSB to

determine which chip is present since in the DS21Q42 the MSB will be set to a zero and in the DS21Q44

it will be set to a one. The lower 4 bits of the IDR are used to display the die revision of the chip.

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DS21Q44

Power-Up Sequence

The DS21Q44 does not automatically clear its register space on power–up. After the supplies are stable,

each of the four framer’s register space should be configured for operation by writing to all of the internal

registers. This includes setting the Test and all unused registers to 00Hex.

This can be accomplished using a two-pass approach on each framer within the DS21Q44.

1) Clear framer’s register space by writing 00H to the addresses 00H through 0BFH.

2) Program required registers to achieve desired operating mode.

NOTE:

When emulating the DS21Q43 feature set (FMS = 1), the full address space (00H through 0BFH) must be

initialized. DS21Q43 emulation require address pin A7 to be used.

Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero

to a one (this step can be skipped if the elastic stores are disabled).

IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)

(MSB)

(LSB)

T1E1

0

POSITION

IDR.7

0

ID3

ID2

ID1

ID0

SYMBOL

NAME AND DESCRIPTION

T1E1

T1 or E1 Chip Determination Bit.

0=T1 chip

1=E1 chip

ID3

IDR.3

Chip Revision Bit 3. MSB of a decimal code that represents the

chip revision.

ID2

ID1

ID0

IDR.1

IDR.2

IDR.0

Chip Revision Bit 2.

Chip Revision Bit 1.

Chip Revision Bit 0. LSB of a decimal code that represents the

chip revision.

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DS21Q44

RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)

(MSB)

(LSB)

RSMF

RSM

RSIO

POSITION

RCR1.7

–

FRC

SYNCE

RESYNC

SYMBOL

RSMF

NAME AND DESCRIPTION

RSYNC Multiframe Function. Only used if the RSYNC pin is

programmed in the multiframe mode (RCR1.6=1).

0 = RSYNC outputs CAS multiframe boundaries

1 = RSYNC outputs CRC4 multiframe boundaries

RSYNC Mode Select.

RSM

RSIO

RCR1.6

RCR1.5

0 = frame mode (see the timing in Section 18)

1 = multiframe mode (see the timing in Section 18)

RSYNC I/O Select. (note: this bit must be set to zero when

RCR2.1=0).

0 = RSYNC is an output (depends on RCR1.6)

1 = RSYNC is an input (only valid if elastic store enabled)

Not Assigned. Should be set to zero when written.

Frame Resync Criteria.

–

RCR1.4

RCR1.3

RCR1.2

FRC

0 = resync if FAS received in error 3 consecutive times

1 = resync if FAS or bit 2 of non–FAS is received in error 3

consecutive times

SYNCE

RCR1.1

RCR1.0

Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

RESYNC

Resync. When toggled from low to high, a resync is initiated.

Must be cleared and set again for a subsequent resync.

Table 6-1. SYNC/RESYNC CRITERIA

FRAME OR

MULTIFRAME

LEVEL

SYNC CRITERIA

RESYNC CRITERIA

ITU SPEC.

Three consecutive incorrect

FAS received

FAS present in frame N and

N + 2, and FAS not present in

frame N + 1

G.706

4.1.1

4.1.2

FAS

Alternate (RCR1.2=1) the

above criteria is met or three

consecutive incorrect bit 2 of

non–FAS received

915 or more CRC4 code

words out of 1000 received in

error

Two valid MF alignment

words found within 8 ms

G.706

CRC4

CAS

4.2 and 4.3.2

Valid MF alignment word

found and previous timeslot

16 contains code other than all

zeros

Two consecutive MF

alignment words received in

error

G.732 5.2

27 of 105

DS21Q44

RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)

(MSB)

(LSB)

Sa8S

Sa7S

Sa6S

POSITION

RCR2.7

Sa5S

Sa4S

RBCS

RESE

–

SYMBOL

Sa8S

NAME AND DESCRIPTION

Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit

position; set to zero to force RLCLK low during Sa8 bit

position. See Section 18 for timing details.

Sa7S

Sa6S

Sa5S

Sa4S

RBCS

RESE

–

RCR2.6

RCR2.5

RCR2.4

RCR2.3

RCR2.2

RCR2.1

RCR2.0

Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit

position; set to zero to force RLCLK low during Sa7 bit

position. See Section 18 for timing details.

Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit

position; set to zero to force RLCLK low during Sa6 bit

position. See Section 18 for timing details.

Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit

position; set to zero to force RLCLK low during Sa5 bit

position. See Section 18 for timing details.

Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit

position; set to zero to force RLCLK low during Sa4 bit

position. See Section 18 for timing details.

Receive Side Backplane Clock Select.

0 = if RSYSCLK is 1.544 MHz

1 = if RSYSCLK is 2.048 MHz

Receive Side Elastic Store Enable.

0 = elastic store is bypassed

1 = elastic store is enabled

Not Assigned. Should be set to zero when written.

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)

(MSB)

(LSB)

ODF

TFPT

T16S

POSITION

TCR1.7

TUA1

TSiS

TSA1

TSM

TSIO

SYMBOL

ODF

NAME AND DESCRIPTION

Output Data Format.

0 = bipolar data at TPOS and TNEG

1 = NRZ data at TPOS; TNEG=0

Transmit Timeslot 0 Pass Through.

TFPT

T16S

TCR1.6

TCR1.5

0 = FAS bits/Sa bits/Remote Alarm sourced internally from the

TAF and TNAF registers

1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

Transmit Timeslot 16 Data Select.

0 = sample timeslot 16 at TSER pin

1 = source timeslot 16 from TS0 to TS15 registers

28 of 105

DS21Q44

SYMBOL

POSITION

NAME AND DESCRIPTION

TUA1

TCR1.4

Transmit Unframed All Ones.

0 = transmit data normally

1 = transmit an unframed all one’s code at TPOS and TNEG

Transmit International Bit Select.

0 = sample Si bits at TSER pin

TSiS

TCR1.3

1 = source Si bits from TAF and TNAF registers (in this mode,

TCR1.6 must be set to 0)

TSA1

TSM

TCR1.2

CR1.1

Transmit Signaling All Ones.

0 = normal operation

1 = force timeslot 16 in every frame to all ones

TSYNC Mode Select.

0 = frame mode (see the timing in Section 18)

1 = CAS and CRC4 multiframe mode (see the timing in Section

18)

TSIO

TCR1.0

TSYNC I/O Select.

0 = TSYNC is an input

1 = TSYNC is an output

Note: See Figure 18–15 for more details about how the Transmit Control Registers affect the operation

of the DS21Q44.

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)

(MSB)

(LSB)

Sa8S

Sa7S

Sa6S

POSITION

TCR2.7

Sa5S

Sa4S

ODM

AEBE

PF

SYMBOL

NAME AND DESCRIPTION

Sa8S

Sa8 Bit Select. Set to one to source the Sa8 bit from the

TLINK pin; set to zero to not source the Sa8 bit. See Section

18 for timing details.

Sa7S

Sa6S

Sa5S

Sa4S

TCR2.6

TCR2.5

TCR2.4

TCR2.3

Sa7 Bit Select. Set to one to source the Sa7 bit from the

TLINK pin; set to zero to not source the Sa7 bit. See Section

18 for timing details.

Sa6 Bit Select. Set to one to source the Sa6 bit from the

TLINK pin; set to zero to not source the Sa6 bit. See Section

18 for timing details.

Sa5 Bit Select. Set to one to source the Sa5 bit from the

TLINK pin; set to zero to not source the Sa5 bit. See Section

18 for timing details.

Sa4 Bit Select. Set to one to source the Sa4 bit from the

TLINK pin; set to zero to not source the Sa4 bit. See Section

18 for timing details.

29 of 105

DS21Q44

SYMBOL

POSITION

NAME AND DESCRIPTION

Output Data Mode.

ODM

TCR2.2

0 = pulses at TPOS and TNEG are one full TCLK period wide

1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide

Automatic E–Bit Enable.

AEBE

PF

TCR2.1

TCR2.0

0 = E–bits not automatically set in the transmit direction

1 = E–bits automatically set in the transmit direction

Function of RLOS/LOTC Pin.

0 = Receive Loss of Sync (RLOS)

1 = Loss of Transmit Clock (LOTC)

CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)

(MSB)

(LSB)

FLB

THDB3

TG802

POSITION

CCR1.7

TCRC4

RSM

RHDB3

RG802

RCRC4

SYMBOL

FLB

NAME AND DESCRIPTION

Framer Loopback.

0=loopback disabled

1=loopback enabled

Transmit HDB3 Enable.

0=HDB3 disabled

THDB3

TG802

TCRC4

RSM

CCR1.6

CCR1.5

CCR1.4

CCR1.3

CCR1.2

CCR1.1

CCR1.0

1=HDB3 enabled

Transmit G.802 Enable. See Section 18 for details.

0=do not force TCHBLK high during bit 1 of timeslot 26

1=force TCHBLK high during bit 1 of timeslot 26

Transmit CRC4 Enable.

0=CRC4 disabled

1=CRC4 enabled

Receive Signaling Mode Select.

0=CAS signaling mode

1=CCS signaling mode

RHDB3

RG802

RCRC4

Receive HDB3 Enable.

0=HDB3 disabled

1=HDB3 enabled

Receive G.802 Enable. See Section 18 for details.

0=do not force RCHBLK high during bit 1 of timeslot 26

1=force RCHBLK high during bit 1 of timeslot 26

Receive CRC4 Enable.

0=CRC4 disabled

1=CRC4 enabled

30 of 105

DS21Q44

FRAMER LOOPBACK

When CCR1.7 is set to a one, the framer will enter a Framer LoopBack (FLB) mode. See Figure 1–1 for

more details. This loopback is useful in testing and debugging applications. In FLB, the framer will loop

data from the transmit side back to the receive side. When FLB is enabled, the following will occur:

1) Data will be transmitted as normal at TPOS and TNEG.

2) Data input via RPOS and RNEG will be ignored.

3) The RCLK output will be replaced with the TCLK input.

CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)

(MSB)

(LSB)

ECUS

VCRFS

AAIS

POSITION

CCR2.7

ARA

RSERC

LOTCMC

RFF

RFE

SYMBOL

NAME AND DESCRIPTION

ECUS

Error Counter Update Select. See Section 8 for details.

0=update error counters once a second

1=update error counters every 62.5 ms (500 frames)

VCR Function Select. See Section 8 for details.

0=count BiPolar Violations (BPVs)

VCRFS

AAIS

CCR2.6

CCR2.5

CCR2.4

CCR2.3

CCR2.2

1=count Code Violations (CVs)

Automatic AIS Generation.

0=disabled

1=enabled

ARA

Automatic Remote Alarm Generation.

0=disabled

1=enabled

RSERC

LOTCMC

RSER Control.

0=allow RSER to output data as received under all conditions

1=force RSER to one under loss of frame alignment conditions

Loss of Transmit Clock Mux Control. Determines whether

the transmit side formatter should switch to the ever present

RCLK if the TCLK should fail to transition (see Figure 1–1).

0=do not switch to RCLK if TCLK stops

1=switch to RCLK if TCLK stops

RFF

RFE

CCR2.1

CCR2.0

Receive Force Freeze. Freezes receive side signaling at RSIG

(and RSER if CCR3.3=1); will override Receive Freeze Enable

(RFE). See Section 10 or details.

0=do not force a freeze event

1=force a freeze event

Receive Freeze Enable. See Section 10 for details.

0=no freezing of receive signaling data will occur

1=allow freezing of receive signaling data at RSIG (and RSER

if CCR3.3=1).

31 of 105

DS21Q44

AUTOMATIC ALARM GENERATION

The DS21Q44 can be programmed to automatically transmit AIS or Remote Alarm. When automatic

AIS generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the

following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception,

or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the

framer will transmit an AIS alarm.

When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to

determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm

(all one’s) reception, loss of receive carrier or if CRC4 multiframe synchronization (if enabled) cannot be

found within 128 ms of FAS synchronization. If any one (or more) of the above conditions is present,

then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a

constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization

within 400 ms as per G.706.

It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)

(MSB)

(LSB)

TESE

TCBFS

TIRFS

POSITION

CCR3.7

–

RSRE

THSE

TBCS

RCLA

SYMBOL

NAME AND DESCRIPTION

TESE

Transmit Side Elastic Store Enable.

0=elastic store is bypassed

1=elastic store is enabled

TCBFS

TIRFS

CCR3.6

CCR3.5

Transmit Channel Blocking Registers (TCBR) Function

Select.

0=TCBRs define the operation of the TCHBLK output pin

1=TCBRs define which signaling bits are to be inserted

Transmit Idle Registers (TIR) Function Select. See Section

11 for details.

0=TIRs define in which channels to insert idle code

1=TIRs define in which channels to insert data from RSER

(i.e., Per Channel Loopback function)

–

CCR3.4

CCR3.3

Not Assigned. Should be set to zero when written.

Receive Side Signaling Re–Insertion Enable. See Section 10

for details.

RSRE

0=do not re–insert signaling bits into the data stream presented

at the RSER pin

1=re–insert the signaling bits into data stream presented at the

RSER pin

THSE

CCR3.2

Transmit Side Hardware Signaling Insertion Enable. See

Section 10 for details.

0=do not insert signaling from the TSIG pin into the data

stream presented at the TSER pin

1=insert signaling from the TSIG pin into the data stream

presented at the TSER pin

32 of 105

DS21Q44

SYMBOL

POSITION

NAME AND DESCRIPTION

TBCS

CCR3.1

Transmit Side Backplane Clock Select.

0=if TSYSCLK is 1.544 MHz

1=if TSYSCLK is 2.048 MHz

RCLA

CCR3.0

Receive Carrier Loss (RCL) Alternate Criteria.

0=RCL declared upon 255 consecutive zeros (125 us)

1=RCL declared upon 2048 consecutive zeros (1 ms)

CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)

(MSB)

(LSB)

RLB

–

POSITION

CCR4.7

TCM4

TCM3

TCM2

TCM1

TCM0

SYMBOL

RLB

NAME AND DESCRIPTION

Remote Loopback.

0 = loopback disabled

1 = loopback enabled

–

CCR4.6

CCR4.5

CCR4.4

Not Assigned. Should be set to zero when written.

TCM4

Transmit Channel Monitor Bit 4. MSB of a channel decode

that deter-mines which transmit channel data will appear in the

TDS0M register. See Section 9 or details.

Transmit Channel Monitor Bit 3.

TCM3

TCM2

TCM1

TCM0

CCR4.3

CCR4.2

CCR4.1

CCR4.0

Transmit Channel Monitor Bit 2.

Transmit Channel Monitor Bit 1.

Transmit Channel Monitor Bit 0. LSB of the channel

decode.

CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)

(MSB)

(LSB)

–

RESALGN TESALGN

RCM4

NAME AND DESCRIPTION

Not Assigned. Should be set to zero when written

RCM3

RCM2

RCM1

RCM0

SYMBOL

POSITION

–

CCR5.7

CCR5.6

RESALGN

Receive Elastic Store Align. Setting this bit from a zero to a

one may force the receive elastic store’s write/read pointers to a

minimum separation of half a frame. No action will be taken if

the pointer separation is already greater or equal to half a frame.

If pointer separation is less then half a frame, the command will

be executed and data will be disrupted. Should be toggled after

RSYSCLK has been applied and is stable. Must be cleared and

set again for a subsequent align. See Section 13 for details.

33 of 105

DS21Q44

SYMBOL

POSITION

NAME AND DESCRIPTION

TESALGN

CCR5.5

Transmit Elastic Store Align. Setting this bit from a zero to a

one may force the transmit elastic store’s write/read pointers to

a minimum separation of half a frame. No action will be taken

if the pointer separation is already greater or equal to half a

frame. If pointer separation is less then half a frame, the

command will be executed and data will be disrupted. Should

be toggled after TSYSCLK has been applied and is stable.

Must be cleared and set again for a subsequent align. See

Section 13 for details.

RCM4

CCR5.4

Receive Channel Monitor Bit 4. MSB of a channel decode

that determines which receive channel data will appear in the

RDS0M register. See Section 9 for details.

RCM3

RCM2

RCM1

RCM0

CCR5.3

CCR5.2

CCR5.1

CCR5.0

Receive Channel Monitor Bit 3.

Receive Channel Monitor Bit 2.

Receive Channel Monitor Bit 1.

Receive Channel Monitor Bit 0. LSB of the channel decode.

CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)

(MSB)

(LSB)

–

TCLKSRC

RESR

TESR

SYMBOL

POSITION

NAME AND DESCRIPTION

–

CCR6.7

CCR6.6

CCR6.5

CCR6.4

CCR6.3

CCR6.2

Not Assigned. Should be set to zero when written

–

TCLKSRC

Transmit Clock Source Select. This function allows the user

to internally select RCLK as the clock source for the transmit

side formatter.

0 = Transmit side formatter clocked with signal applied at

TCLK pin. LOTC Mux function is operational (TCR1.7)

1 = Transmit side formatter clocked with RCLK.

Receive Elastic Store Reset. Setting this bit from a zero to a

one will force the receive elastic store to a depth of one frame.

Receive data is lost during the reset. Should be toggled after

RSYSCLK has been applied and is stable. Do not leave this bit

set high.

RESR

TESR

CCR6.1

CCR6.0

Transmit Elastic Store Reset. Setting this bit from a zero to a

one will force the transmit elastic store to a depth of one frame.

Transmit data is lost during the reset. Should be toggled after

TSYSCLK has been applied and is stable. Do not leave this bit

set high.

34 of 105

DS21Q44

7. STATUS AND INFORMATION REGISTERS

There is a set of seven registers per framer that contain information on the current real time status of a

framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register

(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.

The specific details on the four registers pertaining to the HDLC controller are covered in Section 15 but

they operate the same as the other status registers in the DS21Q44 and this operation is described below.

When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers

will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The

Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and

a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be

cleared when it is read and it will not be set again until the event has occurred again (or in the case of the

RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still

present).

The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte

written to the register will inform the framer which bits the user wishes to read and have cleared. The

user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and

a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is

written to a bit location, the read register will be updated with the latest information. When a zero is

written to a bit position, the read register will not be updated and the previous value will be held. A write

to the status and information registers will be immediately followed by a read of the same register. The

read result should be logically AND’ed with the mask byte that was just written and this value should be

written back into the same register to insure that bit does indeed clear. This second write step is

necessary because the alarms and events in the status registers occur asynchronously in respect to their

access via the parallel port. This write–read– write scheme allows an external microcontroller or

microprocessor to individually poll certain bits without disturbing the other bits in the register. This

operation is key in controlling the DS21Q44 with higher–order software languages.

The SSR register operates differently than the other three. It is a read only register and it reports the

status of the synchronizer in real time. This register is not latched and it is not necessary to precede a

read of this register with a write.

The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*

output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked

from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and

HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 15.

The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act

differently than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA,

RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts

will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive

according to the set/clear criteria in Table 7-1). The INT* pin will be allowed to return high (if no other

interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is

still present, the register bit will remain set.

The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be

allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the

interrupt to occur.

35 of 105

DS21Q44

ISR: INTERRUPT STATUS REGISTER (Any address from 0C0 Hex to 0FF Hex)

(MSB)

(LSB)

F3HDLC

F3SR

F2HDLC

POSITION

ISR.7

F2SR

F1HDLC

F1SR

F0HDLC

F0SR

SYMBOL

NAME AND DESCRIPTION

F3HDLC

FRAMER 3 HDLC CONTROLLER INTERRUPT

REQUEST.