DS2250T64-16 [MAXIM]
8-BIT, 16MHz, MICROCONTROLLER, SMA40, SIMM-40;
| 型号： | DS2250T64-16 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 8-BIT, 16MHz, MICROCONTROLLER, SMA40, SIMM-40 时钟 外围集成电路 |
| 文件： | 总18页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2250(T)
Soft Microcontroller Module
www.maxim-ic.com
DESCRIPTION
FEATURES
The DS2250(T) soft microcontroller module is a ꢀ 8-Bit 8051-Compatible Microcontroller
fully 8051-compatible 8-bit CMOS microcontroller that
offers “softness” in all aspects of its application.
This is accomplished through the comprehensive
use of nonvolatile technology to preserve all
information in the absence of system VCC. The
Adapts to Task-At-Hand
8, 32, or 64kbytes of Nonvolatile RAM for
Program and/or Data Memory Storage
Initial Downloading of Software in End System
via On-Chip Serial Port
internal
program/data
memory
space
is
Capable of Modifying its Own Program and/or
Data Memory in End Use
implemented using 8, 32, or 64kbytes of nonvolatile
CMOS SRAM. Furthermore, internal data registers ꢀ High-Reliability Operation
and key configuration registers are also nonvolatile.
An optional real-time clock gives permanently
powered timekeeping. The clock keeps time to a
hundredth of a second using an on-board crystal.
All nonvolatile memory and resources are
maintained for over 10 years at room temperature in
the absence of power.
Maintains All Nonvolatile Resources Up to 10
Years in the Absence of VCC at Room
Temperature
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer
ꢀ
Software Security Feature
Executes Encrypted Software to Prevent
Unauthorized Disclosure
PIN CONFIGURATION
ꢀ
ꢀ
ꢀ
ꢀ
On-Chip, Full-Duplex Serial I/O Ports
Two On-Chip Timer/Event Counters
32 Parallel I/O Lines
Compatible with Industry Standard 8051
Instruction Set
1
20
21
40
ꢀ
Permanently Powered Real-Time Clock
Operating information is contained in the Secure Microcontroller
User’s Guide. This data sheet provides ordering information,
pinout, and electrical specifications.
40-Pin SIMM
ORDERING INFORMATION
PART
RAM SIZE (kB)
MAX CRYSTAL SPEED (MHz) TIMEKEEPING?
DS2250-32-16
DS2250-32-16+
DS2250-64-16
DS2250-64-16#
32
32
64
64
32
32
64
64
16
16
16
16
16
16
16
16
No
No
No
No
DS2250T-32-16
DS2250T-32-16+
DS2250T-64-16
DS2250T-64-16+
+ Denotes lead-free/RoHS-compliant package
Yes
Yes
Yes
Yes
# Denotes RoHS-compliant device that may contain lead exempt under the RoHS requirements.
1 of 18
REV: 060906
DS2250(T)
DS2250(T) BLOCK DIAGRAM Figure 1
2 of 18
DS2250(T)
PIN DESCRIPTION
PIN
DESCRIPTION
1, 3, 5, 7, 9,
P1.0 - P1.7. General purpose I/O Port 1
11, 13, 15
17
RST - Active high reset input. A logic 1 applied to this pin will activate a reset state.
This pin is pulled down internally so this pin can be left unconnected if not used. An
RC power-on reset circuit is not needed and is not recommended.
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the
19
21
23
25
on board UART. This pin should not be connected directly to a PC COM port.
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the
on board UART. This pin should not be connected directly to a PC COM port.
P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
27
29
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded
31
bus operation.
P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded
33
bus operation.
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator.
35, 37
39
XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
GND - Logic ground.
26, 28, 30, 32, P2.7-P2.0. General purpose I/O Port 2. Also serves as the MSB of the Expanded
34, 36, 38, 40 Address bus.
PSEN - Program Store Enable. This active low signal is used to enable an external
program memory when using the Expanded bus. It is normally an output and should
be unconnected if not used. PSEN also is used to invoke the Bootstrap Loader. At this
24
time, PSEN will be pulled down externally. This should only be done once the
DS2250(T) is already in a reset state. The device that pulls down should be open-drain
since it must not interfere with PSEN under normal operation.
ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded
Address/Data bus on Port 0. This pin is normally connected to the clock input on a
22
’373 type transparent latch. When using a parallel programmer, this pin also assumes
the PROG function for programming pulses.
EA - External Access. This pin forces the DS2250(T) to behave like an 8031. No
internal memory (or clock) will be available when this pin is at a logic low. Since this
20
pin is pulled down internally, it should be connected to +5V to use NV RAM. In a
parallel programmer, this pin also serves as VPP for super voltage pulses.
P0.0-P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a
4, 6, 8, 10, 12,
logic 1. It requires external pullups. Port 0 is also the multiplexed Expanded
14, 16, 18
Address/Data bus. When used in this mode, it does not require pullups.
2
VCC + - 5 volts.
3 of 18
DS2250(T)
INSTRUCTION SET
The DS2250(T) executes an instruction set which is object code-compatible with the industry standard
8051 microcontroller. As a result, software development packages which have been written for the 8051
are compatible with the DS2250(T), including cross-assemblers, high-level language compilers, and
debugging tools. Note that the DS2250(T) is functionally identical to the DS5000(T) except for package
and the 64k memory option.
A complete description for the DS2250(T) instruction set is available in the Secure Microcontroller
User’s Guide.
MEMORY ORGANIZATION
Figure 2 illustrates the address spaces which are accessed by the DS2250(T). As illustrated in the figure,
separate address spaces exist for program and data memory. Since the basic addressing capability of the
machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be
accessed by the DS2250(T) CPU. The 8- or 32-kbyte RAM area inside of the DS2250(T) can be used to
contain both program and data memory. A second 32k RAM is available for data only.
The Real Time Clock (RTC) in the DS2250(T) is reached in the memory map by setting a SFR bit. The
MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2=1, all MOVXs will be
routed to this alternate memory map. The real time clock is a serial device that resides in this area. A full
description of the RTC access and example software is given in the Secure Microcontroller User’s Guide.
DS2250(T) MEMORY MAP Figure 2
DATA MEMORY (MOVX)
4 of 18
DS2250(T)
PROGRAM LOADING
The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization
may be performed in one of two ways:
1. Serial Program Loading which is capable of performing Bootstrap Loading of the DS2250(T). This
feature allows the loading of the application program to be delayed until the DS2250(T) is installed in
the end system.
2. Parallel Program Load cycles which perform the initial loading from parallel address/data information
presented on the I/O port pins. This mode is timing set-compatible with the 87C51H microcontroller
programming mode.
The DS2250(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the
RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS2250(T)
will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at
9600, 2400, 1200, or 300 bps over the serial port.
The hardware configurations used to select these modes of operation are illustrated in Figure 3.
PROGRAM LOADING CONFIGURATIONS Figure 3
5 of 18
DS2250(T)
SERIAL BOOTSTRAP LOADER
The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of
initially loading application software into the DS2250(T) nonvolatile RAM. Communication can be
performed over a standard asynchronous serial communications port. A typical application would use a
simple RS232C serial interface to program the DS2250(T) as a final production procedure. The hardware
configuration which is required for the Serial Program Load Mode is illustrated in Figure 3. Port pins 2.7
and 2.6 must be either open or pulled high to avoid placing the device in a parallel load cycle. Although
an 11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are
supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a
standard UART. The receive, transmit, and ground wires are all that are necessary to establish
communication with the DS2250(T).
The Serial Bootstrap Loader implements an easy-to-use command line interface which allows an
application program in an Intel hex representation to be loaded into and read back from the device. Intel
hex is the typical format which existing 8051 cross-assemblers output. The serial loader responds to
single character commands which are summarized below:
COMMAND
FUNCTION
C
D
F
Return CRC-16 checksum of embedded RAM
Dump Intel hex File
Fill embedded RAM block with constant
Load 40-bit encryption key
Load Intel hex file
K
L
R
T
Read MCON register
Trace (Echo) incoming Intel hex data
Clear Security Lock
U
V
W
Z
Verify Embedded RAM with incoming Intel hex
Write MCON register
Set security lock
P
Put a value to a port
G
Get a value from a port
Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated
with these cycles is illustrated in the electrical specs.
PARALLEL PROGRAM LOAD CYCLES Table 1
MODE
Program
Security Set
RST
P2.7
P2.6
P2.5
X
X
X
0
0
1
1
PSEN
PROG
EA
VPP
VPP
1
VPP
1
1
1
1
1
1
1
1
0
0
X
0
0
0
0
0
0
X
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
Verify
Prog Expanded
Verify Expanded
Prog MCON or Key registers
Verify MCON registers
VPP
1
6 of 18
DS2250(T)
The Parallel Program cycle is used to load a byte of data into a register or memory location within the
DS2250(T). The Verify cycle is used to read this byte back for comparison with the originally loaded
value to verify proper loading. The Security Set cycle may be used to enable and the software security
feature. One may also enter bytes for the MCON register or for the five encryption registers using the
Program MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1
and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be
verified using the Verify MCON cycle.
When the DS2250(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in
the Program Load Mode following a power-on reset, the internal hardware of the device is initialized so
that an existing 4-kbyte program can be programmed into a DS2250(T) with little or no modification.
This initialization automatically sets the range address for 8 kbytes and maps the lowest 4-kbyte bank of
embedded RAM as program memory. The next 4 kbytes of embedded RAM are mapped as data memory.
In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be
used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32 kbyte
Program/Verify cycles take much longer than the normal 4 kbyte Program/Verify cycles.
A typical parallel loading session would follow this procedure. First, set the contents of the MCON
register with the correct range and partition only if using expanded programming cycles. Next, the
encryption registers can be loaded to enable encryption of the program/data memory (not required). Then,
program the DS2250(T) using either normal or expanded program cycles and check the memory contents
using Verify cycles. The last operation would be to turn on the security lock feature by either a Security
Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.
SERIAL LOADER BAUD RATES FOR
DIFFERENT CRYSTAL FREQUENCIES Table 2
BAUD RATE
2400 9600
CRYSTAL FREQ
(MHz)
300
1200
Y
Y
Y
Y
19200
Y
57600
14.7456
11.0592
9.21600
7.37280
5.52960
1.84320
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
ADDITIONAL INFORMATION
A complete description for all operational aspects of the DS2250(T) is provided in the Secure
Microcontroller User’s Guide.
DEVELOPMENT SUPPORT
The DS89C450-K00 evaluation kit can be used to develop and test user code. It allows the user to
download Intel hex formatted code to the DS2250(T) from a PC. The user must purchase the DS2250 and
DS9072-40V mechanical adapter separately. Refer to the Secure Microcontroller User’s Guide for further
details.
7 of 18
DS2250(T)
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +7.0V
Operating Temperature Range………………………………………………………………...0°C to +70°C
Storage Temperature………………………………………………………………………...-40°C to +70°C
Soldering Temperature………………………………………………………………+260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
DC CHARACTERISTICS
(VCC = 5V ±5%, TA = 0°C to +70°C.)
PARAMETER
SYMBOL MIN
TYP
MAX
+0.8
VCC+0.3
VCC+0.3
0.45
UNITS NOTES
Input Low Voltage
Input High Voltage
Input High Voltage RST, XTAL1
VIL
VIH1
VIH2
VOL1
-0.3
2.0
3.5
V
V
V
V
1
1
1
Output Low Voltage
0.15
0.15
4.8
@ IOL=1.6 mA (Ports 1, 2, 3)
Output Low Voltage
@ IOL=3.2 mA (Ports 0, ALE, PSEN )
Output High Voltage
@ IOH=-80 µA (Ports 1, 2, 3)
Output High Voltage
@ IOH=-400 µA (Ports 0, ALE, PSEN )
VOL2
VOH1
VOH2
IIL
0.45
V
V
V
1
1
1
2.4
2.4
4.8
Input Low Current VIN = 0.45V
-50
-500
±10
µA
µA
µA
(Ports 1, 2, 3)
Transition Current; 1 to 0
VIN=2.0V (Ports 1, 2, 3)
ITL
Input Leakage Current
IL
0.45 < VIN < VCC (Port 0)
RRE
ISM
VPFW
VCCmin
VPP
40
125
80
4.75
4.65
13
RST, EA Pulldown Resistor
Stop Mode Current
Power Fail Warning Voltage
Minimum Operating Voltage
kΩ
µA
V
V
V
4
1
1
1
4.15
4.05
12.5
4.6
4.5
Programming Supply Voltage
(Parallel Program Mode)
Program Supply Current
IPP
ICC
15
20
mA
mA
Operating Current DS2250-8k
43
48
54
2
3
DS2250-32k @ 12 MHz
DS2250(T)-64-16 @ 16 MHz
Idle Mode Current @ 8 MHz
ICC
6.2
mA
8 of 18
DS2250(T)
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS
(VCC = 5V ±5%, TA = 0°C to +70°C.)
#
1
2
3
4
5
PARAMETER
SYMBOL
1/tCLK
MIN
1.0
2tCLK -40
tCLK -40
tCLK -35
MAX
16 (-16)
UNITS
MHz
ns
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In
tALPW
tAVALL
tAVAAV
tALLVI
ns
ns
ns
@ 12 MHz
@ 16 MHz
4tCLK -150
4tCLK -90
6
7
8
tALLPSL
tPSPW
tPSLVI
tCLK -25
3tCLK -35
ns
ns
ns
ns
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instr. In
3tCLK -150
3tCLK -90
@ 12 MHz
@ 16 MHz
9
10
11
tPSIV
tPSIX
tPSAV
tAVVI
0
ns
ns
ns
Input Instr. Hold after PSEN Going High
Input Instr. Float after PSEN Going High
Address Hold after PSEN Going High
tCLK -20
tCLK -8
12 Address Valid to Valid Instr. In @ 12 MHz
5tCLK -150
5tCLK -90
ns
@ 16 MHz
ns
13
14
15
16
tPSLAZ
tRDPW
tWRPW
tRDLDV
0
ns
ns
ns
ns
ns
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
6tCLK -100
6tCLK -100
5tCLK -165
5tCLK -105
RD Low to Valid Data In
@ 12 MHz
@ 16 MHz
17
18
tRDHDV
tRDHDZ
tALLVD
0
ns
ns
Data Hold after RD High
Data Float after RD High
2tCLK -70
19 ALE Low to Valid Data In
@ 12 MHz
@ 16 MHz
8CLK -150
ns
8tCLK -90
ns
20 Valid Addr. to Valid Data In
@ 12 MHz
tAVDV
9tCLK -165
9tCLK -105
ns
ns
@ 16 MHz
21
22
23
24
tALLRDL
tAVRDL
tDVWRL
tDVWRH
3tCLK -50
4tCLK -130
tCLK -60
7tCLK -150
7tCLK -90
3tCLK +50
ns
ns
ns
ns
ns
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Going Low
Data Valid to WR High
@ 12 MHz
@ 16 MHz
25
26
27
tWRHDV
tRDLAZ
tRDHALH
tCLK -50
ns
ns
ns
Data Valid after WR High
RD Low to Address Float
RD or WR High to ALE High
0
tCLK -40
tCLK +50
9 of 18
DS2250(T)
EXPANDED PROGRAM MEMORY READ CYCLE
EXPANDED DATA MEMORY READ CYCLE
10 of 18
DS2250(T)
EXPANDED DATA MEMORY WRITE CYCLE
EXTERNAL CLOCK TIMING
11 of 18
DS2250(T)
AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE
(VCC = 5V ±5%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
28 External Clock High Time
29 External Clock Low Time
30 External Clock Rise Time
31 External Clock Fall Time
@ 12 MHz
@ 16 MHz
tCLKHPW
20
ns
15
ns
@ 12 MHz
tCLKLPW
tCLKR
20
15
ns
ns
@ 16 MHz
@ 12 MHz
@ 16 MHz
20
15
ns
ns
@ 12 MHz
tCLKF
20
ns
ns
@ 16 MHz
15
AC CHARACTERISTICS—SERIAL PORT TIMING: MODE 0
(VCC = 5V ±5%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
tSPCLK
MIN
12tCLK
MAX
UNITS
µs
35 Serial Port Cycle Time
36 Output Data Setup to Rising Clock Edge
37 Output Data Hold after Rising Clock Edge
38 Clock Rising Edge to Input Data Valid
39 Input Data Hold after Rising Clock Edge
tDOCH
tCHDO
tCHDV
tCHDIV
10tCLK -133
2tCLK -117
ns
ns
ns
ns
10tCLK -133
0
SERIAL PORT TIMING: MODE 0
12 of 18
DS2250(T)
AC CHARACTERISTICS—POWER CYCLING TIMING
(VCC = 5V ±5%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
32 Slew Rate from VCCmin to 3.3V
tF
40
µs
33 Crystal Start-up Time
34 Power-On Reset Delay
tCSU
tPOR
(Note 5)
21504
tCLK
POWER CYCLE TIMING
13 of 18
DS2250(T)
AC CHARACTERISTICS—PARALLEL PROGRAM LOAD TIMING
(VCC = 5V ±5%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
1/tCLK
MIN
1.0
MAX
12.0
UNITS
MHz
40 Oscillator Frequency
41
42
43
44
tAVPRL
tPRHAV
tDVPRL
tPRHDV
tP27HVP
tVPHPRL
tPRHVPL
tPRW
0
0
0
0
0
0
0
2400
Address Setup to PROG Low
Address Hold after PROG High
Data Setup to PROG Low
Data Hold after PROG High
45 P2.7, 2.6, 2.5 Setup to VPP
46
47
48
VPP Setup to PROG Low
VPP Hold after PROG Low
PROG Width Low
tCLK
tCLK
49 Data Output from Address Valid
50 Data Output from P2.7 Low
51 Data Float after P2.7 High
tAVDV
48
1800*
tDVP27L
tP27HDZ
48
tCLK
tCLK
1800*
0
48
1800*
52
53
tPORPV
tRAVPH
21504
1200
tCLK
tCLK
Delay to Reset/ PSEN Active after Power On
Reset/ PSEN Active (or Verify Inactive) to
VPP High
54 VPP Inactive (Between Program Cycles)
55 Verify Active Time
tVPPPC
tVFT
1200
tCLK
tCLK
48
2400*
*Second set of numbers refers to expanded memory programming up to 32kbytes.
14 of 18
DS2250(T)
PARALLEL PROGRAM LOAD TIMING
CAPACITANCE
(Test Frequency = 1MHz, TA = +25°C.)
PARAMETER
SYMBOL MIN
TYP
MAX
10
10
UNITS NOTES
Output Capacitance
Input Capacitance
CO
CI
pF
pF
15 of 18
DS2250(T)
DS2250(T) TYPICAL ICC VS. FREQUENCY
FREQUENCY OF OPERATION (MHz)
(VCC = +5V, TA =+25°C)
NORMAL OPERATION IS MEASURED USING:
IDLE MODE OPERATION IS MEASURED USING:
1)
2)
3)
4)
EXTERNAL CRYSTALS ON XTAL1 AND 2.
ALL PORT PINS DISCONNECTED.
RST = 0V AND EA = VCC.
PART PERFORMING ENDLESS LOOP WRITING TO INTERNAL
MEMORY.
1) EXTERNAL CLOCK SOURCE AT XTAL1; XTAL2 FLOATING.
2) ALL PORT PINS DISCONNECTED.
3) RST = 0V AND EA = VCC
.
4) PART SET IN IDLE MODE BY SOFTWARE.
NOTES:
1. All voltages are referenced to ground.
2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR
,
,
t
CLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC.
3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven at 8 MHz with tCLKR
tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS.
4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not
connected; RST = VSS.
5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from
the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for the worst-case spec on this time.
16 of 18
DS2250(T)
PACKAGE DRAWING
PKG
DIM
A
INCHES
MIN
MAX
2.655
2.389
0.855
0.405
0.255
2.645
2.379
0.845
0.395
0.245
B
C
D
E
F
0.050 BSC
G
H
0.075
0.245
0.085
0.255
I
0.950 BSC
J
0.120
1.320
1.445
0.057
-
0.130
1.330
1.455
0.067
0.160
0.195
0.054
K
L
M
N
O
P
-
0.047
17 of 18
DS2250(T)
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/13/95 and 08/16/96 version of the DS2250(T)
data sheet. Please review this summary carefully.
1. Correct Figure 3 to show RST active high.
2. Add minimum value to PCB thickness.
The following represent the key differences between 11/20/99 and 06/09/06 version of the DS2250(T)
data sheet. Please review this summary carefully.
1. Updated reference (Features) to 10-year NV RAM data life to include room temperature caveat.
2. Added lead-free package information to the Ordering Information table.
3. Removed 8kB package versions from Ordering Information table.
4. Removed references to “Secure Microcontroller Data Book” and changed them to “Secure
Microcontroller User’s Guide.”
5. Removed references to DS5000TK.
18 of 18
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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