DS2251T-64-16# [MAXIM]
Microcontroller, 8-Bit, 16MHz, CMOS, ROHS COMPLIANT, SIMM-72;
| 型号： | DS2251T-64-16# |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microcontroller, 8-Bit, 16MHz, CMOS, ROHS COMPLIANT, SIMM-72 时钟 微控制器 外围集成电路 |
| 文件： | 总22页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2251T
128k Soft Microcontroller Module
www.maxim-ic.com
FEATURES
PIN CONFIGURATION
ꢀ 8051-Compatible Microcontroller Adapts
to Its Task
32, 64, or 128kbytes of Nonvolatile SRAM
for Program and/or Data Storage
In-System Programming via On-Chip Serial
Port
Capable of Modifying its Own Program or
Data Memory in the End System
Provides Separate Byte-Wide Bus for
Peripherals
Performs CRC-16 Check of NV RAM
Memory
ꢀ High-Reliability Operation
Maintains All Nonvolatile Resources Up to
10 Years in the Absence of VCC at Room
Temperature
Power-Fail Reset
Early Warning Power-fail Interrupt
Watchdog Timer
Lithium Backed Memory Remembers System
State
Precision Reference for Power Monitor
ꢀ Fully 8051-Compatible
128 Bytes Scratchpad RAM
Two Timer/Counters
On-Chip Serial Port
32 Parallel I/O Port Pins
ꢀ Permanently Powered Real-Time Clock
72-Pin SIMM
DESCRIPTION
The DS2251T 128k soft microcontroller module is an 8051-compatible microcontroller module based on
nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory.
Like other members of the secure microcontroller family, it provides full compatibility with the 8051
instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can
program, then reprogram the microcontroller while in-system. The application software can even change
its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc.
In addition, by using NV RAM, the DS2251T is ideal for data logging applications. The powerful real-
time clock includes interrupts for time stamp and date. It keeps time to one-hundredth of seconds using its
on-board 32kHz crystal.
1 of 22
REV: 061306
DS2251T
The DS2251T provides the benefits of NV RAM without using I/O resources. Between 32 kbytes and 128
kbytes of onboard NV RAM are available. A non-multiplexed Byte-wide address and data bus is used for
memory access. This bus, which is available at the connector, can perform all memory access and also
provide decoded chip enables for off-board memory mapped peripherals. This leaves the 32 I/O port pins
free for application use.
The DS2251T provides high-reliability operation in portable systems or systems with unreliable power.
These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and
Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room
temperature in the absence of power.
A user loads programs into the DS2251T via its on-chip serial Bootstrap loader. This function supervises
the loading of software into NV RAM, validates it, then becomes transparent to the user. Software is
stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2251T can divide a common
RAM into user-selectable program and data segments. This Partition can be selected at program loading
time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM,
access memory via its Byte-wide bus and write-protect the memory portion designated as program
(ROM).
Operating information is contained in the Secure Microcontroller User’s Guide. This data sheet provides
ordering information, pinout, and electrical specifications.
ORDERING INFORMATION
MAX CRYSTAL
PART
RAM SIZE (kB)
TIMEKEEPING?
SPEED (MHz)
DS2251T-32-16
DS2251T-32-16#
DS2251T-64-16
DS2251T-64-16#
DS2251T-128-16
DS2251T-128-16#
32
32
64
64
128
128
16
16
16
16
16
16
Yes
Yes
Yes
Yes
Yes
Yes
# Denotes a RoHS-compliant package that may contain lead exempt under the RoHS requirements.
2 of 22
DS2251T
DS2251T BLOCK DIAGRAM Figure 1
3 of 22
DS2251T
PIN ASSIGNMENT
PIN
1
NAME
P1.0
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NAME
XTAL2
GND
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
PIN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NAME
P0.2
P0.1
P0.0
VCC
PIN
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NAME
INTB
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
R/ W
PF
2
P1.1
3
P1.2
4
P1.3
5
P1.4
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
P3.0/RXD
P3.1/TXD
P3.2/ INT0
P3.3/ INT1
P3.4/T0
P3.5/T1
P3.6/ WR
P3.7/ RD
XTAL1
P2.7
PSEN
ALE
PROG
P0.7
P0.6
P0.5
PE3
PE4
INTP
INTA
SQW
VRST
BA15
P0.4
P0.3
PIN DESCRIPTION
PIN
DESCRIPTION
P0.0–P0.7. General-purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It
39–32 requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. When
used in this mode, it does not require pullups.
1–8
P1.0–P1.7. General-purpose I/O Port 1.
P2.0–P2.7. General-purpose I/O Port 2. Also serves as the MSB of the Expanded Address
21–28
bus.
P3.0/RXD. General-purpose I/O port pin 3.0. Also serves as the receive signal for the on-
10
11
12
board UART. This pin should NOT be connected directly to a PC COM port.
P3.1/TXD. General-purpose I/O port pin 3.1. Also serves as the transmit signal for the on-
board UART. This pin should NOT be connected directly to a PC COM port.
P3.2/INT0 . General-purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
P3.3/INT1 . General-purpose I/O port pin 3.3. Also serves as the active low External
13
14
Interrupt 1.
P3.4/T0. General-purpose I/O port pin 3.4. Also serves as the Timer 0 input.
4 of 22
DS2251T
PIN
DESCRIPTION
15
P3.5/T1. General-purpose I/O port pin 3.5. Also serves as the Timer 1 input.
P3.6/ WR . General-purpose I/O port pin. Also serves as the write strobe for Expanded bus
16
17
operation.
P3.7/ RD . General-purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
RST. Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit
is not needed and is NOT recommended.
9
PSEN . Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected
if not used.
29
ALE. Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent
latch.
30
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
19, 18
the input to an inverting amplifier and XTAL2 is the output.
20
40
72
GND. Logic ground.
VCC. +5V
BA15. Monitor test point to reflect the logical value of A15. Not needed for memory access.
BA13–BA 0. Byte-wide Address bus bits 13–0. This bus is combined with the non-
multiplexed data bus (BD7–BD0) to access onboard NV SRAM and off-board peripherals.
Peripheral decoding is performed using PE3 and PE4 . These are on 16k boundaries, so
BA14 or BA15 are not needed. Read/write access is controlled by R/ W . BA13–BA0 connect
directly to memory-mapped peripherals.
54–41
BD7–BD0. Byte-wide Data Bus Bits 7–0. This 8-bit bi-directional bus is combined with the
63–56 non-multiplexed address bus (BA14–BA0) to access on-board NV SRAM and off-board
peripherals.
R/ W . Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
bus. It is controlled by the memory map and Partition. The blocks selected as Program
64
(ROM) will be write-protected. This signal is also used for the write enable to off-board
peripherals.
PE3 . Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
66
67
31
when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any
type of peripheral function.
PE4 . Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any
type of peripheral function.
PROG . Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading
on power-up. This signal is pulled up internally.
5 of 22
DS2251T
PIN
DESCRIPTION
VRST . This I/O pin (open-drain with internal pullup) indicates that the power supply (VCC)
has fallen below the VCCMIN level and the micro is in a reset state. When this occurs, the
DS2251T will drive this pin to a logic 0. Because the micro is lithium backed, this signal is
guaranteed even when VCC = 0V. Because it is an I/O pin, it will also force a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
71
PF . This output goes to a logic 0 to indicate that the micro has switched to lithium backup.
It corresponds to VCC < VLI. Because the micro is lithium backed, this signal is guaranteed
even when VCC = 0V.
65
INTB . INTB from the real-time clock. This output may be connected to a micro interrupt
55
68
69
70
input.
INTP . INTP from the real-time clock. This open-drain output requires a pullup and may be
connected to a micro interrupt input.
INTA . INTA from the real-time clock. This output may be connected to a micro interrupt
input.
SQW. Square-wave output from the DS1283 real-time clock. Can be programmed to output
a 1024Hz square wave.
INSTRUCTION SET
The DS2251T executes an instruction set that is object code compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS2251T.
A complete description of the instruction set and operation are provided in the Secure Microcontroller
User’s Guide.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS2251T. The entire 64k of program and 64k of
data are available to the byte-wide bus. This preserves the I/O ports for application use. The user controls
the portion of memory that is actually mapped to the byte-wide bus by selecting the Program Range and
Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2.
An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Selecting
PES = 1 provides access to the real-time clock on the DS2251T and enables PE3 and PE4 for peripheral
access as shown in Figure 4. These selections are made using Special Function Registers. The memory
map and its controls are covered in detail in the Secure Microcontroller User’s Guide.
6 of 22
DS2251T
DS2251T MEMORY MAP IN NON-PARTITIONABLE MODE (PM = 1) Figure 2
DS2251T MEMORY MAP IN PARTITIONABLE MODE (PM = 0) Figure 3
7 of 22
DS2251T
DS2251T MEMORY MAP WITH (PES = 1) Figure 4
POWER MANAGEMENT
The DS2251T monitors VCC to provide power-fail reset, early warning power-fail interrupt, and
switchover to lithium backup. It uses an internal band-gap reference in determining the switch points.
These are called VPFW, VCCMIN, and VLI, respectively. When VCC drops below VPFW, the DS2251T will
perform an interrupt vector to location 2Bh if the power-fail warning is enabled. Full processor operation
continues regardless. When power falls further to VCCMIN, the DS2251T invokes a reset state. No further
code execution will be performed unless power rises back above VCCMIN. All decoded chip enables and
the R/ W signal go to an inactive (logic 1) state. The VRST signal will be driven to a logic 0. VCC is still
the power source at this time. When VCC drops further to below VLI, internal circuitry will switch to the
built-in lithium cell for power. The majority of internal circuits will be disabled and the remaining
nonvolatile states will be retained. PF will be driven to a logic 0. The Secure Microcontroller User’s
Guide has more information on this topic. The trip points VCCMIN and VPFW are listed in the electrical
specifications.
8 of 22
DS2251T
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………...-0.3V to (VCC + 0.5V)
Voltage Range on VCC Relative to Ground………………………………………………….-0.3V to +6.0V
Operating Temperature Range………………………………………………………………-40°C to +85°C
Storage Temperature (Note 1)……………………………………………………………..-55°C to +125°C
Soldering Temperature………………………………………………………………+260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
Note 1: Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this state
the contents of SRAM are not battery backed and are undefined.
DC CHARACTERISTICS
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
PARAMETER
SYMBOL MIN TYP
MAX
+0.8
VCC+0.3
VCC+0.3
UNITS NOTES
Input Low Voltage
Input High Voltage
Input High Voltage RST, XTAL1 PROG
VIL
VIH1
VIH2
-0.3
2.0
3.5
V
V
V
1
1
1
Output Low Voltage
VOL1
VOL2
VOH1
0.15
0.15
4.8
0.45
V
V
V
1, 7
at IOL = 1.6mA (Ports 1, 2, 3, PF )
Output Low Voltage
0.45
1
at IOL = 3.2mA (Ports 0, ALE, PSEN ,
BA13:BA0, BD7:BD0, R/W, PE3:PE4)
Output High Voltage
at IOH = -80µA (Ports 1, 2, 3)
Output High Voltage
at IOH = -400µA (Ports 0, ALE, PSEN ,
PF , BA13:BA0, BD7:BD0, R/W,
PE3:PE4)
2.4
2.4
1
VOH2
4.8
V
1
Input Low Current
IIL
ITL
IIL
-50
µA
µA
µA
VIN = 0.45V (Ports 1, 2, 3)
Transition Current; 1 to 0
-500
VIN = 2.0V (Ports 1, 2, 3)
Input Leakage Current
±10
0.45 < VIN < VCC (Port 0)
RST Pulldown Resistor
VRST Pullup Resistor
PROG Pullup Resistor
Power-Fail Warning Voltage
Minimum Operating Voltage
Operating Current at 16MHz
RRE
RVR
RPR
40
150
kΩ
kΩ
kΩ
V
V
mA
4.7
40
VPFW
VCC(MIN)
ICC
4.25 4.37
4.00 4.12
4.50
4.25
45
1
1
2
9 of 22
DS2251T
DC CHARACTERISTICS (continued)
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
PARAMETER
SYMBOL MIN TYP
MAX
7.0
80
UNITS NOTES
Idle Mode Current at 12MHz
Stop Mode Current
Pin Capacitance
IIDLE
ISTOP
CIN
mA
µA
pF
3
4
5
10
With BAT =
4.0
4.4
4.25
4.65
3.0V
Reset Trip Point in
Stop Mode
V
1
With BAT =
3.3V
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
1
2
3
4
PARAMETER
SYMBOL
1/tCLK
tALPW
tAVALL
tAVAAV
MIN
1.0
2tCLK - 40
tCLK - 40
tCLK - 35
MAX
16 (-16)
UNITS
MHz
ns
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ns
ns
At 12MHz
At 16MHz
4tCLK - 150
4tCLK - 90
ALE Low to Valid Instruction
In
5
tALLVI
ns
6
7
tALLPSL
tPSPW
tCLK - 25
3tCLK - 35
ns
ns
ALE Low to PSEN Low
PSEN Pulse Width
At 12MHz
At 16MHz
3tCLK - 150
3tCLK - 90
PSEN Low to Valid
Instruction In
8
tPSLVI
ns
9
10
11
tPSIV
tPSIX
tPSAV
0
ns
ns
ns
Input Instr. Hold after PSEN Going High
Input Instr. Float after PSEN Going High
Address Hold after PSEN Going High
tCLK - 20
tCLK - 8
At 12MHz
At 16MHz
5tCLK - 150
5tCLK - 90
Address Valid to Valid
Instruction In
12
tAVVI
ns
13
14
15
tPSLAZ
tRDPW
tWRPW
0
ns
ns
ns
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
6tCLK - 100
6tCLK - 100
At 12MHz
At 16MHz
5tCLK - 165
5tCLK - 105
16
tRDLDV
ns
RD Low to Valid Data In
17
18
tRDHDV
tRDHDZ
tALLVD
0
ns
ns
ns
Data Hold after RD High
Data Float after RD High
2tCLK - 70
8CLK - 150
19 ALE Low to Valid Data In
At 12MHz
10 of 22
DS2251T
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS
(continued)
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
PARAMETER
#
SYMBOL
At 12MHz
At 16MHz
At 12MHz
At 16MHz
MIN
MAX
UNITS
8CLK - 150
8tCLK - 90
9tCLK - 165
9tCLK - 105
3tCLK + 50
19 ALE Low to Valid Data In
tALLVD
ns
ns
Valid Address to Valid Data
20
In
tAVDV
21
22
23
tALLRDL
tAVRDL
tDVWRL
3tCLK -50
4tCLK -130
tCLK - 60
ns
ns
ns
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Going Low
At 12MHz
At 16MHz
7tCLK - 150
7tCLK - 90
tCLK - 50
24
tDVWRH
ns
Data Valid to WR High
25
26
27
tWRHDV
tRDLAZ
tRDHALH
ns
ns
ns
Data Valid after WR High
RD Low to Address Float
RD or WR High to ALE High
0
tCLK - 40
tCLK + 50
EXPANDED PROGRAM MEMORY READ CYCLE
11 of 22
DS2251T
EXPANDED DATA MEMORY READ CYCLE
12 of 22
DS2251T
EXPANDED DATA MEMORY WRITE CYCLE
13 of 22
DS2251T
AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
At 12MHz
At 16MHz
20
28 External Clock High Time
tCLKHPW
ns
15
At 12MHz
At 16MHz
At 12MHz
At 16MHz
At 12MHz
At 16MHz
20
15
29 External Clock Low Time
30 External Clock Rise Time
31 External Clock Fall Time
tCLKLPW
tCLKR
ns
ns
ns
20
15
20
15
tCLKF
EXTERNAL CLOCK TIMING
14 of 22
DS2251T
AC CHARACTERISTICS—POWER CYCLE TIMING
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
32 Slew Rate from VCCMIN to 3.3V
tF
130
µs
33 Crystal Startup Time
34 Power-On Reset Delay
tCSU
tPOR
(Note 6)
21,504
tCLK
POWER CYCLE TIMING
15 of 22
DS2251T
AC CHARACTERISTICS—SERIAL PORT TIMING: MODE 0
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
tSPCLK
MIN
12tCLK
MAX
UNITS
µs
35 Serial Port Cycle Time
36 Output Data Setup to Rising Clock Edge
37 Output Data Hold after Rising Clock Edge
38 Clock Rising Edge to Input Data Valid
39 Input Data Hold after Rising Clock Edge
tDOCH
tCHDO
tCHDV
tCHDIV
10tCLK - 133
2tCLK - 117
ns
ns
ns
ns
10tCLK - 133
0
SERIAL PORT TIMING: MODE 0
16 of 22
DS2251T
AC CHARACTERISTICS—PARALLEL PROGRAM LOAD TIMING
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
41
tCEPW
4tCLK - 35
ns
Pulse Width of PE 3-4
Byte-wide Address Hold after PE 3-4 High
During MOVX
Delay from Byte-wide Address Valid PE 3-4
Low During MOVX
Byte-wide Data Setup to PE 3-4 High During
MOVX (read)
Byte-wide Data Hold after PE 3-4 High
During MOVX (read)
Byte-wide Address Valid to R/ W Active
During MOVX (write)
Delay from R/ W Low to Valid Data Out
During MOVX (write)
45
46
47
48
49
50
tCEHDA
tCELDA
tDACEH
tCEHDV
tAVRWL
tRWLDV
4tCLK - 30
4tCLK - 35
1tCLK + 40
10
ns
ns
ns
ns
ns
ns
3tCLK - 35
20
51
52
53
tCEHDV
tRWHDV
tRWLPW
1tCLK - 15
0
6tCLK - 20
ns
ns
ns
Valid Data Out Hold Time from PE 3-4 High
Valid Data Out Hold Time from R/ W High
Write Pulse Width (R/ W Low Time)
BYTE-WIDE BUS TIMING
17 of 22
DS2251T
RPC AC CHARACTERISTICS—DBB READ
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
tAR
MIN
0
0
MAX
UNITS
ns
54
55
56
57
58
59
CS , A0 Setup to RD
CS , A0 Hold After RD
RD Pulse Width
CS , A0 to Data Out Delay
RD to Data Out Delay
RD to Data Float Delay
tRA
tRR
tAD
tRD
ns
ns
ns
ns
160
130
130
85
0
tRDZ
ns
RPC AC CHARACTERISTICS—DBB WRITE
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
60
PARAMETER
SYMBOL
tAW
MIN
0
0
20
20
130
20
MAX
UNITS
ns
CS , A0 Setup to WR
CS , Hold After WR
A0, Hold After WR
WR Pulse Width
61A
61B
62
tWA
tWA
tWW
tDW
ns
ns
ns
ns
63
64
Data Setup to WR
Data Hold After WR
tWD
ns
AC CHARACTERISTICS—DMA
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
tACC
MIN
MAX
UNITS
65
66
67
68
0
0
0
ns
ns
ns
ns
DACK to WR or RD
RD or WR to DACK
DACK to Data Valid
RD or WR to DRQ Cleared
tCAC
tACD
tCRQ
130
110
AC CHARACTERISTICS—PROG
(VCC = 5V ±10%, TA = 0˚C to +70˚C.)
#
PARAMETER
SYMBOL
tPRA
MIN
48
48
MAX
UNITS
CLKS
CLKS
69
PROG Low to Active
PROG High to Inactive
70
tPRI
18 of 22
DS2251T
RPC TIMING MODE 16
RPC TIMING MODE 16 (continued)
19 of 22
DS2251T
NOTES:
1. All voltages are referenced to ground.
2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR
,
tCLKF=10ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC.
3. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF
=
10ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS.
4. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not
connected; RST = XTAL1 = VSS.
5. Pin capacitance is measured with a test frequency—1MHz, TA = +25°C.
6. Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the
time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst-case specification on this time.
7. PF pin operation is specified with VBAT ≥ 3.0V.
20 of 22
DS2251T
PACKAGE DRAWING
PKG
DIM
A
INCHES
MIN
MAX
4.255
3.989
1.005
0.405
0.255
4.245
3.979
0.995
0.395
0.245
B
C
D
E
F
0.050 BSC
G
H
0.075
0.245
0.085
0.255
I
1.750 BSC
J
0.120
2.120
2.245
0.057
-
0.130
2.130
2.255
0.067
0.275
0.145
0.054
K
L
M
N
O
P
-
0.047
21 of 22
DS2251T
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/13/95 and 08/13/96 version of the DS2251T data
sheet. Please review this summary carefully.
1. Change VCC slew rate definition to reference 3.3V instead of VLI.
2. Add minimum value to PCB thickness.
The following represent the key differences between 08/15/96 and 05/29/97 version of the DS2251T data
sheet. Please review this summary carefully.
1. PF signal moved from VOL2 test specification to VOL1. (PCND73001)
The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2251T data
sheet. Please review this summary carefully. (PCN I80903)
1. Correct Absolute Maximum Ratings to reflect changes to DS5001FP microprocessor.
2. Add note clarifying that SRAM contents are not defined under storage temperature conditions.
The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2251T data
sheet. Please review this summary carefully.
1. Document converted from interleaf to Microsoft Word.
The following represent the key differences between 01/18/00 and 06/13/06 version of the DS2251T data
sheet. Please review this summary carefully.
1. Updated reference in Features (High-Reliability Operation) to 10-year NV RAM data life to
include room temperature caveat.
2. Added RoHS-compliant packages to Ordering Information table.
3. Replaced references to “Secure Microcontroller Data Book” with “Secure Microcontroller User’s
Guide.”
22 of 22
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products • Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
相关型号：
©2020 ICPDF网 联系我们和版权申明