DS2431Q+R [MAXIM]
1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently; 1024位的1-Wire EEPROM独立的存储器页面可永久
| 型号： | DS2431Q+R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently |
| 文件： | 总26页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4675; Rev 10; 3/11
1024-Bit, 1-Wire EEPROM
DS2431
General Description
Features
♦ 1024 Bits of EEPROM Memory Partitioned Into
®
The DS2431 is a 1024-bit, 1-Wire EEPROM chip orga-
nized as four memory pages of 256 bits each. Data is
written to an 8-byte scratchpad, verified, and then
copied to the EEPROM memory. As a special feature, the
four memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. The DS2431 communi-
cates over the single-conductor 1-Wire bus. The commu-
nication follows the standard 1-Wire protocol. Each
device has its own unalterable and unique 64-bit ROM
registration number that is factory lasered into the chip.
The registration number is used to address the device in
a multidrop, 1-Wire net environment.
Four Pages of 256 Bits
♦ Individual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(“Write to 0”)
♦ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
♦ IEC 1000-4-2 Level 4 ESD Protection ( 8ꢀk
Contact, 15ꢀk ꢁir, ꢂypical)
♦ Reads and Writes Over a Wide koltage Range
from 2.8k to 5.25k from -40°C to +85°C
♦ Communicates to Host with a Single Digital
Signal at 15.4ꢀbps or 125ꢀbps Using 1-Wire
Protocol
Applications
Accessory/PCB Identification
♦ ꢁlso ꢁvailable as ꢁutomotive kersion Meeting
ꢁEC-Q100 Grade 1 Qualification Requirements
(DS2431-ꢁ1; Refer to the IC Data Sheet for
Details)
Medical Sensor Calibration Data Storage
Analog Sensor Calibration Including IEEE
P1451.4 Smart Sensors
Ink and Toner Print Cartridge Identification
After-Market Management of Consumables
Ordering Information
PART
DS2431+
TEMP RANGE PIN-PACKAGE
-40°C to +85°C 3 TO-92
-40°C to +85°C 3 TO-92
-40°C to +85°C 6 TSOC
Typical Operating Circuit
DS2431+T&R
DS2431P+
DS2431P+T&R -40°C to +85°C 6 TSOC
DS2431G+ -40°C to +85°C 2 SFN
V
CC
DS2431G+T&R -40°C to +85°C 2 SFN
R
PUP
DS2431Q+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs)
IO
DS2431X-S+
DS2431X+
-40°C to +85°C 3x3 UCSPR (2.5k pcs)
-40°C to +85°C 3x3 UCSPR (10k pcs)
DS2431
μC
Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For
details, refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
GND
*EP = Exposed pad.
Pin Configurations appear at end of data sheet.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1024-Bit, 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .......................................-0.5V to +6V
IO Sink Current ...................................................................20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (excluding UCSP, soldering, 10s).....+300°C
Soldering Temperature (reflow)
TO-92 ............................................................................+250°C
AIl other packages, excluding SFN ..............................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS2431
ELECTRICAL CHARACTERISTICS
(T = -40°C to +85°C.) (Note 1)
A
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
R
(Note 2)
2.8
0.3
5.25
2.2
V
PUP
PUP
(Notes 2, 3)
(Notes 4, 5)
kꢀ
pF
μA
C
1000
6.7
IO
L
Input Load Current
I
IO pin at V
0.05
0.5
PUP
V
-
PUP
1.8
High-to-Low Switching Threshold
Input Low Voltage
V
TL
(Notes 5, 6, 7)
(Notes 2, 8)
V
V
V
V
0.5
IL
V
-
PUP
1.0
Low-to-High Switching Threshold
V
TH
(Notes 5, 6, 9)
(Notes 5, 6, 10)
1.0
Switching Hysteresis
Output Low Voltage
V
V
0.21
1.70
0.4
V
V
HY
At 4mA (Note 11)
Standard speed, R
OL
= 2.2kꢀ
= 2.2kꢀ
5
2
PUP
Overdrive speed, R
Recovery Time
(Notes 2,12)
PUP
t
μs
REC
REH
Overdrive speed, directly prior to reset
pulse; R = 2.2kꢀ
5
PUP
Standard speed
Overdrive speed
Standard speed
Overdrive speed
0.5
5.0
Rising-Edge Hold-Off Time
(Notes 5, 13)
t
μs
μs
Not applicable (0)
65
Time Slot Duration
(Notes 2, 14)
t
SLOT
8
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
480
48
15
2
640
80
60
6
Reset Low Time (Note 2)
Presence-Detect High Time
Presence-Detect Low Time
t
μs
μs
μs
μs
RSTL
t
PDH
60
8
240
24
75
10
t
PDL
60
6
Presence-Detect Sample Time
(Notes 2, 15)
t
MSP
2
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
ELECTRICAL CHARACTERISTICS (continued)
(T = -40°C to +85°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Standard speed
60
5
120
15.5
15.5
15
Write-Zero Low Time
(Notes 2, 16, 17)
t
μs
μs
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
> 4.5V
W0L
PUP
6
1
Write-One Low Time
(Notes 2, 17)
t
W1L
1
2
IO PIN: 1-Wire READ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
15 - ꢁ
2 - ꢁ
15
Read Low Time
(Notes 2, 18)
t
μs
μs
RL
t
t
+ ꢁ
Read Sample Time
(Notes 2, 18)
RL
RL
t
MSR
+ ꢁ
2
EEPROM
Programming Current
Programming Time
I
t
(Notes 5, 19)
(Notes 20, 21)
At +25°C
0.8
10
mA
ms
PROG
PROG
200k
50k
Write/Erase Cycles (Endurance)
(Notes 22, 23)
N
CY
ꢂ
At +85°C (worst case)
Data Retention
(Notes 24, 25, 26)
t
At +85°C (worst case)
40
Years
DR
Note 1: Specifications at T = -40°C are guaranteed by design only and not production tested.
A
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Maximum value represents the internal parasite capacitance when V
is first applied. If a 2.2kΩ resistor is used to pull
PUP
up the data line, 2.5µs after V
has been applied, the parasite capacitance does not affect normal communications.
PUP
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: , V , and V are a function of the internal supply voltage, which is a function of V
V
, R , 1-Wire timing, and
PUP PUP
TL TH
HY
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values of
REC
PUP
PUP
V , V , and V
TL TH
.
HY
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic 0 level.
ILMAX
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V to be detected as logic 0.
TH
HY
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
after V has been reached on the preceding rising edge.
TH
REH
Note 14: Defines maximum possible bit rate. Equal to t
+ t
.
W0LMIN
RECMIN
Note 15: Interval after t
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS2431 present.
RSTL
Minimum limit is t
; maximum limit is t
+ t
.
PDHMAX
PDHMIN
PDLMIN
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V . The actual
IL
TH
maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
W0LMAX F
W1LMAX
F
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high
IL
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
RLMAX
F
_______________________________________________________________________________________
3
1024-Bit, 1-Wire EEPROM
Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to V
. If V
in the system is close to V
, a low-
PUPMIN
PUP
PUPMIN
impedance bypass of R , which can be activated during programming, may need to be added.
PUP
Note 20: Interval begins t
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
REHMAX
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by
the device has returned from I to I .
PROG
L
Note 21: t
for units branded version “A1” is 12.5ms. t
for units branded version “A2” and later is 10ms.
PROG
PROG
Note 22: Write-cycle endurance is degraded as T increases.
A
DS2431
Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as T increases.
A
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
COMPARISON TABLE
LEGACY VALUES
DS2431 VALUES
STANDARD SPEED
(μs)
OVERDRIVE SPEED
(μs)
STANDARD SPEED
(μs)
OVERDRIVE SPEED
(μs)
PARAMETER
MIN
61
MAX
MIN
7
MAX
MIN
65*
480
15
MAX
MIN
8*
48
2
MAX
t
t
t
t
t
(including t
)
(undefined)
(undefined)
60
(undefined)
(undefined)
640
(undefined)
SLOT
RSTL
PDH
PDL
REC
480
15
48
2
80
6
80
6
60
60
240
8
24
16
60
240
8
24
60
120
6
60
120
6
15.5
W0L
*Intentional change; longer recovery time requirement due to modified 1-Wire front-end.
Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.
4
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
Pin Description
PIN
NAME
FUNCTION
TSOC
TO-92
TDFN-EP
SFN
UCSPR
A2, A3, C2,
C3
3, 4, 5, 6
3
1, 4, 5, 6
—
N.C.
Not Connected
1-Wire Bus Interface. Open-drain signal
that requires an external pullup resistor.
2
1
2
1
2
3
1
2
C1
A1
IO
GND
Ground Reference
Exposed Pad. Solder evenly to the
board’s ground plane for proper
operation. Refer to Application Note
3273: Exposed Pads: A Brief
—
—
EP
—
—
EP
Introduction for additional information.
Detailed Description
The DS2431 combines 1024 bits of EEPROM, an
8-byte register/control page with up to 7 user read/write
bytes, and a fully featured 1-Wire interface in a single
chip. Each DS2431 has its own 64-bit ROM registration
number that is factory lasered into the chip to provide a
guaranteed unique identity for absolute traceability.
Data is transferred serially through the
1-Wire protocol, which requires only a single data lead
and a ground return. The DS2431 has an additional
memory area called the scratchpad that acts as a
buffer when writing to the main memory or the register
page. Data is first written to the scratchpad from which
it can be read back. After the data has been verified, a
Copy Scratchpad command transfers the data to its
final memory location. The DS2431 applications include
accessory/PCB identification, medical sensor calibra-
tion data storage, analog sensor calibration including
IEEE P1451.4 smart sensors, ink and toner print car-
tridge identification, and after-market management of
consumables.
PARASITE POWER
1-Wire
FUNCTION CONTROL
64-BIT
LASERED ROM
IO
DS2431
MEMORY
FUNCTION
CONTROL UNIT
CRC-16
GENERATOR
64-BIT
SCRATCHPAD
DATA MEMORY
4 PAGES OF
256 BITS EACH
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS2431. The DS2431 has four main data components:
64-bit lasered ROM, 64-bit scratchpad, four 32-byte
pages of EEPROM, and a 64-bit register page.
REGISTER PAGE
64 BITS
Figure 1. Block Diagram
_______________________________________________________________________________________
5
1024-Bit, 1-Wire EEPROM
AVAILABLE COMMANDS:
DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
DS2431 COMMAND LEVEL:
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
RC-FLAG
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
RC-FLAG, OD-FLAG
64-BIT REG. #, RC-FLAG, OD-FLAG
DS2431
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
DS2431-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSB
LSB
LSB
8-BIT
CRC CODE
8-BIT FAMILY CODE
(2Dh)
48-BIT SERIAL NUMBER
MSB
LSB MSB
LSB MSB
Figure 3. 64-Bit Lasered ROM
The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide
one of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, Resume,
Overdrive-Skip ROM, or Overdrive-Match ROM. Upon
completion of an Overdrive-Skip ROM or Overdrive-
Match ROM command byte executed at standard
speed, the device enters overdrive mode where all
subsequent communication occurs at a higher speed.
The protocol required for these ROM function com-
mands is described in Figure 9. After a ROM function
command is successfully executed, the memory func-
tions become accessible and the master can provide
any one of the four memory function commands. The
protocol for these memory function commands is
described in Figure 7. All data is read and written
least significant bit first.
64-Bit Lasered ROM
Each DS2431 contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated
using a polynomial generator consisting of a shift regis-
ter and XOR gates as shown in Figure 4. The polynomial
8
5
4
is X + X + X + 1. Additional information about the
1-Wire CRC is available in Application Note 27:
Understanding and Using Cyclic Redundancy Checks
®
with Maxim iButton Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the last bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
6
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
8
5
4
POLYNOMIAL = X + X + X + 1
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
0
1
2
3
4
5
6
7
8
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 4. 1-Wire CRC Generator
ally set to open (unprotected), write protected, or
EPROM mode by setting the associated protection byte
in the register row. The last two rows contain protection
registers and reserved bytes. The register row consists
of 4 protection control bytes, a copy-protection byte,
the factory byte, and 2 user byte/manufacture ID bytes.
The manufacturer ID can be a customer-supplied iden-
tification code that assists the application software in
identifying the product the DS2431 is associated with.
Memory Access
Data memory and registers are located in a linear
address space, as shown in Figure 5. The data memory
and the registers have unrestricted read access. The
DS2431 EEPROM array consists of 18 rows of 8 bytes
each. The first 16 rows are divided equally into four
memory pages (32 bytes each). These four pages are
the primary data memory. Each page can be individu-
ADDRESS RANGE
0000h to 001Fh
0020h to 003Fh
0040h to 005Fh
0060h to 007Fh
TYPE
R/(W)
R/(W)
R/(W)
R/(W)
DESCRIPTION
Data Memory Page 0
Data Memory Page 1
Data Memory Page 2
Data Memory Page 3
PROTECTION CODES
—
—
—
—
55h: Write Protect P0; AAh: EPROM Mode P0;
55h or AAh: Write Protect 80h
0080h*
0081h*
0082h*
0083h*
0084h*
0085h
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R
Protection Control Byte Page 0
Protection Control Byte Page 1
Protection Control Byte Page 2
Protection Control Byte Page 3
Copy Protection Byte
55h: Write Protect P1; AAh: EPROM Mode P1;
55h or AAh: Write Protect 81h
55h: Write Protect P2; AAh: EPROM Mode P2;
55h or AAh: Write Protect 82h
55h: Write Protect P3; AAh: EPROM Mode P3;
55h or AAh: Write Protect 83h
55h or AAh: Copy Protect 0080h:008Fh, and Any
Write-Protected Pages
AAh: Write Protect 85h, 86h, 87h;
55h: Write Protect 85h; Unprotect 86h, 87h
Factory Byte. Set at Factory.
0086h
0087h
R/(W)
R/(W)
—
User Byte/Manufacturer ID
User Byte/Manufacturer ID
Reserved
—
—
—
0088h to 008Fh
*Once programmed to AAh or 55h this address becomes read only. All other codes can be stored, but neither write protect the
address nor activate any function.
Figure 5. Memory Map
_______________________________________________________________________________________
7
1024-Bit, 1-Wire EEPROM
Contact the factory to set up and register a custom
manufacturer ID. The last row is reserved for future use.
It is undefined in terms of R/W functionality and should
not be used.
byte is set to 55h or AAh, all copy attempts to the regis-
ter row and user-byte row are blocked. In addition, all
copy attempts to write-protected main memory pages
(i.e., refresh) are blocked.
In addition to the main EEPROM array, an 8-byte
volatile scratchpad is included. Writes to the EEPROM
array are a two-step process. First, data is written to the
scratchpad and then copied into the main array. This
allows the user to first verify the data written to the
scratchpad prior to copying into the main array. The
device only supports full row (8-byte) copy operations.
For data in the scratchpad to be valid for a copy opera-
tion, the address supplied with a Write Scratchpad
command must start on a row boundary, and 8 full
bytes must be written into the scratchpad.
Address Registers and Transfer Status
The DS2431 employs three address registers: TA1, TA2,
and E/S (Figure 6). These registers are common to
many other 1-Wire devices but operate slightly different-
ly with the DS2431. Registers TA1 and TA2 must be
loaded with the target address to which the data is writ-
ten or from which data is read. Register E/S is a read-
only transfer-status register used to verify data integrity
with write commands. E/S bits E[2:0] are loaded with the
incoming T[2:0] on a Write Scratchpad command and
increment on each subsequent data byte. This is, in
effect, a byte-ending offset counter within the 8-byte
scratchpad. Bit 5 of the E/S register, called PF, is a logic
1 if the data in the scratchpad is not valid due to a loss
of power or if the master sends fewer bytes than needed
to reach the end of the scratchpad. For a valid write to
the scratchpad, T[2:0] must be 0 and the master must
have sent 8 data bytes. Bits 3, 4, and 6 have no func-
tion; they always read 0. The highest valued bit of the
E/S register, called authorization accepted (AA), acts as
a flag to indicate that the data stored in the scratchpad
has already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
DS2431
The protection control registers determine how incom-
ing data on a Write Scratchpad command is loaded
into the scratchpad. A protection setting of 55h (write
protect) causes the incoming data to be ignored and
the target address main memory data to be loaded into
the scratchpad. A protection setting of AAh (EPROM
mode) causes the logical AND of incoming data and
target address main memory data to be loaded into the
scratchpad. Any other protection control register set-
ting leaves the associated memory page open for unre-
stricted write access. Protection-control byte settings of
55h or AAh also write protect the protection-control
byte. The protection-control byte setting of 55h does
not block the copy. This allows write-protected data to
be refreshed (i.e., reprogrammed with the current data)
in the device.
Writing with Verification
To write data to the DS2431, the scratchpad must be
used as intermediate storage. First, the master issues
the Write Scratchpad command to specify the desired
target address, followed by the data to be written to the
scratchpad. Note that Copy Scratchpad commands
must be performed on 8-byte boundaries, i.e., the three
The copy-protection byte is used for a higher level of
security and should only be used after all other protec-
tion control bytes, user bytes, and write-protected
pages are set to their final value. If the copy-protection
BIT #
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
TARGET ADDRESS (TA2)
T15
AA
T14
0
T13
PF
T12
0
T11
0
T10
E2
T9
E1
T8
E0
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
Figure 6. Address Registers
_______________________________________________________________________________________
8
1024-Bit, 1-Wire EEPROM
DS2431
LSBs of the target address (T2, T1, T0) must be equal
to 000b. If T[2:0] are sent with nonzero values, the copy
function is blocked. Under certain conditions (see the
Write Scratchpad [0Fh] section) the master receives an
inverted CRC-16 of the command, address (actual
address sent), and data at the end of the Write
Scratchpad command sequence. Knowing this CRC
value, the master can compare it to the value it has cal-
culated to decide if the communication was successful
and proceed to the Copy Scratchpad command. If the
master could not receive the CRC-16, it should send
the Read Scratchpad command to verify data integrity.
As a preamble to the scratchpad data, the DS2431
repeats the target address TA1 and TA2 and sends the
contents of the E/S register. If the PF flag is set, data
did not arrive correctly in the scratchpad, or there was
a loss of power since data was last written to the
scratchpad. The master does not need to continue
reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag together with a
cleared PF flag indicates that the device did not recog-
nize the Write command.
Write Scratchpad [0Fh]
The Write Scratchpad command applies to the data
memory and the writable addresses in the register
page. For the scratchpad data to be valid for copying
to the array, the user must perform a Write Scratchpad
command of 8 bytes starting at a valid row boundary.
The Write Scratchpad command accepts invalid
addresses and partial rows, but subsequent Copy
Scratchpad commands are blocked.
After issuing the Write Scratchpad command, the mas-
ter must first provide the 2-byte target address, fol-
lowed by the data to be written to the scratchpad. The
data is written to the scratchpad starting at the byte off-
set of T[2:0]. The E/S bits E[2:0] are loaded with the
starting byte offset and increment with each subse-
quent byte. Effectively, E[2:0] is the byte offset of the
last full byte written to the scratchpad. Only full data
bytes are accepted.
When executing the Write Scratchpad command, the
CRC generator inside the DS2431 (Figure 13) calcu-
lates a CRC of the entire data stream, starting at the
command code and ending at the last data byte as
sent by the master. This CRC is generated using the
CRC-16 polynomial by first clearing the CRC generator
and then shifting in the command code (0Fh) of the
Write Scratchpad command, the target addresses (TA1
and TA2), and all the data bytes. Note that the CRC-16
calculation is performed with the actual TA1 and TA2
and data sent by the master. The master can end the
Write Scratchpad command at any time. However, if
the end of the scratchpad is reached (E[2:0] = 111b),
the master can send 16 read time slots and receive the
CRC generated by the DS2431.
If everything went correctly, both flags are cleared.
Now the master can continue reading and verifying
every data byte. After the master has verified the data,
it can send the Copy Scratchpad command, for exam-
ple. This command must be followed exactly by the
data of the three address registers, TA1, TA2, and E/S.
The master should obtain the contents of these regis-
ters by reading the scratchpad.
Memory Function Commands
The Memory Function Flowchart (Figure 7) describes
the protocols necessary for accessing the memory of
the DS2431. An example on how to use these functions
to write to and read from the device is in the Memory
Function Example section. The communication
between the master and the DS2431 takes place either
at standard speed (default, OD = 0) or at overdrive
speed (OD = 1). If not explicitly set into overdrive
mode, the DS2431 assumes standard speed.
If a Write Scratchpad command is attempted to a write-
protected location, the scratchpad is loaded with the
data already existing in memory rather than the data
transmitted. Similarly, if the target address page is in
EPROM mode, the scratchpad is loaded with the bit-
wise logical AND of the transmitted data and data
already existing in memory.
_______________________________________________________________________________________
9
1024-Bit, 1-Wire EEPROM
BUS MASTER Tx MEMORY
FUNCTION COMMAND
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 9)
0Fh
AAh
TO FIGURE 7b
N
N
WRITE SCRATCHPAD?
READ SCRATCHPAD?
DS2431
Y
Y
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
BUS MASTER Rx
TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE
DS2431
SETS PF = 1
CLEARS AA = 0
SETS E[2:0] = T[2:0]
DS2431 SETS
SCRATCHPAD
BYTE COUNTER = T[2:0]
MASTER Tx DATA BYTE
TO SCRATCHPAD
DS2431
INCREMENTS
BYTE COUNTER
BUS MASTER Rx
DATA BYTE FROM
SCRATCHPAD
APPLIES ONLY
IF THE MEMORY
AREA IS NOT
PROTECTED.
IF WRITE PROTECTED,
THE DS2431 COPIES
THE DATE BYTE FROM
THE TARGET ADDRESS
INTO THE SCRATCHPAD.
DS2431
INCREMENTS
E[2:0]
Y
MASTER Tx RESET?
N
Y
MASTER Tx RESET?
N
IF IN EPROM MODE,
THE DS2431 LOADS
THE BITWISE LOGICAL
AND OF THE TRANSMITTED
BYTE AND THE DATA
BYTE FROM THE TARGETED
ADDRESS INTO THE
N
E[2:0] = 7?
Y
N
BYTE COUNTER
= E[2:0]?
Y
SCRATCHPAD.
N
BUS MASTER Rx CRC-16
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
AS SENT BY THE DS2431
T[2:0] = 0?
Y
PF = 0
N
BUS MASTER
Rx "1"s
MASTER Tx RESET?
Y
DS2431 Tx CRC-16 OF
COMMAND, ADDRESS,
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER
N
BUS MASTER
Rx "1"s
MASTER Tx RESET?
Y
FROM FIGURE 7b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)
Figure 7a. Memory Function Flowchart
10 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
FROM FIGURE 7a
55h
F0h
N
N
COPY SCRATCHPAD?
READ MEMORY?
Y
Y
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
Y
ADDRESS < 90h?
Y
Y
AUTH. CODE
MATCH?
T[15:0] < 0090h?
N
DS2431 SETS MEMORY
N
N
ADDRESS = (T[15:0])
N
PF = 0?
Y
DS2431
INCREMENTS
ADDRESS
BUS MASTER Rx
DATA BYTE FROM
MEMORY ADDRESS
COUNTER
Y
COPY PROTECTED?
Y
BUS MASTER
Rx "1"s
MASTER Tx RESET?
N
N
AA = 1
N
MASTER Tx RESET?
Y
Y
ADDRESS < 8Fh?
N
DS2431 COPIES
SCRATCHPAD
DATA TO ADDRESS
DURATION: t
PROG
*
BUS MASTER
Rx "1"s
N
DS2431 Tx "0"
BUS MASTER
Rx "1"s
MASTER Tx RESET?
Y
N
Y
MASTER Tx RESET?
Y
MASTER Tx RESET?
N
DS2431 Tx "1"
N
MASTER Tx RESET?
Y
TO FIGURE 7a
* 1-Wire IDLE HIGH FOR POWER.
Figure 7b. Memory Function Flowchart (continued)
______________________________________________________________________________________ 11
1024-Bit, 1-Wire EEPROM
Read Scratchpad [AAh]
The Read Scratchpad command allows verifying the
target address and the integrity of the scratchpad data.
After issuing the command code, the master begins
reading. The first two bytes are the target address. The
next byte is the ending offset/data status byte (E/S) fol-
lowed by the scratchpad data, which may be different
from what the master originally sent. This is of particular
importance if the target address is within the register
page or a page in either write-protection mode or
EPROM mode. See the Write Scratchpad [0Fh] section
for details. The master should read through the scratch-
pad (E[2:0] - T[2:0] + 1 bytes), after which it receives
the inverted CRC based on data as it was sent by the
DS2431. If the master continues reading after the CRC,
all data is logic 1.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus mas-
ter and one or more slaves. In all instances the DS2431
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, trans-
action sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transac-
tions in terms of the bus state during specific time slots,
which are initiated on the falling edge of sync pulses
from the bus master.
DS2431
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS2431 is
open drain with an internal circuit equivalent to that
shown in Figure 8.
Copy Scratchpad [55h]
The Copy Scratchpad command is used to copy data
from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master
must provide a 3-byte authorization pattern, which
should have been obtained by an immediately preced-
ing Read Scratchpad command. This 3-byte pattern
must exactly match the data contained in the three
address registers (TA1, TA2, E/S, in that order). If the
pattern matches, the target address is valid, the PF flag
is not set, and the target memory is not copy protected,
then the AA flag is set and the copy begins. All 8 bytes
of scratchpad contents are copied to the target memo-
ry location. The duration of the device’s internal data
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2431 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. Note that legacy
1-Wire products support a standard communication
speed of 16.3kbps and overdrive of 142kbps. The
slightly reduced rates for the DS2431 are a result of
additional recovery times, which in turn were driven by
a 1-Wire physical interface enhancement to improve
noise immunity. The value of the pullup resistor primari-
ly depends on the network size and load conditions.
The DS2431 requires a pullup resistor of 2.2kΩ (max) at
any speed.
transfer is t
during which the voltage on the 1-Wire
PROG
bus must not fall below 2.8V. A pattern of alternating 0s
and 1s are transmitted after the data has been copied
until the master issues a reset pulse. If the PF flag is set
or the target memory is copy protected, the copy does
not begin and the AA flag is not set.
The idle state for the 1-Wire bus is high. If for any rea-
son a transaction needs to be suspended, the bus
must be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 16µs (overdrive speed) or more than 120µs
(standard speed), one or more devices on the bus
could be reset.
Read Memory [F0h]
The Read Memory command is the general function to
read data from the DS2431. After issuing the com-
mand, the master must provide the 2-byte target
address. After these 2 bytes, the master reads data
beginning from the target address and can continue
until address 008Fh. If the master continues reading,
the result is logic 1s. The device’s internal TA1, TA2,
E/S, and scratchpad contents are not affected by a
Read Memory command.
Transaction Sequence
The protocol for accessing the DS2431 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory Function Command
• Transaction/Data
12 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
V
PUP
BUS MASTER
DS2431 1-Wire PORT
R
PUP
DATA
Rx
Tx
Rx
Tx
I
L
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
100Ω MOSFET
Figure 8. Hardware Configuration
Search ROM [F0h]
Initialization
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the regis-
tration number, starting with the least significant bit, the
bus master issues a triplet of time slots. On the first slot,
each slave device participating in the search outputs
the true value of its registration number bit. On the sec-
ond slot, each slave device participating in the search
outputs the complemented value of its registration num-
ber bit. On the third slot, the master writes the true
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participat-
ing in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states
of the bit. By choosing which state to write, the bus
master branches in the ROM code tree. After one com-
plete pass, the bus master knows the registration num-
ber of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to
Application Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
All transactions on the 1-Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS2431 is on the bus and is ready to operate. For more
details, see the 1-Wire Signaling section.
1-Wire ROM Function
Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS2431 supports. All ROM function commands are
8 bits long. A list of these commands follows (see the
flowchart in Figure 9).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS2431’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one slave
is present on the bus, a data collision occurs when all
slaves try to transmit at the same time (open drain pro-
duces a wired-AND result). The resultant family code and
48-bit serial number result in a mismatch of the CRC.
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. If
more than one slave is present on the bus and, for
example, a read command is issued following the Skip
ROM command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS2431 on a multidrop bus. Only the DS2431 that exact-
ly matches the 64-bit ROM sequence responds to the
subsequent memory function command. All other slaves
wait for a reset pulse. This command can be used with a
single device or multiple devices on the bus.
______________________________________________________________________________________ 13
1024-Bit, 1-Wire EEPROM
BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
OD
N
OD = 0
RESET PULSE?
DS2431
Y
BUS MASTER Tx ROM
FUNCTION COMMAND
DS2431 Tx
PRESENCE PULSE
33h
READ ROM
COMMAND?
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
CCh
SKIP ROM
COMMAND?
N
N
N
N
TO FIGURE 9b
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
DS2431 Tx BIT 0
DS2431 Tx BIT 0
MASTER Tx BIT 0
DS2431 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
N
N
N
N
N
N
BIT 0 MATCH?
BIT 0 MATCH?
Y
Y
DS2431 Tx BIT 1
DS2431 Tx BIT 1
MASTER Tx BIT 1
DS2431 Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
DS2431 Tx BIT 63
DS2431 Tx BIT 63
MASTER Tx BIT 63
DS2431 Tx
CRC BYTE
MASTER Tx BIT 63
BIT 63 MATCH?
BIT 63 MATCH?
Y
Y
RC = 1
RC = 1
TO FIGURE 9b
FROM FIGURE 9b
TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
Figure 9a. ROM Functions Flowchart
14 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
TO FIGURE 9a
A5h
RESUME
COMMAND?
3Ch
OVERDRIVE-
SKIP ROM?
69h
OVERDRIVE-
MATCH ROM?
FROM FIGURE 9a
N
N
N
Y
Y
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
Y
MASTER Tx BIT 0
Y
N
N
N
MASTER Tx
RESET?
BIT 0 MATCH?
OD = 0
OD = 0
OD = 0
N
Y
MASTER Tx BIT 1
Y
MASTER Tx
RESET?
BIT 1 MATCH?
Y
N
MASTER Tx BIT 63
BIT 63 MATCH?
Y
RC = 1
FROM FIGURE 9a
TO FIGURE 9a
Figure 9b. ROM Functions Flowchart (continued)
______________________________________________________________________________________ 15
1024-Bit, 1-Wire EEPROM
Resume [A5h]
To maximize the data throughput in a multidrop envi-
ronment, the Resume command is available. This com-
mand checks the status of the RC bit and, if it is set,
directly transfers control to the memory function com-
mands, similar to a Skip ROM command. The only way
to set the RC bit is through successfully executing the
Match ROM, Search ROM, or Overdrive-Match ROM
command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume com-
mand. Accessing another device on the bus clears the
RC bit, preventing two or more devices from simultane-
ously responding to the Resume command.
1-Wire Signaling
The DS2431 requires strict protocols to ensure data
integrity. The protocol consists of four types of signal-
ing on one line: reset sequence with reset pulse and
presence pulse, write-zero, write-one, and read-data.
Except for the presence pulse, the bus master initiates
all falling edges. The DS2431 can communicate at two
different speeds: standard speed and overdrive speed.
If not explicitly set into the overdrive mode, the DS2431
communicates at standard speed. While in overdrive
mode, the fast timing applies to all waveforms.
DS2431
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
below the threshold V . To get
TL
PUP
Overdrive-Skip ROM [3Ch]
from active to idle, the voltage needs to rise from
past the threshold V . The time it takes for the
On a single-drop bus this command can save time by
allowing the bus master to access the memory func-
tions without providing the 64-bit ROM code. Unlike the
normal Skip ROM command, the Overdrive-Skip ROM
command sets the DS2431 into the overdrive mode
(OD = 1). All communication following this command
must occur at overdrive speed until a reset pulse of
minimum 480µs duration resets all devices on the bus
to standard speed (OD = 0).
V
ILMAX
TH
voltage to make this rise is seen in Figure 10 as ε, and
its duration depends on the pullup resistor (R ) used
PUP
and the capacitance of the 1-Wire network attached.
The voltage V
is relevant for the DS2431 when
ILMAX
determining a logical level, not triggering any events.
Figure 10 shows the initialization sequence required to
begin any communication with the DS2431. A reset
pulse followed by a presence pulse indicates that the
DS2431 is ready to receive data, given the correct ROM
and memory function command. If the bus master uses
slew-rate control on the falling edge, it must pull down
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be
issued followed by a Match ROM or Search ROM com-
mand sequence. This speeds up the time for the
search process. If more than one slave supporting
overdrive is present on the bus and the Overdrive-Skip
ROM command is followed by a read command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
the line for t
RSTL
+ t to compensate for the edge. A
F
duration of 480µs or longer exits the overdrive
RSTL
t
mode, returning the device to standard speed. If the
DS2431 is in overdrive mode and t is no longer
RSTL
than 80µs, the device remains in overdrive mode. If the
device is in overdrive mode and t is between 80µs
RSTL
and 480µs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to V
PUP
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-
bit ROM sequence transmitted at overdrive speed
allows the bus master to address a specific DS2431 on
a multidrop bus and to simultaneously set it in overdrive
mode. Only the DS2431 that exactly matches the 64-bit
ROM sequence responds to the subsequent memory
function command. Slaves already in overdrive mode
from a previous Overdrive-Skip ROM or successful
Overdrive-Match ROM command remain in overdrive
mode. All overdrive-capable slaves return to standard
speed at the next reset pulse of minimum 480µs dura-
tion. The Overdrive-Match ROM command can be used
with a single device or multiple devices on the bus.
through the pullup resistor or, in the case of a DS2482-
x00 or DS2480B driver, through the active circuitry.
When the threshold V
is crossed, the DS2431 waits
TH
for t
and then transmits a presence pulse by pulling
PDH
the line low for t
. To detect a presence pulse, the
PDL
master must test the logical state of the 1-Wire line at
t
.
MSP
The t
window must be at least the sum of
RSTH
t
t
, t
, and t
. Immediately after
RECMIN
PDHMAX PDLMAX
RSTH
is expired, the DS2431 is ready for data commu-
nication. In a mixed population network, t
should
RSTH
be extended to minimum 480µs at standard speed and
48µs at overdrive speed to accommodate other 1-Wire
devices.
16 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
MASTER Tx "RESET PULSE"
MASTER Rx "PRESENCE PULSE"
ε
t
MSP
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
PDH
t
t
t
REC
RSTL
PDL
t
F
t
RSTH
RESISTOR
MASTER
DS2431
Figure 10. Initialization Procedure: Reset and Presence Pulse
Slave-to-Master
Read/Write Time Slots
Data communication with the DS2431 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
until the read low time t
is expired. During the t
RL
RL
window, when responding with a 0, the DS2431 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS2431 does not hold the data line low at all, and the
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V , the DS2431 starts its internal
TL
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
voltage starts rising as soon as t is over.
RL
The sum of t + δ (rise time) on one side and the inter-
nal timing generator of the DS2431 on the other side
RL
define the master sampling window (t
to
MSRMIN
Master-to-Slave
t
), in which the master must perform a read
MSRMAX
For a write-one time slot, the voltage on the data line
from the data line. For the most reliable communication,
should be as short as permissible, and the master
must have crossed the V threshold before the write-
TH
t
RL
one low time t
is expired. For a write-zero time
W1LMAX
should read close to but no later than t
. After
MSRMAX
slot, the voltage on the data line must stay below the
threshold until the write-zero low time t is
reading from the data line, the master must wait until
is expired. This guarantees sufficient recovery
V
TH
W0LMIN
t
SLOT
time t
expired. For the most reliable communication, the volt-
age on the data line should not exceed V during
for the DS2431 to get ready for the next time
REC
ILMAX
slot. Note that t
specified herein applies only to a
REC
the entire t
or t
window. After the V threshold
W1L TH
W0L
single DS2431 attached to a 1-Wire line. For multide-
vice configurations, t must be extended to accom-
has been crossed, the DS2431 needs a recovery time
before it is ready for the next time slot.
REC
t
REC
modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.
______________________________________________________________________________________ 17
1024-Bit, 1-Wire EEPROM
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
DS2431
V
TL
V
ILMAX
0V
ε
t
F
t
SLOT
RESISTOR
MASTER
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
REC
t
SLOT
RESISTOR
MASTER
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER
SAMPLING
WINDOW
V
TL
V
ILMAX
0V
δ
t
t
REC
F
t
SLOT
RESISTOR
MASTER
DS2431
Figure 11. Read/Write Timing Diagrams
18 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
(Figure 12, Case B, t < t
). Deep voltage drops
GL
REH
Improved Network Behavior
(Switchpoint Hysteresis)
or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
window can-
REH
In a 1-Wire environment, line termination is possible
only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are suscep-
tible to noise of various origins. Depending on the
physical size and topology of the network, reflections
from end points and branch points can add up or can-
cel each other to some extent. Such reflections are visi-
ble as glitches or ringing on the 1-Wire communication
line. Noise coupled onto the 1-Wire line from external
sources can also result in signal glitching. A glitch dur-
ing the rising edge of a time slot can cause a slave
device to lose synchronization with the master and,
consequently, result in a Search ROM command com-
ing to a dead end or cause a device-specific function
command to abort. For better performance in network
applications, the DS2431 uses a new 1-Wire front-end,
which makes it less sensitive to noise.
not be filtered out and are taken as the beginning of a
new time slot (Figure 12, Case C, t ≥ t ).
GL
REH
Devices that have the parameters V
and t
speci-
REH
HY
fied in their electrical characteristics use the improved
1-Wire front-end.
CRC Generation
The DS2431 uses two different types of CRCs. One
CRC is an 8-bit type and is stored in the most signifi-
cant byte of the 64-bit ROM. The bus master can com-
pute a CRC value from the first 56 bits of the 64-bit
ROM and compare it to the value stored within the
DS2431 to determine if the ROM data has been
received error-free. The equivalent polynomial function
8
5
4
of this CRC is X + X + X + 1. This 8-bit CRC is
received in the true (noninverted) form. It is computed
at the factory and lasered into the ROM.
The DS2431’s 1-Wire front-end differs from traditional
slave devices in three characteristics.
The other CRC is a 16-bit type, generated according to
16
15
the standardized CRC-16 polynomial function X + X
2
1) There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at
overdrive speed.
+ X + 1. This CRC is used for fast verification of a data
transfer when writing to or reading from the scratchpad.
In contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC generator
inside the DS2431 chip (Figure 13) calculates a new 16-
bit CRC, as shown in the command flowchart (Figure 7).
The bus master compares the CRC value read from the
device to the one it calculates from the data and
decides whether to continue with an operation or to
reread the portion of the data with the CRC error.
2) There is a hysteresis at the low-to-high switching
threshold V . If a negative glitch crosses V
but
TH
TH
does not go below V
- V , it is not recognized
HY
TH
(Figure 12, Case A). The hysteresis is effective at
any 1-Wire speed.
With the Write Scratchpad command, the CRC is gen-
erated by first clearing the CRC generator and then
shifting in the command code, the target addresses
TA1 and TA2, and all the data bytes as they were sent
3) There is a time window specified by the rising edge
hold-off time t
during which glitches are ignored,
REH
even if they extend below the V
- V
threshold
HY
TH
t
t
REH
REH
V
PUP
V
TH
V
HY
CASE A
CASE B
CASE C
0V
t
t
GL
GL
Figure 12. Noise Suppression Scheme
______________________________________________________________________________________ 19
1024-Bit, 1-Wire EEPROM
16
15
2
POLYNOMIAL = X + X + X + 1
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
0
1
2
3
4
5
6
7
X
X
X
X
X
X
X
X
DS2431
9TH
STAGE
10TH
STAGE
11TH
STAGE
12TH
STAGE
13TH
STAGE
14TH
STAGE
15TH
STAGE
16TH
STAGE
8
9
10
11
12
13
14
15
16
CRC OUTPUT
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 13. CRC-16 Hardware Description and Polynomial
by the bus master. The DS2431 transmits this CRC only
if E[2:0] = 111b.
TA1 and TA2, the E/S byte, and the scratchpad data as
they were sent by the DS2431. The DS2431 transmits
this CRC only if the reading continues through the end
of the scratchpad. For more information on generating
CRC values, refer to Application Note 27.
With the Read Scratchpad command, the CRC is gen-
erated by first clearing the CRC generator and then
shifting in the command code, the target addresses
Command-Specific 1-Wire Communication Protocol—Legend
SYMBOL
RST
DESCRIPTION
1-Wire reset pulse generated by master.
PD
1-Wire presence pulse generated by slave.
Select
Command and data to satisfy the ROM function protocol.
Command "Write Scratchpad."
WS
RS
Command "Read Scratchpad."
CPS
Command "Copy Scratchpad."
RM
Command "Read Memory."
TA
Target address TA1, TA2.
TA-E/S
Target address TA1, TA2 with E/S byte.
<8–T[2:0] bytes>
<Data to EOM>
CRC-16
FF Loop
AA Loop
Programming
Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
Transfer of as many data bytes as are needed to reach the end of the memory.
Transfer of an inverted CRC-16.
Indefinite loop where the master reads FF bytes.
Indefinite loop where the master reads AA bytes.
Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.
20 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
Command-Specific 1-Wire Communication Protocol—Color Codes
Master to Slave
Slave to Master
Programming
1-Wire Communication Examples
Write Scratchpad (Cannot Fail)
RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop
Read Scratchpad (Cannot Fail)
RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop
Copy Scratchpad (Success)
RST PD Select CPS TA-E/S Programming AA Loop
Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected)
RST PD Select CPS TA-E/S FF Loop
Read Memory (Success)
RST PD Select RM TA <Data to EOM> FF Loop
Read Memory (Invalid Address)
RST PD Select RM TA FF Loop
______________________________________________________________________________________ 21
1024-Bit, 1-Wire EEPROM
Memory Function Example
Write to the first 8 bytes of memory page 1. Read the
entire memory.
With only a single DS2431 connected to the bus mas-
ter, the communication looks like this:
MASTER MODE
DATA (LSB FIRST)
COMMENTS
Reset pulse
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
—
(Reset)
(Presence)
Presence pulse
DS2431
CCh
Issue “Skip ROM” command
Issue “Write Scratchpad” command
TA1, beginning offset = 20h
TA2, address = 0020h
0Fh
20h
00h
<8 Data Bytes>
Write 8 bytes of data to scratchpad
Read CRC to check for data integrity
Reset pulse
<2 Bytes CRC-16>
(Reset)
(Presence)
Presence pulse
CCh
Issue “Skip ROM” command
Issue “Read Scratchpad” command
Read TA1, beginning offset = 20h
Read TA2, address = 0020h
Read E/S, ending offset = 111b, AA, PF = 0
Read scratchpad data and verify
Read CRC to check for data integrity
Reset pulse
AAh
20h
00h
07h
<8 Data Bytes>
<2 Bytes CRC-16>
(Reset)
(Presence)
CCh
Presence pulse
Issue “Skip ROM” command
Issue “Copy Scratchpad” command
TA1
55h
20h
(AUTHORIZATION CODE)
00h
TA2
E/S
07h
<1-Wire Idle High>
AAh
Wait t
for the copy function to complete
PROGMAX
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
Read copy status, AAh = success
Reset pulse
(Reset)
(Presence)
CCh
Presence pulse
Issue “Skip ROM” command
Issue “Read Memory” command
TA1, beginning offset = 00h
TA2, address = 0000h
Read the entire memory
Reset pulse
F0h
00h
00h
<144 Data Bytes>
(Reset)
(Presence)
Presence pulse
22 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
Pin Configurations
SIDE VIEW
FRONT VIEW
GND
1
2
3
1
2
3
IO
N.C.
FRONT VIEW (T&R VERSION)
1
TO-92
2
3
TOP VIEW
TOP VIEW
GND N.C. N.C.
+
A1
A2
A3
GND
IO
1
6
5
4
N.C.
N.C.
N.C.
2
3
DS2431
DS2431
N.C.
C1
IO
C2
C3
N.C. N.C.
TSOC
UCSPR
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DS2431
1
2
+
N.C.
IO
1
6
5
4
N.C.
N.C.
N.C.
IO
GND
2
3
GND
*EP
SFN
6mm × 0.9mm)
(6mm
×
NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL
CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE
INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT
METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.
TDFN-EP
(3mm 3mm)
×
*EXPOSED PAD
______________________________________________________________________________________ 23
1024-Bit, 1-Wire EEPROM
SFN Package Orientation on Tape and Reel
DS2431
USER DIRECTION OF FEED
LEADS FACE UP IN ORIENTATION SHOWN ABOVE.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
3 TO-92 (Bulk)
3 TO-92 (T&R)
6 TSOC
PACKAGE CODE
Q3+1
OUTLINE NO.
21-0248
LAND PATTERN NO.
—
—
Q3+4
21-0250
D6+1
21-0382
90-0321
—
2 SFN
G266+1
T633+2
21-0390
6 TDFN-EP
21-0137
90-0058
Refer to
Application Note 1891
6 UCSPR
BR622+1
21-0376
24 ______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
050704
Initial release.
——
1
Replaced Pin Configuration.
In the Electrical Characteristics table, changed V
from 0.5V to 0.46V and
TL(MIN)
1
2
081604
090506
2
V
from 4.1V to 4.4V; changed V
from 0.22V to 0.21V
TL(MAX)
HY(MIN)
In the Copy Scratchpad [55h] section, corrected the copy time from 13ms to 12.5ms.
Added the SFN package and updated the Ordering Information table.
14
1, 24
In the Pin Configuration, added a note to the CSP package outline “*See package
reliability report for important guidelines on qualified usage conditions.”
1
In the Electrical Characteristics table, changed the t
(programming time) EC
PROG
table parameter from 12.5ms to 10ms for version A2 (see also pages 1, 13).
Removed t and updated t , t , t accordingly. Changed I max to
1, 2, 3, 13
FPD
PDH MSP W0L
PROG
0.8mA to match GBD.
Updated Memory Function Example table.
Added CSP package outline drawing number to Pin Configuration.
Changed V from 0.46V to 0.5V in the Electrical Characteristics table.
23
1
2
TL(MIN)
In the Absolute Maximum Ratings, changed storage temp to -55°C to +125°C; in the
Electrical Characteristics table, changed V , V based on V and data retention
3
122106
TH TL
PUP
to 40 years min at 85°C; added note to retention spec: “EEPROM writes can become
nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability
after 10 years at +125°C or 40 years at +85°C.”
1, 2, 3
In the Ordering Information table, removed all leaded part numbers and added the
TDFN-EP package.
1, 24
2, 3
In the Electrical Characteristics table, changed the V
spec from 0.3V to 0.5V;
IL(MAX)
removed ꢀ from the t
spec; added Note 17 to t
spec; updated EC table
W1L(MAX)
W0L
Notes 17 and 18; corrected Note 20.
Added EP function to the Pin Description table.
3
4
102207
Added ꢀ to Figure 11 Write-Zero Time Slot.
19
In the Pin Configuration, added the package drawing information/weblink and a note
that the SFN package is qualified for electro-mechanical contact applications only,
not for soldering. Added the SFN Package Orientation on Tape-and-Reel section. In
the Ordering Information, added note to contact factory for availability of the UCSPR
package. Added note that TO-92 T&R leads are formed to approximately 100-mil
spacing.
24
In the SFN Pin Configuration, added reference to Application Note 4132.
Added Package Information table.
24
25
All
5
6
032008
8/08
Created newer template-style data sheet.
______________________________________________________________________________________ 25
1024-Bit, 1-Wire EEPROM
Revision History (continued)
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
Deleted “contact factory” note in Ordering Information; updated Pin Description and
Pin Configurations to reflect changes in pin assignment of UCSPR package.
7
6/09
1, 5, 23
DS2431
8
9
10/09
12/10
3/11
Corrected part number in Ordering Information table.
1
1
1
Deleted the automotive version reference in the Features section
Added the automotive version reference to the Features section
10
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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