DS2484Q+T [MAXIM]
Interface Circuit, PDSO8, 3 X 2 MM, ROHS COMPLIANT, TDFN-8;
| 型号： | DS2484Q+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, PDSO8, 3 X 2 MM, ROHS COMPLIANT, TDFN-8 光电二极管 接口集成电路 |
| 文件： | 总29页 (文件大小：1741K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
General Description
Benefits and Features
2
M
2
2
The DS2484 is an I C-to-1-Wire bridge device that
interfaces directly to standard (100kHz max) or fast
S I C Host Interface Supports 100kHz and 400kHz
I C Communication Speeds
2
(400kHz max) I C masters to perform protocol con-
version between the I C master and any downstream
S Standard and Overdrive 1-Wire Communication
2
Speeds
1-Wire slave devices. Relative to any attached 1-Wire
slave device, the DS2484 is a 1-Wire master. Internal,
user-adjustable timers relieve the system host processor
from generating time-critical 1-Wire waveforms, support-
ing both standard and overdrive 1-Wire communication
speeds. In addition, the 1-Wire bus can be powered
down under software control. The dual-voltage operation
S Adjustable 1-Wire Timing for t
, t
, t
,
RSTL MSP W0L
and t
REC0
S 1-Wire Port Can Be Powered Down Under
Software Control
S Supports Power-Saving Sleep Mode (SLPZ Pin),
Where the 1-Wire Port is in High Impedance
2
allows different operating voltages on the I C and 1-Wire
2
S I C Operating Voltages: 1.8V ±±5, ꢀ.ꢀV ±105, and
side. Strong pullup features support 1-Wire power deliv-
ery to 1-Wire devices such as EEPROMs and sensors.
When not in use, the DS2484 can be put in sleep mode
where power consumption is minimal.
±.0V +±/-105
S Built-In Level Translator: 1-Wire Operating Voltage
2
from 1.8V -±5 to ±.0V +±5, Independent of I C
Voltage
Applications
S Built-In ESD Protection Level of ±8kV Human
Body Model (HBM) Contact Discharge on IO Pin
Printers
S -40NC to +8±NC Operating Temperature Range
S 8-Pin TDFN and 6-Pin SOT2ꢀ Packages
Medical Instruments
Industrial Sensors
Cell Phones
Ordering Information appears at end of data sheet.
Typical Application Circuit
3V
5V
R *
P
V
CC
SDA
SCL
2
(I C PORT)
DS2484
µC
1-Wire BUS
SLPZ
IO
1-Wire
1-Wire
1-Wire
DEVICE #1
DEVICE #2
DEVICE #n
2
*R = I C PULLUP RESISTOR (SEE THE Pullup Resistor R Sizing SECTION FOR R SIZING)
P
P
P
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6701; Rev 1; 7/15
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.......-0.5V to +6V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Continuous Power Dissipation (T = +70NC)
A
SOT23 (derate 8.7mW/NC above +70NC).................695.7mW
TDFN (derate 16.7mW/NC above +70NC)...............1333.3mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
1.71
1.71
2.97
4.5
TYP
MAX
5.25
1.89
3.63
5.25
300
4
UNITS
V
V
CC
1.8V
3.3V
5V
1.8
3.3
5.0
2
I C Voltage (Note 2)
V
V
CI2C
No communication, V
= full range
CC
Supply Current
I
Sleep mode, V
Sleep mode, V
= 5.25V
= 3.6V
FA
CC
CC
3.0
CC
Power-On-Reset Trip Point
V
V
= full range
1.0
1.5
V
POR
CC
IO PIN: GENERAL DATA
0.6 O
1-Wire Input High Voltage
1-Wire Input Low Voltage
V
V
V
= full range
= full range
V
V
IH1
CC
V
CC
0.2 O
V
IL1
CC
V
CC
Low range
High range
375
700
500
815
1375
0.2
I
1-Wire Weak Pullup Resistor
R
WPU
1000
1-Wire Output Low Voltage
Active Pullup On-Threshold
V
I
= 8mA sink current
OL
V
V
OL1
V
V
= full range
0.6
0.95
1.2
IAPO
CC
1-Wire time slot
See APU bit description
Active Pullup On-Time (Note 3)
Active Pullup Impedance
t
1-Wire reset standard speed
1-Wire reset overdrive speed
2.375
0.475
2.5
0.5
2.625
0.525
100
60
Fs
APU
V
V
V
= 1.71V, 4mA load
= 3.0V, 4mA load
= 4.5V, 4mA load
CC
CC
CC
I
R
APU
40
Standard, 10pF < C
< 400pF
< 400pF
0.25
0.05
1
LOAD
1-Wire Output Fall Time (Note 4)
IO PIN: 1-Wire TIMING (Note ±)
Reset Low Time
t
Fs
F1
Overdrive, 10pF < C
0.2
LOAD
Standard
Overdrive
See
Table 7
t
-5%
+5%
Fs
Fs
RSTL
Reset High Time
t
Standard and overdrive
Equal to t
RSTL
RSTH
Maxim Integrated
2
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard
Overdrive
Standard
Overdrive
Standard
See
Table 7
Presence-Detect Sample Time
t
-5%
+5%
Fs
MSP
7.6
0.71
7.6
8
8.4
0.79
8.4
Sampling for Short and Interrupt
Write-One/Read Low Time
Read Sample Time
t
Fs
Fs
Fs
Fs
SI
0.75
8
t
W1L
MSR
Overdrive (Note 6)
Standard
0.71
11.4
1.66
0.75
12
0.79
12.6
1.84
t
Overdrive
1.75
Standard
See
Table 7
Write-Zero Low Time
t
-5%
-5%
+5%
W0L
Overdrive
See
Table 7
Write-Zero Recovery Time
t
Standard and overdrive
Standard and overdrive
+5%
REC0
Fs
Fs
REC0
1-Wire Time Slot
t
Equal to t
+ t
SLOT
W0L
SLPZ PIN
Low-Level Input Voltage
High-Level Input Voltage
V
V
= full range
-0.5
1.3
+0.5
V
V
IL
CC
V
(Note 7)
V
IH
CCACT
6
V
V
V
< 1.89V
< 3.63V
< 5.25V
CI2C
CI2C
CI2C
Input Leakage Current (Note 2)
Wake-Up Time from Sleep Mode
I
15
32
2
FA
I
t
(Notes 4, 8)
ms
SWUP
2
I C SCL AND SDA PINS (Note 9)
0.3 O
Low-Level Input Voltage
High-Level Input Voltage
V
V
= full range
-0.5
V
V
IL
CI2C
V
CI2C
0.7 O
V
+
CI2C
0.5V
V
IH
V
CI2C
0.05 O
V
> 2.0V
CI2C
V
Hysteresis of Schmitt Trigger
Inputs (Note 4)
CI2C
V
V
V
HYS
0.1 O
V
V
V
< 2.0V
> 2.0V
< 2.0V
CI2C
CI2C
CI2C
V
CI2C
0.4
Low-Level Output Voltage at
3mA Sink Current
V
0.2 O
OL
V
CI2C
Output Fall Time from V
to
IH(MIN)
V
with a Bus Capacitance
t
(Note 4)
60
250
50
ns
ns
IL(MAX)
OF
from 10pF to 400pF
Pulse Width of Spikes
Suppressed by Input Filter
t
SP
Maxim Integrated
3
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current with Input Voltage
Between 0.1 O V
and 0.9
I
(Note 10)
(Note 4)
-10
+10
FA
CC(MAX)
I
O V
CC(MAX)
Input Capacitance
C
10
pF
I
SCL Clock Frequency
f
0
400
kHz
SCL
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
t
t
0.6
Fs
HD:STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
Fs
SU:STA
Data Hold Time
t
(Notes 11, 12)
(Note 13)
0.9
Fs
ns
Fs
HD:DAT
Data Setup Time
t
t
250
0.6
SU:DAT
SU:STO
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
t
1.3
Fs
BUF
Capacitive Load for Each Bus
Line
C
(Notes 4, 14)
(Notes 4, 8)
400
2
pF
B
Oscillator Warmup Time
t
ms
OSCWUP
Note 1: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range and relevant supply volt-
A
age range are guaranteed by design and characterization. Typical values are at +25°C.
Note 2: The V
voltage is applied at the SLPZ pin. V
must always be < V . The DS2484 measures V
after t
CI2C
CI2C
CC
CI2C SWUP
(wakeup from sleep mode) or after t
measure V
(power-on reset). The Device Reset command does not cause the DS2484 to
OSCWUP
.
CI2C
Note ꢀ: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset command or during the
recovery after a short on the 1-Wire line.
Note 4: Guaranteed design and not production tested.
Note ±: Except for t , all 1-Wire timing specifications are derived from the same timing circuit.
F1
Note 6: Although 1-Wire slave data sheets specify a t
and t minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
W1L
RL
t
V
and t of the DS2484.
W1L
RL
Note 7:
refers to the V
level being applied in the application.
CCACT
CC
2
Note 8: I C communication should not take place for the max t
from sleep mode.
Note 9: All I C timing values are referenced to V
Note 10: The DS2484 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if V
Note 11: The DS2484 provides a hold time of at least 300ns for the SDA signal (referenced to the V
or t
time following a power-on reset or a wake-up
OSCWUP
SWUP
2
and V
levels.
IH(MIN)
IL(MAX)
is switched off.
CC
of the SCL signal) to
IH(MIN)
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
must only be met if the device does not stretch the low period (t
) of the SCL signal.
LOW
HD:DAT
2
2
Note 1ꢀ: A fast mode I C bus device can be used in a standard mode I C bus system, but the requirement t
R 250ns
SU:DAT
must then be met. This requirement is met since the DS2484 does not stretch the low period of the SCL signal. Also the
acknowledge timing must meet this setup time (I C bus specification Rev. 03, 19 June 2007).
2
Note 14: C = Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depend-
B
2
ing on the actual operating voltage and frequency of the application (I C bus specification Rev. 03, 19 June 2007).
Maxim Integrated
4
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Pin Configurations
TOP VIEW
TOP MARK
SCL
SDA
1
2
3
4
GND
IO
8
7
6
5
2484
YMrr
TDFN
(2mm x 3mm)
DS2484
V
SLPZ
N.C.
CC
EP
N.C.
TOP VIEW
TOP MARK
V
CC
6
IO
5
GND
4
3Hrr
SOT23
DS2484
1
2
3
SLPZ
SDA
SCL
“rr” = REVISION CODE
Pin Description
PIN
TDFN-EP
NAME
FUNCTION
SOT2ꢀ
2
2
I C Serial-Clock Input. Must be connected to the I C bus supply voltage through a pullup
resistor.
1
2
3
SCL
SDA
2
2
I C Serial-Data Input/Output. Must be connected to the I C bus supply voltage through a
pullup resistor.
2
1
2
Power Supply for I C Port and Active-Low Control Input to Activate the Low-Power Sleep
3
SLPZ
N.C.
Mode. This pin can be driven directly by a push-pull port or by an open-drain port with a
2
2.2kI pullup resistor to the I C voltage (V
No Connection. Not internally connected.
Power-Supply Input
) over the entire operating voltage range.
CI2C
4, 5
6
—
6
V
CC
7
5
IO
Input/Output Driver for 1-Wire Line
Ground Reference
8
4
GND
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation.
Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
—
—
EP
Maxim Integrated
5
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
CONFIGURATION AND
TIMING REGISTER
V
T-TIME OSC
CC
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
2
IO
I C
SDA
SCL
INTERFACE
CONTROLLER
STATUS
REGISTER
SLPZ
GND
DS2484
READ DATA
REGISTER
Figure 1. Block Diagram
Table 1. Device Configuration Register Bit Assignment
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
SPU
BIT 1
BIT 0
1WS
PDN
APU
1WS
SPU
PDN
APU
pointer. The position of the read pointer, i.e., the reg-
ister that the host reads in a subsequent read access,
is defined by the instruction the DS2484 executed last.
To enable certain 1-Wire features, the host has read-
and write-access to the Device Configuration and Port
Configuration registers.
Detailed Description
The DS2484 is a self-timed 1-Wire master that supports
advanced 1-Wire waveform features including standard
and overdrive speeds, active pullup, and strong pullup
for power delivery. The active pullup affects rising edges
on the 1-Wire side. The strong pullup function uses the
same pullup transistor as the active pullup, but with a
different control algorithm. Once supplied with command
and data, the input/output controller of the DS2484 per-
forms time-critical 1-Wire communication functions such
as reset/presence-detect cycle, read-byte, write-byte,
single bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status register and data through the Read Data regis-
ter. The DS2484 communicates with a host processor
Device Configuration Register
The DS2484 supports four 1-Wire features that are
enabled or selected through the Device Configuration
register (Table 1). These features are as follows:
• Active Pullup (APU)
• 1-Wire Power-Down (PDN)
• Strong Pullup (SPU)
• 1-Wire Speed (1WS)
APU, SPU, and 1WS can be selected in any combination.
While APU and 1WS maintain their states, SPU returns to
its inactive state as soon as the strong pullup has ended.
2
through its I C bus interface in standard mode or in fast
mode. See Figure 1 for a block diagram.
After a device reset (power-up cycle or initiated by the
Device Reset command), the Device Configuration reg-
ister reads 00h. When writing to the Device Configuration
register, the new data is accepted only if the upper nibble
(bits 7 to 4) is the one’s complement of the lower nibble
(bits 3 to 0). When read, the upper nibble is always 0h.
Device Registers
2
The DS2484 has four registers that the I C host can
read: Device Configuration, Status, Read Data, and Port
Configuration. These registers are addressed by a read
Maxim Integrated
6
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Active Pullup (APU)
The APU bit controls whether an active pullup (low
activates a low-impedance pullup transistor, as repre-
sented by the dashed line. The active pullup remains
impedance transistor) or a passive pullup (R
resis-
active until the end of the time slot (t ), after which the
resistive pullup continues. The shortest duration of the
WPU
3
tor) is used to drive a 1-Wire line from low to high. When
APU = 0, active pullup is disabled (resistor mode).
Enabling active pullup is generally recommended for
best 1-Wire bus performance. The active pullup does
not apply to the rising edge of a recovery after a short
on the 1-Wire line. If enabled, a fixed-duration active
pullup (typically 2.5Fs standard speed, 0.5Fs overdrive
speed) also applies in a reset/presence detect cycle on
active pullup is t
and the longest duration is t
- (t - t ) in a write-zero time slot
REC0
2
1
+ t
- t
- (t - t )
W0L
REC0 W1L 2 1
in a write-one time slot. In a read-data time slot, the active
pullup duration is slave dependent. See the Strong Pullup
(SPU) section for a way to keep the pullup transistor con-
ducting beyond t .
3
1-Wire Power Down (PDN)
the rising edges after t
and after t
.
RSTL
PDL
The PDN bit is used to remove power from the 1-Wire
port, e.g., to force a 1-Wire slave to perform a power-on
reset. PDN can as well be used in conjunction with the
sleep mode (see Table 2 for details). While PDN is 1,
no 1-Wire communication is possible. To end the 1-Wire
power-down state, the PDN bit must be changed to 0.
The circuit that controls rising edges operates as follows
(Figure 2): At t , the pulldown (from DS2484 or 1-Wire
1
slave) ends. From this point on the 1-Wire bus is pulled
high through R
internal to the DS2484. V
and the
WPU
CC
capacitive load of the 1-Wire line determine the slope. In
case that active pullup is disabled (APU = 0), the resis-
tive pullup continues, as represented by the solid line.
Writing both the PDN bit and the SPU bit to 1 forces the
SPU bit to 0. With the DS2483, both bits can be written
to 1, which can be used to logically distinguish between
both parts.
With active pullup enabled (APU = 1), and when at t the
2
voltage has reached the V
threshold, the DS2484
IAPO
Table 2. Effects of PDN and SLPZ
PDN =
SLPZ IS LOGIC 0
SLPZ IS LOGIC 1
• R
is connected.
• R
is connected.
WPU
WPU
0
• IO is at V , keeping the slaves powered.
• IO is at V , keeping the slaves powered.
CC
CC
• The DS2484 is powered down (sleep mode).
• The DS2484 is powered up (normal operation).
• R
is disconnected.
• R
is disconnected.
WPU
WPU
1
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered down (sleep mode).
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered up.
V
CC
APU = 1
NEXT TIME SLOT
APU = 0
V
V
IAPO
IL1MAX
0V
1-Wire BUS IS
t
REC0
DISCHARGED
t
1
t
2
t
3
Figure 2. Rising Edge Pullup as Seen at the End of a Write-Zero Time Slot
Maxim Integrated
7
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Strong Pullup (SPU)
The SPU bit is used to activate the strong pullup func-
tion prior to a 1-Wire Write Byte or 1-Wire Single Bit
command. Strong pullup is commonly used with 1-Wire
EEPROM devices when copying scratchpad data to the
main memory or when performing a SHA computation
and with parasitically powered temperature sensors or
A/D converters. The respective Maxim 1-Wire IC data
sheets specify the location in the communications proto-
col after which the strong pullup should be applied. The
SPU bit must be set immediately prior to issuing the com-
mand that puts the 1-Wire device into the state where it
needs the extra power. The strong pullup uses the same
internal pullup transistor as the active pullup feature.
case), the SPU bit in the Device Configuration register
is written to 0, or the DS2484 receives the Device Reset
command. When the strong pullup ends, the SPU bit is
automatically reset to 0. Using the strong pullup feature
does not change the state of the APU bit in the Device
Configuration register.
1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire com-
munication generated by the DS2484. All 1-Wire slave
devices support standard speed (1WS = 0). Many
1-Wire devices can also communicate at a higher data
rate, called overdrive speed. To change from standard
to overdrive speed, a 1-Wire device needs to receive
an Overdrive-Skip ROM or Overdrive-Match ROM com-
mand, as explained in the Maxim 1-Wire IC data sheets.
The change in speed occurs immediately after the 1-Wire
device has received the speed-changing command
code. The DS2484 must take part in this speed change
to stay synchronized. This is accomplished by writing to
the Device Configuration register with the 1WS bit as 1
immediately after the 1-Wire Byte command that changes
the speed of a 1-Wire device. Writing to the Device
Configuration register with the 1WS bit as 0, followed by
a 1-Wire Reset command, changes the DS2484 and any
1-Wire devices on the active 1-Wire line back to standard
speed.
See the R
parameter in the Electrical Characteristics
APU
to determine whether the voltage drop is low enough to
maintain the required 1-Wire voltage at a given load cur-
rent and 1-Wire supply voltage.
If SPU is 1 and APU is 0, the DS2484 treats the rising
edge of the time slot as if the active pullup was activat-
ed, but uses V
as the threshold to enable the strong
IH1
pullup. If SPU is 1 and APU is 1, the threshold voltage
to enable the strong pullup is V . Once enabled, in
IAPO
contrast to the active pullup, the internal pullup transis-
tor remains conducting, as shown in Figure 3, until one
of three events occurs: the DS2484 receives a com-
mand that generates 1-Wire communication (the typical
LAST BIT OF 1-Wire WRITE BYTE OR 1-Wire SINGLE BIT FUNCTION
WRITE-ONE CASE
V
CC
NEXT
TIME SLOT
OR 1-Wire
RESET
SEE TEXT
0V
WRITE-ZERO CASE
t
SLOT
DS2484 RESISTIVE PULLUP
DS2484 PULLDOWN
DS2484 STRONG PULLUP
Figure 3. Low-Impedance Pullup Timing
Maxim Integrated
8
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Table ꢀ. Status Register Bit Assignment
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
BIT 1
BIT 0
DIR
TSB
SBR
RST
LL
SD
PPD
1WB
Logic Level (LL)
Status Register
The LL bit reports the logic state of the active 1-Wire line
without initiating any 1-Wire communication. The 1-Wire
line is sampled for this purpose every time the Status
register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the
DS2484 in read mode (during the acknowledge cycle),
provided that the read pointer is positioned at the Status
register.
The read-only Status register is the general means for
the DS2484 to report bit-type data from the 1-Wire side,
1-Wire busy status, and its own reset status to the host
processor (Table 3). All 1-Wire communication com-
mands and the Device Reset command position the read
pointer at the Status register for the host processor to
read with minimal protocol overhead. Status information
is updated during the execution of certain commands
only. Bit details are given in the following descriptions.
Device Reset (RST)
If the RST bit is 1, the DS2484 has performed an internal
reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is
cleared automatically when the DS2484 executes a Write
Device Configuration command to restore the selection
of the desired 1-Wire features.
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB
is 1; once the command is completed, 1WB returns to
its default 0. Details on when 1WB changes state and
for how long it remains at 1 are found in the Function
Commands section.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire
Presence-Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset com-
mand. If the DS2484 detects a logic 0 on the 1-Wire line
line sampled at t
of a 1-Wire Single Bit command or
MSR
the first bit of a 1-Wire Triplet command. The power-on
default of SBR is 0. If the 1-Wire Single Bit command
sends a 0 bit, SBR should be 0. With a 1-Wire Triplet
command, SBR could be 0 as well as 1, depending on
the response of the 1-Wire devices connected. The same
result applies to a 1-Wire Single Bit command that sends
a 1 bit.
at t
during the presence-detect cycle, the PPD bit is
MSP
set to 1. This bit returns to its default 0 if there is no pres-
ence pulse during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset com-
mand. If the DS2484 detects a logic 0 on the 1-Wire line
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire
at t during the presence-detect cycle, the SD bit is set
SI
to 1. This bit returns to its default 0 with a subsequent
1-Wire Reset command, provided that the short has been
line sampled at t
of the second bit of a 1-Wire Triplet
MSR
command. The power-on default of TSB is 0. This bit is
updated only with a 1-Wire Triplet command and has no
function with other commands.
removed. If the 1-Wire line is shorted at t
, the PPD
MSP
bit is also set. The DS2484 cannot distinguish between a
short and a DS1994 or DS2404 signaling a 1-Wire inter-
rupt. For this reason, if a DS2404 or DS1994 is used in
the application, the interrupt function must be disabled.
The interrupt signaling is explained in the respective
Maxim 1-Wire IC data sheets.
Branch Direction Taken (DIR)
Whenever a 1-Wire Triplet command is executed, this bit
reports to the host processor the search direction that
was chosen by the third bit of the triplet. The power-on
default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other com-
mands. For additional information, see the description of
the 1-Wire Triplet command and Application Note 187:
1-Wire Search Algorithm.
Maxim Integrated
9
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Table 4. Port Configuration Register Bit Assignment
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
BIT 1
BIT 0
0
0
0
0
VAL3
VAL2
VAL1
VAL0
VAL[ꢀ:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.
BITS 3:0
Port Configuration Register
Function Commands
The Port Configuration register allows verifying the set-
tings for the 1-Wire port (Table 4). The Adjust 1-Wire
Port command positions the read pointer to the Port
Configuration register for the host processor to read
with minimal protocol overhead. When reading the Port
Configuration register, the parameter values are reported
in this sequence:
The DS2484 understands nine function commands that
2
fall into four categories: device control, I C communi-
cation, 1-Wire setup, and 1-Wire communication. The
feedback path to the host is controlled by a read pointer,
which is set automatically by each function command
for the host to efficiently access relevant information.
The host processor sends these commands and appli-
cable parameters as strings of 1 or 2 bytes using the
I C interface. The I C protocol requires that each byte
be acknowledged by the receiving party to confirm
acceptance or not be acknowledged to indicate an error
condition (invalid code or parameter) or to end the com-
Parameter 000 (t
) standard speed, overdrive speed
) standard speed, overdrive speed
) standard speed, overdrive speed
RSTL
Parameter 001 (t
Parameter 010 (t
MSP
2
2
W0L
Parameter 011 (t
)
REC0
Parameter 100 (R
)
WPU
2
munication. See the I C Interface section for details of
the I C protocol including acknowledge.
2
If one continues reading, the parameter number rolls
over to 000 and one receives the same data again.
The function commands are as follows:
1) Device Reset
Note that the upper 4 bits read from the port configura-
tion register are always 0. See Table 7 for the conversion
between parameter value code and actual parameter
value.
2) Set Read Pointer
3) Write Device Configuration
4) Adjust 1-Wire Port
5) 1-Wire Reset
6) 1-Wire Single Bit
7) 1-Wire Write Byte
8) 1-Wire Read Byte
9) 1-Wire Triplet
Maxim Integrated
10
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Device Reset
Command Code
F0h
Command Parameter
None
Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire
communication.
Description
Typical Use
Device initialization after power-up; reinitialization (reset) as desired.
None (can be executed at any time)
Restriction
Error Response
Command Duration
1-Wire Activity
None
Maximum 525ns. Counted from falling SCL edge of the command code acknowledge bit.
Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status register (for busy polling).
Read Pointer Position
Status Bits Affected
RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.
Device Configurations Affected 1WS, APU, PDN, SPU set to 0.
Port Configurations Affected
t
, t
, t
, t
, and R
default values apply.
RSTL MSP W0L REC0
WPU
Set Read Pointer
Command Code
E1h
Pointer Code (see Table 5)
Command Parameter
Sets the read pointer to the specified register. Overwrites the read pointer position of any
1-Wire communication command in progress.
Description
To prepare reading the result from a 1-Wire Read Byte command; random read access of
registers.
Typical Use
Restriction
None (can be executed at any time).
If the pointer code is not valid, the pointer code is not acknowledged and the command is
ignored.
Error Response
Command Duration
1-Wire Activity
None. The read pointer is updated on the rising SCL edge of the pointer code acknowledge bit.
Not affected.
Read Pointer Position
Status Bits Affected
As specified by the pointer code.
None
Device Configurations Affected None
Port Configurations Affected None
Table ±. Valid Read Pointer Codes
REGISTER
Device Configuration Register
Status Register
CODE
C3h
F0h
Read Data Register
E1h
Port Configuration Register
B4h
Maxim Integrated
11
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Write Device Configuration
Command Code
D2h
Command Parameter
Configuration Byte
Writes a new device configuration byte. The new settings take effect immediately. Note:
When writing to the Device Configuration register, the new data is accepted only if the upper
nibble (bits 7 to 4) is the one’s complement of the lower nibble (bits 3 to 0). When read, the
upper nibble is always 0h.
Description
Typical Use
Restriction
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2484 can process this command.
Command code and parameter are not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
Error Response
None. The Device Configuration register is updated on the rising SCL edge of the
configuration-byte acknowledge bit.
Command Duration
1-Wire Activity
None
Read Pointer Position
Status Bits Affected
Device Configuration register (to verify write).
RST set to 0.
Device Configurations Affected 1WS, SPU, PDN, APU updated.
Port Configurations Affected
None
Adjust 1-Wire Port
Command Code
C3h
Command Parameter
Control Byte
Updates the selected 1-Wire port parameter, which affects the 1-Wire timing or pullup
resistor selection. See Table 6 for the control byte format. Note: Upon a power-on reset or
after a Device Reset command, the parameter default values apply.
Description
To adapt the 1-Wire port to the needs of the application. This can be necessary to
accommodate the slave timing requirements, which are different at lower pullup voltage.
Typical Use
Restriction
1-Wire activity must have ended before this command can be processed.
Command code and data byte are not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
Error Response
None. The selected port parameter is updated on the rising SCL edge of the control-byte
acknowledge bit.
Command Duration
1-Wire Activity
None
Read Pointer Position
Status Bits Affected
Port Configuration register (for verification).
None
Device Configurations Affected None
Port Configurations Affected
As specified by the control byte.
Maxim Integrated
12
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Table 6. Bit Allocation in the Control Byte
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
BIT 1
BIT 0
P2
P1
P0
OD
VAL3
VAL2
VAL1
VAL0
P[2:0]: Parameter Selection
000: selects t
001: selects t
010: selects t
011: selects t
RSTL
MSP
W0L
BITS 7:5
; the OD flag does not apply (don’t care)
; the OD flag does not apply (don’t care)
REC0
100: selects R
WPU
OD: Overdrive Control
BIT 4
0: the value provided applies to the standard speed setting
1: the value provided applies to the overdrive speed setting
VAL[ꢀ:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.
BITS 3:0
Table 7. Conversion Between Parameter Code and Typical Parameter Value
PARAMETER 000
(µs)
PARAMETER 001
PARAMETER 010
(µs)
PARAMETER 011
(µs)
PARAMETER 100
(W)
PARAMETER
VALUE
t
t
µs)
t
t
R
WPU
RSTL
MSP (
W0L
REC0
CODE
OD = 0
440
460
480
500
520
540
±60
580
600
620
640
660
680
700
720
740
OD = 1
OD = 0
58
OD = 1
5.5
OD = 0
52
OD = 1
OD = N/A
2.75
OD = N/A
500
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
44
46
48
50
52
54
±6
58
60
62
64
66
68
70
72
74
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10
58
5.5
54
2.75
500
60
6.0
56
2.75
500
62
6.5
58
2.75
500
64
7.0
60
2.75
500
66
68
7.5
8.0
62
64
2.75
±.2±
500
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
70
8.5
66
7.75
72
9.0
68
10.25
12.75
15.25
17.75
20.25
22.75
25.25
25.25
74
9.5
70
76
10.0
10.5
11.0
11.0
11.0
11.0
70
76
70
10
76
70
10
76
70
10
76
70
10
76
70
10
Note: The power-on default values are bold.
Maxim Integrated
13
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
1-Wire Reset
Command Code
B4h
Command Parameter
None
Generates a 1-Wire reset/presence-detect cycle at the 1-Wire line (Figure 4). The state of
Description
the 1-Wire line is sampled at t and t
and the result is reported to the host processor
SI
MSP
through the Status register bits PPD and SD.
Typical Use
Restriction
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2484 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received
and the command is ignored.
Error Response
2 O t
acknowledge bit.
+ maximum 262.5ns, counted from the falling SCL edge of the command code
RSTL
Command Duration
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status register (for busy polling).
Read Pointer Position
Status Bits Affected
1WB (set to 1 for 2 O t
), PPD is updated at t
+ t
, SD is updated at t
+ t .
RSTL
RSTL
MSP
RSTL SI
Device Configurations Affected 1WS, APU apply.
Port Configurations Affected , t , t , t
t
, and R
current values apply.
RSTL MSP W0L REC0
WPU
RESET PULSE
PRESENCE/SHORT DETECT
t
MSP
t
SI
V
CC
APU CONTROLLED
EDGE
V
IH1
V
IL1
0V
t
F1
PRESENCE PULSE
t
t
RSTH
RSTL
PULLUP (SEE FIGURE 2)
DS2484 PULLDOWN
1-Wire SLAVE PULLDOWN
Figure 4. 1-Wire Reset/Presence-Detect Cycle
Maxim Integrated
14
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
1-Wire Single Bit
Command Code
87h
Command Parameter
Bit Byte
Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the
1-Wire line (Table 8). A V value of 0b generates a write-zero time slot (Figure 5); a V value of
1b generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In
Description
either case, the logic level at the 1-Wire line is tested at t
and SBR is updated.
MSR
To perform single-bit writes or reads at the 1-Wire line when single bit communication is
necessary (the exception).
Typical Use
Restriction
1-Wire activity must have ended before the DS2484 can process this command.
Command code and bit byte are not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
Error Response
t
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit
SLOT
Command Duration
byte.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.
Status register (for busy polling and data reading).
Read Pointer Position
Status Bits Affected
1WB (set to 1 for t
), SBR is updated at t
, DIR (may change its state).
SLOT
MSR
Device Configurations Affected 1WS, APU, SPU apply.
Port Configurations Affected , t , t , t
t
, and R
current values apply.
RSTL MSP W0L REC0
WPU
Table 8. Bit Allocation in the Bit Byte
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
BIT 1
BIT 0
V
X
X
X
X
X
X
X
X = Don’t care
Maxim Integrated
15
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
t
WOL
t
MSR
V
CC
V
IH1
V
IL1
0V
t
F1
t
EC0
R
t
SLOT
PULLUP (SEE FIGURE 2)
DS2484 PULLDOWN
Figure 5. Write-Zero Time Slot
t
MSR
t
W1L
V
CC
V
IH1
V
IL1
0V
t
F1
t
SLOT
PULLUP (SEE FIGURE 2)
DS2484 PULLDOWN
1-Wire SLAVE PULLDOWN
NOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g., THE DS2484). WHEN RESPONDING WITH A 0,
A 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING t . ITS INTERNAL TIMING GENERATOR DETERMINES WHEN THIS PULLDOWN ENDS AND THE VOLTAGE
W1L
STARTS RISING AGAIN. WHEN RESPONDING WITH A 1, A 1-Wire SLAVE DOES NOT HOLD THE LINE LOW AT ALL, AND THE VOLTAGE STARTS RISING AS SOON AS t
W1L
IS OVER. 1-Wire DEVICE DATA SHEETS USE THE TERM t INSTEAD OF t
TO DESCRIBE A READ-DATA TIME SLOT. TECHNICALLY, t AND t
HAVE IDENTICAL
RL
W1L
RL
W1L
SPECIFICATIONS AND CANNOT BE DISTINGUISHED FROM EACH OTHER.
Figure 6. Write-One and Read-Data Time Slot
Maxim Integrated
16
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
1-Wire Write Byte
Command Code
Command Parameter
Description
A5h
Data Byte
Writes a single data byte to the 1-Wire line.
To write commands or data to the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit
commands, but faster due to less I C traffic.
Typical Use
Restriction
2
1-Wire activity must have ended before the DS2484 can process this command.
Command code and data byte are not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
Error Response
8 x t
byte.
+ maximum 262.5ns, counted from falling edge of the last bit (LSB) of the data
SLOT
Command Duration
1-Wire Activity
Begins maximum 262.5ns after falling SCL edge of the LSB of the data byte (i.e., before the
data-byte acknowledge). Note: The bit order on the I C bus and the 1-Wire line is different
(1-Wire: LSB first; I C: MSB first). Therefore, 1-Wire activity cannot begin before the DS2484
2
2
has received the full data byte.
Read Pointer Position
Status Bits Affected
Status register (for busy polling).
1WB (set to 1 for 8 x t
).
SLOT
Device Configurations Affected 1WS, SPU, APU apply.
Port Configurations Affected
t
, t
, t
, t
, and R
current values apply.
RSTL MSP W0L REC0
WPU
1-Wire Read Byte
Command Code
96h
Command Parameter
None
Generates eight read-data time slots on the 1-Wire line and stores result in the Read Data
register.
Description
To read data from the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands
with V = 1 (write-one time slot), but faster due to less I C traffic.
Typical Use
Restriction
2
1-Wire activity must have ended before the DS2484 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received
and the command is ignored.
Error Response
8 x t
acknowledge bit.
+ maximum 262.5ns, counted from the falling SCL edge of the command code
SLOT
Command Duration
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status register (for busy polling). Note: To read the data byte received from the 1-Wire line,
issue the Set Read Pointer command and select the Read Data register. Then access the
DS2484 in read mode.
Read Pointer Position
Status Bits Affected
1WB (set to 1 for 8 x t
).
SLOT
Device Configurations Affected 1WS, APU apply.
Port Configurations Affected
t
, t
, t
, t
, and R
current values apply.
RSTL MSP W0L REC0
WPU
Maxim Integrated
17
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
1-Wire Triplet
Command Code
78h
Command Parameter
Direction Byte
Generates three time slots: two read time slots and one write time slot at the 1-Wire line.
The type of write time slot depends on the result of the read time slots and the direction
byte. The direction byte determines the type of write time slot if both read time slots are 0 (a
typical case). In this case, the DS2484 generates a write-one time slot if V = 1 and a write-
zero time slot if V = 0. See Table 9.
Description
If the read time slots are 0 and 1, they are followed by a write-zero time slot.
If the read time slots are 1 and 0, they are followed by a write-one time slot.
If the read time slots are both 1 (error case), the subsequent write time slot is a write-one.
To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be
executed 64 times to identify and address one device.
Typical Use
Restriction
1-Wire activity must have ended before the DS2484 can process this command.
Command code and direction byte is not acknowledged if 1WB = 1 at the time the
command code is received and the command is ignored.
Error Response
3 x t
direction byte.
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the
SLOT
Command Duration
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MSB of the direction byte.
Status Register (for busy polling).
Read Pointer Position
1WB (set to 1 for 3 x t
), SBR is updated at the first t
, TSB and DIR are updated at
SLOT
MSR
Status Bits Affected
the second t
(i.e., at t
+ t
).
MSR
SLOT
MSR
Device Configurations Affected 1WS, APU apply.
Port Configurations Affected , t , t , t
t
, and R
current values apply.
RSTL MSP W0L REC0
WPU
Table 9. Bit Allocation in the Direction Byte
BIT 7
BIT 6
BIT ±
BIT 4
BIT ꢀ
BIT 2
BIT 1
BIT 0
V
X
X
X
X
X
X
X
X = Don’t care
Maxim Integrated
18
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
MSB FIRST
MSB
LSB
MSB
LSB
SDA
SCL
SLAVE
ADDRESS
R/W
8
ACK
9
DATA
ACK
9
DATA
ACK/
NACK
1–7
1–7
8
1–7
8
9
IDLE
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
2
Figure 7. I C Protocol Overview
A device that sends data on the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The device that controls the communication is
called a master. The devices that are controlled by the
master are slaves. To be individually accessed, each
device must have a slave address that does not conflict
with other devices on the bus.
7-BIT SLAVE ADDRESS
A6
0
A5
0
A4
1
A3
1
A2
0
A1
A0
0
0
R/W
MSB
DETERMINES
READ OR WRITE
Data transfers can be initiated only when the bus is not
busy. The master generates the serial clock (SCL), con-
trols the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data
is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.
Figure 8. DS2484 Slave Address
2
I C Interface
General Characteristics
2
The I C bus uses a data line (SDA) and a clock signal
(SCL) for communication. Both SDA and SCL are bidi-
rectional lines connected to a positive supply voltage
through a pullup resistor. When there is no communica-
tion, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on the
Slave Address
Figure 8 shows the slave address to which the DS2484
responds. The slave address is part of the slave address/
control byte. The last bit of the slave address/control
byte (R/W) defines the data direction. When set to 0,
subsequent data flows from master to slave (write access
mode); when set to 1, data flows from slave to master
(read access mode).
2
I C bus can be transferred at rates of up to 100kbps in
standard mode and up to 400kbps in fast mode. The
DS2484 works in both modes.
Maxim Integrated
19
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
remain valid and unchanged during the entire high
pulse of SCL plus the required setup and hold time
I C Definitions
The following terminology is commonly used to describe
I C data transfers. See Figure 9 for a timing diagram.
2
(t
after the falling edge of SCL and t
HD:DAT
SU:DAT
before the rising edge of SCL; see Figure 9). There is
one clock pulse per bit of data. Data is shifted into the
receiving device during the rising edge of SCL pulse.
Bus Idle or Not Busy: Both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: To initiate communication with a
slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time
(minimum t
+ t in Figure 9) before the next ris-
SU:DAT
R
ing edge of SCL to start reading. The slave shifts out
each data bit on SDA at the falling edge of the previ-
ous SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. The master generates
all SCL clock pulses, including those needed to read
from a slave.
STOP Condition: To end communication with a
slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of SDA
from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs are
commonly used for read accesses to select a specific
data source or address from which to read. The mas-
ter can use a repeated START condition at the end
of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle after
a STOP condition.
Acknowledge: Typically a receiving device, when
addressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must
generate a clock pulse that is associated with this
acknowledge bit. A device that acknowledges must
pull SDA low during the acknowledge clock pulse
in such a way that SDA is stable low during the high
period of the acknowledge-related clock pulse plus
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA must
the required setup and hold time (t
after the
HD:DAT
falling edge of SCL and t
edge of SCL).
before the rising
SU:DAT
SDA
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
SCL
t
HIGH
SPIKE
SUPPRESSION
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V .
IH(MIN)
IL(MAX)
2
Figure 9. I C Timing Diagram
Maxim Integrated
20
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Not Acknowledged by Slave: A slave device could
2
I C Communication Examples
be unable to receive or transmit data, e.g., because
it is busy performing a real-time function or is in
sleep mode. In this case, the slave device does not
acknowledge its slave address and leaves the SDA
line high. A slave device that is ready to communicate
acknowledges at least its slave address. However,
some time later the slave can refuse to accept data,
e.g., because of an invalid command or parameter.
In this case, the slave device does not acknowledge
any of the bytes that it refuses and leaves SDA high.
In either case, after a slave has failed to acknowledge,
the master first should generate a repeated START
condition or a STOP condition followed by a START
condition to begin a new data transfer.
2
See Table 10 and Table 11 for the I C communication
legend and data direction codes.
2
Table 10. I C Communication—Legend
SYMBOL
S
DESCRIPTION
START Condition
AD, 0
AD, 1
Sr
Select DS2484 for Write Access
Select DS2484 for Read Access
Repeated START Condition
STOP Condition
P
A
Acknowledged
A\
Not Acknowledged
Not Acknowledged by Master: At some time when
receiving data, the master must signal an end of data
to the slave device. To achieve this, the master does
not acknowledge the last byte that it has received
from the slave. In response, the slave releases SDA,
allowing the master to generate the STOP condition.
(Idle)
<byte>
DRST
SRP
Bus Not Busy
Transfer of One Byte
Command “Device Reset” (F0h)
Command “Set Read Pointer” (E1h)
Command “Write Device Configuration” (D2h)
Command “Adjust 1-Wire Port” C3h)
Command “1-Wire Reset” (B4h)
Command “1-Wire Single Bit” (87h)
Command “1-Wire Write Byte” (A5h)
Command “1-Wire Read Byte” (96h)
Command “1-Wire Triplet” (78h)
WCFG
ADJP
1WRS
1WSB
1WWB
1WRB
1WT
Writing to the DS2484
To write to the DS2484, the master must access the
device in write mode, i.e., the slave address must be sent
with the direction bit set to 0. The next byte to be sent is
a command code, which, depending on the command,
may be followed by a command parameter. The DS2484
acknowledges valid command codes and expected/
valid command parameters. Additional bytes or invalid
command parameters are never acknowledged.
Table 11. Data Direction Codes
Reading from the DS2484
To read from the DS2484, the master must access the
device in read mode, i.e., the slave address must be sent
with the direction bit set to 1. The read pointer determines
the register that the master reads from. The master can
continue reading the same register over and over again,
without having to readdress the device, e.g., to watch
the 1WB changing from 1 to 0. To read from a different
register, the master must issue the Set Read Pointer com-
mand and then access the DS2484 again in read mode.
Master-to-Slave Slave-to-Master
Maxim Integrated
21
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
I C Communication Examples (continued)
Device Reset (After Power-Up)
S
AD,0
A
DRST
A
Sr
AD,1
A
<byte> A\
P
Activities that are underlined denote an optional read access to verify the success of the command.
Set Read Pointer (To Read from Another Register)
Case A: Valid Read Pointer Code
S
AD,0
A
SRP
A
C3h
A
P
C3h is the read pointer code for the Device Configuration register.
Case B: Invalid Read Pointer Code
S
AD,0
A
SRP
A
E5h
A\
P
E5h is an invalid read pointer code.
Write Device Configuration (Before Starting 1-Wire Activity)
Case A: 1-Wire Idle (1WB = 0)
S
AD,0
A
WCFG
A
<byte>
A
Sr
AD,1
A
<byte> A\
P
Activities that are underlined denote an optional read access to verify the success of the command.
Case B: 1-Wire Busy (1WB = 1)
S
AD,0
A
WCFG
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Adjust 1-Wire Port (after power-up, e.g., to select a 1-Wire timing other than the default)
Case A: 1-Wire Idle (1WB = 0)
S
AD,0
A
ADJP
A
<byte>
A
<byte>
A
P
Repeat to set additional port parameters
The control byte is always acknowledged, regardless of its value. See the Adjust 1-Wire Port command description
for the format of the control byte.
Case B: 1-Wire Busy (1WB = 1)
S
AD,0
A
ADJP
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated
22
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
I C Communication Examples (continued)
Verifying the 1-Wire port configuration
The Adjust 1-Wire Port command sets the read pointer to the Port Configuration register. If other commands were
issued to the DS2484 since then, use the Set Read Pointer command first to position the read pointer to the Port
Configuration register.
Condition: 1-Wire Idle (1WB = 0), Read Pointer at Port Configuration Register
S
AD,1
A
<byte>
A
<byte>
A
<byte>
A\
P
Repeat to read additional port parameters
1-Wire Reset (To Begin or End 1-Wire Communication)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling to Read the Result
S
AD,0
A
1WRS
A
P
(Idle)
S
AD,1
A
<byte> A\
P
In the first cycle, the master sends the command. Then the master waits (Idle) for the 1-Wire reset to complete. In
the second cycle, the DS2484 is accessed to read the result of the 1-Wire reset from the Status register.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed, then Read the Result
S
AD,0
A
1WRS
A
Sr
AD,1
A
<byte>
A
<byte> A\
P
Repeat until the 1WB bit has changed to 0.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WRS
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated
23
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
I C Communication Examples (continued)
1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WSB
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Single Bit command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WSB
A
<byte>
A
Repeat until the 1WB bit
has changed to 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WSB
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
1-Wire Write Byte (To Send a Command Code or Data Byte to the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WWB
A
33h
A
P
(Idle)
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to
complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed.
S
AD,0
A
1WWB
A
33h
A
Repeat until the 1WB bit
has changed to 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WWB
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated
24
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
I C Communication Examples (continued)
1-Wire Read Byte (To Read a Byte from the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time
S
AD,0
A
1WRB
A
P
(Idle)
S
AD,0
A
SRP
A
E1h
A
Sr
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the Read Data register
(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case B: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer Before Idle Time
S
AD,0
A
1WRB
A
Sr
AD,0
A
SRP
A
E1h
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The read pointer is set to the Read Data register (code E1h) while the 1-Wire Read Byte command is still in prog-
ress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was obtained
from the 1-Wire line.
Case C: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WRB
A
Repeat until the 1WB bit
has changed to 0.
Sr
AD,1
A
A
<byte>
A
<byte> A\
Sr
AD,0
A
SRP
E1h
A
Sr
AD,1
A
<byte> A\
P
Poll the Status segister until the 1WB bit has changed from 1 to 0. Then set the read pointer to the Read Data reg-
ister (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case D: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WRB
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated
25
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
2
I C Communication Examples (continued)
1-Wire Triplet (To Perform a Search ROM Function on 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WT
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Triplet command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WT
A
<byte>
A
Repeat until the 1WB bit
has changed to 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Triplet command.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WT
A\
P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated
26
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
must not exceed 300ns. Assuming maximum rise time,
Applications Information
the maximum resistor value at any given capacitance C
B
is calculated as: R
= ꢀ00ns/(C x ln(7/ꢀ)). For a
P(MAX)
B
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS2484 that requires
a pullup resistor to realize high-logic levels. Because the
DS2484 uses SCL only as input (no clock stretching), the
master can drive SCL either through an open-drain/col-
lector output with a pullup resistor or a push-pull output.
bus capacitance of 400pF, the maximum pullup resistor
would be 885I.
Because an 885I pullup resistor, as would be required
to meet the rise time specification at 400pF bus capaci-
tance, is lower than R
is necessary. The “Maximum Load at Minimum R Fast
at 5.5V, a different approach
P(MIN)
P
Pullup Resistor R Sizing
P
Mode” line in Figure 10 is generated by first calculating
the minimum pullup resistor at any given operating volt-
2
According to the I C specification, a slave device must
be able to sink at least 3mA at a V of 0.4V. This DC
OL
age (“Minimum R ” line) and then calculating the respec-
P
condition determines the minimum value of the pullup
tive bus capacitance that yields a 300ns rise time.
2
resistor: R
lup voltage V
= (V
- 0.4V)/ꢀmA. With an I C pul-
CI2C
P(MIN)
Only for pullup voltages of 3V and lower can the maxi-
mum permissible 400pF bus capacitance be maintained.
A reduced 300pF bus capacitance is acceptable for 4V
and lower pullup voltages. For fast mode operation at
any pullup voltage, the bus capacitance must not exceed
200pF. The corresponding pullup resistor value at the
of 5.5V, the minimum value for the pul-
CI2C
lup resistor is 1.7kI. The “Minimum R ” line in Figure 10
P
shows how the minimum pullup resistor changes with the
operating (pullup) voltage.
2
For I C systems, the rise time and fall time are measured
from 30% to 70% of the pullup voltage. The maximum
voltage is indicated by the “Minimum R ” line.
P
bus capacitance, C , is 400pF. The maximum rise time
B
2000
1600
1200
500
400
300
200
MINIMUM R
P
800
400
0
MAXIMUM LOAD AT MINIMUM R FAST MODE
P
100
0
1
2
3
4
5
PULLUP VOLTAGE (V)
2
Figure 10. I C Fast Mode Pullup Resistor Selection Chart
Maxim Integrated
27
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Ordering Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE PIN-PACKAGE
DS2484R+T
DS2484Q+T
-40NC to +85NC 6 SOT23 (3k pieces)
-40NC to +85NC 8 TDFN-EP* (2.5k pieces)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 SOT23
U6SN+1
T823+1
21-00±8
21-0174
90-017±
90-0091
8 TDFN-EP
Maxim Integrated
28
DS2484
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
5/13
Initial release
—
9
7/15
Updated the Presence-Pulse Detect (PPD) and Short Detected (SD) sections
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
29
©
2015 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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