DS26334_技术文档

19-5753; Rev 3/11

DEMO KIT AVAILABLE

DS26334

3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul

Line Interface Unit

GENERAL DESCRIPTION

FEATURES

.

16 E1, T1, or J1 Short/Long-Haul Line

Interface Units

The DS26334 is a 16-channel short/long-haul line

interface unit (LIU) that supports E1/T1/J1 from a

single 3.3V power supply. A single bill of material can

support E1/T1/J1 that requires no external

termination. Redundancy is supported through

nonintrusive monitoring, optimal high-impedance

modes and configurable 1:1 or 1+1 backup

enhancements. An on-chip synthesizer generates the

E1/T1/J1 clock rates by a single master clock input of

various frequencies. Two clock output references are

also offered. The device is offered in a 256-pin

TE-CSBGA, the smallest package available for a

16-channel LIU.

.

Independent E1, T1 or J1 Selections

Fully Internal Impedance Match Requires No

External Resistors

.

Software-Selectable Transmit and Receive-

Side Impedance Match

.

Crystal-Less Jitter Attenuator

Selectable Single-Rail and Dual-Rail Mode

and AMI or HDB3/B8ZS Line Encoding and

Decoding

.

Detection and Generation of AIS

Digital/Analog Loss of Signal Detection as

per T1.231, G.775 and ETS 300 233

APPLICATIONS

T1 Digital Cross-Connects

ATM and Frame Relay Equipment

Wireless Base Stations

ISDN Primary Rate Interface

E1/T1/J1 Multiplexer and Channel Banks

E1/T1/J1 LAN/WAN Routers

.

External Master Clock Can Be Multiple of

2.048MHz or 1.544MHz for T1/J1 or E1

Operation; This Clock Will Be Internally

Adapted for T1 or E1 Usage

.

Receiver Signal Level Indicator from -2.5dB to

-38dB in T1 Mode and -3dB to -43dB in E1

Mode in 2.5dB Increments

FUNCTIONAL DIAGRAM

.

Two Built-In BERT Testers for Diagnostics

JTAG

MODE

LOSS

8-Bit Parallel Interface Support for Intel or

Motorola Mode or a 4-Wire Serial Interface

SOFTWARE CONTROL

AND JTAG

.

Transmit Short-Circuit Protection

G.772 Nonintrusive Monitoring

Receive Monitor Mode Handles Combinations

of 14dB to 30dB of Resistive Attenuation

Along with 12dB to 30dB of Cable Attenuation

RTIP

RPOS

RNEG

RCLK

RECEIVER

RRING

TPOS

TTIP

TNEG

TCLK

TRANSMITTER

TRING

.

Specification Compliance to the Latest T1

and E1 Standards

1

.

Single 3.3V Supply with 5V Tolerant I/O

JTAG Boundary Scan as Per IEEE 1149.1

ORDERING INFORMATION

16

PART

TEMP RANGE PIN-PACKAGE

DS26334G

DS26334G+

DS26334GN

0°C to +70°C 256 TE-CSBGA

-40°C to +85°C 256 TE-CSBGA

DS26334GN+ -40°C to +85°C 256 TE-CSBGA

+Denotes a lead(Pb)-free/RoHS compliant package.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TABLE OF CONTENTS

1

STANDARDS COMPLIANCE ........................................................................................................ 6

1.1 TELECOM SPECIFICATIONS COMPLIANCE ....................................................................................... 6

DETAILED DESCRIPTION ............................................................................................................ 7

2

3

4

5

BLOCK DIAGRAMS ...................................................................................................................... 8

PIN DESCRIPTION ...................................................................................................................... 10

FUNCTIONAL DESCRIPTION ..................................................................................................... 17

5.1 PORT OPERATION ...................................................................................................................... 17

5.1.1 Serial Port Operation ..................................................................................................................... 17

5.1.2 Parallel Port Operation................................................................................................................... 18

5.1.3 Interrupt Handling .......................................................................................................................... 18

5.2 POWER-UP AND RESET .............................................................................................................. 19

5.3 MASTER CLOCK ......................................................................................................................... 19

5.4 TRANSMITTER............................................................................................................................ 20

5.4.1 Transmit Line Templates................................................................................................................ 22

5.4.2 LIU Transmit Front-End.................................................................................................................. 25

5.4.3 Transmit Dual-Rail Mode ............................................................................................................... 26

5.4.4 Transmit Single-Rail Mode............................................................................................................. 26

5.4.5 Zero Suppression—B8ZS or HDB3................................................................................................ 26

5.4.6 Transmit Power-Down.................................................................................................................... 26

5.4.7 Transmit All Ones .......................................................................................................................... 27

5.4.8 Driver Fail Monitor.......................................................................................................................... 27

5.5 RECEIVER.................................................................................................................................. 27

5.5.1 Receiver Impedance Matching Calibration ..................................................................................... 27

5.5.2 Receiver Monitor Mode.................................................................................................................. 27

5.5.3 Peak Detector and Slicer ............................................................................................................... 28

5.5.4 Receive Level Indicator.................................................................................................................. 28

5.5.5 Clock and Data Recovery............................................................................................................... 28

5.5.6 Loss of Signal................................................................................................................................ 28

5.5.7 AIS ................................................................................................................................................ 29

5.5.8 Receive Dual-Rail Mode ................................................................................................................ 30

5.5.9 Receive Single-Rail Mode.............................................................................................................. 30

5.5.10 Bipolar Violation and Excessive Zero Detector ............................................................................... 30

5.6 JITTER ATTENUATOR.................................................................................................................. 31

5.7 G.772 MONITOR ........................................................................................................................ 32

5.8 LOOPBACKS............................................................................................................................... 32

5.8.1 Analog Loopback ........................................................................................................................... 32

5.8.2 Digital Loopback ............................................................................................................................ 33

5.8.3 Remote Loopback.......................................................................................................................... 33

5.9 BERT........................................................................................................................................ 34

5.9.1 General Description ....................................................................................................................... 34

5.9.2 Configuration and Monitoring ......................................................................................................... 35

5.9.3 Receive Pattern Detection.............................................................................................................. 36

5.9.4 Transmit Pattern Generation.......................................................................................................... 38

6

7

REGISTER MAPS AND DEFINITION .......................................................................................... 39

6.1 REGISTER DESCRIPTION............................................................................................................. 48

6.1.1 Primary Register Bank................................................................................................................... 48

6.1.2 Secondary Register Bank............................................................................................................... 63

6.1.3 Individual LIU Register Bank.......................................................................................................... 66

6.1.4 BERT Registers............................................................................................................................. 85

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................. 92

7.1 TAP CONTROLLER STATE MACHINE............................................................................................ 93

7.1.1 Test-Logic-Reset ........................................................................................................................... 93

7.1.2 Run-Test-Idle................................................................................................................................. 93

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

7.1.3 Select-DR-Scan............................................................................................................................. 93

7.1.4 Capture-DR ................................................................................................................................... 93

7.1.5 Shift-DR......................................................................................................................................... 93

7.1.6 Exit1-DR........................................................................................................................................ 93

7.1.7 Pause-DR...................................................................................................................................... 93

7.1.8 Exit2-DR........................................................................................................................................ 93

7.1.9 Update-DR..................................................................................................................................... 93

7.1.10 Select-IR-Scan............................................................................................................................... 94

7.1.11 Capture-IR..................................................................................................................................... 94

7.1.12 Shift-IR .......................................................................................................................................... 94

7.1.13 Exit1-IR.......................................................................................................................................... 94

7.1.14 Pause-IR ....................................................................................................................................... 94

7.1.15 Exit2-IR.......................................................................................................................................... 94

7.1.16 Update-IR ...................................................................................................................................... 94

7.2 INSTRUCTION REGISTER............................................................................................................. 96

7.2.1 EXTEST ........................................................................................................................................ 96

7.2.2 HIGHZ........................................................................................................................................... 96

7.2.3 CLAMP.......................................................................................................................................... 96

7.2.4 SAMPLE/PRELOAD...................................................................................................................... 96

7.2.5 IDCODE ........................................................................................................................................ 96

7.2.6 BYPASS........................................................................................................................................ 96

7.3 TEST REGISTERS ....................................................................................................................... 97

7.3.1 Boundary Scan Register ................................................................................................................ 97

7.3.2 Bypass Register............................................................................................................................. 97

7.3.3 Identification Register .................................................................................................................... 97

8

9

DC ELECTRICAL CHARACTERIZATION ................................................................................... 98

8.1 DC PIN LOGIC LEVELS................................................................................................................ 98

8.2 SUPPLY CURRENT AND OUTPUT VOLTAGE................................................................................... 98

AC TIMING CHARACTERISTICS ................................................................................................ 99

9.1 LINE INTERFACE CHARACTERISTICS ............................................................................................ 99

9.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS...............................................................100

9.3 SERIAL PORT............................................................................................................................112

9.4 SYSTEM TIMING ........................................................................................................................113

9.5 JTAG TIMING............................................................................................................................115

10 PIN CONFIGURATION................................................................................................................116

11 PACKAGE INFORMATION.........................................................................................................117

12 THERMAL INFORMATION.........................................................................................................118

13 DATA SHEET REVISION HISTORY...........................................................................................120

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LIST OF FIGURES

Figure 3-1. Block Diagram ..................................................................................................................................... 8

Figure 3-2. Receive Logic Detail ............................................................................................................................ 9

Figure 3-3. Transmit Logic Detail ........................................................................................................................... 9

Figure 5-1. Serial Port Operation for Write Access ............................................................................................... 17

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0........................................................................ 17

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1........................................................................ 18

Figure 5-4. Interrupt Handling Flow Diagram........................................................................................................ 19

Figure 5-5. Prescaler PLL and Clock Generator ................................................................................................... 20

Figure 5-6. T1 Transmit Pulse Templates............................................................................................................. 23

Figure 5-7. E1 Transmit Pulse Templates............................................................................................................. 24

Figure 5-8. LIU Front-End .................................................................................................................................... 25

Figure 5-9. Jitter Attenuation................................................................................................................................ 31

Figure 5-10. Analog Loopback ............................................................................................................................. 32

Figure 5-11. Digital Loopback .............................................................................................................................. 33

Figure 5-12. Remote Loopback............................................................................................................................ 33

Figure 5-13. PRBS Synchronization State Diagram.............................................................................................. 36

Figure 5-14. Repetitive Pattern Synchronization State Diagram............................................................................ 37

Figure 7-1. JTAG Functional Block Diagram......................................................................................................... 92

Figure 7-2. TAP Controller State Diagram ............................................................................................................ 95

Figure 9-1. Intel Nonmuxed Read Cycle............................................................................................................. 101

Figure 9-2. Intel Mux Read Cycle....................................................................................................................... 102

Figure 9-3. Intel Nonmux Write Cycle................................................................................................................. 104

Figure 9-4. Intel Mux Write Cycle ....................................................................................................................... 105

Figure 9-5. Motorola Nonmux Read Cycle.......................................................................................................... 107

Figure 9-6. Motorola Mux Read Cycle................................................................................................................ 108

Figure 9-7. Motorola Nonmux Write Cycle.......................................................................................................... 110

Figure 9-8. Motorola Mux Write Cycle ................................................................................................................ 111

Figure 9-9. Serial Bus Timing Write Operation.................................................................................................... 112

Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0 .......................................................................... 112

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1 .......................................................................... 112

Figure 9-12. Transmitter Systems Timing........................................................................................................... 113

Figure 9-13. Receiver Systems Timing............................................................................................................... 114

Figure 9-14. JTAG Timing.................................................................................................................................. 115

Figure 10-1. 256-Ball TE-CSBGA....................................................................................................................... 116

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LIST OF TABLES

Table 4-1. Pin Descriptions.................................................................................................................................. 10

Table 5-1. Parallel Port Mode Selection and Pin Functions................................................................................... 18

Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters........................................... 21

Table 5-3. Registers Related to Control of DS26334 Transmitters........................................................................ 21

Table 5-4. Template Selections for Short-Haul Mode............................................................................................ 22

Table 5-5. Template Selections for Long-Haul Mode............................................................................................ 22

Table 5-6. LIU Front-End Values.......................................................................................................................... 26

Table 5-7. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications .......................................... 28

Table 5-8. AIS Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications............................................ 29

Table 5-9. AIS Detection and Reset Criteria for DS26334..................................................................................... 29

Table 5-10. Registers Related to AIS Detection.................................................................................................... 30

Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting................................................................. 30

Table 5-12. Pseudorandom Pattern Generation ................................................................................................... 35

Table 5-13. Repetitive Pattern Generation............................................................................................................ 35

Table 6-1. Primary Register Set ........................................................................................................................... 40

Table 6-2. Secondary Register Set....................................................................................................................... 41

Table 6-3. Individual LIU Register Set.................................................................................................................. 42

Table 6-4. BERT Register Set.............................................................................................................................. 43

Table 6-5. Primary Register Set Bit Map .............................................................................................................. 44

Table 6-6. Secondary Register Set Bit Map.......................................................................................................... 45

Table 6-7. Individual LIU Register Set Bit Map ..................................................................................................... 46

Table 6-8. BERT Register Bit Map ....................................................................................................................... 47

Table 6-9. G.772 Monitoring Control (LIU 1)......................................................................................................... 54

Table 6-10. G.772 Monitoring Control (LIU 9)....................................................................................................... 54

Table 6-11. TST Template Select Transmitter Register (LIUs 1–8) ....................................................................... 59

Table 6-12. TST Template Select Transmitter Register (LIUs 9–16) ..................................................................... 59

Table 6-13. Template Selection............................................................................................................................ 60

Table 6-14. Address Pointer Bank Selection ........................................................................................................ 63

Table 6-15. DS26334 MCLK Selections ............................................................................................................... 69

Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection ............................................................................. 75

Table 6-17. Receiver Signal Level........................................................................................................................ 76

Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8........................................................................... 80

Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16 ......................................................................... 80

Table 6-20. PLL Clock Select............................................................................................................................... 83

Table 6-21. Clock A Select................................................................................................................................... 83

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture ................................................................................... 96

Table 7-2. ID Code Structure ............................................................................................................................... 97

Table 7-3. Device ID Codes ................................................................................................................................. 97

Table 8-1. Recommended DC Operating Conditions............................................................................................ 98

Table 8-2. Pin Capacitance.................................................................................................................................. 98

Table 8-3. DC Characteristics .............................................................................................................................. 98

Table 9-1. Transmitter Characteristics.................................................................................................................. 99

Table 9-2. Receiver Characteristics...................................................................................................................... 99

Table 9-3. Intel Read Mode Characteristics........................................................................................................ 100

Table 9-4. Intel Write Cycle Characteristics........................................................................................................ 103

Table 9-5. Motorola Read Cycle Characteristics................................................................................................. 106

Table 9-6. Motorola Write Cycle Characteristics................................................................................................. 109

Table 9-7. Serial Port Timing Characteristics...................................................................................................... 112

Table 9-8. Transmitter System Timing................................................................................................................ 113

Table 9-9. Receiver System Timing.................................................................................................................... 114

Table 9-10. JTAG Timing Characteristics........................................................................................................... 115

Table 12-1. Thermal Characteristics................................................................................................................... 118

Table 12-2. Package Power Dissipation (for Thermal Considerations)................................................................ 118

Table 12-3. Per-Channel Power-Down Savings (for Thermal Considerations)..................................................... 119

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

1 STANDARDS COMPLIANCE

1.1 Telecom Specifications Compliance

The DS26334 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1

and E1 Specifications and relevant sections that are applicable to the DS26334.

•

T1-Related Telecommunications Specifications

•

ANSI T1.102: Digital Hierarchy Electrical Interface

ANSI T1.231: Digital Hierarchy- Layer 1 in Service Performance Monitoring

ANSI T1.403: Network and Customer Installation Interface- DS1 Electrical Interface

G.736: Characteristics of a synchronous digital multiplex equipment operating at 2048kbps

G.823: The control of jitter and wander within digital networks which are based on the 2048kbps hierarchy

Pub 62411: High Capacity Terrestrial Digital Service

ITU-T G.772: Protected monitoring points provided on digital transmission systems

•

E1-Related Telecommunications Specifications

•

ITU-T G.703: Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces

ITU-T G.736: Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps

ITU-T G.742: Second Order Digital Multiplex Equipment Operating at 8448kbps

ITU-T G.772: Protected monitoring points provided on digital transmission systems

ITU-T G.775: Loss of signal (LOS) and alarm indication signal (AIS) defect detection and clearance criteria

ETS 300 166: Physical and electrical characteristics of hierarchical digital interfaces for equipment using

the 2048kbps-based plesiosynchronous or synchronous digital hierarchies

•

ETS 300 233: Integrated Services Digital Network (ISDN)

G.736: Characteristics of a synchronous digital multiplex equipment operating at 2048kbps

G.823: The control of jitter and wander within digital networks which are based on the 2048kbps hierarchy

Pub 62411: High Capacity Terrestrial Digital Service

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

2 DETAILED DESCRIPTION

The DS26334 is a single-chip, 16-channel, long-haul and short-haul line interface unit for T1 (1.544Mbps) and E1

(2.048Mbps) applications. Sixteen independent receivers and transmitters are provided in a single TE-CSBGA

package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single master

reference clock. This clock can be either 1.544MHz or 2.048MHz or multiples thereof, and either frequency can be

internally adapted for T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive

paths reduces external component count. The transmit waveforms are compliant to G.703 and T1.102

specification. The DS26324 provides software-selectable internal transmit termination for 100Ω T1 twisted pair,

110Ω J1 twisted pair, 120Ω E1 twisted pair, and 75Ω E1 coaxial applications. The transmitters have fast high-

impedance capability and can be individually powered down.

The receivers can function with up to a receive signal attenuation of 36dB for T1 mode, or 43dB for E1 mode. A

monitor gain setting also can be enabled to provide 14dB, 20dB, 26dB, and 32dB of resistive gain. The DS26334

can be configured as a 14-channel LIU with Channel 1 and 9 used for nonintrusive monitoring in accordance with

G.772. The receivers and transmitters can be programmed into single or dual-rail mode. AMI or HDB3/B8ZS

encoding and decoding is selectable in single-rail mode. A 128-bit crystal-less on-board jitter attenuator for each

LIU can be placed in receive or transmit directions. The jitter attenuator meets the ETS CTR12/13 ITU-T G.736,

G.742, G.823, and AT&T Pub 62411 specifications.

The DS26334 detects and generates AIS in accordance with T1.231, G.775, and ETS 300 233. Loss of signal is

detected in accordance with T1.231, G.775, and ETS 300 233. The DS26334 can perform digital, analog, remote,

and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.

The DS26334 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial

port selection is also available for configuration and monitoring of the device.

The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled

into the RTIP and RRING pins of the DS26334. The user can terminate the receive line using only internal

termination that requires no external resistors. Or, the user has the option to use partially internal impedance

matching using a common 120Ω external resistor for E1, T1, and J1, and matching the line impedance internally to

obtain 75Ω, 100Ω, 110Ω, or 120Ω termination values. Note that fully internal impedance match requires a 1:1

transformer on the receive line. Partially internal impedance matching supports either a 1:1 or a 1:2 transformer on

the receive line. If a 1:2 transformer is used, the external termination resistor should be 30Ω. For long-haul

applications, a 1:1 transformer on the receive line is preferred. The DS26334 drives the E1 or T1 line from the TTIP

and TRING pins by a 1:2 coupling transformer.

The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator

outputting the received line clock at RCLK and data at RPOS and RNEG.

The DS26334 receivers can recover data and clock for up to 36dB of attenuation of the transmitted signals in T1

mode and 43dB for E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8.

Receiver 9 can monitor the performance of receivers 10 to 16 or transmitters 10 to 16.

The DS26334 contains 16 identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to

TCLK. The data at these pins can be single-rail or dual-rail. This data is processed by waveshaping circuitry and

the line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

3 BLOCK DIAGRAMS

Figure 3-1. Block Diagram

TYPICAL OF ALL 16 CHANNELS

T1CLK E1CLK

DS26334

MUX

VCO/PLL

LOS

RPOS/RDAT

RRING

RTIP

Receive Logic

RCLK

RNEG/CV

Unframed All

Ones Insertion

TPOS/TDAT

TCLK

TRING

Transmit Logic

TTIP

OE

TNEG

Reset

T1CLK

E1CLK

16

Control

and

Interrupt

Master Clock

Adapter

Port Interface

JTAG PORT

5

8

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 3-2. Receive Logic Detail

RCLK

Excessive

Zero

Detect

T1.231

IAISEL

AISEL

POS

NEG

EN

RPOS

All Ones

Insert

(AIS)

MUX

NRZ Data

B8ZS/HDB3/AMI

Decoder (G.703, T1.102)

RNEG/CV

BPVs, Code Violatiions

(T1.231, O.161)

BPV/CV/EXZ

AIS

Detector

G.775, ETSI 300233,

T1.231

Figure 3-3. Transmit Logic Detail

B8ZS/HDB3/AMI

Coder (G.703,

T1.102)

To Remote

Loopback

BPV

Insert

MUX

TPOS/

TDATA

TNEG/

BPV

TCLK

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

4 PIN DESCRIPTION

Table 4-1. Pin Descriptions

NAME

TYPE

FUNCTION

ANALOG TRANSMIT AND RECEIVE

TTIP1

TTIP2

E1

F1

TTIP3

K1

TTIP4

TTIP5

TTIP6

TTIP7

TTIP8

TTIP9

L1

T5

T6

Transmit Bipolar Tip for Channels 1–16. These pins are differential

line driver tip outputs. These pins can be high impedance if pin OE is

low. When “1” is set in the Output Enable Register OE bit, the

associated TTIPn pin will be enabled when the OE pin is high. The

differential outputs of TTIPn and TRINGn can provide internal

matched impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

T10

T11

M16

L16

G16

F16

A12

A11

A7

A6

E2

F2

K2

Analog

output

TTIP10

TTIP11

TTIP12

TTIP13

TTIP14

TTIP15

TTIP16

TRING1

TRING2

TRING3

TRING4

TRING5

TRING6

TRING7

TRING8

TRING9

TRING10

TRING11

TRING12

TRING13

TRING14

TRING15

TRING16

RTIP1

If the TCLK input for a given LIU is held low for 64 MCLKs, that LIU’s

transmitter is powered down and the TTIP/TRING outputs are high

impedance.

L2

R5

R6

Transmit Bipolar Ring for Channels 1–16. These pins are

differential line driver ring outputs. These pins can be high impedance

if pin OE is low. When “1” is set in the Output Enable Register OE bit,

the associated TRINGn pin will be enabled when the OE pin is high.

The differential outputs of TTIPn and TRINGn can provide internal

matched impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

R10

R11

M15

L15

G15

F15

B12

B11

B7

Analog

output

If the TCLK input for a given LIU is held low for 64 MCLKs, that LIU’s

transmitter is powered down and the TTIP/TRING outputs are high

impedance.

B6

A1

RTIP2

C1

RTIP3

H1

RTIP4

N1

RTIP5

T1

RTIP6

RTIP7

RTIP8

RTIP9

RTIP10

RTIP11

RTIP12

RTIP13

RTIP14

RTIP15

RTIP16

T3

T8

Receive Bipolar Tip for Channels 1–16. Receive analog input for

differential receiver. Data and clock are recovered and output at

RPOS/RNEG and RCLK pins, respectively. The differential inputs of

RTIPn and RRINGn can provide internal impedance matching with

external resistance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

T13

T16

P16

J16

D16

A16

A14

A9

Analog

input

A4

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

Resistor Reference. If fully internal receive impedance match is

selected, a 16kΩ ±1% resistor to GND is needed. If not used, tie pin

low.

Analog

input

RESREF

R9

RRING1

RRING2

RRING3

RRING4

RRING5

RRING6

RRING7

RRING8

RRING9

RRING10

RRING11

RRING12

RRING13

RRING14

RRING15

RRING16

A2

C2

H2

N2

R1

R3

R8

Receive Bipolar Ring for Channels 1–16. Receive analog input for

differential receiver. Data and clock are recovered and output at

RPOS/RNEG and RCLK pins, respectively. The differential inputs of

RTIPn and RRINGn can provide internal impedance matching with

external resistance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

R13

T15

P15

J15

D15

B16

B14

B9

Analog

input

B4

DIGITAL Tx/Rx

TPOS1/TDATA1

TPOS2/TDATA2

TPOS3/TDATA3

TPOS4/TDATA4

TPOS5/TDATA5

TPOS6/TDATA6

TPOS7/TDATA7

TPOS8/TDATA8

TPOS9/TDATA9

TPOS10/TDATA10

TPOS11/TDATA11

TPOS12/TDATA12

TPOS13/TDATA13

TPOS14/TDATA14

TPOS15/TDATA15

TPOS16/TDATA16

TNEG1

F6

G7

J6

K6

L9

Transmit Positive Data Input for Channels 1–6. When DS26334 is

configured in dual-rail mode, the data input to TPOSn is output as a

positive pulse on the line (tip and ring).

N5

P12

M11

L11

J11

G11

C14

F9

E7

N12

D5

I

Transmit Data Input for Channels 1–16. When the device is

configured in single-rail mode NRZ data is input to TDATAn. The data

is sampled on the falling edge of TCLKn and encoded HDB3/B8ZS or

AMI before being output to the line.

C3

TNEG2

TNEG3

TNEG4

TNEG5

J14

J5

G10

M6

P6

Transmit Negative Data for Channels 1–16. When DS26334 is

configured in dual-rail mode. The data input to TNEGn is output as a

negative mark on the line. TPOS and TNEG in dual-rail mode result in

positive and negative pulses sent on the line:

TNEG6

TPOSn

TNEGn

OUTPUT PULSE

Space

Negative mark

Positive mark

Space

TNEG7

TNEG8

TNEG9

TNEG10

TNEG11

TNEG12

TNEG13

TNEG14

P7

K9

0

1

0

1

0

1

I

L12

J12

H11

E13

G8

F7

TNEG15

C6

TNEG16

C5

11 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

TCLK1

TCLK2

TCLK3

TCLK4

TCLK5

F5

G4

G9

H6

M7

L8

Transmit Clock for Channels 1–16. The transmit clock has to be

1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock used

to sample the data TPOS/TNEG or TDAT on the falling edge. The

expected TCLK can be inverted.

TCLK6

TCLK7

TCLK8

TCLK9

TCLK10

TCLK11

TCLK12

TCLK13

TCLK14

L10

P9

If TCLKn is ‘high’ for 16 or more MCLKs, then transmit all ones

(TAOs) is sent to the line side of the corresponding transmit channel.

When TCLKn starts clocking again, normal operation will begin again

for the corresponding transmit channel.

I

K11

K12

F14

E12

C11

D12

N7

If TCLKn is ‘low’ for 64 or more MCLKs, then the corresponding

transmit channel on the line side will power-down and be put into high

impedance. When TCLKn starts clocking again the corresponding

transmit channel will power-up and come out of high impedance.

TCLK15

TCLK16

D11

F4

RPOS1/RDATA1

RPOS2/RDATA2

RPOS3/RDATA3

RPOS4/RDATA4

RPOS5/RDATA5

RPOS6/RDATA6

RPOS7/RDATA7

RPOS8/RDATA8

RPOS9/RDATA9

RPOS10/RDATA10

RPOS11/RDATA11

RPOS12/RDATA12

RPOS13/RDATA13

RPOS14/RDATA14

RPOS15/RDATA15

RPOS16/RDATA16

RNEG1/CV1

RNEG2/CV2

RNEG3/CV3

RNEG4/CV4

RNEG5/CV5

RNEG6/CV6

RNEG7/CV7

RNEG8/CV8

RNEG9/CV9

RNEG10/CV10

RNEG11/CV11

RNEG12/CV12

RNEG13/CV13

RNEG14/CV14

RNEG15/CV15

RNEG16/CV16

F3

L3

L4

K8

M9

P8

M12

M14

K13

G12

E14

C12

C10

C8

E5

E3

G5

K4

Receive Positive Data Output for Channels 1–16. In dual-rail mode

the NRZ data output indicates a positive pulse on RTIP/RRING. Upon

detecting an LOS, AIS can be inserted if the AISEL bit in the GC

(0Fh) register is set; otherwise, the pins will be active. AIS insertion

can also be controlled on an individual LIU basis by the IAISEL (05h)

register. If a given receiver is in power-down mode, the associated

RPOS pin is high impedance.

O,

tri-state

Receive Data Output for Channels 1–16. In single-rail mode, NRZ

data is sent out on this pin. If a given receiver is in power-down mode,

the associated RPOS pin is high impedance.

Note: During an LOS condition, the RPOS/RDATA outputs remain

active.

Receive Negative Data Output for Channels 1–16. In dual-rail

mode the NRZ data output indicates a negative pulse on

RTIP/RRING. Upon detecting a LOS, AIS can be inserted if AISEL bit

in the GC register is set; otherwise, the pins will be active. AIS

insertion can also be controlled on an individual LIU basis by IAISEL

register. If a given receiver is in power-down mode, the associated

RNEG pin is high impedance.

M3

L7

M10

P11

K10

M13

L14

F13

F11

E10

C9

O,

tri-state

Code Violation for Channels 1–16. In single-rail mode, bipolar

violation, code violation, and excessive zeros are reported on CVn. If

HDB3 or B8ZS is not selected, this pin indicates only BPVs. If a given

receiver is in power-down mode, the associated CV pin is high

impedance.

C7

J3

12 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

RCLK1

RCLK2

RCLK3

RCLK4

RCLK5

RCLK6

RCLK7

RCLK8

RCLK9

RCLK10

RCLK11

RCLK12

RCLK13

RCLK14

RCLK15

RCLK16

D3

G6

K3

K5

P5

M8

P10

P13

L13

K14

G13

F12

E8

Receive Clock for Channels 1–16. The receive data (RPOS/RNEG)

is clocked out on the rising edge of RCLK. If a given receiver is in

power-down mode the RCLK is high impedance. Upon an LOS being

detected, the RCLK is switched from the recovered clock to MCLK.

RCLK can be inverted by the RCLKI register.

O,

tri-state

E9

F8

E6

Master Clock. This is an independent free-running clock that can be

a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm

for T1 mode. The clock selection is available by MC bits MPS0,

MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be internal

adapted to 1.544MHz and a multiple of 1.544MHz can be internal

adapted to 2.048MHz.

MCLK

H12

I

LOS1

LOS2

LOS3

LOS4

LOS5

LOS6

LOS7

LOS8

LOS9

D2

G2

J2

M2

R2

T2

Loss-of-Signal Output. This output goes high when there is no

transition on the received signal over a specified interval. The output

will go low when there is sufficient ones density in the received signal.

The LOS criteria for assertion and desertion criteria are described in

Section 5.5.6. The LOS outputs can be configured to comply with

T1.231, ITU-T G.775, or ETS 300 233.

R4

R7

O

T1/E1 Clock (TECLK) (Ball E11 only). This output becomes a T1 or

E1 programmable clock output when enabled by register MC. For T1

or E1 frequency selection, see the CCR register.

R14

N15

K15

H15

B10

B8

LOS10

LOS11

LOS12

LOS13

LOS14

LOS15/TECLK

LOS16/CLKA

Clock A (CLKA) (Ball F10 only). This output becomes a

programmable clock output when enabled by register MC. For

frequency options, see the CCR register.

E11

F10

HOST SELECTION

Mode Selection. This pin is used to select the control mode of the

DS26334:

Low → Serial Host Mode

MODESEL

A3

I

High → Parallel Host Mode

Motorola Intel Select. When this pin is low, Motorola mode is

selected. When this pin is high Intel mode is selected.

Chip Select Bar. This signal must be low during all accesses to the

registers.

MOTEL

CSB

B3

I

P14

13 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

Shift Clock. In the serial host mode, this pin is the serial clock. Data

on SDI is clocked on the rising edge of SCLK. The data is clocked on

SDO on the rising edge of SCLK if CLKE is high. If CLKE is low the

data on SDO is clocked on the falling edge of SCLK.

Address Latch Enable. In parallel Intel multiplexed mode, the

address lines are latched on the falling edge of ALE.

SCLK/ALE/ASB

N14

I

Address Strobe Bar. In parallel Motorola multiplexed mode, the

address is sampled on the falling edge of ASB.

Note: Tie ALE/ASB pin high if using nonmuxed mode.

Read Bar. In Intel host mode, this pin must be low for read operation.

RDB/RWB

H14

G14

I

Read Write Bar. In Motorola mode, this pin is low for write operation

and high for read operation.

Serial Data Input. In the serial host mode, this pin is the serial input

SDI; it is sampled on the rising edge of SCLK.

Write Bar. In Intel host mode, this pin is active low during write

operation. The data or address (multiplexed mode) is sampled on the

rising edge of WRB.

SDI/WRB/DSB

Data Strobe Bar. In the parallel Motorola mode, this pin is active low.

During a write operation the data or address is sampled on the rising

edge of DSB. During a read operation the data or address is driven

on the rising edge of DSB. In the nonmultiplexed Motorola mode the

address bus (A[5:0]) is latched on the falling edge of DSB.

Serial Data Out. In serial host mode, the SDO data is output on this

pin. If a serial write is in progress this pin is high impedance. During a

read SDO is high impedance when the SDI is in command/address

mode. If CLKE is low SDO is output on the rising edge of SCLK, if

CLKE is high on the falling edge.

SD0/RDYB/ACKB

C13

O

Ready Bar Output. A high on this pin reports to the host that the

cycle is not complete and wait states must be inserted. A low means

the cycle is complete.

Acknowledge Bar. In Motorola parallel mode, a low on this pin

indicates that the read data is available for the Host or that the written

data cycle is complete.

Interrupt Bar (Active Low). This signal is tri-state when RSTB pin is

low. This interrupt signal is driven low when an event is detected on

any of the enabled interrupt sources in any of the register banks.

When there are no active and enabled interrupt sources, the pin can

be programmed to either drive high or as open drain. The reset

default is open drain when there are no active enabled interrupt

sources. All interrupt sources are disabled when RSTB = 0 and they

must be programmed to be enabled.

O,

open

drain

INTB

D7

14 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

D7/AD7

D6/AD6

D5/AD5

D4/AD4

D3/AD3

D2/AD2

D1/AD1

D0/AD0

N3

P3

M4

L5

K7

P4

M5

L6

Data Bus 7–0. In nonmultiplexed host mode, these pins are the

bidirectional data bus.

I/O,

tri-state

Address/Data Bus 7–0. In multiplexed host mode, these pins are the

bidirectional address/data bus. Note: AD7 and AD6 do not carry

address information.

In serial host mode, these pins should be grounded.

Address 5. In the host nonmultiplexed mode, this is the most

significant bit of the address bus.

A5/BSWP

E4

I

Bit Swap. In serial host mode, this bit defines the serial data position

to be MSB first when low and LSB first when high.

In multiplexed host mode, this pin should be grounded.

A4

A3

A2

A1

A0

C4

H5

G3

H3

Address Bus 4–0. These five pins are address pins in the parallel

host mode.

In serial host mode and multiplexed host mode, these pins should be

grounded.

N10

Output Enable. If this pin is pulled low all the transmitters outputs

(TTIP and TRING) are high impedance. If pulled high all the

transmitters are enabled when the associated output enable OE bit is

set. If TST.RHPMC is set, the OE pin is granted control of the

receiver internal termination. When OE is low, receiver internal

termination will be high impedance. When OE is high, receiver

termination will be enabled. The receiver can still monitor incoming

signals even when termination is in high impedance.

OE

R12

T14

I

Clock Edge. If CLKE is high, SDO is clocked out on falling edge of

SCLK and if low SDO is on rising edge of SCLK.

Multiplexed/Nonmultiplexed Select Pin. When in parallel port

mode, this pin is used to select multiplexed address and data

operation or separate address and data. When mux is a high

multiplexed address and data is used and when mux is low

nonmultiplexed is used.

CLKE/MUX

JTAG

JTAG Test Port Reset. This pin if low will reset the JTAG port. If not

used it can be left unconnected.

JTAG Test Mode Select. This pin is clocked on the rising edge of

TCK and is used to control the JTAG selection between scan and

Test Machine control.

I,

TRSTB

TMS

E15

B13

pullup

I,

pullup

JTAG Test Clock. The data TDI and TMS are clocked on rising edge

of TCK and TDO is clocked out on the falling edge of TCK.

JTAG Test Data Out. This is the serial output of the JTAG port. The

data is clocked out on the falling edge of TCK.

TCK

TDO

D14

A15

I

O,

high-Z

Test Data Input. This pin input is the serial data of the JTAG Test.

The data on TDI is clocked on the rising edge of TCK. This pin can be

left unconnected.

I,

TDI

B15

pullup

15 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

NAME

TYPE

FUNCTION

RESET

Reset Bar. This is the asynchronous reset input bar. It is internally

pulled high. A 1µs low on this pin will reset the DS26334 registers to

default value.

I,

RSTB

B5

pullup

POWER SUPPLIES

H8,

J9

H9,

J8

3.3V Digital Power Supply

DVDD

DVSS

I

Digital Ground

VDDT1

VDDT2

VDDT3

VDDT4

VDDT5

VDDT6

VDDT7

VDDT8

VDDT9

VDDT10

VDDT11

VDDT12

VDDT13

VDDT14

VDDT15

VDDT16

GNDT1

GNDT2

GNDT3

GNDT4

GNDT5

GNDT6

GNDT7

GNDT8

GNDT9

GNDT10

GNDT11

GNDT12

GNDT13

GNDT14

GNDT15

GNDT16

D1

G1

J1

M1

T4

T7

T9

T12

N16

K16

H16

E16

A13

A10

A8

A5

D4

H4

J4

N4

N6

N8

N9

N11

N13

J13

H13

D13

D10

D9

3.3V Power Supply for the Transmitter. All VDDT pins must be

connected to VDDT, which has to be 3.3V.

I,

high-Z

Analog Ground for Transmitters

I

D8

D6

B1,

C16,

P1,

R16,

H7,

J10

B2,

C15,

P2,

R15,

H10,

J7

3.3V Analog Core Power Supply. Decouple each pin separately.

AVDD

AVSS

I

Analog Core Ground

16 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5 FUNCTIONAL DESCRIPTION

5.1 Port Operation

5.1.1 Serial Port Operation

Setting MODESEL = ‘low’ enables the serial bus interface on the DS26334. Port read/write timing is unrelated to

the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 9.3 for the

AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when

BSWP is low. Figure 5-1 to Figure 5-3 show operation with LSB first.

This port is compatible with the SPI interface defined for Motorola Processors. An example of this is the MMC2107

from Motorola.

Reading or writing to the internal registers requires writing one address/command byte prior to transferring register

data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write

(0). The next 6 bits identify the register address (A1 to A6) (A7 is ignored).

All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising

edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling

or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO

is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.

Figure 5-1. Serial Port Operation for Write Access

SCLK

CSB

SDI

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DO

D6

A1

A2

A3

A4

A5

A

x

D1

D2

D3

D4

D5

D7

(msb)

0

(lsb)

(adrs

msb)

(lsb)

WRITE ACCESS ENABLED

SDO

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CSB

SDI

A1

A2

A3

A4

A5

X

A6

0

(msb)

(lsb)

SDO

D0

(lsb)

D1

D2

D3

D4

D5

D6

D7

(msb)

Read

Access

Enabled

17 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CSB

SDI

X

A1

A2

A3

A4

A5

0

A6

(lsb)

(msb)

SDO

D0

D1

D3

D4

D5

D7

D2

D6

(lsb)

(msb)

5.1.2 Parallel Port Operation

When using the parallel interface on the DS26334 the user has the option for either multiplexed bus operation or

nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26334 can

operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects

the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the

pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.

Table 5-1. Parallel Port Mode Selection and Pin Functions

MODESEL, MOTEL,

PARALLEL HOST

INTERFACE

ADDRESS, DATA, AND CONTROL

MUX

100

110

101

111

Nonmultiplexed Motorola CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB

Nonmultiplexed Intel

Multiplexed Motorola

Multiplexed Intel

CSB, RDYB, WRB, RDB, ALE, A [5:0], D[7:0], INTB

CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB

CSB, RDYB, WRB, RDB, ALE, AD[7:0], INTB

5.1.3 Interrupt Handling

There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:

•

When status changes on an interruptible event, INTB pin will go low if the event is enabled through the

corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10kΩ resister for

wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when

not active by setting register GISC.INTM.

•

When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source

of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The

Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear

on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ‘1’ to

it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a

register without clearing them on all bits.

•

Subsequently the host processor can read the corresponding Status Register to check the real-time status of

the event.

18 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-4. Interrupt Handling Flow Diagram

Interrupt Allowed

No

Interrupt Conditon

Exist?

Yes

Read Interrupt Status

Register

Read Corresponding Status

Register (Optional)

Service the Interrupt

5.2 Power-Up and Reset

Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values.

Writing to the Software Reset Register (SWR) generates at least 1µs reset cycle, which has the same effect as the

power-up reset.

The DS26334 can be reset by a low going pulse on the RSTB pin (see Table 4-1). A reset can also be performed in

software by writing any value to the SWR register.

5.3 Master Clock

The DS26334 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK

as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS transmission uses

MCLK for transmit all ones condition. See register MC to set desired incoming frequency. When the PLLE bit is set,

the master clock adapter will generate both 2.048MHz (E1) and 1.544MHz (T1) clocks. If the PLLE bit is clear, both

internal reference clocks will track MCLK.

MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register CCR is used to select the clock

generated for CLKA and the TECLK. Any RCLK can also be selected as an input to the clock generator using this

same register. For a detailed description of selections available see Figure 5-5.

19 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-5. Prescaler PLL and Clock Generator

PCLKS2..0

RLCK1..8

CLKA3..0

PLLE

RLOS16

T1CLK

PCLKI1..0

CLKAE

MPS1..0

FREQS

LOS16

CLK

CLKA

GEN

Pre

MCLK

Scaler

PLL

E1CLK

TECLK

LOS15

PLLE

TECLKS

TECLKE

RLCK9..16

RLOS15

PCLKS2..0

5.4 Transmitter

NRZ data arrives on TPOS and TNEG on the transmit system side. The TPOS and TNEG data is sampled on the

falling edge of TCLK.

The data is encoded with HDB3 or B8ZS or AMI encoding when single-rail mode is selected (only TPOS as the

data source). When in single-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Pre-

encoded data is expected when dual-rail mode is selected. The encoded data passes through a jitter attenuator if it

is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms compliant

with T1.102 and G.703 pulse masks.

The line driver supports internal impedance matching for 75Ω, 100Ω, 110Ω, and 120Ω modes.

The DS26334 drivers have short and open circuit driver fail monitor detection. There is an OE pin that can high

impedance the transmitter outputs for protection switching when low. The individual transmitters are by default in

high impedance. The OE register is used to enable the transmitters individually when the OE pin is high. The

DS26334 has to have the transmitter’s enabled by setting the register and then pulling the OE pin high. The

registers that control the transmitter operation are shown in Table 5-2.

20 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters

TRANSMITTER FUNCTION

TELECOMMUNICATIONS COMPLIANCE

AMI Coding, B8ZS Substitution, DS1 Electrical Interface

T1 Telecom Pulse Mask compliance

ANSI T1.102

ANSI T1.403

ANSI T1.102

Transmit Electrical Characteristics for E1 Transmission

and Return Loss Compliance

ITU-T G.703

Table 5-3. Registers Related to Control of DS26334 Transmitters

REGISTER

Transmit All Ones Enable

NAME

TAOE

FUNCTION

Transmit all ones enable.

Driver Fault Monitor Status

DFMS

DFMIE

DFMIS

ATAOS

Driver fault status.

Driver Fault Monitor Interrupt Enable

Driver Fault Monitor Interrupt Status

Automatic Transmit All Ones Select

Driver fault status interrupt mask.

Transmit all ones enabled automatically on LOS.

Global control of jitter attenuator, line coding and short

circuit protection.

Global Configuration

GC

The transmitter that the Template Select Transmitter

Register applies to.

Template Select Transmitter

TST

The TS2 to TS0 bits for selection of the templates for

transmitter and TIMPOFF and TIMPRIM bits to control

transmit impedance match.

Template Select

TS

These register bits can be used to enable the transmitter

outputs.

Selects the MCLK frequency used for transmit and

receive.

This register can be used to select between single-rail

and dual-rail mode.

Output Enable Configuration

Master Clock Selection

Single-Rail Mode Select

OE

MC

SRMS

The individual transceiver line codes can be selected to

overwrite the global setting.

Line Code Selection

LCS

Transmit Power-Down Enable

Individual Jitter Attenuator Enable

Individual Jitter Attenuator Position

Select

Individual Jitter Attenuator FIFO

Depth Select

TPDE

IJAE

Individual transmitters can be powered down.

Enables the jitter attenuator.

Selects whether jitter attenuator is in transmit or receive

path

IJAPS

IJAFDS

IJAFLT

Selects depth of jitter attenuator FIFO.

Individual Jitter Attenuator FIFO

Limit Trip

Indicates jitter attenuator FIFO within 4 bits of its useful

limit.

Individual Short-Circuit Protection

Disable

Short-Haul/Long-Haul Select

This register allows the individual transmitters to have

short-circuit protection disable.

This selects between short-haul and long-haul templates.

This register allows mapping of the internal BERTs into

an individual transmit path.

Inverts TCLK input.

Inserts a bipolar error in the transmit path when in single-

rail mode.

ISCPD

SHLHS

BTCR

TCLKI

BEIR

Bit Error Rate Tester Control

Transmit Clock Invert

BPV Error Insertion

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.4.1 Transmit Line Templates

The DS26334 transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1

pulse mask is shown in the Transmit Pulse Template and can be configured on an individual LIU basis. The

transmit template is selected via the TS[2:0] bits in the TS register. Transmit impedance matching is selected using

the TIMPOFF and the TIMPRM bits of the same register. When transmit impedance matching is enabled TIMPRM

will select between 75Ω and 120Ω impedance if an E1 template is selected, and between 100Ω and 110Ω

impedance if a T1/J1 template is selected. In E1 mode, if 75Ω is selected via the TIMPRM bit, the output pulse

amplitude will be 2.37V, if 120Ω is selected via the TIMPRIM bit, the output pulse amplitude will be 3.0V.

The E1 pulse template is shown in Figure 5-7 and the T1 pulse template is shown in Figure 5-6.

Table 5-4. Template Selections for Short-Haul Mode

TS2, TS1, TS0

APPLICATION

000

001

010

011

100

101

110

111

E1

Reserved

DSX-1 (0–133ft)

DSX-1 (133–266ft)

DSX-1 (266–399ft)

DSX-1 (399–533ft)

DSX-1 (533–655ft)

Table 5-5. Template Selections for Long-Haul Mode

TS2, TS1, TS0

APPLICATION

000

001

010

011

100

101

110

E1

Reserved

0dB CSU

-7.5dB CSU

-15dB CSU

-22dB CSU

22 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-6. T1 Transmit Pulse Templates

1 .2

1 .1

1 .0

0 .9

0 .8

0 .7

0 .6

0 .5

0 .4

0 .3

0 .2

0 .1

0

-0 .1

-0 .2

-0 .3

-0 .4

-0 .5

T 1 .1 0 2 /8 7 , T 1 .4 0 3 ,

C B 1 1 9 (O c t. 7 9 ), &

I.4 3 1 T e m p la te

-5 0 0 -4 0 0

-3 0 0

-2 0 0

-1 0 0

0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

7 0 0

T IM E (n s )

D S 1 T e m p la te (p e r A N S I T 1 .4 0 3 -1 9 9 5 )

D S X -1 T e m p la te (p e r A N S I T 1 .1 0 2 -1 9 9 3 )

M A X IM U M C U R V E

M IN IM U M C U R V E

M A X IM U M C U R V E

M IN IM U M C U R V E

U I

T im e

A m p .

U I

T im e

A m p .

U I

T im e

A m p .

U I

T im e

A m p .

-0 .7 7

-0 .3 9

-0 .2 7

-0 .1 2

0 .0 0

0 .2 7

0 .3 5

0 .9 3

1 .1 6

-5 0 0

-2 5 5

-1 7 5

-7 5

0 .0 5

0 .8 0

1 .1 5

1 .0 5

-0 .0 7

0 .0 5

-0 .7 7

-0 .2 3

-0 .1 5

0 .0 0

0 .1 5

0 .2 3

0 .4 6

0 .6 6

0 .9 3

1 .1 6

-5 0 0

-1 5 0

-1 0 0

0

1 0 0

1 5 0

3 0 0

4 3 0

6 0 0

7 5 0

-0 .0 5

0 .5 0

0 .9 5

0 .9 0

0 .5 0

-0 .4 5

-0 .2 0

-0 .0 5

-0 .7 7 -5 0 0

-0 .3 9 -2 5 5

-0 .2 7 -1 7 5

-0 .1 2 -7 5

0 .0 5

0 .8 0

1 .2 0

1 .0 5

-0 .0 5

0 .0 5

-0 .7 7 -5 0 0

-0 .2 3 -1 5 0

-0 .1 5 -1 0 0

-0 .0 5

0 .5 0

0 .9 5

0 .9 0

0 .5 0

-0 .4 5

-0 .2 6

-0 .0 5

0 .0 0

0 .1 5

0 .2 3

0 .4 6

0 .6 1

0 .9 3

1 .1 6

0

0 .0 0

0 .2 7

0 .3 4

0 .7 7

1 .1 6

0

1 0 0

1 5 0

3 0 0

4 3 0

6 0 0

7 5 0

1 7 5

2 2 5

6 0 0

7 5 0

1 7 5

2 2 5

6 0 0

7 5 0

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-7. E1 Transmit Pulse Templates

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

269ns

G.703

Template

194ns

219ns

-0.1

-0.2

-250

-200

-150

-100

-50

0

50

100

150

200

250

TIME (ns)

24 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.4.2 LIU Transmit Front-End

It is recommended that the LIU for the transmitter be configured as described in Figure 5-8 and in Table 5-6.

Figure 5-8. LIU Front-End

3.3V

TFt

Dt

1:2

VDDTn

GNDTn

AVDDn

AVSSn

TTIP

Dt

C1

C2

Tx Line

Ct

TRING

(One Channel)

3.3V

TFr

1:1 or 1:2

Dt

optional

RTIP

Rt

C3

C4

Rx Line

C5

A75 A100 A110

RRING

termination

3.3V

TVS1

25 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 5-6. LIU Front-End Values

75Ω COAX, 120Ω TWISTED PAIR,

100/110Ω TWISTED PAIR

560pF typical. Adjust for board parasitics for optimal return loss.

MODE

Tx Capacitance

COMPONENT

Ct

Dt¹

TFr

International Rectifier 11DQ04 or 10BQ060,

Motorola MBR0540T1

Tx Protection

Rx Transformer RTR 1:1

Pulse TX1475 (recommended for both short/long-haul modes),

Halo TG83-S005NU (recommended for short-haul only)

Tx Transformer 1:2

TFt

TFr

Rx Transformer RTR 1:2

Pulse T1124 (0°C to +70°C),

Pulse T1114 (-40°C to 85°C)

Tx Transformer 1:2

TFt

C1

C2

Tx Decoupling (TVDDn)

Rx Decoupling (AVDD)

Rx Termination

Rx Termination RTR 1:1

Rx Termination RTR 1:2

Voltage Protection

Common decoupling for all 16 channels = 68µF.

Recommended decoupling per channel = 0.1µF.

Common decoupling for all 16 channels = 68µF.

Decouple all six pins separately with a 0.1µF capacitor.

Rx capacitance for all 16 channels = 0.1µF.

Need two resistors = 60.4Ω ±1%.

C3

C4

C5¹

Rt¹

Need two resistors = 15.0Ω ±1%.

SGS-Thomson SMLVT 3V3 (3.3V Transient Suppressor)

TVS1

¹Only use if necessary for application.

5.4.3 Transmit Dual-Rail Mode

Transmit dual-rail mode consists of the TPOS, TNEG, and TCLK pins on the system side. NRZ data is sampled on

the falling edge of TCLK as shown in Figure 9-12.

B8ZS or HDB3 encoding is not available in transmit dual-rail mode. The data that appears on the TPOS and TNEG

pins is output on TTIP and TRING without any modification. The Single-Rail Mode Select Register (SRMS) is used

for selection of dual-rail or single-rail mode. The data that arrives at the TPOS and TNEG can be overwritten in the

maintenance mode by setting the BERT Control Register (BTCR).

5.4.4 Transmit Single-Rail Mode

Transmit single-rail mode consists of the TPOS and TCLK pins on the system side (TNEG is not used.). NRZ data

is sampled on the falling edge of TCLK as shown in Figure 9-12. The zero substitution B8ZS or HDB3 encoding is

allowed. The TPOS data is encoded in AMI or B8ZS/HDB3 format on the TTIP and TRING pins after pulse

shaping. The Single-Rail Mode Select Register (SRMS) is used for selection of dual-rail or single-rail mode. The

data that arrives at the TPOS can be overwritten in the maintenance mode by setting in Bit Error Rate Tester

Control Register (BTCR).

5.4.5 Zero Suppression—B8ZS or HDB3

B8ZS coding is available when the device is in T1 mode (selected by TS2, TS1 and TS0 bits in the TS register).

B8ZS/HDB3 coding are enabled by default in single-rail mode. Setting the LCS bit in the LCS Register disables

B8ZS/HDB3. Note that if the individual LIU is configured in E1 mode then HDB3 code substitution will be selected.

B8ZS substitution is defined in ANSI T1.102 and HDB3 in ITU-T G.703 standards.

5.4.6 Transmit Power-Down

The transmitter will be powered down if the relevant bits in the TPDE are set. The TTIP/TRING outputs will be high

impedance when TPDE is set.

26 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.4.7 Transmit All Ones

When Transmit All Ones is invoked, continuous ones are transmitted using MCLK as the timing reference. Data

input at TPOS and TNEG is ignored.

Transmit All Ones can be sent by setting bits in the TAOE Register. Also, Transmit All Ones will be enabled if bits

in ATAOS are set and the corresponding receiver goes into LOS state in status register LOSS.

5.4.8 Driver Fail Monitor

The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a short or open circuit on the

secondary side of the transmit transformer. The drive current will be limited to 50mA if a short circuit is detected.

The DFMS status registers and the corresponding interrupt and enable registers can be used to monitor the driver

failure.

5.5 Receiver

The DS26334’s 16 receivers are all identical. A 1:2 or 1:1 transformer can be used on the receive side (selected by

the RTR bit), but only a 1:1 transformer can be used if fully internal impedance match is enabled. Fully internal

receive impedance match does not require the use of any external resistor on the receive line. If partially internal

impedance matching is selected, the DS26334 will need only an external 120Ω resistor (30Ω for a 1:2 transformer)

for E1, T1, and J1. The receive impedance match settings are controlled by the transmit template/impedance

selection. See Figure 5-8 and Table 5-6 for external component values. Partially internal impedance matching is

enabled via the TS.RIMPON bit. Fully internal impedance matching is enabled by setting GC.RIMPMS and

TS.RIMPON.

The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data

recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery

system derives E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form a 16 times

oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding

performance to meet jitter tolerance specifications.

B8ZS/HDB3/AMI decoding is available when single-rail mode is selected. The selection of single-rail or dual rail is

done by settings in the SRMS register.

The receiver is capable of recovering signals up to 36dB worth of attenuation for T1 mode, and up to 43dB for E1

mode. The receiver contains functionality to provide resistive gain up to 32dB for monitor mode.

Three receive termination modes are available:

1) External Impedance Matching. Internal impedance matching is disabled, external resistor should match

line impedance.

2) Partially Internal Impedance Matching. Internal impedance matching is enabled, in parallel with an

external termination resistor (one value for all terminations).

3) Fully Internal Impedance Matching. Internal impedance matching is enabled, no external termination

necessary. This mode requires a 1:1 receive-side transformer.

5.5.1 Receiver Impedance Matching Calibration

In fully internal impedance matching mode, calibration of the internal resistors is necessary to match the line

impedance accurately. Calibration must be done upon power-up of the device. The resistance of the internal

resistors does vary across temperature. Therefore, it may be necessary to recalibrate if the ambient temperature

changes more than 30°C. The user may conclude that it is necessary to recalibrate on a periodic basis if he

expects such temperature swings. Calibration is not necessary for partially internal impedance match mode.

5.5.2 Receiver Monitor Mode

The receive equalizer is equipped with monitor mode function that allows for resistive gain up to 32dB, along with

cable attenuation of 6dB to 24dB as shown in the RSMM1–4 registers.

27 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.5.3 Peak Detector and Slicer

The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock

and data recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination

of the slicing threshold.

5.5.4 Receive Level Indicator

The DS26334 will report the signal strength at RTIP and RRING in increments described in Table 6-17 via register

bits CnRL3–CnRL0 located in the RSL1–4 registers.

5.5.5 Clock and Data Recovery

The resultant E1 or T1 clock derived from the 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL

and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16

times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding

performance to meet jitter tolerance specifications.

5.5.6 Loss of Signal

The DS26334 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for

T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode of operation.

LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this

can be termed as having received “zeros” for certain duration. The signal level and timing duration are defined in

accordance with the ANSI T1.231, ITU-T G.775, or ETS 300 233 specifications.

For short-haul mode, the loss detection thresholds are based on cable loss of 18dB for both T1 and E1 modes. For

long-haul mode, the LOS detection threshold is based on cable loss of 38dB for T1 mode and 45dB for E1 mode.

RCLK is replaced by MCLK when the receiver detects a loss of signal. If the AISEL bit is set in the GC register or

the IAISEL bit is set, the RPOS/RNEG data is replaced by AIS. The loss state is exited when the receiver detects a

certain number of ones density at a higher signal level than the loss detection level. The loss detection signal level

and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between “LOS” and

“no LOS” states.

Table 5-7 outlines the specifications governing the loss function.

Table 5-7. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications

STANDARD

CRITERIA

T1.231

ITU-T G.775

No pulses are detected for

duration of 10 to 255 bit

periods.

ETS 300 233

No pulses are detected for a

duration of 2048 bit periods or

1ms.

Loss

No pulses are detected for 175

±75 bits.

Detection

Criteria

Loss is terminated if a duration

of 12.5% ones are detected over

duration of 175 ±75 bits.

The incoming signal has

transitions for duration of 10 to

255 bit periods.

Loss is not terminated if 8

consecutive zeros are found if

B8ZS encoding is used. If B8ZS

is not used loss is not

Loss Reset

Criteria

Loss reset criteria is not

defined.

terminated if 100 consecutive

pulses are zero.

28 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.5.6.1 ANSI T1.231 for T1 and J1 Modes

For short-haul mode, loss is detected if the received signal level is less than 200mV for duration of 192 bit periods.

LOS is reset if the all of the following criteria are met:

•

24 or more ones are detected in 192-bit period with a detection threshold of 300mV measured

at RTIP and RRING.

•

During the 192 bits less than 100 consecutive zeros are detected.

8 consecutive zeros are not detected if B8ZS is set.

For long-haul mode, loss is detected if the received signal level is less than 30mV for duration of 192 bit periods.

LOS is reset if the all of the following criteria are met:

•

24 or more ones are detected in 192-bit period with a detection threshold of 40mV measured

at RTIP and RRING.

•

During the 192 bits less than 100 consecutive zeros are detected.

8 consecutive zeros are not detected if B8ZS is set.

5.5.6.2 ITU-T G.775 for E1 Modes

For short-haul mode, LOS is detected if the received signal level is less than 200mV for a continuous duration of

192 bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.

For long-haul mode, LOS is detected if the received signal level is less than 12mV for a continuous duration of 192

bit periods. LOS is reset if the receive signal level is greater than 20mV for a duration of 192 bit periods.

5.5.6.3 ETS 300 233 for E1 Modes

For short-haul mode, LOS is detected if the received signal level is less than 200mV for a continuous duration of

2048 (1ms) bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit

periods.

For long-haul mode, LOS is detected if the received signal level is less than 12mV for a continuous duration of 192

bit periods. LOS is reset if the receive signal level is greater than 20mV for a duration of 192 bit periods.

5.5.7 AIS

Table 5-8 outlines the DS26334 AIS related specifications. Table 5-9 states the AIS functionality in the DS26334.

The registers related to the AIS detection are shown in Table 5-10.

Table 5-8. AIS Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications

STANDARD

CRITERIA

ITU-T G.775 for E1

ETS 300 233 for E1

ANSI T1.231 for T1

Fewer than 9 zeros detected in

Fewer than 3 zeros detected in a 8192-bit period (a ones

AIS

Detection

Criteria

2 or fewer zeros in each of 2

consecutive 512-bit stream

received.

512 bit period.

density of 99.9% over a period

of 5.3ms) are received.

AIS

Clearance

Criteria

3 or more zeros in each of 2

consecutive 512-bit streams

received.

3 or more zeros in 512 bits

received.

9 or more zeros detected in a

8192-bit period are received.

Table 5-9. AIS Detection and Reset Criteria for DS26334

STANDARD

CRITERIA

ITU-T G.775 for E1

2 or fewer zeros in each of 2

consecutive 512-bit streams

received.

ETS 300 233 for E1

ANSI T1.231 for T1

AIS

Fewer than 3 zeros detected in Fewer than 9 zeros contained

512-bit period.

Detection

Criteria

AIS

in 8192 bits.

3 or more zeros in each of 2

consecutive 512-bit streams

received.

3 or more zeros in 512 bits

received.

9 or more bits received in a

8192-bit stream.

Clearance

Criteria

29 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 5-10. Registers Related to AIS Detection

REGISTER

NAME

FUNCTIONALITY

LOS/AIS Criteria Selection

Alarm Indication Signal Status

AIS Interrupt Enable

LASCS

AIS

AISIE

AISI

Section criteria for AIS (T1.231, G.775, ETS 300 233 for E1).

Set when AIS is detected.

If reset, interrupt due to AIS is not generated.

Latched if there is a change in AIS and the interrupt is enabled.

AIS Interrupt Status

5.5.8 Receive Dual-Rail Mode

Receive dual-rail mode consists of the RPOS, RNEG, and RCLK pins on the system side. In receive dual-rail

mode, B8ZS and HDB3 decoding is not available. The data that appears on the RTIP and RRING pins is output on

RPOS and RNEG without any modification. The Single-Rail Mode Select Register (SRMS) is used for selection of

dual-rail or single-rail mode. The bipolar violation (and B8ZS/HDB3) detectors detect violations in dual-rail and

single-rail modes, but in dual-rail mode the violations will only be reported to the Line Violation Detect Status

(LVDS) registers.

5.5.9 Receive Single-Rail Mode

Receive single-rail mode consists of the RPOS, RCLK, and CV pins on the system side. B8ZS or HDB3 decoding

is available. The Single-Rail Mode Select Register (SRMS) is used for selection of dual-rail or single-rail mode.

5.5.10 Bipolar Violation and Excessive Zero Detector

The DS26334 detects HDB3 code violations, BPVs, and excessive zero errors. The reporting of the errors is done

through the RNEGn/CVn pin in single-rail mode and the LVDS registers in both single- and dual-rail modes. Code

violations are only detected in E1 mode with HDB3 encoding. The code violation detection declares an error when

a bipolar violation of the same polarity as the last bipolar violation is received.

Excessive zeros are detected if eight consecutive zeros are detected with B8ZS enabled and four consecutive

zeros are detected with HDB3 enabled. Excessive zero detection is enabled via the Excessive Zero Detect Enable

Register (EZDE) and when HDB3/B8ZS encoding/decoding is selected via the Line Code Selection Register (LCS).

The bits in the LCS, EZDE, and CVDEB registers determine the combinations that are reported. Table 5-11

outlines the functionality.

Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting

CONDITIONS

ERRORS DETECTED

LCS

EZDE

CVDEB

0

1

0

1

X

0

1

0

1

X

BPV (T1)/Code Violation (E1)

BPV

Excessive Zeros and BPV (T1)/Code Violation (E1)

Excessive Zeros and BPV

BPV

30 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.6 Jitter Attenuator

The DS26334 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS

bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register.

The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used

in delay sensitive applications. The characteristics of the attenuation are shown in Figure 5-9. The jitter attenuator

can be placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE

bits in register GC. These selections can be changed on an individual LIU basis by settings in the IJAPS and IJAE.

In order for the jitter attenuator to operate properly, a 2.048MHz clock or multiple thereof, or 1.544MHz clock or

multiple thereof, must be applied at MCLK. ITU-T specification G.703 requires an accuracy of ±50ppm for both T1

and E1 applications. AT&T Pub 62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board

circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin

to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to

provide a jittery clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter

exceeds either 120UI_P-P(buffer depth is 128 bits) or 28UI_P-P(buffer depth is 32 bits), the DS26334 will divide the

internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the

buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip

(IJAFLT) bits in the IJAFLT register described.

Figure 5-9. Jitter Attenuation

0dB

ITU G.7XX

TBR12

Prohibited

Area

Prohibited Area

-20dB

-40dB

-60dB

C

ur

v

e A

E1

T1

TR 62411 (Dec. 90)

Prohibited Area

C

ur

v

e B

1

10

100

1K

10K

100K

FREQUENCY (Hz)

31 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.7 G.772 Monitor

In this application, only 14 transceivers are functional and two transceivers are used for nonintrusive monitoring of

input and output of the other 14 channels. Channel 9 is used for 10 to 16 channels and Channel 1 is used for 2 to 8

channels. G.772 monitoring is configured by the BERT and G.772 Monitoring Control Register (BGMC) (see Table

6-9). While monitoring, Channel 1 can be configured in remote loopback and the monitored signal can be output on

TTIP1 and TRING1. While monitoring, Channel 9 can be configured in remote loopback and the monitored signal

can be output on TTIP9 and TRING9.

5.8 Loopbacks

The DS26334 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote

loopback, and dual loopback. Dual loopback is accomplished by turning on digital loopback and remote loopback at

the same time.

5.8.1 Analog Loopback

The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at

RTIP and RRING is ignored in analog loopback. This is shown in Figure 5-10.

Figure 5-10. Analog Loopback

TCLK

TPOS

TNEG

H

B

E

D

8

n

B 3 /

O

p t i o n a l

J i t t e r

t t e n u a t o r

Z

S

T r a n s m i t

A n a lo g

T r a n s m it

Line

c o d e r

A

D

ig i t a l

Driver

RCLK

RPOS

RNEG

Rtip

H

B

D

8 Z

e c o d e r

B 3 /

S

R e c e iv e

D ig i ta l

R e c e iv e

A n a lo g

O

p

t i o

J i t t e

t t e n

n

u

a

l

r

Rring

A

t o r

32 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.8.2 Digital Loopback

The transmit system data TPOS, TNEG, and TCLK will be looped back to output on RCLK, RPOS, and RNEG. The

data input at TPOS and TNEG is output on TTIP and TRING. All ones can also be output when selected by the

Transmit All Ones Enable Register (TAOE). Signals at RTIP and RRING will be ignored. This loopback is

conceptually shown in Figure 5-11.

Figure 5-11. Digital Loopback

TCLK

TPOS

TNEG

TTIP

TPOS

H

B

E

D

8

n

B 3 /

O

p t i o n a l

J i t t e r

t t e n u a t o r

Z

S

T r a n s m i t

A n a lo g

T r a n s m it

Line

c o d e r

A

D

ig i t a l

Driver

TRING

TNEG

RCLK

RPOS

RNEG

RTIP

RRING

H

B

D

8 Z

e c o d e r

B 3 /

S

O

p

t i o

J i t t e

t t e n

n

u

a

l

R e c e iv e

D ig i ta l

R e c e iv e

A n a lo g

r

A

t o r

5.8.3 Remote Loopback

The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS, and TNEG are

ignored during a remote loopback. This loopback is conceptually shown in Figure 5-12.

Note: Remote loopback does not take precedence over transmit power-down and requires TCLK to operate. The

transmitters will use the recovered RCLK in remote loopback. TCLK is still required because if it is removed the

transmitters will power-down (TCLK held low) or transmit all ones (TCLK held high).

Figure 5-12. Remote Loopback

TTIP

TPOS

TCLK

TPOS

TNEG

H

B

E

D

8

n

B 3 /

O

p t i o n a l

J i t t e r

t t e n u a t o r

Z

S

T r a n s m i t

A n a lo g

T r a n s m it

c o d e r

Line

A

D

ig i t a l

Driver

TRING

TNEG

RCLK

RPOS

RNEG

RTIP

H

B

D

8 Z

e c o d e r

B 3 /

S

O

p

t i o

J i t t e

t t e n

n

u

a

l

R e c e iv e

D ig i ta l

R e c e iv e

A n a lo g

r

A

t o r

RRING

33 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.9 BERT

There are two bit error-rate testers available on the DS26334. One BERT can be mapped into LIUs 1–8 and the

other into LIUs 9–16 via the BTCR registers. The two BERTs operate independently of each other.

Each BERT transmitter, by default, replaces data from TPOS and TNEG; each BERT receiver, by default, samples

recovered data from RTIP and RRING.

The BERT can be enabled to replace data received on RTIP and RRING via the BERTDIR bit in the BERT and

G.772 Monitoring Control Register (BGMC). In this mode, the SRMS bit determines whether data comes out single-

rail or dual-rail. BERT data can be sourced using the recovered clock, MCLK, or TCLK. In this mode of operation,

the BERT receiver samples data on TPOS and TNEG on the falling edge of TCLK. This function is useful for

testing the digital side of the LIU. If TCLK is selected as a source for this mode, the input TCLK will control the

BERT transmitter and receiver. If the recovered clock or MCLK is selected, the RCLK output needs to drive the

TCLK input in order for the BERT receiver to sync to the data.

5.9.1 General Description

The BERT is a software-programmable test pattern generator and monitor capable of meeting most error

performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom

patterns with a generation polynomial of the form xⁿ+ x^y+ 1, where n and y can take on values from 1 to 32 and

repetitive patterns of any length up to 32 bits.

The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data

stream.

The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern

payload for the programmable test pattern.

5.9.1.1 BERT Features

•

Programmable PRBS Pattern. The pseudorandom bit sequence (PRBS) polynomial (xⁿ+ x^y+ 1) and

seed are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2ⁿ– 1).

Programmable Repetitive Pattern. The repetitive pattern length and pattern are programmable (the

length n = 1 to 32 and pattern = 0 to 2ⁿ– 1).

•

24-Bit Error Count and 32-Bit Bit Count Registers

Programmable Bit-Error Insertion. Errors can be inserted individually, on a pin transition, or at a specific

rate. The rate 1/10ⁿis programmable (n = 1 to 7).

•

Pattern Synchronization at a 10^-3BER. Pattern synchronization is achieved even in the presence of a

random bit error rate (BER) of 10^-3.

34 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.9.2 Configuration and Monitoring

Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send

and receive common patterns.

Table 5-12. Pseudorandom Pattern Generation

BPCR REGISTER

PLF[4:0]

BERT.CR

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

PATTERN TYPE

PTF[4:0]

(hex)

TPIC,

RPIC

PTS QRSS

(hex)

2⁹-1 O.153 (511 type)

04

08

0

0x0408 0xFFFF 0xFFFF

0x080A 0xFFFF 0xFFFF

0

2¹¹-1 O.152 and O.153

(2047 type)

08

0A

0

2¹⁵-1 O.151

2²⁰-1 O.153

0D

10

02

11

0E

13

16

0

1

0

0x0D0E 0xFFFF 0xFFFF

0x1013 0xFFFF 0xFFFF

0x0253 0xFFFF 0xFFFF

0x1116 0xFFFF 0xFFFF

1

0

1

2²⁰-1 O.151 QRSS

2²³-1 O.151

Table 5-13. Repetitive Pattern Generation

BPCR REGISTER

PTF[4:0] PLF[4:0]

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

PATTERN TYPE

All Ones

PTS QRSS

(hex)

NA

00

1

0

0x0020

0x0021

0x0023

0x0037

0x002F

0x0027

0x0023

0xFFFF

0xFF20

0xFFFF

0xFFFE

0xFFFC

0x0022

0x0001

0xFF01

0xFFF1

All Zeros

NA

00

01

03

17

0F

07

03

Alternating Ones and Zeros

Double Alternating and Zeros

3 in 24

1 in 16

1 in 8

1 in 4

After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one

transition on BCR.TNPL and BCR.RNPL

Monitoring the BERT requires reading the BSR register, which contains the Bit Error Count (BEC) bit and the Out

of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will be

one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it

receives a minimum 6 bit errors within a 64-bit window. The Receive BERT Bit Count Register (RBCR) and the

Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor

Update signal (e.g., BCR.LPMU). This signal will update the registers with the values of the counters since the last

update and will reset the counters.

35 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.9.3 Receive Pattern Detection

The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming

pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or

bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating

polynomial xⁿ+ x^y+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is

bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is

the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if

the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will

be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection

performs either PRBS synchronization or repetitive pattern synchronization.

5.9.3.1 Receive PRBS Synchronization

PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The

receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and

then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If

at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern

re-synchronization is initiated. Automatic pattern re-synchronization can be disabled.

See Figure 5-13 for the PRBS synchronization diagram.

Figure 5-13. PRBS Synchronization State Diagram

Sync

6 of

s

64 bi

or

r

e

t

s

w

hout

t

i

t

h e

w

s

t

r

or

s

32 bi

1 bit error

Verify

Load

32 bits loaded

36 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.9.3.2 Receive Repetitive Pattern Synchronization

Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.

The receive pattern generator is synchronized by searching each incoming data stream bit position for the

repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match

the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS

pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be

disabled.

See Figure 5-14 for the repetitive pattern synchronization state diagram.

Figure 5-14. Repetitive Pattern Synchronization State Diagram

Sync

6 of

s

64 bi

or

r

e

t

s

w

hout

t

i

t

h e

w

s

t

r

or

s

32 bi

1 bit error

Verify

Match

Pattern Matches

5.9.3.3 Receive Pattern Monitoring

Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts

the incoming bits. An Out Of Synchronization (OOS) condition is declared when the synchronization state machine

is not in the “Sync” state. An OOS condition is terminated when the synchronization state machine is in the “Sync”

state.

Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they

do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit

count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.

37 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

5.9.4 Transmit Pattern Generation

Pattern generation generates the outgoing test pattern, and passes it onto error insertion. The transmit pattern

generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant

bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial xⁿ+ x^y+ 1), the

feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and

y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is

enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all

zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits

1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value

before pattern generation starts. The seed/pattern value is programmable (0 – 2ⁿ– 1).

5.9.4.1 Transmit Error Insertion

Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of

one out of every 10ⁿbits. The value of n is programmable (1 to 7 or off). Single bit error insertion can be initiated

from the microprocessor interface, or by the manual error insertion input (TMEI). The method of single error

insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the

overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).

38 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

6 REGISTER MAPS AND DEFINITION

Six address bits are used to control the settings of the registers. In the parallel nonmultiplexed mode address [5:0]

is used. In multiplexed mode AD[5:0] is used and A[6:1] is used in the serial mode. The register space contains two

independent sets of registers. The lower set of registers (LIUs 1–8) is located from address 00 hex to 1F hex and

contains controls for LIUs 1–8. The upper set of registers (LIUs 9–16) is a duplicate of the lower set, located from

address 20 hex to 3F hex that controls LIUs 9–16. Each of these sets of registers consists of four banks: Primary,

Secondary, Individual LIU, and BERT.

The ADDP register for the lower set of registers (LIUs 1–8) is located at address 1F hex. This register is used as a

pointer to access the 4 banks of registers in the lower (LIUs 1–8) register set. Similarly, the ADDP register for the

upper set of registers (LIUs 9–16) is located at address 3F hex. This register is used as a pointer to access the four

banks of registers in the upper (LIUs 9–16) register set. Setting an ADDP register to AA hex will access the

secondary bank of registers, 01 hex will access the Individual LIU bank of registers, 02 hex will access the BERT

bank of registers, and 00 hex (default on power-up) will access the Primary bank of registers. Note that bank

selection for the lower set of registers (LIUs 1–8) is controlled only by the ADDP at 1F hex and that bank selection

for the upper set of registers (LIUs 9–16) is controlled only by the ADDP at 3F hex.

39 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-5. Primary Register Set Bit Map

ADDRESS

FOR LIUs

1–8

REGISTER

R/W

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ID

ALBC

RLBC

TAOE

LOSS

DFMS

LOSIE

DFMIE

LOSIS

DFMIS

SWR

BGMC

DLBC

LASCS

ATAOS

GC

00

01

02

03

04

05

06

07

08

R

ID7

ALBC8

RLBC8

TAOE8

LOSS8

DFMS8

LOSIE8

DFMIE8

LOSIS8

DFMIS8

SWRL

BERTDIR

DLBC8

LASCS8

ATAOS8

RIMPMS

JABWS1

RIMPON

OE8

ID6

ALBC7

RLBC7

TAOE7

LOSS7

DFMS7

LOSIE7

DFMIE7

LOSIS7

DFMIS7

SWRL

BMCKS

DLBC7

LASCS7

ATAOS7

AISEL

ID5

ALBC6

RLBC6

TAOE6

LOSS6

DFMS6

LOSIE6

DFMIE6

LOSIS6

DFMIS6

SWRL

BTCKS

DLBC6

LASCS6

ATAOS6

SCPD

RHPMC

—

ID4

ALBC5

RLBC5

TAOE5

LOSS5

DFMS5

LOSIE5

DFMIE5

LOSIS5

DFMIS5

SWRL

—

DLBC5

LASCS5

ATAOS5

CODE

—

ID3

ALBC4

RLBC4

TAOE4

LOSS4

DFMS4

LOSIE4

DFMIE4

LOSIS4

DFMIS4

SWRL

GMC4

DLBC4

LASCS4

ATAOS4

JADS

ID2

ALBC3

RLBC3

TAOE3

LOSS3

DFMS3

LOSIE3

DFMIE3

LOSIS3

DFMIS3

SWRL

GMC3

DLBC3

LASCS3

ATAOS3

CRIMP

TST2

ID1

ALBC2

RLBC2

TAOE2

LOSS2

DFMS2

LOSIE2

DFMIE2

LOSIS2

DFMIS2

SWRL

GMC2

DLBC2

LASCS2

ATAOS2

JAPS

ID0

ALBC1

RLBC1

TAOE1

LOSS1

DFMS1

LOSIE1

DFMIE1

LOSIS1

DFMIS1

SWRL

GMC1

DLBC1

LASCS1

ATAOS1

JAE

RW

R

09

R

W

0A

0B

0C

0D

0E

0F

10

11

12

13

RW

R

TST

TS

OE

AIS

JABWS0

TIMPOFF

OE7

—

TIMPRM

OE4

TST1

TS1

OE2

AIS2

TST0

TS0

OE1

AIS1

—

OE5

AIS5

TS2

OE3

AIS3

OE6

AIS6

AIS8

AIS7

AIS4

AISIE

AISI

14

15

RW

R

AISIE8

AISI8

AISIE7

AISI7

AISIE6

AISI6

AISIE5

AISI5

AISIE4

AISI4

AISIE3

AISI3

AISIE2

AISI2

AISIE1

AISI1

Not Used

ADDP

16-1E

1F

—

RW

—

ADDP7

—

ADDP6

—

ADDP5

—

ADDP4

—

ADDP3

—

ADDP2

—

ADDP1

—

ADDP0

ADDRESS

FOR LIUs

9–16

REGISTER

R/W

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Not Used

ALBC

RLBC

TAOE

LOSS

DFMS

LOSIE

DFMIE

LOSIS

DFMIS

SWR

BGMC

DLBC

LASCS

ATAOS

GC

20

21

22

23

24

25

26

27

28

R

—

RW

R

ALBC16

RLBC16

TAOE16

LOSS16

DFMS16

LOSIE16

DFMIE16

LOSIS16

DFMIS16

SWRU

BERTDIR

DLBC16

LASCS16

ATAOS16

RIMPMS

—

ALBC15

RLBC15

TAOE15

LOSS15

DFMS15

LOSIE15

DFMIE15

LOSIS15

DFMIS15

SWRU

BMCKS

DLBC15

LASCS15

ATAOS15

AISEL

ALBC14

RLBC14

TAOE14

LOSS14

DFMS14

LOSIE14

DFMIE14

LOSIS14

DFMIS14

SWRU

BTCKS

DLBC14

LASCS14

ATAOS14

SCPD

ALBC13

RLBC13

TAOE13

LOSS13

DFMS13

LOSIE13

DFMIE13

LOSIS13

DFMIS13

SWRU

—

DLBC13

LASCS13

ATAOS13

CODE

—

ALBC12

RLBC12

TAOE12

LOSS12

DFMS12

LOSIE12

DFMIE12

LOSIS12

DFMIS12

SWRU

GMC4

DLBC12

LASCS12

ATAOS12

JADS

—

TIMPRM

OE12

ALBC11

RLBC11

TAOE11

LOSS11

DFMS11

LOSIE11

DFMIE11

LOSIS11

DFMIS11

SWRU

GMC3

DLBC11

LASCS11

ATAOS11

CALEN

TST2

ALBC10

RLBC10

TAOE10

LOSS10

DFMS10

LOSIE10

DFMIE10

LOSIS10

DFMIS10

SWRU

GMC2

DLBC10

LASCS10

ATAOS10

JAPS

TST1

TS1

ALBC9

RLBC9

TAOE9

LOSS9

DFMS9

LOSIE9

DFMIE9

LOSIS9

DFMIS9

SWRU

GMC1

DLBC9

LASCS9

ATAOS9

JAE

29

R

W

2A

2B

2C

2D

2E

2F

30

31

32

33

RW

R

TST

TS

OE

AIS

—

OE14

AIS14

TST0

TS0

OE9

AIS9

RIMPON

OE16

AIS16

TIMPOFF

OE15

AIS15

—

OE13

AIS13

TS2

OE11

AIS11

OE10

AIS10

AIS12

AISIE

AISI

Not Used

ADDP

34

35

36-3E

3F

RW

R

—

AISIE16

AISI16

—

ADDP7

AISIE15

AISI15

—

ADDP6

AISIE14

AISI14

—

AISIE13

AISI13

—

AISIE12

AISI12

—

ADDP3

AISIE11

AISI11

—

ADDP2

AISIE10

AISI10

—

ADDP1

AISIE9

AISI9

—

RW

ADDP5

ADDP4

ADDP0

Note: Underlined bits are read only.

44 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-6. Secondary Register Set Bit Map

ADDRESS

FOR LIUs

1–8

REGISTER

RW

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SRMS

LCS

Not Used

RPDE

TPDE

EZDE

CVDEB

Not Used

ADDP

00

01

02

03

04

05

06

07–1E

1F

RW

—

SRMS8

LCS8

—

RPDE8

TPDE8

EZDE8

CVDEB8

—

SRMS7

LCS7

—

RPDE7

TDPE7

EZDE7

CVDEB7

—

SRMS6

LCS6

—

RPDE6

TPDE6

EZDE6

CVDEB6

—

SRMS5

LCS5

—

RPDE5

TPDE5

EZDE5

CVDEB5

—

SRMS4

LSC4

—

RPDE4

TPDE4

EZDE4

CVDEB4

—

SRMS3

LCS3

—

RPDE3

TPDE3

EZDE3

CVDEB3

—

SRMS2

LSC2

—

RPDE2

TPDE2

EZDE2

CVDEB2

—

SRMS1

LSC1

—

RPDE1

TPDE1

EZDE1

CVDEB1

—

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

ADDRESS

FOR LIUs

9–16

REGISTER

RW

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SRMS

LCS

Not Used

RPDE

TPDE

EZDE

CVDEB

Not Used

ADDP

20

21

22

23

24

25

26

27–3E

3F

RW

—

SRMS16

LCS16

—

RPDE16

TPDE16

EZDE16

CVDEB16

—

SRMS15

LCS15

—

RPDE15

TDPE15

EZDE15

CVDEB15

—

SRMS14

LCS14

—

RPDE14

TPDE14

EZDE14

CVDEB14

—

SRMS13

LCS13

—

RPDE13

TPDE13

EZDE13

CVDEB13

—

SRMS12

LSC12

—

RPDE12

TPDE12

EZDE12

CVDEB12

—

SRMS11

LCS11

—

RPDE11

TPDE11

EZDE11

CVDEB11

—

SRMS10

LSC10

—

RPDE10

TPDE10

EZDE10

CVDEB10

—

SRMS9

LSC9

—

RPDE9

TPDE9

EZDE9

CVDEB9

—

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

45 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-7. Individual LIU Register Set Bit Map

ADDRESS

FOR LIUs

1–8

REGISTER

RW

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IJAE

IJAPS

IJAFDS

IJAFLT

ISCPD

IAISEL

MC

SHLHS

RSMM1

RSMM2

RSMM3

RSMM4

RSL1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

RW

R

RW

R

IJAE8

IJAPS8

IJAFDS8

IJAFLT8

ISCPD8

IAISEL8

PCLKI1

SHLHS8

RTR2

RTR4

RTR6

RTR8

C2RSL3

C4RSL3

C6RSL3

IJAE7

IJAPS7

IJAE6

IJAPS6

IJAE5

IJAPS5

IJAFDS5

IJAFLT5

ISCPD5

IAISEL5

CLKAE

SHLHS5

C2RSM0

C4RSM0

C6RSM0

C8RSM0

C2RSL0

C4RSL0

C6RSL0

C8RSL0/

CALSTAT

—

IJAE4

IJAPS4

IJAFDS4

IJAFLT4

ISCPD4

IAISEL4

MPS1

SHLHS4

RTR1

RTR3

RTR5

RTR7

C1RSL3

C3RSL3

C5RSL3

IJAE3

IJAPS3

IJAE2

IJAPS2

IJAE1

IJAPS1

IJAFDS7

IJAFLT7

ISCPD7

IAISEL7

PCLKI0

SHLHS7

C2RSM2

C4RSM2

C6RSM2

C8RSM2

C2RSL2

C4RSL2

C6RSL2

IJAFDS6

IJAFLT6

ISCPD6

IAISEL6

TECLKE

SHLHS6

C2RSM1

C4RSM1

C6RSM1

C8RSM1

C2RSL1

C4RSL1

C6RSL1

IJAFDS3

IJAFLT3

ISCPD3

IAISEL3

MPS0

SHLHS3

C1RSM2

C3RSM2

C5RSM2

C7RSM2

C1RSL2

C3RSL2

C5RSL2

IJAFDS2

IJAFLT2

ISCPD2

IAISEL2

FREQS

SHLHS2

C1RSM1

C3RSM1

C5RSM1

C7RSM1

C1RSL1

C3RSL1

C5RSL1

IJAFDS1

IJAFLT1

ISCPD1

IAISEL1

PLLE

SHLHS1

C1RSM0

C3RSM0

C5RSM0

C7RSM0

C1RSL0

C3RSL0

C5RSL0

RSL2

RSL3

R

RSL4

0F

R

C8RSL3

C8RSL2

C8RSL1

C7RSL3

C7RSL2

C7RSL1

C7RSL0

BTCR

BEIR

LVDS

RCLKI

TCLKI

CCR

RDULR

GISC

ADDP

10

11

12

13

14

15

16

1E

1F

RW

R

RW

BTS2

BEIR8

LVDS8

RCLKI8

TCLKI8

PCLKS2

RDULR8

—

BTS1

BEIR7

LVDS7

RCLKI7

TCLKI7

PCLKS1

RDULR7

—

BTS0

BEIR6

LVDS6

RCLKI6

TCLKI6

PCLKS0

RDULR6

—

BERTE

BEIR1

BEIR5

LVDS5

BEIR4

LVDS4

RCLKI4

TCLKI4

CLKA3

RDULR4

—

BEIR3

LVDS3

RCLKI3

TCLKI3

CLKA2

RDULR3

—

BEIR2

LVDS2

RCLKI2

TCLKI2

CLKA1

RDULR2

INTM

LVDS1

RCLKI1

TCLKI1

CLKA0

RDULR1

CWE

RCLKI5

TCLKI5

TECLKS

RDULR5

—

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

ADDRESS

FOR LIUs

9–16

REGISTER

RW

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IJAE

IJAPS

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

3E

3F

RW

R

RW

R

IJAE16

IJAPS16

IJAE15

IJAPS15

IJAE14

IJAPS14

IJAE13

IJAPS13

IJAE12

IJAPS12

IJAE11

IJAPS11

IJAE10

IJAPS10

IJAE9

IJAPS9

IJAFDS9

IJAFLT9

ISCPD9

IAISEL9

—

IJAFDS

IJAFLT

ISCPD

IAISEL

Not Used

SHLHS

RSMM1

RSMM2

RSMM3

RSMM4

RSL1

RSL2

RSL3

RSL4

BTCR

BEIR

LVDS

IJAFDS16 IJAFDS15 IJAFDS14 IJAFDS13 IJAFDS12 IJAFDS11 IJAFDS10

IJAFLT16

ISCPD16

IAISEL16

—

SHLHS16

RTR10

RTR12

RTR14

RTR16

C10RSL3

C12RSL3

C14RSL3

C16RSL3

BTS2

BEIR16

LVDS16

RCLKI16

TCLKI16

—

IJAFLT15

ISCPD15

IAISEL15

—

IJAFLT14

ISCPD14

IAISEL14

—

IJAFLT13

ISCPD13

IAISEL13

—

IJAFLT12

ISCPD12

IAISEL12

—

SHLHS12

RTR9

RTR11

RTR13

RTR15

C9RSL3

C11RSL3

C13RSL3

C15RSL3

—

BEIR12

LVDS12

RCLKI12

TCLKI12

—

IJAFLT11

ISCPD11

IAISEL11

—

SHLHS11

C9RSM2

C11RSM2 C11RSM1 C11RSM0

C13RSM2 C13RSM1 C13RSM0

C15RSM2 C15RSM1 C15RSM0

C9RSL2

C11RSL2

C13RSL2

C15RSL2

—

IJAFLT10

ISCPD10

IAISEL10

—

SHLHS10

C9RSM1

SHLHS15

SHLHS14

SHLHS13

SHLHS9

C9RSM0

C10RSM2 C10RSM1 C10RSM0

C12RSM2 C12RSM1 C12RSM0

C14RSM2 C14RSM1 C14RSM0

C16RSM2 C16RSM1 C16RSM0

C10RSL2

C12RSL2

C14RSL2

C16RSL2

BTS1

BEIR15

LVDS15

RCLKI15

TCLKI15

—

C10RSL1

C12RSL1

C14RSL1

C16RSL1

BTS0

BEIR14

LVDS14

RCLKI14

TCLKI14

—

C10RSL0

C12RSL0

C14RSL0

C16RSL0

—

BEIR13

LVDS13

RCLKI13

TCLKI13

—

C9RSL1

C11RSL1

C13RSL1

C15RSL1

—

BEIR10

LVDS10

RCLKI10

TCLKI10

—

C9RSL0

C11RSL0

C13RSL0

C15RSL0

BERTE

BEIR9

LVDS9

RCLKI9

TCLKI9

—

R

RW

R

RW

BEIR11

LVDS11

RCLKI11

TCLKI11

—

RCLKI

TCLKI

Not Used

RDULR

Not Used

ADDP

RDULR16 RDULR15 RDULR14 RDULR13 RDULR12 RDULR11 RDULR10

—

ADDP7

RDULR9

CWE

ADDP0

—

ADDP6

—

ADDP5

—

ADDP4

—

ADDP3

—

ADDP2

INTM

ADDP1

Note: Underlined bits are read only.

46 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-8. BERT Register Bit Map

ADDRESS FOR

LIUs

REGISTER

RW

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

1–8

9–16

BCR

00

01

20

21

RW

—

RW

—

RW

—

RW

—

RW

—

R

PMUM

—

LPMU

—

RNPL

—

RPIC

—

MPR

—

APRD

—

TNPL

—

TPIC

—

Not Used

BPCR1

BPCR2

BSPR1

BSPR2

BSPR3

BSPR4

TEICR

02

22

—

QRSS

—

PTS

—

PLF4

PTF4

BSP4

BSP12

BSP20

BSP28

TEIR1

—

PLF3

PTF3

BSP3

BSP11

BSP19

BSP27

TEIR0

—

PLF2

PTF2

BSP2

BSP10

BSP18

BSP26

BEI

PLF1

PTF1

BSP1

BSP9

BSP17

BSP25

TSEI

—

PLF0

PTF0

BSP0

BSP8

BSP16

BSP24

MEIMS

—

03

23

—

04

24

BSP7

BSP15

BSP23

BSP31

—

BSP6

BSP14

BSP22

BSP30

—

BSP5

BSP13

BSP21

BSP29

TEIR2

—

05

25

06

26

07

27

08

28

Not Used

BSR

09–0B

0C

0D

0E

29–2B

2C

2D

2E

—

PMS

—

BEC

—

OOS

—

Not Used

BSRL

—

R

—

PMSL

—

BEL

BECL

—

OOSL

—

Not Used

BSRIE

0F

2F

—

RW

—

R

—

10

30

—

PMSIE

—

BEIE

—

BECIE

—

OOSIE

—

Not Used

RBECR1

RBECR2

RBECR3

Not Used

RBCR1

RBCR2

RBCR3

11–13

14

31–33

34

—

BEC7

BEC15

BEC23

—

BEC6

BEC14

BEC22

—

BEC5

BEC13

BEC21

—

BEC4

BEC12

BEC20

—

BEC3

BEC11

BEC19

—

BEC2

BEC10

BEC18

—

BEC1

BEC9

BEC17

—

BEC0

BEC8

BEC16

—

15

35

R

16

36

R

17

37

—

R

18

38

BC7

BC15

BC23

BC31

—

BC6

BC14

BC22

BC30

—

BC5

BC13

BC21

BC29

—

BC4

BC12

BC20

BC28

—

BC3

BC2

BC10

BC18

BC26

—

BC1

BC0

19

39

R

BC11

BC19

BC27

—

BC9

BC8

1A

3A

R

BC17

BC25

—

BC16

BC24

—

RBCR4

Not Used

ADDP

1B

3B

R

1C–1E

1F

3C–3E

3F

—

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

Note: Underlined bits are read only.

47 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

6.1 Register Description

This section contains the detailed register descriptions of each bit. Whenever the variable “n” in italics is used in

any of the register descriptions, it represents 1–16. Note that in the register descriptions, there are duplicate

registers for LIUs 1–8 and LIUs 9–16. There are registers in LIUs 1–8 that do not have a duplicate in the register

set for LIUs 9–16. For these registers, only one address is listed. All other registers list two addresses, one for LIUs

1–8 and one for LIUs 9–16.

6.1.1 Primary Register Bank

The ADDP register must be set to 00h to access this bank.

ID

Register Name:

Identification Register

00h

Register Description:

Register Address:

Bit #

7

6

5

4

3

2

1

0

Name

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

Bit 7: Device CODE ID Bit 7 (ID7). This bit is “one” for long-haul operation.

Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID[6:3]). These bits tell the user the number of ports the device contains.

Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID[2:0]). These bits tell the user the revision of the part. Contact the

factory for details.

ALBC

Register Name:

Analog Loopback Control Register

01h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

ALBC8

0

6

ALBC7

0

5

ALBC6

0

4

ALBC5

0

3

ALBC4

0

2

ALBC3

0

1

ALBC2

0

ALBC1

0

21h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

ALBC16

0

6

ALBC15

0

5

ALBC14

0

4

ALBC13

0

3

ALBC12

0

2

ALBC11

0

1

ALBC10

0

ALBC9

0

Bits 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in analog

loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. The

LOS detector is still in operation. The jitter attenuator is in use if enabled for the transmitter or receiver.

48 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RLBC

Register Name:

Remote Loopback Control Register

02h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RLBC8

0

6

RLBC7

0

5

RLBC6

0

4

RLBC5

0

3

RLBC4

0

2

RLBC3

0

1

RLBC2

0

RLBC1

0

22h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RLBC16

0

6

RLBC15

0

5

RLBC14

0

4

RLBC13

0

3

RLBC12

0

2

RLBC11

0

1

RLBC10

0

RLBC9

0

Bits 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, remote loopback is

enabled on LIUn. The analog received signal goes through the receive digital and is looped back to the transmitter.

The data at TPOS and TNEG is ignored. The jitter attenuator is in use if enabled.

TAOE

Register Name:

Transmit All Ones Enable Register

03h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

TAOE8

0

6

TAOE7

0

5

TAOE6

0

4

TAOE5

0

3

TAOE4

0

2

TAOE3

0

1

TAOE2

0

TAOE1

0

23h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

TAOE16

0

6

5

TAOE14

0

4

TAOE13

0

3

TAOE12

0

2

TAOE11

0

1

TAOE10

0

TAOE9

0

TAOE15

0

Bits 7 to 0: Transmit All Ones Enable Channel n (TAOEn). When this bit is set, continuous stream of all ones on

TTIP and TRING are sent on Channel n. MCLK is used as a reference clock for Transmit All Ones Signal. The data

arriving at TPOS and TNEG is ignored.

LOSS

Register Name:

Loss of Signal Status Register

04h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LOSS8

0

6

LOSS7

0

5

LOSS6

0

4

LOSS5

0

3

LOSS4

0

2

LOSS3

0

1

LOSS2

0

LOSS1

0

24h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

LOSS16

0

6

5

LOSS14

0

4

LOSS13

0

3

LOSS12

0

2

LOSS11

0

1

LOSS10

0

LOSS9

0

LOSS15

0

Bits 7 to 0: Loss of Signal Status Channel n (LOSSn). When this bit is set, an LOS condition has been detected

on LIUn. The criteria and conditions of LOS are described in Section 5.5.6.

49 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

DFMS

Register Name:

Driver Fault Monitor Status Register

05h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

DFMS8

0

6

DFMS7

0

5

DFMS6

0

4

DFMS5

0

3

DFMS4

0

2

DFMS3

0

1

DFMS2

0

DFMS1

0

25h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

DFMS16

0

6

5

DFMS14

0

4

DFMS13

0

3

DFMS12

0

2

DFMS11

0

1

DFMS10

0

DFMS9

0

DFMS15

0

Bits 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short

or open circuit at the transmit driver for LIUn.

LOSIE

Register Name:

Loss of Signal Interrupt Enable Register

06h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LOSIE8

0

6

LOSIE7

0

5

LOSIE6

0

4

LOSIE5

0

3

LOSIE4

0

2

LOSIE3

0

1

LOSIE2

0

LOSIE1

0

26h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

LOSIE16

0

6

5

LOSIE14

0

4

LOSIE13

0

3

LOSIE12

0

2

LOSIE11

0

1

LOSIE10

0

LOSIE9

0

LOSIE15

0

Bits 7 to 0: Loss of Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in LOS status

for LIUn can generate an interrupt.

DFMIE

Register Name:

Driver Fault Monitor Interrupt Enable Register

07h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

DFMIE8

0

6

DFMIE7

0

5

DFMIE6

0

4

DFMIE5

0

3

DFMIE4

0

2

DFMIE3

0

1

DFMIE2

0

DFMIE1

0

27h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

DFMIE9

0

DFMIE16 DFMIE15 DFMIE14 DFMIE13 DFMIE12 DFMIE11 DFMIE10

0

Bits 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM

status can generate an interrupt.

50 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LOSIS

Register Name:

Loss of Signal Interrupt Status Register

08h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LOSIS8

0

6

LOSIS7

0

5

LOSIS6

0

4

LOSIS5

0

3

LOSIS4

0

2

LOSIS3

0

1

LOSIS2

0

LOSIS1

0

28h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

LOSIS16

0

6

5

LOSIS14

0

4

LOSIS13

0

3

LOSIS12

0

2

LOSIS11

0

1

LOSIS10

0

LOSIS9

0

LOSIS15

0

Bits 7 to 0: Loss of Signal Interrupt Status Channel n (LOSISn). When this bit is set, it indicates a LOS status

has transition from a “0 to 1” or “1 to 0” and was detected for LIUn. The bit for LIUn is enabled by register LOSIE

(06h). This bit when latched is cleared on a read operation.

DFMIS

Register Name:

Driver Fault Monitor Interrupt Status Register

09h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

DFMIS8

0

6

DFMIS7

0

5

DFMIS6

0

4

DFMIS5

0

3

DFMIS4

0

2

DFMIS3

0

1

DFMIS2

0

DFMIS1

0

29h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

DFMIS9

0

DFMIS16 DFMIS15 DFMIS14 DFMIS13 DFMIS12 DFMIS11 DFMIS10

0

Bits 7 to 0: Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has

transitioned from “0 to 1” or “1 to 0” and was detected for LIUn. The bit for LIUn is enabled by register DFMIE (07h).

This bit when latched is cleared on a read operation.

51 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

SWR

Register Name:

Software Reset Register

0Ah

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

SWRL

0

6

SWRL

0

5

SWRL

0

4

SWRL

0

3

SWRL

0

2

SWRL

0

1

SWRL

0

SWRL

0

Bits 7 to 0: Software Reset (SWRL). Whenever any write is performed to this register, at least 1µs reset will be

generated that resets the lower set of registers (LIUs 1–8). All the registers will be restored to their default values.

A read operation will always read back all zeros.

2Ah

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

SWRU

0

SWRU

0

SWRU

0

SWRU

0

SWRU

0

SWRU

0

SWRU

0

SWRU

0

Bits 7 to 0: Software Reset (SWRU). Whenever any write is performed to this register, at least 1µs reset will be

generated that resets the upper set of registers (LIUs 9–16). All the registers will be restored to their default values.

A read operation will always read back all zeros.

52 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

BGMC

Register Name:

BERT and G.772 Monitoring Control Register

0Bh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

BERTDIR

0

6

BMCKS

0

5

BTCKS

0

4

—

0

3

GMC3

0

2

GMC2

0

1

GMC1

0

GMC0

0

Bit 7: BERT Direction Control Bit (BERTDIR). When this bit is set, the BERT for LIUs 1–8 will be enabled on the

system side of the part (BERT data will come out on RPOS/RNEG and be expected on TPOS/TNEG) for whichever

LIU the BERT is enabled.

Bit 6: BERT MCLK Selection (BMCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit will select MCLK as the BERT clock unless BTCKS is set. If neither BMCKS nor BTCKS is set, the BERT

will use the recovered clock.

Bit 5: BERT TCLK Selection (BTCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit selects TCLK as the BERT clock, regardless of the state of the BMCKS bit. If neither BMCKS nor BTCKS is

set, the BERT will use the recovered clock.

Bits 3 to 0: G.772 Monitoring Control (GMC[3:0]). These bits are used to select transmitter or receiver for

nonintrusive monitoring. Receiver 1 is used to monitor Channels 2 to 8 of one receiver from RTIP2–

RTIP8/RRING2–RRING8 or of one transmitter from TTIP2–TTIP8/TRING2–TRING8. See Table 6-9.

2Bh

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BERTDIR

0

6

BMCKS

0

5

BTCKS

0

4

—

3

GMC3

0

2

GMC2

0

1

GMC1

0

GMC0

0

Bit 7: BERT Direction Control Bit (BERTDIR). When this bit is set, the BERT for LIUs 9–16 will be enabled on

the system side of the part (BERT data will come out on RPOS/RNEG and be expected on TPOS/TNEG) for

whichever LIU the BERT is enabled.

Bit 6: BERT MCLK Selection (BMCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit will select MCLK as the BERT clock unless BTCKS is set. If neither BMCKS nor BTCKS is set, the BERT

will use the recovered clock. If the clock used as the BERT clock is MCLK or the recovered clock, TCLK must be

frequency locked to the BERT clock in order for the BERT to sync.

Bit 5: BERT TCLK Selection (BTCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit selects TCLK as the BERT clock, regardless of the state of the BMCKS bit. If neither BMCKS nor BTCKS is

set, the BERT will use the recovered clock.

Bits 3 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for

nonintrusive monitoring. Receiver 9 is used to monitor Channels 10 to 16 of one receiver from RTIP10–

RTIP16/RRING10–RRING16 or of one transmitter from TTIP10–TTIP16/TRING10–TRING16. See Table 6-10.

53 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-9. G.772 Monitoring Control (LIU 1)

GMC3

GMC2

GMC1

GMC0

SELECTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Monitoring

Receiver 2

Receiver 3

Receiver 4

Receiver 5

Receiver 6

Receiver 7

Receiver 8

No Monitoring

Transmitter 2

Transmitter 3

Transmitter 4

Transmitter 5

Transmitter 6

Transmitter 7

Transmitter 8

Table 6-10. G.772 Monitoring Control (LIU 9)

GMC3

GMC2

GMC1

GMC0

SELECTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Monitoring

Receiver 10

Receiver 11

Receiver 12

Receiver 13

Receiver 14

Receiver 15

Receiver 16

No Monitoring

Transmitter 10

Transmitter 11

Transmitter 12

Transmitter 13

Transmitter 14

Transmitter 15

Transmitter 16

54 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

DLBC

Register Name:

Digital Loopback Control Register

0Ch

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

DLBC8

0

6

DLBC7

0

5

DLBC6

0

4

DLBC5

0

3

DLBC4

0

2

DLBC3

0

1

DLBC2

0

DLBC1

0

2Ch

Register Address (LIUs 9–16):

Bit #

Name

Default

7

DLBC16

0

6

DLBC15

0

5

DLBC14

0

4

DLBC13

0

3

DLBC12

0

2

DLBC11

0

1

DLBC10

0

DLBC9

0

Bits 7 to 0: Digital Loopback Control Channel n (DLBCn). When this bit is set the LIUn is placed in digital

loopback. The data at TPOS/TNEG is encoded and looped back to the decoder and output on RPOS/RNEG. The

Jitter Attenuator can optionally be included in the transmit or receive paths.

LASCS

Register Name:

LOS/AIS Criteria Selection Register

0Dh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LASCS8

0

6

LASCS7

0

5

LASCS6

0

4

LASCS5

0

3

LASCS4

0

2

LASCS3

0

1

LASCS2

0

LASCS1

0

2Dh

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

LASCS9

0

LASCS16 LASCS15 LASCS14 LASCS13 LASCS12 LASCS11 LASCS10

0

Bits 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). This bit is used for LOS/AIS selection criteria for

LIUn. In E1 mode, if set it uses ETS 300 233 mode selections. If reset it uses G.775 criteria. In T1/J1 mode T1.231

criteria is selected.

ATAOS

Register Name:

Automatic Transmit All Ones Select Register

0Eh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

ATAOS8

0

6

ATAOS7

0

5

ATAOS6

0

4

ATAOS5

0

3

ATAOS4

0

2

ATAOS3

0

1

ATAOS2

0

ATAOS1

0

2Eh

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

ATAOS9

0

ATAOS16 ATAOS15 ATAOS14 ATAOS13 ATAOS12 ATAOS11 ATAOS10

0

Bits 7 to 0: Automatic Transmit All Ones Select Channel n (ATAOSn). When this bit is set all ones signal is

sent if an LOS is detected for LIUn. “All Ones Signal” uses MCLK as the reference clock.

55 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

GC

Register Name:

Global Configuration Register

0Fh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RIMPMS

0

6

AISEL

0

5

SCPD

0

4

CODE

0

3

JADS

0

2

CRIMP

0

1

JAPS

0

JAE

0

Note: CRIMP controls all 16 LIUs. All other bits are for LIUs 1–8 only.

Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, fully internal impedance match mode is

selected, so RTIP and RRING require no external resistor. If this bit is set, the receiver line transformer must be a

1:1 turns ratio and the RTR bit set. When reset, external termination mode is selected and an external resistor is

required to terminate the receive line. This external resistor will be adjusted internally to the correct termination

value if partially internal impedance matching is turned on (TS.RIMPON = 1).

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting

LOS for each channel. The individual LIU register IAISEL settings will be ignored when this bit is set. When reset,

the IAISEL register will have control.

Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the short-circuit protection is disabled for all the

transmitters. The individual LIU register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD

register will have control.

Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored

when this bit is set. If reset, the LCS register will have control.

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The

settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.

Bit 2: Calibrate Receive Internal Termination (CRIMP). A low-to-high transition on this bit initiates a calibration

cycle for the receive internal termination. This requires a 16kΩ ±1% resistor on the RESREF pin. Bit 2 of the GC

register at address 0x2F must also be set to enable calibration. While this bit is set, RSL4.4 (0x0F in individual

bank) will indicate the status of the calibration cycle.

Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the jitter attenuator will be in the

receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU

by settings in the IJAPS register. Note that when bit JAE is set, the settings in the IJAPS register will be ignored.

Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the IJAE

register will be ignored if this register is set. If reset, the IJAE register will have control.

56 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

2Fh

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RIMPMS

0

6

AISEL

0

5

SCPD

0

4

CODE

0

3

JADS

0

2

CALEN

0

1

JAPS

0

JAE

0

Note: CALEN controls all 16 LIUs. All other bits are for LIUs 9–16 only.

Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the fully internal receive impedance

matching mode is selected, so RTIP and RRING require no external resistor. If this bit is set, the receiver line

transformer must be a 1:1 turns ratio and the RTR bit set. When reset and TS.RIMPON = 1, partially internal

receive impedance matching mode is selected and an external resistor is required to terminate the receive line.

This external resistor will be adjusted internally to the correct termination value.

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting

LOS for each channel. The individual LIU register IAISEL settings will be ignored when this bit is set. When reset,

the IAISEL register will have control.

Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the short-circuit protection is disabled for all the

transmitters. The individual LIU register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD

register will have control.

Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored

when this bit is set. If reset, the LCS register will have control.

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The

settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.

Bit 2: Calibrate Receive Impedance Match (CALEN). This bit must be set to enable calibration of the receive

termination. If this bit is set and a 16kΩ resistor is on the RESREF pin, then a low-to-high transition on the CRIMP

bit will initiate a calibration cycle for the receive internal termination. The user should wait at least 5µs before

setting the CRIMP bit.

Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set, the jitter attenuator will be in the

receive path for each channel. The individual LIU register IJAPS settings will be ignored when this bit is set. When

reset, the IJAPS register will have control.

Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the IJAE

register will be ignored if this register is set. If reset, the IJAE register will have control.

57 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TST

Register Name:

Template Select Transmitter Register

10h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

JABWS1

0

6

JABWS0

0

5

RHPMC

0

4

—

0

3

—

0

2

TST2

0

1

TST1

0

TST0

0

Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to

control the bandwidth of the jitter attenuator according to the following table:

JABWS

00

BANDWIDTH (Hz)

0.625

1.25

2.5

01

10

11

5

Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match

on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive

impedance match is off (Internal impedance to RTIP and RRING is high impedance). When this bit is reset, the

RIMPON register bit will control receive impedance match.

Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the

Transmit Template Select Register (0x11) will configure for LIUs 1–8. See Table 6-11.

30h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

JABWS1

0

6

5

RHPMC

0

4

—

0

3

—

0

2

TST2

0

1

TST1

0

TST0

0

JABWS0

0

Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to

control the bandwidth of the jitter attenuator according to the following table:

JABWS

00

BANDWIDTH (Hz)

0.625

1.25

2.5

01

10

11

5

Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match

on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive

impedance match is off (internal impedance to RTIP and RRING is high impedance). When this bit is reset, the

RIMPON register bit will control receive impedance match.

Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the

Transmit Template Select Register (0x11) will configure for LIUs 9–16. See Table 6-12.

58 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-11. TST Template Select Transmitter Register (LIUs 1–8)

TST[2:0]

000

CHANNEL

TST[2:0]

100

CHANNEL

1

2

3

4

5

6

7

8

001

010

011

101

110

111

Table 6-12. TST Template Select Transmitter Register (LIUs 9–16)

TST[2:0]

000

CHANNEL

TST[2:0]

100

CHANNEL

9

13

14

15

16

001

010

011

10

11

12

101

110

111

59 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TS

Register Name:

Template Select Register

Register Description:

11h

31h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RIMPON

0

6

TIMPOFF

0

5

—

0

4

—

0

3

TIMPRM

0

2

TS2

0

1

TS1

0

TS0

0

Note: This register configures each LIU individually. This register configures the LIU selected by TST.TST[2:0].

Bit 7: Receive Impedance Match On (RIMPON). If this bit is set, internal receive impedance matching is turned

on. Otherwise, the receiver is in high impedance. Note that the OE pin can have control instead of this bit when the

TST.RHPMC bit is set.

Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set all the internal transmit terminating

impedance is turned off.

Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal transmit termination

impedance and receive impedance match for E1 mode and T1/J1 mode.

0 = 75Ω for E1 mode or 100Ω for T1 mode.

1 = 120Ω for E1 mode or 110Ω for J1 mode.

Bits 2 to 0: Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the template,

and the settings for various cable lengths. The impedance termination for the transmitter and impedance match for

the receiver are specified by bit TIMPRM. Short-haul or long-haul operation is selected by the SHLHS bit in the

individual registers SHLHS (07). See Table 6-13 for bit selection of TS[2:0].

Table 6-13. Template Selection

TEMPLATE SELECTION

IMPEDANCE

(Ω)

CABLE LOSS

TS[2:0]

LINE LENGTH (ft)

OPERATION MODE

(dB)

0.6

1.2

1.8

2.4

3.0

011

100

101

110

111

0–133 ABAM

133–266 ABAM

266–399 ABAM

399–533 ABAM

533–655 ABAM

100/110

75/120

T1/J1 Short Haul

T1 Short Haul

E1 Short/Long Haul

Short/Long Haul

T1/J1 Long Haul

000

G.703 coaxial and twisted pair cable

—

001 and 010

011

Reserved

0db CSU

-7.5dB CSU

-15dB CSU

—

100/110

—

100

101

110

—

-22.5dB CSU

60 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

OE

Register Name:

Output Enable Configuration Register

12h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

OE8

0

6

OE7

0

5

OE6

0

4

OE5

0

3

OE4

0

2

OE3

0

1

OE2

0

OE1

0

32h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

OE16

0

6

OE15

0

5

OE14

0

4

OE13

0

3

OE12

0

2

OE11

0

1

OE10

0

OE9

0

Bits 7 to 0: Output Enable Channel n (OEn). When this bit is reset, the transmitter output for LIUn is high

impedance. When this bit is set, the transmitter output for LIUn is enabled. Note that the OE pin will override this

setting when low.

AIS

Register Name:

Alarm Indication Signal Status Register

13h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

AIS8

0

6

AIS7

0

5

AIS6

0

4

AIS5

0

3

AIS4

0

2

AIS3

0

1

AIS2

0

AIS1

0

33h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

AIS16

0

6

AIS15

0

5

AIS14

0

4

AIS13

0

3

AIS12

0

2

AIS11

0

1

AIS10

0

AIS9

0

Bits 7 to 0: Alarm Indication Signal Channel n (AISn). This bit will be set when AIS is detected for LIUn. The

criteria for AIS selection is detailed in Section 5.5.7. The selection of the AIS criteria is done by settings in the

LASCS (0D) register.

61 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

AISIE

Register Name:

AIS Interrupt Enable Register

14h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

AISIE8

0

6

AISIE7

0

5

AISIE6

0

4

AISIE5

0

3

AISIE4

0

2

AISIE3

0

1

AISIE2

0

AISIE1

0

34h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

AISIE16

0

6

AISIE15

0

5

AISIE14

0

4

AISIE13

0

3

AISIE12

0

2

AISIE11

0

1

AISIE10

0

AISIE9

0

Bits 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if

AIS status transitions.

AISI

Register Name:

AIS Interrupt Status Register

15h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

AISI8

0

6

AISI7

0

5

AISI6

0

4

AISI5

0

3

AISI4

0

2

AISI3

0

1

AISI2

0

AISI1

0

35h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

AISI16

0

6

AISI15

0

5

AISI14

0

4

AISI13

0

3

AISI12

0

2

AISI11

0

1

AISI10

0

AISI9

0

Bits 7 to 0: AIS Interrupt Status Channel n (AISIn). This bit is set when AIS ransitions from a “0 to 1” or “1 to 0”

and interrupts are enabled by the AISIE(14) register for LIUn. If set, this bit is cleared on a read operation or when

the interrupt enable register is disabled.

62 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

ADDP

Register Name:

Address Pointer for Bank Selection Register

Register Description:

1Fh

3Fh

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

ADDP7

0

6

ADDP6

0

5

ADDP5

0

4

ADDP4

0

3

ADDP3

0

2

ADDP2

0

1

ADDP1

0

ADDP0

0

Bits 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the primary registers, the

secondary registers, individual registers, and BERT registers. See Table 6-14 for bank selection. The register

space contains control for Channels 1 to 8 from address 00 hex to 1F hex and a duplicate set of registers for

control of Channels 9 to 16 from address 20 hex to 3F hex. The ADDP at address 1F hex select the banks for the

set of registers for LIUs 1–8. The ADDP register at address 3F select the banks for the set of registers for LIUs 9–

16.

Table 6-14. Address Pointer for Bank Selection

ADDP[7:0] (HEX)

BANK NAME

Primary Bank

Secondary Bank

Individual LIU Bank

BERT Bank

00

AA

01

02

6.1.2 Secondary Register Bank

The ADDP register must be set to AAh in order to access this bank.

SRMS

Register Name:

Single-Rail Mode Select Register

00h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

SRMS8

0

6

SRMS7

0

5

SRMS6

0

4

SRMS5

0

3

SRMS4

0

2

SRMS3

0

1

SRMS2

0

SRMS1

0

20h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

SRMS16

0

6

5

SRMS14

0

4

SRMS13

0

3

SRMS12

0

2

SRMS11

0

1

SRMS10

0

SRMS9

0

SRMS15

0

Bits 7 to 0: Single-Rail Mode Select Channel n (SRMSn). When this bit is set single-rail mode is selected for the

system transmit and receive n. If this bit is reset, dual-rail is selected.

63 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LCS

Register Name:

Line Code Selection Register

01h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LCS8

0

6

LCS7

0

5

LCS6

0

4

LCS5

0

3

LCS4

0

2

LCS3

0

1

LCS2

0

LCS1

0

21h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

LCS16

0

6

LCS15

0

5

LCS14

0

4

LCS13

0

3

LCS12

0

2

LCS11

0

1

LCS10

0

LCS9

0

Bits 7 to 0: Line Code Select Channel n (LCSn). When this bit is set AMI encoding/decoding is selected for LIUn.

If reset, B8ZS or HDB3 encoding/decoding is selected for LIUn. Note that if the GC.CODE register bit is set it will

ignore this register.

RPDE

Register Name:

Receive Power-Down Enable Register

03h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RPDE8

0

6

RPDE7

0

5

RPDE6

0

4

RPDE5

0

3

RPDE4

0

2

RPDE3

0

1

RPDE2

0

RPDE1

0

23h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RPDE16

0

6

5

RPDE14

0

4

RPDE13

0

3

RPDE12

0

2

RPDE11

0

1

RPDE10

0

RPDE9

0

RPDE15

0

Bits 7 to 0: Receive Power-Down Enable Channel n (RPDEn). When this bit is set the receiver for LIUn is

powered down.

TPDE

Register Name:

Transmit Power-Down Enable Register

04h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

TPDE8

0

6

TPDE7

0

5

TPDE6

0

4

TPDE5

0

3

TPDE4

0

2

TPDE3

0

1

TPDE2

0

TPDE1

0

24h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

TPDE16

0

6

5

TPDE14

0

4

TPDE13

0

3

TPDE12

0

2

TPDE11

0

1

TPDE10

0

TPDE9

0

TPDE15

0

Bits 7 to 0: Transmit Power-Down Enable Channel n (TPDEn). When this bit is set the transmitter for LIUn is

powered down.

64 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

EZDE

Register Name:

Excessive Zero Detect Enable Register

05h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

EZDE8

0

6

EZDE7

0

5

EZDE6

0

4

EZDE5

0

3

EZDE4

0

2

EZDE3

0

1

EZDE2

0

EZDE1

0

25h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

EZDE16

0

6

5

EZDE14

0

4

EZDE13

0

3

EZDE12

0

2

EZDE11

0

1

EZDE10

0

EZDE9

0

EZDE15

0

Bits 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset excessive zero detection is

disabled for LIUn. When this bit is set excessive zero detect enable is enabled. Excessive zero detection is only

relevant when HDB3 or B8ZS decoding is enabled (LCS register).

CVDEB

Register Name:

Code Violation Detect Enable Bar Register

06h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

CVDEB8

0

6

CVDEB7

0

5

CVDEB6

0

4

CVDEB5

0

3

CVDEB4

0

2

CVDEB3

0

1

CVDEB2

0

CVDEB1

0

26h

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

CVDEB16 CVDEB15 CVDEB14 CVDEB13 CVDEB12 CVDEB11 CVDEB10 CVDEB9

0

Bits 7 to 0: Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is

disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only

relevant when HDB3 decoding is enabled (LCS register).

65 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

6.1.3 Individual LIU Register Bank

The ADDP register must be set to 01h to access this bank.

IJAE

Register Name:

Individual Jitter Attenuator Enable Register

00h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

IJAE8

0

6

IJAE7

0

5

IJAE6

0

4

IJAE5

0

3

IJAE4

0

2

IJAE3

0

1

IJAE2

0

IJAE1

0

20h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

IJAE16

0

6

IJAE15

0

5

IJAE14

0

4

IJAE13

0

3

IJAE12

0

2

IJAE11

0

1

IJAE10

0

IJAE9

0

Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIU jitter attenuator

n is enabled. Note that if the GC.JAE register bit is set, this register will be ignored.

IJAPS

Register Name:

Individual Jitter Attenuator Position Select Register

01h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

IJAPS8

0

6

IJAPS7

0

5

IJAPS6

0

4

IJAPS5

0

3

IJAPS4

0

2

IJAPS3

0

1

IJAPS2

0

IJAPS1

0

21h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

IJAPS16

0

6

5

IJAPS14

0

4

IJAPS13

0

3

IJAPS12

0

2

IJAPS11

0

1

IJAPS10

0

IJAPS9

0

IJAPS15

0

Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high, the jitter

attenuator is in the receive path n; when this bit is default or set low the jitter attenuator is in the transmit path n.

Note that if the GC.JAE register bit is set, this register will be ignored.

66 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

IJAFDS

Register Name:

Individual Jitter Attenuator FIFO Depth Select Register

02h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

IJAFDS8

0

6

IJAFDS7

0

5

IJAFDS6

0

4

IJAFDS5

0

3

IJAFDS4

0

2

IJAFDS3

0

1

IJAFDS2

0

IJAFDS1

0

22h

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

IJAFDS16 IJAFDS15 IJAFDS14 IJAFDS13 IJAFDS12 IJAFDS11 IJAFDS10 IJAFDS9

0

Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn). When this bit is set for LIUn the jitter

attenuator FIFO depth will be 128 bits. When reset the jitter attenuator FIFO depth will be 32 bits. Note that if the

GC.IJAFDS register bit is set, this register will be ignored.

IJAFLT

Register Name:

Individual Jitter Attenuator FIFO Limit Trip Register

03h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

IJAFLT8

0

6

IJAFLT7

0

5

IJAFLT6

0

4

IJAFLT5

0

3

IJAFLT4

0

2

IJAFLT3

0

1

IJAFLT2

0

IJAFLT1

0

23h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

IJAFLT9

0

IJAFLT16 IJAFLT15 IJAFLT14 IJAFLT13 IJAFLT12 IJAFLT11 IJAFLT10

0

Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO

reaches to within 4 bits of its useful limit for transmitter n. This bit will be cleared when read.

ISCPD

Register Name:

Individual Short-Circuit Protection Disable Register

04h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

ISCPD8

0

6

ISCPD7

0

5

ISCPD6

0

4

ISCPD5

0

3

ISCPD4

0

2

ISCPD3

0

1

ISCPD2

0

ISCPD1

0

24h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

ISCPD16

0

6

5

ISCPD14

0

4

ISCPD13

0

3

ISCPD12

0

2

ISCPD11

0

1

ISCPD10

0

ISCPD9

0

ISCPD15

0

Bits 7 to 0: Individual Short-Circuit Protection Disable n. (ISCPDn). When this bit is set the short-circuit

protection is disabled for the individual transmitter n. Note that if the GC.SCPD register bit is set, the settings in this

register will be ignored.

67 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

IAISEL

Register Name:

Individual AIS Select Register

05h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

IAISEL8

0

6

IAISEL7

0

5

IAISEL6

0

4

IAISEL5

0

3

IAISEL4

0

2

IAISEL3

0

1

IAISEL2

0

IAISEL1

0

25h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

IAISEL9

0

IAISEL16 IAISEL15 IAISEL14 IAISEL13 IAISEL12 IAISEL11 IAISEL10

0

Bits 7 to 0: Individual AIS Enable During Loss n (IAISELn). When this bit is set, individual AIS enable during

loss is enabled for the individual receiver n, and AIS is sent to the system side upon detection of an LOS. Note that

if the GC.AISEL register bit is set, the settings in this register will be ignored.

68 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

MC

Register Name:

Master Clock Select Register

06h

Register Description:

Register Address:

Bit #

Name

Default

7

PCLKI1

0

6

PCLKI0

0

5

TECLKE

0

4

CLKAE

0

3

MPS1

0

2

MPS0

0

1

FREQS

0

PLLE

0

Bits 7 and 6: PLL Clock Input [1:0] (PCLKI[1:0]). These bits select the input into to the PLL.

00: MCLK is used.

01: RCLK1 to 8 is used based on the selection in register CCR.

10: RCLK9 to 16 is used based on the selection in register CCR.

11: Reserved.

Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK will be

disabled and the TECLK output is a LOS output. TECLK requires PLLE to be set for correct functionality.

Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set CLKA will be disabled

and the CLKA output is a LOS output. CLKA requires PLLE to be set for correct functionality.

Bits 3 and 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK frequency

for the DS26334. See Table 6-15 for details. This register when written to will also controller functionality of

Channels 9 to 16.

Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the

DS26334. If this bit is set the external Master clock can be 1.544MHz or multiple thereof. If not set the external

master clock can be 2.048MHz or multiple thereof. See Table 6-15 for details. This register when written to will also

controller functionality of Channels 9 to 16.

Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If not set MCLK will

be the applied input clock.

Table 6-15. DS26334 MCLK Selections

MCLK,

MHz ±50ppm

PLLE

MPS1, MPS0

FREQS

MODE

0

1

xx

00

01

10

11

00

01

10

11

1.544

2.048

1.544

3.088

6.176

12.352

2.048

4.096

8.192

x

1

0

T1

E1

T1/J1 or E1

16.384

69 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

SHLHS

Register Name:

Short-Haul/Long-Haul Select Register

07h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

SHLHS8

0

6

SHLHS7

0

5

SHLHS6

0

4

SHLHS5

0

3

SHLHS4

0

2

SHLHS3

0

1

SHLHS2

0

SHLHS1

0

27h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

2

1

0

SHLHS9

0

SHLHS16 SHLHS15 SHLHS14 SHLHS13 SHLHS12 SHLHS11 SHLHS10

0

Bits 7 to 0: Short-Haul/Long-Haul Select n. (SHLHSn). When this bit is set, the long-haul mode is enabled for

the individual transmitter n.

70 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSMM1

Register Name:

Receive Sensitivity Monitor Mode 1 Register

08h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RTR2

0

6

C2RSM2

0

5

C2RSM1

0

4

C2RSM0

0

3

RTR1

0

2

C1RSM2

0

1

C1RSM1

0

C1RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 2 (RTR2). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS2). Note that in order to use fully internal receive impedance termination, a 1:1 transformer must be

used and this bit must be set to 1.

Bits 6 to 4: Channel 2 Receive Sensitivity/Monitor Select [2:0] (C2RSM[2:0]). Bits C2RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 1 (RTR1). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS1). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must

be used and this bit must be set to 1.

Bits 2 to 0: Channel 1 Receive Sensitivity/Monitor Select [2:0] (C1RSM[2:0]). Bits C1RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

28h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RTR10

0

6

5

4

3

RTR9

0

2

C9RSM2

0

1

C9RSM1

0

C9RSM0

0

C10RSM2 C10RSM1 C10RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 10 (RTR10). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS10). Note that in order to use fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 6 to 4: Channel 10 Receive Sensitivity/Monitor Select [2:0] (C10RSM[2:0]). Bits C10RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 9 (RTR9). If this bit is set the Turns Ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS9). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 2 to 0: Channel 9 Receive Sensitivity/Monitor Select [2:0] (C9RSM[2:0]). Bits C9RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

71 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSMM2

Register Name:

Receive Sensitivity Monitor Mode 2 Register

09h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RTR4

0

6

C4RSM2

0

5

C4RSM1

0

4

C4RSM0

0

3

RTR3

0

2

C3RSM2

0

1

C3RSM1

0

C3RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 4 (RTR4). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS4). Note that in order to use fully internal receive impedance termination, a 1:1 transformer must be

used and this bit must be set to 1.

Bit 6 to 4: Channel 4 Receive Sensitivity/Monitor Select [2:0] (C4RSM[2:0]). Bits C4RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 3 (RTR3). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS3). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must

be used and this bit must be set to 1.

Bit 2 to 0: Channel 3 Receive Sensitivity/Monitor Select [2:0] (C3RSM[2:0]). Bits C3RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

29h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RTR12

0

6

5

4

3

RTR11

0

2

1

0

C12RSM2 C12RSM1 C12RSM0

C11RSM2 C11RSM1 C11RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 12 (RTR12). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS12). Note that in order to use fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 6 to 4: Channel 12 Receive Sensitivity/Monitor Select [2:0] (C12RSM[2:0]). Bits C12RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 11 (RTR11). If this bit is set the rurns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS11). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 2 to 0: Channel 11 Receive Sensitivity/Monitor Select [2:0] (C11RSM[2:0]). Bits C11RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

72 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSMM3

Register Name:

Receive Sensitivity Monitor Mode 3 Register

0Ah

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RTR6

0

6

C6RSM2

0

5

C6RSM1

0

4

C6RSM0

0

3

RTR5

0

2

C5RSM2

0

1

C5RSM1

0

C5RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 6 (RTR6). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS6). Note that in order to use fully internal receive impedance termination, a 1:1 transformer must be

used and this bit must be set to 1.

Bits 6 to 4: Channel 6 Receive Sensitivity/Monitor Select [2:0] (C6RSM[2:0]). Bits C6RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 5 (RTR5). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS5). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must

be used and this bit must be set to 1.

Bits 2 to 0: Channel 5 Receive Sensitivity/Monitor Select [2:0] (C5RSM[2:0]). Bits C5RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

2Ah

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RTR14

0

6

5

4

3

RTR13

0

2

1

0

C14RSM2 C14RSM1 C14RSM0

C13RSM2 C13RSM1 C13RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 14 (RTR14). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS14). Note that in order to use fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 6 to 4: Channel 14 Receive Sensitivity/Monitor Select [2:0] (C14RSM[2:0]). Bits C14RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 13 (RTR13). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS13). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 2 to 0: Channel 13 Receive Sensitivity/Monitor Select [2:0] (C13RSM[2:0]). Bits C13RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

73 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSMM4

Register Name:

Receive Sensitivity Monitor Mode 4 Register

0Bh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RTR8

0

6

C8RSM2

0

5

C8RSM1

0

4

C8RSM0

0

3

RTR7

0

2

C7RSM2

0

1

C7RSM1

0

C7RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 8 (RTR8). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS8). Note that in order to use fully internal receive impedance termination, a 1:1 transformer must be

used and this bit must be set to 1.

Bits 6 to 4: Channel 8 Receive Sensitivity/Monitor Select [2:0] (C8RSM[2:0]). Bits C8RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 7 (RTR7). If this bit is set the turns ratio is 1:1 on the receiver

side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-haul

mode (SHLHS7). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must

be used and this bit must be set to 1.

Bits 2 to 0: Channel 7 Receive Sensitivity/Monitor Select [2:0] (C7RSM[2:0]). Bits C7RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

2Bh

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RTR16

0

6

5

4

3

RTR15

0

2

1

0

C16RSM2 C16RSM1 C16RSM0

C15RSM2 C15RSM1 C15RSM0

0

Bit 7: Receiver Transformer Turns Ratio Channel 16 (RTR16). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS16). Note that in order to use fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bit 6 to 4: Channel 16 Receive Sensitivity/Monitor Select [2:0] (C16RSM[2:0]). Bits C16RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 15 (RTR15). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used and is recommended when using long-

haul mode (SHLHS15). Note that in order to use the fully internal receive impedance termination, a 1:1 transformer

must be used and this bit must be set to 1.

Bits 2 to 0: Channel 15 Receive Sensitivity/Monitor Select [2:0] (C15RSM[2:0]). Bits C15RSM[2:0] are used to

select the receiver sensitivity level and the monitor mode resistive gain. See Table 6-16.

74 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection

RECEIVER

SENSITIVITY

(MAXIMUM

LOSS)

RECEIVER

MONITOR

MODE GAIN

SETTINGS

RECEIVER

MONITOR

MODE

LOSS

DECLARATION

LEVEL

CnRSM[2:0],

T1/ E1 MODE

DISABLED

(dB)

No flat gain

000

001

010

12

18

30

0

15

21

33

39 for T1,46 for

E1

36 for T1, 43

for E1

No flat gain

011

0

Receiver

monitor mode

enabled

Receiver

Max cable loss monitor mode

gain settings

CnRSM[2:0]

—

Flat gain

100

101

110

111

30

22.5

17.5

12

14

20

26

32

37

45.5

47.5

47

RSL1

Register Name:

Receive Signal Level Indicator 1 Register

0Ch

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

C2RSL3

0

6

C2RSL2

0

5

C2RSL1

0

4

C2RSL0

0

3

C1RSL3

0

2

C1RSL2

0

1

C1RSL1

0

C1RSL0

0

Bits 7 to 4: Channel 2 Receive Signal Level [3:0] (C2RSL[3:0]). C2RSL[3:0] bits provide the receive signal

lLevel as shown in Table 6-17.

Bits 3 to 0: Channel 1 Receive Signal Level [3:0] (C1RSL[3:0]). C1RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

2Ch

Register Address (LIUs 9–16):

Bit #

Name

Default

7

6

5

4

3

C9RSL3

0

2

C9RSL2

0

1

C9RSL1

0

C9RSL0

0

C10RSL3 C10RSL2 C10RSL1 C10RSL0

0

Bits 7 to 4: Channel 10 Receive Signal Level [3:0] (C10RSL[3:0]). C10RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

Bits 3 to 0: Channel 9 Receive Signal Level [3:0] (C9RSL[3:0]). C9RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

75 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-17. Receiver Signal Level

RECEIVE LEVEL (dB)

CnRSL3 to

CnRSL0

T1

E1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

>-2.5

-2.5 to -5

-5 to -7.5

-7.5 to -10

-10 to -12.5

-12.5 to -15

-15 to -17.5

-17.5 to -20

-20 to -22.5

-22.5 to -25

-25 to -27.5

-27.5 to -30

-30 to -34

<-34

-2.5 to -5

-5 to -7.5

-7.5 to -10

-10 to -12.5

-12.5 to -15

-15 to -17.5

-17.5 to -20

-20 to -22.5

-22.5 to -25

-25 to -27.5

-27.5 to -30

-30 to -34

-34 to -38

-38 to -43

<-43

—

RSL2

Register Name:

Receive Signal Level Indicator 2 Register

0Dh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

C4RSL3

0

6

C4RSL2

0

5

C4RSL1

0

4

C4RSL0

0

3

C3RSL3

0

2

C3RSL2

0

1

C3RSL1

0

C3RSL0

0

Bits 7 to 4: Channel 4 Receive Signal Level [3:0] (C4RSL[3:0]). C4RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

Bits 3 to 0: Channel 3 Receive Signal Level [3:0] (C3RSL[3:0]). C3RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

2Dh

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

C12RSL3 C12RSL2 C12RSL1 C12RSL0 C11RSL3 C11RSL2 C11RSL1 C11RSL0

0

Bits 7 to 4: Channel 12 Receive Signal Level [3:0] (C12RSL[3:0]). C12RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

Bits 3 to 0: Channel 11 Receive Signal Level [3:0] (C11RSL[3:0]). C11RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

76 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSL3

Register Name:

Receive Signal Level Indicator 3 Register

0Eh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

C6RSL3

0

6

C6RSL2

0

5

C6RSL1

0

4

C6RSL0

0

3

C5RSL3

0

2

C5RSL2

0

1

C5RSL1

0

C5RSL0

0

Bits 7 to 4: Channel 6 Receive Signal Level [3:0] (C6RSL[3:0]). C6RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

Bits 3 to 0: Channel 5 Receive Signal Level [3:0] (C5RSL[3:0]). C5RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

2Eh

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

C14RSL3 C14RSL2 C14RSL1 C14RSL0 C13RSL3 C13RSL2 C13RSL1 C13RSL0

0

Bits 7 to 4: Channel 14 Receive Signal Level [3:0] (C14RSL[3:0]). C14RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

Bits 3 to 0: Channel 13 Receive Signal Level [3:0] (C13RSL[3:0]). C13RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

77 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RSL4

Register Name:

Receive Signal Level Indicator 4 Register

0Fh

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

7

C8RSL3

0

6

C8RSL2

0

5

C8RSL1

0

4

3

C7RSL3

0

2

C7RSL2

0

1

C7RSL1

0

C7RSL0

0

C8RSL0/

CALSTAT

0

Default

Bits 7 to 4: Channel 8 Receive Signal Level [3:0] (C8RSL[3:0]). C8RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

Bit 4: Channel 8 Receive Signal Level 0/Calibration Status (C8RSL0/CALSTAT). When CRIMP is high,

C8RSL0 will be replaced by a real-time status bit for the receive internal termination calibration circuit. If the bit is

low, this indicates that the calibration has not completed. If the bit is high, this indicates the calibration completed

successfully. Normally this bit should go high within 7µs of the low-to-high transition of the CRIMP bit. Receive

termination values will be updated subsequently.

Bits 3 to 0: Channel 7 Receive Signal Level [3:0] (C7RSL[3:0]). C7RSL[3:0] bits provide the receive signal level

as shown in Table 6-17.

2Fh

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

C16RSL3 C16RSL2 C16RSL1 C16RSL0 C15RSL3 C15RSL2 C15RSL1 C15RSL0

0

Bits 7 to 4: Channel 16 Receive Signal Level [3:0] (C16RSL[3:0]). C16RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

Bits 3 to 0: Channel 15 Receive Signal Level [3:0] (C15RSL[3:0]). C15RSL[3:0] bits provide the receive signal

level as shown in Table 6-17.

78 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

BTCR

Register Name:

Bit Error Rate Tester Control Register

10h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

BTS2

0

6

BTS1

0

5

BTS0

0

4

—

0

3

—

0

2

—

0

1

—

0

BERTE

0

Note: This register enables the LIU1-LIU8 BERT. The BERT can only connect to one LIU at a time. The LIU1-LIU8 BERT operates

independently of the LIU9-LIU16 BERT.

Bits 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]). These bits BTS[2:0] select the LIU that the BERT

applies to (see Table 6-18). This is only applicable if the BERTE bit is set.

Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2µs have past, the BERT will be enabled.

The BERT register set should be written and read to only after being enabled. The BERT is only active for one LIU

at a time selected by BTS[2:0]. If the BERT is enabled on the transmit (line) side, the BERT data will be

automatically B8ZS/HDB3 encoded before it is transmitted.

30h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BTS2

0

6

BTS1

0

5

BTS0

0

4

—

0

3

—

0

2

—

0

1

—

0

BERTE

0

Note: This register enables the LIU9-LIU16 BERT. The BERT can only connect to one LIU at a time. The LIU9-LIU16 BERT operates

independently of the LIU1–LIU8 BERT.

Bits 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]) These bits BTS[2:0] select the LIU that the BERT

applies too (see Table 6-19). This is only applicable if the BERTE bit is set.

Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2µs have past, the BERT will be enabled.

The BERT register set should be written and read to only after being enabled. The BERT is only active for one LIU

at a time selected by BTS[2:0]. If the BERT is enabled on the transmit (line) side, the BERT data will be

automatically B8ZS/HDB3 encoded before it is transmitted.

79 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8

REGISTER

ADDRESS

10h

CHANNEL BERT

APPLIES TO

Channel 1

BTS2

BTS1

BTS0

0

1

0

1

0

1

0

1

0

1

0

1

10h

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16

REGISTER

ADDRESS

30h

CHANNEL BERT

APPLIES TO

Channel 9

BTS2

BTS1

BTS0

0

1

0

1

0

1

0

1

0

1

0

1

30h

Channel 10

Channel 11

Channel 12

Channel 13

Channel 14

Channel 15

Channel 16

BEIR

Register Name:

BPV Error Insertion Register

11h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

BEIR8

0

6

BEIR7

0

5

BEIR6

0

4

BEIR5

0

3

BEIR4

0

2

BEIR3

0

1

BEIR2

0

BEIR1

0

31h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BEIR16

0

6

BEIR15

0

5

BEIR14

0

4

BEIR13

0

3

BEIR12

0

2

BEIR11

0

1

BEIR10

0

BEIR9

0

Bits 7 to 0: BPV Error Insertion Register n (BEIRn). A 0-to-1 transition on this bit will cause a single bipolar

violation (BPV) to be inserted into the transmit data stream Channel n. This bit must be cleared and set again for a

subsequent error to be inserted.

80 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LVDS

Register Name:

Line Violation Detect Status Register

12h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

LVDS8

0

6

LVDS7

0

5

LVDS6

0

4

LVDS5

0

3

LVDS4

0

2

LVDS3

0

1

LVDS2

0

LVDS1

0

32h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

LVDS16

0

6

LVDS15

0

5

LVDS14

0

4

LVDS13

0

3

LVDS12

0

2

LVDS11

0

1

LVDS10

0

LVDS9

0

Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, a code violation, or excessive zeros will

cause the associated LVDSn bit to latch. This bit will be cleared on a read operation. The LVDS register captures

the first violation within a three clock period window. If a second violation occurs after the first violation within the

three clock period window, then the second violation will not be latched even if a read to the LVDS register was

performed. Excessive zeros need to be enabled by the EZDE register for detection by this register. Code violations

are only relevant when in HDB3 mode and can be disabled for detection by this register by setting the CVDEB

register.

RCLKI

Register Name:

Receive Clock Invert Register

13h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RCLKI8

0

6

RCLKI7

0

5

RCLKI6

0

4

RCLKI5

0

3

RCLKI4

0

2

RCLKI3

0

1

RCLKI2

0

RCLKI1

0

33h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

RCLKI16

0

6

5

RCLKI14

0

4

RCLKI13

0

3

RCLKI12

0

2

RCLKI11

0

1

RCLKI10

0

RCLKI9

0

RCLKI15

0

Bit 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLK for Channel n is inverted. This aligns

RPOS/RNEG on the falling edge of RCLK. When reset or default RPOS/RNEG is aligned on the rising edge of

RCLK.

81 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TCLKI

Register Name:

Transmit Clock Invert Register

14h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

TCLKI8

0

6

TCLKI7

0

5

TCLKI6

0

4

TCLKI5

0

3

TCLKI4

0

2

TCLKI3

0

1

TCLKI2

0

TCLKI1

0

34h

Register Address (LIUs 9–16):

Bit #

Name

Default

7

TCLKI16

0

6

5

TCLKI14

0

4

TCLKI13

0

3

TCLKI12

0

2

TCLKI11

0

1

TCLKI10

0

TCLKI9

0

TCLKI15

0

Bits 7 to 0: Transmit Clock Invert n (TCLKIn). When this bit is set the expected TCLK for Channel n is inverted.

TPOS/TNEG should be aligned on the falling edge of TCLK. When reset or default TPOS/TNEG should be aligned

on the rising edge of TCLK.

82 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

CCR

Register Name:

Clock Control Register

15h

Register Description:

Register Address:

Bit #

Name

Default

7

PCLKS2

0

6

PCLKS1

0

5

PCLKS0

0

4

TECLKS

0

3

CLKA3

0

2

CLKA2

0

1

CLKA1

0

CLKA0

0

Bits 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the

PLL. If an LOS is detect for the channel that RCLK is recovered from, the PLL will switch to MCLK until the LOS is

cleared. When the LOS is cleared RCLK will be used again. See Table 6-20 for RCLK selection. MC.PCLKI[1:0]

must be set to ‘01’ or ‘10’ in order for these settings to take effect.

Table 6-20. PLL Clock Select

PLL CLOCK

SELECTED

PLL CLOCK

SELECTED

PCLKS[2:0]

MC.PCLKI[1:0]=01 MC.PCLKI[1:0]=10

000

001

010

011

100

101

110

111

RCLK1

RCLK2

RCLK3

RCLK4

RCLK5

RCLK6

RCLK7

RCLK8

RCLK9

RCLK10

RCLK11

RCLK12

RCLK13

RCLK14

RCLK15

RCLK16

Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is

reset the T1/E1 clock rate is 1.544MHz

Bits 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See Table 6-21 for

available frequencies. For best jitter performance, select MCLK as the source for CLKA and input a 2.048MHz

MCLK.

Table 6-21. Clock A Select

CLKA[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CLKA (Hz)

2.048M

4.096M

8.192M

16.384M

1.544M

3.088M

6.176M

12.352M

1.536M

3.072M

6.144M

12.288M

32k

64k

128k

256k

83 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RDULR

Register Name:

RCLK Disable Upon LOS Register

16h

Register Description:

Register Address (LIUs 1–8):

Bit #

Name

Default

7

RDULR8

0

6

RDULR7

0

5

RDULR6

0

4

RDULR5

0

3

RDULR4

0

2

RDULR3

0

1

RDULR2

0

RDULR1

0

36h

Register Address (LIUs 9–16):

Bit #

7

6

5

4

3

2

1

0

Name

Default

RDULR16 RDULR15 RDULR14 RDULR13 RDULR12 RDULR11 RDULR10 RDULR9

0

Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for Channel n is

disabled upon a loss of signal and set as a low output. When reset or default RCLK will switch to MCLK upon a

loss of signal within 10ms.

GISC

Register Name:

Global Interrupt Status Control Register

1Eh

Register Description:

Register Address:

Bit #

Name

Default

7

—

0

6

—

0

5

—

0

4

—

0

3

—

0

2

—

0

1

INTM

0

CWE

0

Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INT pin. The INT pin always drives low

when active.

0 = Pin is high impedance when not active.

1 = Pin drives high when not active.

Bit 0: Clear On Write Enable (CWE). When this bit is set the clear on write is enabled for all the latched interrupt

status registers. The host processor must write a 1 to the latched interrupt status register bit position before the

particular bit will be cleared. Default for all the latched interrupt status registers is to clear on a read.

84 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

6.1.4 BERT Registers

BCR

Register Name:

BERT Control Register

Register Description:

00h

20h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

PMUM

0

6

LPMU

0

5

RNPL

0

4

RPIC

0

3

MPR

0

2

APRD

0

1

TNPL

0

TPIC

0

Bit 7: Performance Monitoring Update Mode (PMUM). When 0, a performance monitoring update is initiated by

the LPMU register bit. When 1, a performance monitoring update is initiated by the receive performance monitoring

update signal (RPMU). Note: If RPMU or LPMU is one, changing the state of this bit may cause a performance

monitoring update to occur.

Bit 6: Local Performance Monitoring Update (LPMU). This bit causes a performance monitoring update to be

initiated if local performance monitoring update is enabled (PMUM = 0). A 0-to-1 transition causes the performance

monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance

monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit

goes high, an update might not be performed. This bit has no affect when PMUM = 1.

Bit 5: Receive New Pattern Load (RNPL). A 0-to-1 transition of this bit will cause the programmed test pattern

(QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit must be

changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the receive

pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note: QRSS, PTS,

PLF[4:0], PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four RXCK

clock cycles after this bit transitions from 0 to 1.

Bit 4: Receive Pattern Inversion Control (RPIC). When 0, the receive incoming data stream is not altered. When

1, the receive incoming data stream is inverted.

Bit 3: Manual Pattern Resynchronization (MPR). A zero to one transition of this bit will cause the receive pattern

generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another

resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator out of the

“Sync” state.

Bit 2: Automatic Pattern Resynchronization Disable (APRD). When 0, the receive pattern generator will

automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the

incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern

generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is

prevented by not allowing the receive pattern generator to automatically exit the “Sync” state.

Bit 1: Transmit New Pattern Load (TNPL). A 0-to-1 transition of this bit will cause the programmed test pattern

(QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit must be

changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0], PTF[4:0], and

BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this bit

transitions from 0 to 1.

Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered.

When 1, the transmit outgoing data stream is inverted.

85 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

BPCR1

Register Name:

BERT Pattern Configuration Register 1

Register Description:

02h

22h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

QRSS

0

5

PTS

0

4

PLF4

0

3

PLF3

0

2

PLF2

0

1

PLF1

0

PLF0

0

Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and

PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a

generating polynomial of x²⁰+ x¹⁷+ 1. The output of the pattern generator will be forced to one if the next fourteen

output bits are all zero.

Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive

pattern.

Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These five bits control the “length” feedback of the pattern

generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,

the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.

BPCR2

Register Name:

BERT Pattern Configuration Register 2

Register Description:

03h

23h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

—

0

5

—

0

4

PTF4

0

3

PTF3

0

2

PTF2

0

1

PTF1

0

PTF0

0

Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern

generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored

when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.

86 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

BSPR1

Register Name:

BERT Seed/Pattern Register 1

Register Description:

04h

24h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BSP7

0

6

BSP6

0

5

BSP5

0

4

BSP4

0

3

BSP3

0

2

BSP2

0

1

BSP1

0

BSP0

0

BSPR2

Register Name:

BERT Seed/Pattern Register 2

Register Description:

05h

25h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BSP15

0

6

BSP14

0

5

BSP13

0

4

BSP12

0

3

BSP11

0

2

BSP10

0

1

BSP9

0

BSP8

0

BSPR3

Register Name:

BERT Seed/Pattern Register 3

Register Description:

06h

26h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BSP23

0

6

BSP22

0

5

BSP21

0

4

BSP20

0

3

BSP19

0

2

BSP18

0

1

BSP17

0

BSP16

0

BSPR4

Register Name:

BERT Seed/Pattern Register 4

Register Description:

07h

27h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BSP31

0

6

BSP30

0

5

BSP29

0

4

BSP28

0

3

BSP27

0

2

BSP26

0

1

BSP25

0

BSP24

0

Bits 31 to 0: BERT Seed/Pattern (BSP[31:0]). These 32 bits are the programmable seed for a transmit PRBS

pattern, or the programmable pattern for a transmit or receive repetitive pattern. BSP(31) will be the first bit output

on the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the

receive side for a 32-bit repetitive pattern.

87 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TEICR

Register Name:

Transmit Error Insertion Control Register

Register Description:

08h

28h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

—

0

5

TEIR2

0

4

TEIR1

0

3

TEIR0

0

2

BEI

0

1

TSEI

0

MEIMS

0

Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are

inserted in the output data stream. One out of every 10ⁿbits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value

of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A

TEIR[2:0] value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to

with a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process,

the new error rate will be started after the next error is inserted.

Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error

insertion is enabled.

Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if

manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a

single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If

MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be

inserted.

Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.

When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is

one, changing the state of this bit may cause a bit error to be inserted.

BSR

Register Name:

BERT Status Register

Register Description:

0Ch

2Ch

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

—

0

5

—

0

4

—

0

3

PMS

0

2

—

0

1

BEC

0

OOS

0

Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance

monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is

asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low.

Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more.

Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming

pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.

88 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

BSRL

Register Name:

BERT Status Register Latched Register

Register Description:

0Eh

2Eh

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

—

0

5

—

0

4

—

0

3

PMSL

0

2

BEL

0

1

BECL

0

OOSL

0

Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from

0 to 1. A read operation clears this bit.

Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected. A read operation clears this bit.

Bit 1: Bit Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1. A read operation

clears this bit.

Bit 0: Out Of Synchronization Latched (OOSL). This bit is set when the OOS bit changes state. A read operation

clears this bit.

BSRIE

Register Name:

BERT Status Register Interrupt Enable Register

Register Description:

10h

30h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

—

0

6

—

0

5

—

0

4

—

0

3

PMSIE

0

2

BEIE

0

1

BECIE

0

OOSIE

0

Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the

PMSL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 2: Bit Error Interrupt Enable (BEIE). This bit enables an interrupt if the BEL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set.

0 = interrupt disabled

1 = interrupt enabled

89 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RBECR1

Register Name:

Receive BERT Bit Error Count Register 1

Register Description:

14h

34h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BEC7

0

6

BEC6

0

5

BEC5

0

4

BEC4

0

3

BEC3

0

2

BEC2

0

1

BEC1

0

BEC0

0

RBECR2

Register Name:

Receive BERT Bit Error Count Register 2

Register Description:

15h

35h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BEC15

0

6

BEC14

0

5

BEC13

0

4

BEC12

0

3

BEC11

0

2

BEC10

0

1

BEC9

0

BEC8

0

RBECR3

Register Name:

Receive BERT Bit Error Count Register 3

Register Description:

16h

36h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BEC23

0

6

BEC22

0

5

BEC21

0

4

BEC20

0

3

BEC19

0

2

BEC18

0

1

BEC17

0

BEC16

0

Bits 23 to 0: BERT Bit Error Count (BEC[23:0]). These 24 bits indicate the number of bit errors detected in the

incoming data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit

error counter will not incremented when an OOS condition exists.

90 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

RBCR1

Register Name:

Receive BERT Bit Count Register 1

Register Description:

18h

38h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BC7

0

6

BC6

0

5

BC5

0

4

BC4

0

3

BC3

0

2

BC2

0

1

BC1

0

BC0

0

RBCR2

Register Name:

Receive BERT Bit Count Register 2

Register Description:

19h

39h

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

15

BC15

0

14

BC14

0

13

BC13

0

12

BC12

0

11

BC11

0

10

BC10

0

9

BC9

0

8

BC8

0

RBCR3

Register Name:

Receive BERT Bit Count Register 3

Register Description:

1Ah

3Ah

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

7

BC23

0

6

BC22

0

5

BC21

0

4

BC20

0

3

BC19

0

2

BC18

0

1

BC17

0

BC16

0

RBCR4

Register Name:

Receive BERT Bit Count Register 4

Register Description:

1Bh

3Bh

Register Address (LIUs 1–8):

Register Address (LIUs 9–16):

Bit #

Name

Default

15

BC31

0

14

BC30

0

13

BC29

0

12

BC28

0

11

BC27

0

10

BC26

0

9

BC25

0

8

BC24

0

Bits 31 to 0: BERT Bit Count (BC[31:0]). These 32 bits indicate the number of bits in the incoming data stream.

This count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not

incremented when an OOS condition exists.

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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

The DS26334 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26334 contains the

following as required by IEEE 1149.1 Standard Test-Access Port and Boundary-Scan Architecture:

Test Access Port (TAP)

TAP Controller

Instruction Register

Bypass Register

Boundary Scan Register

Device Identification Register

Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE

1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: TRSTB, TCLK,

TMS, TDI, and TDO. See the pin descriptions for details. For the latest BSDL files

go to www.maxim-ic.com/tools/bsdl/ and search for DS26334.

Figure 7-1. JTAG Functional Block Diagram

BOUNDARY SCAN

REGISTER

INDENTIFICATION

REGISTER

BYPASS

REGISTER

MUX

INSTRUCTION

REGISTER

SELECT

TEST ACCESS PORT

OUTPUT ENABLE

CONTROLLER

+V

10kΩ

TDI

TMS

TRSTB

TDO

TCLK

92 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

7.1 TAP Controller State Machine

The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCLK. The

state diagram is shown in Figure 7-2.

7.1.1 Test-Logic-Reset

Upon power-up, the TAP controller will be in the Test-Logic-Reset state. The instruction register will contain the

IDCODE instruction. All system logic of the device will operate normally. This state is automatically entered during

power-up. This state is entered from any state if the TMS is held high for at least 5 clocks.

7.1.2 Run-Test-Idle

The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test

registers will remain idle. The controller remains in this state when TMS is held low. When the TMS is high and

rising edge of TCLK is applied the controller moves to the Select-DR-Scan state.

7.1.3 Select-DR-Scan

All test registers retain their previous state. With TMS LOW, a rising edge of TCLK moves the controller into the

Capture-DR state and will initiate a scan sequence. TMS HIGH during a rising edge on TCLK moves the controller

to the Select-IR-Scan state.

7.1.4 Capture-DR

Data can be parallel-loaded into the test-data registers if the current instruction is EXTEST or SAMPLE/PRELOAD.

If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test

register will remain at its current value. On the rising edge of TCLK, the controller will go to the shift-DR state if

TMS is LOW or it will go to the exit1-DR state if TMS is HIGH.

7.1.5 Shift-DR

The test-data register selected by the current instruction will be connected between TDI and TDO and will shift data

one stage towards its serial output on each rising edge of TCLK. If a test register selected by the current instruction

is not placed in the serial path, it will maintain its previous state. When the TAP controller is in this state and a

rising edge of TCLK is applied, the controller enters the Exit1-DR state if TMS is high or remains in Shift-DR state if

TMS is low.

7.1.6 Exit1-DR

While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the

scanning process, if TMS is HIGH. A rising edge on TCLK with TMS LOW will put the controller in the Pause-DR

state.

7.1.7 Pause-DR

Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will

retain their previous state. The controller will remain in this state while TMS is LOW. A rising edge on TCLK with

TMS HIGH will put the controller in the Exit2-DR state.

7.1.8 Exit2-DR

A rising edge on TCLK with TMS HIGH while in this state will put the controller in the Update-DR state and

terminate the scanning process. A rising edge on TCLK with TMS LOW will enter the Shift-DR state.

7.1.9 Update-DR

A falling edge on TCLK while in the Update-DR state will latch the data from the shift register path of the test

registers into the data output latches. This prevents changes at the parallel output due to changes in the shift

register.

93 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

7.1.10 Select-IR-Scan

All test registers retain their previous state. The instruction register will remain unchanged during this state. With

TMS LOW, a rising edge on TCLK moves the controller into the Capture-IR state and will initiate a scan sequence

for the instruction register. TMS HIGH during a rising edge on TCLK puts the controller back into the Test-Logic-

Reset state.

7.1.11 Capture-IR

The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is

loaded on the rising edge of TCLK. If TMS is HIGH on the rising edge of TCLK, the controller will enter the Exit1-IR

state. If TMS is LOW on the rising edge of TCLK, the controller will enter the Shift-IR state.

7.1.12 Shift-IR

In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one

stage for every rising edge of TCLK towards the serial output. The parallel registers as well as all test registers

remain at their previous states. A rising edge on TCLK with TMS HIGH will move the controller to the Exit1-IR

state. A rising edge on TCLK with TMS LOW will keep the controller in the Shift-IR state while moving data one

stage thorough the instruction shift register.

7.1.13 Exit1-IR

A rising edge on TCLK with TMS LOW will put the controller in the pause-IR state. If TMS is HIGH on the rising

edge of TCLK, the controller will enter the update-IR state and terminate the scanning process.

7.1.14 Pause-IR

Shifting of the instruction shift register is halted temporarily. With TMS HIGH, a rising edge on TCLK will put the

controller in the Exit2-IR state. The controller will remain in the Pause-IR state if TMS is LOW during a rising edge

on TCLK.

7.1.15 Exit2-IR

A rising edge on TCLK with TMS HIGH will put the controller in the Update-IR state. The controller will loop back to

Shift-IR if TMS is LOW during a rising edge of TCLK in this state.

7.1.16 Update-IR

The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of

TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising

edge on TCLK with TMS LOW will put the controller in the Run-Test-Idle state. With TMS HIGH, the controller will

enter the Select-DR-Scan state.

94 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 7-2. TAP Controller State Diagram

Test Logic

Reset

1

0

1

Run Test/

Idle

Select

DR-Scan

IR-Scan

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

0

1

Exit DR

Exit IR

0

Pause DR

Pause IR

0

1

0

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

95 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

7.2 Instruction Register

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the

TAP controller enters the Shift-IR state, the instruction shift register will be connected between TDI and TDO. While

in the Shift-IR state, a rising edge on TCLK with TMS LOW will shift the data one stage towards the serial output at

TDO. A rising edge on TCLK in the Exit1-IR state or the Exit2-IR state with TMS HIGH will move the controller to

the Update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the

instruction parallel output. Instructions supported by the DS26334 and its respective operational binary codes are

shown in Table 7-1.

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture

INSTRUCTION

SELECTED REGISTER

INSTRUCTION CODES

EXTEST

HIGHZ

CLAMP

Boundary Scan

Bypass

000

010

011

100

110

111

Bypass

SAMPLE/PRELOAD

IDCODE

Boundary Scan

Device Identification

Bypass

BYPASS

7.2.1 EXTEST

This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction

register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output

pins will be driven. The Boundary Scan Register will be connected between TDI and TDO. The Capture-DR will

sample all digital inputs into the Boundary Scan Register.

7.2.2 HIGHZ

All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected

between TDI and TDO.

7.2.3 CLAMP

All digital outputs of the device will output data from the boundary scan parallel output while connecting the Bypass

Register between TDI and TDO. The outputs will not change during the CLAMP instruction.

7.2.4 SAMPLE/PRELOAD

This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the

device can be sampled at the Boundary Scan Register without interfering with the normal operation of the device

by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the Boundary Scan

Register via TDI using the Shift-DR state.

7.2.5 IDCODE

When the IDCODE instruction is latched into the Parallel Instruction Register, the Identification Test Register is

selected. The device identification code will be loaded into the Identification Register on the rising edge of TCLK

following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via TDO.

During Test-Logic-Reset, the identification code is forced into the Instruction Register’s parallel output. The ID code

will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number

of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 7-2. Table 7-3 lists the

device ID code for the DS26334.

7.2.6 BYPASS

When the BYPASS instruction is latched into the Parallel Instruction Register, TDI connects to TDO through the

one-bit test Bypass Register. This allows data to pass from TDI to TDO not affecting the device’s normal operation.

96 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 7-2. ID Code Structure

MSB

LSB

Version

Contact Factory

4 bits

Device ID

16 bits

JEDEC

1

00010100001

1

Table 7-3. Device ID Codes

DEVICE

16-BIT ID

DS26334

003Ch

7.3 Test Registers

IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An

optional test register has been included with the DS26334 design. This test register is the Identification Register

and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.

7.3.1 Boundary Scan Register

This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells

and is n bits in length.

7.3.2 Bypass Register

This register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a

short path between TDI and TDO.

7.3.3 Identification Register

The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See Table

7-2 and Table 7-3 for more information about bit usage.

97 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

8 DC ELECTRICAL CHARACTERIZATION

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Lead with Respect to V_SS(except V_DD)…………………………………………….-0.3V to +5.5V

Supply Voltage (V_DD) Range with Respect to V_SS…..………………………………………………………-0.3V to +3.63V

Operating Temperature Range for DS26334G………………………………………………………………..0°C to +70°C

Operating Temperature Range for DS26334GN………………………………………………..…………..-40°C to +85°C

Storage Temperature…………………………………………………………………………………………-55°C to +125°C

Soldering Temperature (reflow)

Lead(Pb)-free........................................................................................................................................+260°C

Containing lead(Pb)...............................................................................................................................+240°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

8.1 DC Pin Logic Levels

Table 8-1. Recommended DC Operating Conditions

(T_A= -40°C to +85°C for DS26334GN.)

PARAMETER

SYMBOL

V_IH

MIN

2.0

TYP

MAX UNITS

NOTES

Logic 1

Logic 0

Supply

5.5

V

V_IL

-0.3

+0.8

3.465

V_DD

3.135

3.3

Table 8-2. Pin Capacitance

(T_A= +25°C)

PARAMETER

SYMBOL

C_IN

MIN

TYP

7

MAX UNITS

NOTES

Input Capacitance

Output Capacitance

pF

C_OUT

7

8.2 Supply Current and Output Voltage

Table 8-3. DC Characteristics

(V_DD= 3.135 to 3.465V, T_A= -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL

Supply Current at 3.465V

MIN

TYP

MAX

UNITS

NOTES

I_DD

1100

mA

2, 3

Supply Current at 3.3V

Input Leakage

500

I_IL

-10.0

2.4

+10.0

µA

V

Tri-State Output Leakage

Output Voltage (I_o= –4.0mA)

Output Voltage (I_o= +4.0mA)

I_OL

V_OH

V_OL

0.4

V

Note 1:

Note 2:

Note 3:

Specifications to -40°C are guaranteed by design (GBD) and not production tested.

RCLK1-n = TCLK1-n = 1.544MHz.

Power dissipation with all ports active, TTIP and TRING driving a 25Ω load, for an all-ones data density.

98 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

9 AC TIMING CHARACTERISTICS

9.1 Line Interface Characteristics

Table 9-1. Transmitter Characteristics

PARAMETER

E1 75Ω

SYMBOL

MIN

2.14

2.7

TYP

2.37

3.0

MAX

2.6

UNITS

NOTES

3.3

E1 120Ω

T1 100Ω

T1 110Ω

Output Mark

Amplitude

V_M

V

2.4

3.0

3.6

2.4

3.0

3.6

Output Zero Amplitude

V_S

-0.3

-1

+0.3

+1

V

1

Transmit Amplitude Variation with

Supply

%

Single-Rail

Transmit Path Delay

Dual-Rail

8

3

UI

Table 9-2. Receiver Characteristics

PARAMETER

Cable Attenuation

SYMBOL

Attn

MIN

TYP

MAX

UNITS

dB

NOTES

12

Analog Loss-of-Signal Threshold

Hysteresis Short-Haul Mode

200

100

mV

1

mV

Analog Loss-of-Signal Threshold

Long-Haul Mode

30

mV

Hysteresis Long-Haul Mode

40

192

2048

24

Allowable Zeros Before Loss

2

3

192

Allowable Ones Before Loss

192

Single-Rail

Dual-Rail

8

3

Receive Path Delay

UI

Note 1:

Note 2:

Measured at the RRING and RTIP pins.

192 zeros for T1 and T1.231 Specification Compliance; 192 zeros for E1 and G.775 Specification

Compliance; 2048 zeros for ETS 300 233 compliance.

Note 3:

24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETS 300 233.

99 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

9.2 Parallel Host Interface Timing Characteristics

The following tables show the AC characteristics for the external bus interface.

Table 9-3. Intel Read Mode Characteristics

(V_DD= 3.3V ±5%, T_J= -40°C to +125°C.) (Note 1) (See Figure 9-1 and Figure 9-2.)

SIGNAL

NAME(S)

SYMBOL

DESCRIPTION

MIN TYP MAX UNITS NOTES

RDB

CSB

t1

t2

Pulse width if not using RDYB

Setup time to RDB

40

0

ns

2

CSB

t3

Hold time from RDB

0

AD[7:0]

A[5:0]

t4

Setup time to ALE

2

t5

Hold time from RDB

0

D[7:0], AD[7:0]

RDYB

t6

Delay time RDB, CSB active

Deassert delay from RDB, CSB inactive

Enable delay time from CSB active

Disable delay time from the CSB inactive

Hold time from ALE

40

20

15

t7

2

t8

RDYB

t9

AD[7:0]

ALE

t10

t11

t12

t13

t14

t15

3

5

Pulse width

D[7:0]

Output delay from ALE Latched

Setup time to RDB

40

35

A[5:0]

10

0

RDYB

Delay time from RDB

RDYB

Active output delay time from RDB

10

Note 1:

Note 2:

The timing parameters in this table are guaranteed by design (GBD).

The input/output timing reference level for all signals is V_DD/2.

100 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-1. Intel Nonmuxed Read Cycle

t3

t2

CSB

RDB

t1

ALE=(1)

A[5:0]

t5

t13

ADDRESS

t6

t7

D[7:0]

RDYB

DATA OUT

t8

t9

t14

t15

101 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-2. Intel Mux Read Cycle

t3

t2

CSB

t1

RDB

t11

t12

t6

ALE

t4

t10

t7

AD[7:0]

DATA OUT

ADDRESS

t9

t8

t14

RDYB

t15

102 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 9-4. Intel Write Cycle Characteristics

(V_DD= 3.3V ±5%, T_J= -40°C to +125°C.) (Note 1) (See Figure 9-3 and Figure 9-4.)

SIGNAL

NAME(S)

SYMBOL

DESCRIPTION

MIN TYP MAX UNITS NOTES

WRB

t1

t2

Pulse width

40

0

ns

2

CSB

Setup time to WRB

t3

Hold time to WRB

0

AD[7:0]

A[5:0]

t4

Setup time to ALE

2

t5

Hold time from WRB

0

D[7:0], AD[7:0]

RDYB

t6

Input setup time to WRB

Input hold time to WRB

Enable delay from CSB active

Delay time from WRB active

Delay time from WRB inactive

Disable delay time from CSB inactive

Pulse width

10

5

t7

t8

20

15

RDYB

t9

10

0

RDYB

t10

t11

t12

t13

t14

RDYB

ALE

5

3

AD[7:0]

A[5:0]

Hold time from ALE inactive

Valid address to WRB inactive

35

Note 1:

Note 2:

The timing parameters in this table are guaranteed by design (GBD).

The input/output timing reference level for all signals is V_DD/2.

103 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-3. Intel Nonmux Write Cycle

t3

t2

CSB

t1

WRB

ALE=(1)

A[5:0]

t14

t5

ADDRESS

t6

t7

D[7:0]

RDYB

WRITE DATA

t11

t10

t8

t9

104 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-4. Intel Mux Write Cycle

t3

t2

CSB

t1

WRB

t12

ALE

t13

t4

t6

t7

AD[7:0]

WRITE DATA

ADDRESS

t11

t8

t10

RDYB

t9

105 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 9-5. Motorola Read Cycle Characteristics

(V_DD= 3.3V ±5%, T_J= -40°C to +125°C.) (Note 1) (See Figure 9-5 and Figure 9-6.)

SIGNAL

NAME(S)

SYMBOL

DESCRIPTION

MIN TYP MAX UNITS NOTES

DSB

CSB

t1

t2

Pulse width

40

0

ns

2

Setup time to DSB active

CSB

t3

Hold time from DSB inactive

0

RWB

t4

Setup time to DSB active

0

RWB

t5

Hold time from DSB inactive

0

AD[7:0]

AD[7:0], D[7:0]

ACKB

t6

Setup time to ASB active

2

t7

Hold time to ASB inactive

3

t8

Output delay time from DSB active

Output valid delay time from DSB inactive

Output delay time from CSB inactive

Output delay time from DSB inactive

Enable output delay time from DSB active

Output delay time from DSB active

Hold time from DSB inactive

40

20

15

t10

t11

t12

t13

t14

t15

t16

2

0

ACKB

20

35

ACKB

10

0

A[5:0]

Setup time to DSB active

10

Note 1:

Note 2:

The timing parameters in this table are guaranteed by design (GBD).

The input/output timing reference level for all signals is V_DD/2.

106 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-5. Motorola Nonmux Read Cycle

t3

t2

CSB

t4

t5

RWB

DSB

t1

ASB=(1)

A[5:0]

t16

t15

ADDRESS

t8

t10

D[7:0]

ACKB

DATA OUT

t11

t12

t13

t14

107 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-6. Motorola Mux Read Cycle

t3

t2

CSB

t4

t5

RWB

t1

DSB

ASB

t14

t7

t6

t8

t10

AD[7:0]

ACKB

ADDRESS

DATA OUT

t11

t12

t13

t14

108 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 9-6. Motorola Write Cycle Characteristics

(V_DD= 3.3V ±5%, T_J= -40°C to +125°C.) (Note 1) (See Figure 9-7 and Figure 9-8.)

SIGNAL

NAME(S)

SYMBOL

DESCRIPTION

MIN TYP MAX UNITS NOTES

DSB

t1

t2

Pulse width

35

0

ns

2

CSB

Setup time to DSB active

t3

Hold time from DSB inactive

Setup time to DSB active

0

RWB

t4

0

RWB

t5

Hold time to DSB inactive

0

AD[7:0]

AD[7:0], D[7:0]

A[5:0]

t6

Setup time to ASB active

2

t7

Hold time from ASB active

Setup time to DSB inactive

Hold time from DSB inactive

Setup time to DSB active

3

t8

10

5

t9

t10

t11

t12

t13

t14

t15

10

ACKB

Output delay from CSB inactive

Output delay from DSB inactive

Output enable delay time from DSB active

Output delay time from DSB active

Hold time from DSB

15

20

ACKB

0

ACKB

10

0

A[5:0]

Note 1:

Note 2:

The timing parameters in this table are guaranteed by design (GBD).

The input/output timing reference level for all signals is V_DD/2.

109 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-7. Motorola Nonmux Write Cycle

t3

t2

CSB

t4

t5

RWB

DSB

t1

ASB=(1)

A[5:0]

t10

t15

ADDRESS

t8

t9

D[7:0]

ACKB

WRITE DATA

t11

t12

t13

t14

110 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 9-8. Motorola Mux Write Cycle

t3

t2

CSB

t4

t5

RWB

t1

DSB

ASB

t13

t6

t7

t9

t8

AD[7:0]

ACKB

WRITE DATA

ADDRESS

t12

t11

t13

t14

111 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

9.3 Serial Port

Table 9-7. Serial Port Timing Characteristics

(See Figure 9-9, Figure 9-10, and Figure 9-11.)

PARAMETER

SYMBOL

MIN

TYP MAX

UNITS

NOTES

SCLK High Time

SCLK Low Time

t1

t2

t3

t4

t5

t6

t7

25

50

5

ns

Active CSB to SCLK Setup Time

Last SCLK to CSB Inactive Time

CSB Idle Time

SDI to SCLK Setup Time

SCLK to SDI Hold Time

5

SCLK Falling Edge to SDO

High Impedance (CLKE = 0); CSB Rising to SDO

High Impedance (CLKE = 1)

t8

100

ns

Figure 9-9. Serial Bus Timing Write Operation

t5

CSB

t3

t4

SCLK

t1

t2

t6

LSB

t7

SDI

MSB

Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CSB

t4

SDO

t8

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CSB

t4

t8

SDO

112 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

9.4 System Timing

Table 9-8. Transmitter System Timing

(See Figure 9-12.)

PARAMETER

SYMBOL

MIN

TYP MAX UNITS NOTES

TPOS, TNEG Setup Time with Respect to TCLK

Falling Edge

t1

40

ns

TPOS, TNEG Hold Time with Respect to TCLK

Falling Edge

t2

40

ns

TCLK Pulse-Width High

TCLK Pulse-Width Low

t3

t4

75

ns

488

TCLK Period

t5

ns

648

TCLK Rise Time

TCLK Fall Time

t6

t7

25

ns

Figure 9-12. Transmitter Systems Timing

t5

t4

t3

t7

t6

TCLK

t1

TPOS, TNEG

t2

113 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 9-9. Receiver System Timing

(See Figure 9-13.)

PARAMETER

SYMBOL

MIN

TYP

MAX

50

UNITS NOTES

Delay RCLK to RPOS, RNEG Valid

Delay RCLK to CV Valid in Single-Rail Mode

RCLK Pulse-Width High

t1

t2

t3

t4

ns

50

200

RCLK Pulse-Width Low

488

648

RCLK Period

t5

ns

Figure 9-13. Receiver Systems Timing

RCLK¹

t3

t4

RCLK²

t1

t5

RPOS,RNEG

t2

CV

BPV/

EXZ/

CV

EXZ/

CV

Notes:

1) CLKE = 1.

2) CLKE = 0.

114 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

9.5 JTAG Timing

Table 9-10. JTAG Timing Characteristics

(See Figure 9-14.)

PARAMETER

SYMBOL

MIN

100

25

TYP

MAX

UNITS

ns

NOTES

TCK Period

t1

t2

t3

t4

TMS and TDI Setup to TCK

TMS and TDI Hold to TCK

TCK to TDO Hold

ns

25

ns

50

ns

Figure 9-14. JTAG Timing

t1

TCK

t3

t2

TMS

TDI

t4

TDO

115 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

10 PIN CONFIGURATION

Figure 10-1. 256-Ball TE-CSBGA

1

2

3

MODESEL

MOTEL

TNEG1

RCLK1

RNEG1

RPOS2

A2

4

RTIP16

RRING16

A4

5

6

7

8

9

10

VDDT14

LOS13

RPOS14

GNDT13

RNEG13

LOS16

TNEG4

AVSS

11

12

13

VDDT13

TMS

14

RTIP14

15

TDO

16

RTIP13

RRING13

AVDD

RTIP1

AVDD

RTIP2

VDDT1

TTIP1

TTIP2

VDDT2

RTIP3

VDDT3

TTIP3

TTIP4

VDDT4

RTIP4

AVDD

RRING5

RTIP5

RRING1

AVSS

VDDT16

RSTB

TTIP16

TRING16

TNEG15

GNDT16

RCLK16

TPOS1

RCLK2

TCLK4

TPOS3

TPOS4

D0

TTIP15

TRING15

RNEG15

INTB

VDDT15

LOS14

RPOS15

GNDT15

RCLK13

RCLK15

TNEG13

DVDD

RTIP15

RRING15

RNEG14

GNDT14

RCLK14

TPOS13

TCLK3

TTIP14

TRING14

TCLK13

TCLK16

LOS15

TTIP13

TRING13

RPOS13

TCLK14

TCLK12

RCLK12

RPOS11

MCLK

A

B

C

D

E

F

RRING14

TPOS12

TCK

TDI

RRING2

LOS1

TNEG16

TPOS16

RPOS16

TCLK1

RNEG2

A3

SDO/RDY/ACKB

GNDT12

TNEG12

RNEG11

RCLK11

GNDT11

GNDT10

RPOS10

RCLK9

AVSS

GNDT1

A5

RRING12

TRSTB

TRING12

TRING11

LOS12

RRING11

LOS11

TRING10

TRING9

LOS10

RRING10

AVSS

RTIP12

VDDT12

TTIP12

TTIP11

VDDT11

RTIP11

VDDT10

TTIP10

TTIP9

TRING1

TRING2

LOS2

TPOS14

TNEG14

TPOS2

AVDD

RPOS12

TCLK11

SDI/WRB/DSB

RDB/RWB

TNEG2

RPOS1

TCLK2

GNDT2

GNDT3

RNEG3

RPOS4

D5

RNEG12

TPOS11

TNEG11

TPOS10

TCLK9

G

H

J

RRING3

LOS3

A1

DVSS

RNEG16

RCLK3

RPOS3

RNEG4

D7

TNEG3

RCLK4

D4

AVSS

DVSS

DVDD

AVDD

TNEG10

TCLK10

TNEG9

RPOS8

TPOS15

TPOS7

OE

TRING3

TRING4

LOS4

D3

RPOS5

TCLK6

RCLK6

GNDT6

RPOS7

RRING7

RTIP7

TNEG8

TPOS5

RPOS6

GNDT7

TCLK8

RNEG8

TCLK7

RNEG6

A0

RCLK10

RNEG10

RPOS9

K

L

RNEG5

TCLK5

TCLK15

TNEG7

LOS8

TPOS9

TPOS8

GNDT8

RNEG7

TRING8

TTIP8

D1

TNEG5

GNDT5

TNEG6

TRING6

TTIP6

RNEG9

M

N

P

R

T

RRING4

AVSS

GNDT4

D2

TPOS6

RCLK5

TRING5

TTIP5

GNDT9

SCLK/ALE/ASB

CSB

VDDT9

RTIP10

AVDD

D6

RCLK7

TRING7

TTIP7

RCLK8

LOS5

RRING6

RTIP6

LOS7

RESREF

VDDT7

RRING8

RTIP8

LOS9

LOS6

VDDT5

VDDT6

VDDT8

CLKE/MUX

RRING9

RTIP9

116 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

11 PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix

character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTERN NO.

256 TE-CSBGA

X256T+2

21-0315

90-0291

117 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

12 THERMAL INFORMATION

Table 12-1. Thermal Characteristics

PARAMETER

MIN

TYP

MAX

V (m/s)

NOTES

Ambient Temperature

Junction Temperature

1

-40°C

+85°C

+125°C

0

2

Theta-JA (θ_JA) in Still Air Conduction

Theta-JC (θ_JC) Conduction

Theta-JB (θ_JB) Conduction

Theta-JA (θ_JA) in Forced Air

16.6°C/W

3.0°C/W

7.5°C/W

15.0°C/W

14.6°C/W

14.0°C/W

0.75

1.25

2.5

Note 1:

Note 2:

The package is mounted on a four-layer JEDEC standard test board.

Theta-JA (θ_JA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard

test board.

Table 12-2. Package Power Dissipation (for Thermal Considerations)

TYPICAL 50% 1s (Note 1)

TYPICAL 100% 1s (Note 2)

MAXIMUM 100% 1s (Note 3)

MODE

FULLY PARTIALLY

INTERNAL INTERNAL

FULLY

INTERNAL INTERNAL

PARTIALLY

FULLY

INTERNAL INTERNAL

PARTIALLY

EXTERNAL

E1-75Ω

1.64

1.49

1.87

1.92

1.95

1.99

2.02

1.84

1.89

1.92

1.95

1.99

1.43

1.19

1.52

1.57

1.60

1.63

1.67

1.49

1.54

1.57

1.60

1.63

1.31

1.19

1.47

1.51

1.55

1.58

1.61

1.47

1.51

1.55

1.58

1.61

2.56

2.23

2.96

3.03

3.06

3.12

3.16

2.90

2.96

2.99

3.05

3.10

2.15

1.62

2.26

2.32

2.35

2.41

2.46

2.20

2.26

2.29

2.35

2.39

1.90

1.62

2.14

2.20

2.29

2.34

2.14

2.20

2.29

2.34

2.82

2.54

3.56

3.63

3.66

3.72

3.77

3.44

3.51

3.54

3.60

3.65

2.36

1.69

2.51

2.57

2.60

2.67

2.72

2.36

2.42

2.45

2.52

2.57

1.98

1.69

2.23

2.30

2.39

2.44

2.23

2.30

2.39

2.44

E1-120Ω

T1-LBO0

T1-LBO1

T1-LBO2

T1-LBO3

T1-LBO4

J1-LBO0

J1-LBO1

J1-LBO2

J1-LBO3

J1-LBO4

Note 1:

Note 2:

Note 3:

Typical voltage, transmitting/receiving 50% 1s in Watts.

Typical voltage, transmitting/receiving 100% 1s in Watts.

Maximum voltage, transmitting/receiving 100% 1s in Watts.

Table 12-3 describes how much power to deduct per-channel from the total power dissipation values listed in

Table 12-2.

118 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Table 12-3. Per-Channel Power-Down Savings (for Thermal Considerations)

TYPICAL 50% 1s (Note 1)

TYPICAL 100% 1s (Note 2)

MAXIMUM 100% 1s (Note 3)

MODE

FULLY PARTIALLY

INTERNAL INTERNAL

FULLY

INTERNAL INTERNAL

PARTIALLY

FULLY

INTERNAL INTERNAL

PARTIALLY

EXTERNAL

0.093

0.084

0.108

0.111

0.113

0.115

0.117

0.106

0.109

0.111

0.113

0.115

0.080

0.065

0.086

0.089

0.091

0.093

0.095

0.084

0.087

0.089

0.091

0.093

0.072

0.065

0.083

0.086

0.088

0.090

0.092

0.083

0.086

0.088

0.090

0.092

0.151

0.130

0.176

0.180

0.182

0.186

0.189

0.172

0.176

0.178

0.182

0.185

0.125

0.092

0.132

0.136

0.138

0.142

0.145

0.128

0.132

0.134

0.138

0.141

0.109

0.092

0.125

0.129

0.134

0.137

0.125

0.129

0.134

0.137

0.166

0.148

0.213

0.217

0.219

0.223

0.226

0.205

0.209

0.211

0.215

0.218

0.137

0.095

0.147

0.151

0.153

0.157

0.160

0.137

0.141

0.143

0.147

0.150

0.113

0.095

0.130

0.134

0.140

0.143

0.130

0.134

0.140

0.143

E1-75Ω

E1-120Ω

T1-LBO0

T1-LBO1

T1-LBO2

T1-LBO3

T1-LBO4

J1-LBO0

J1-LBO1

J1-LBO2

J1-LBO3

J1-LBO4

Note 1:

Note 2:

Note 3:

Typical voltage, transmitting/receiving 50% 1s in Watts.

Typical voltage, transmitting/receiving 100% 1s in Watts.

Maximum voltage, transmitting/receiving 100% 1s in Watts.

T_A°C + θ_JAx Power Dissipation ≤ Maximum Junction Temperature

Where: T_A= Maximum Ambient Temperature

Example:

T_A= +70°C

Mode = Typical 100% 1s E1-75Ω, Fully Internal Impedance Matching

Air Flow = 1.25m/s

70°C + 14.6°C/W x 2.56W = 107°C

This is below the maximum junction temperature and, therefore, this solution will support the thermal requirements.

119 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

13 DATA SHEET REVISION HISTORY

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

Initial release.

070105

—

Added descriptions of feature enhancements implemented in revision A2:

1) Programmable corner frequency for the jitter attenuator in E1 mode.

2) Fully internal impedance matching option for RTIP/RRING.

3) Option for system-side deployment of BERT.

4) Revised B8ZS/HDB3 sections for clarification of functions.

5) Added RESREF pin for receive termination calibration.

See below for the detailed list of changes made to this data sheet revision.

See Features bullets, Detailed Description, and Section 5.5.1 for mention of fully

internal receive impedance matching.

1, 7, 27

Added RESREF pin (R9).

11

15

16

In OE pin description, changed GC.RTCTL to TST.RHPMC

Deleted R9 from DVSS.

In Section 5.4: Transmitter, second paragraph, changed NRZ encoding to AMI

encoding.

20

25

26

Replaced Figure 5-8.

In Table 5-6, updated Rt; updated Section 5.4.3 and Section 5.4.4; in Section 5.4.5:

Zero Suppression—B8ZS or HDB3, removed last sentence from first paragraph.

Changed Section 5.4.8 name from Drive Failure Monitor to Driver Fail Monitor;

updated Section 5.5; added new Section 5.5.1: Receive Impedance Matching

Calibration.

27

30

Added Section 5.5.8: Receive Dual-Rail Mode; added new Section 5.5.9: Receive

Single-Rail Mode; updated Table 5-11.

012507

Updated Section 5.8.2: Digital Loopback.

33

34

40

Added new paragraph to Section 5.9: BERT.

Changed GMC to BGMC (Table 6-1) (see also page 53).

In Table 6-4, deleted Receive Bit Error Count Register 4 (does not exist for this

part).

43

In Table 6-5, changed bit names for LOSS (LIUs 1–16) to correctly match bit

description on page 49; for TST, changed bits 7–5 from Reserved to JABWS1,

JABWS0, and RHPMC (see also page 58).

44

45

46

In Table 6-6, changed SRS bit to correctly say SRMS.

In Table 6-7, added missing address (27) to SHLHS for LIUs 9–16; changed bit 7

and bits 3–0 names for RSMM4 (LIUs 9–16) to correctly match bit description on

page 74; changed “GISC” (3E) to “Not Used” for LIUs 9–16.

In Table 6-8, changed BSR register bit 3 (PMS) to show it is read only (added

underline), matching the bit description on page 88, as well as changed “RW” to “R”

to correctly show all bits are read only; changed BSRL register bit 3 (PMSL) to show

it is read only (added underline), matching the bit description on page 89, as well as

changed “RL/W” to “R” to correctly show all bits are read only.

47

In the LOSS register, corrected bit names from LOS[8:1] to LOSS[8:1].

Changed GMC to BGMC; changed bits 7, 6, and 5 from Reserved to BERTDIR,

BMCKS, and BTCKS.

49

53

In the GC register (LIUs 1–8), changed bit 7 from Reserved to RIMPMS and bit 2

from RTCTL to CRIMP (see also page 44, Table 6-5).

56

120 of 121

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

REVISION

DATE

PAGES

DESCRIPTION

CHANGED

In the GC register (LIUs 9–16), changed bit 7 from Reserved to RIMPMS and

57

58

changed bit 2 from Reserved to CALEN (see also page 44, Table 6-5).

For TST, changed bits 7, 6, and 5 from Reserved to JABWS1, JABWS0, and

RHPMC.

In the bit 7 (RIMPON) description, changed GC.RTCTL to TST.RHPMC; added note

to bit description.

60

61

Changed bit description for OE bits 7 to 0.

For EZDE, corrected bit names for LIUs 1–16 from EXZDE[1:16] to EZDE[1:16];

changed bit description to say “Excessive zero detection is only relevant when

HDB3 or B8ZS decoding is enabled.” For CVDEB, changed bit description to say

“Code violation detection is only relevant when HDB3 decoding is enabled (LCS

register).”

65

In Table 12-1, deleted “Power Dissipation in Package”; added new Table 12-2.

Package Power Dissipation (for Thermal Considerations) and Table 12-3. Per-

Channel Power-Down Saving (for Thermal Considerations).

118

Added note to bit 3 (RSMM1:RSSM4) description and updated descriptions for bits

6–4 and 2–0 (deleted “When” from each sentence for clarity).

71, 72, 73,

74

Updated package drawing information.

117

Table 8-3: added “Note 1: Specifications to -40°C are guaranteed by design (GBD)

and not production tested.”

98

053107

012108

Table 9-3, 9-4, 9-5, 9-6: added “Note 1: The timing parameters in this table are

guaranteed by design (GBD).”

100, 103,

106, 109

Changed the GC (2Fh) register bit 1 (JAPS) description.

57

116

1

Figure 10-1 in Section 10 PIN CONFIGURATION: Corrected cell R9. Changed from

DVSS to RESREF

Pb-free ordering information added

3/11

Table 4-1. PIN DESCRIPTION. TRSTB Function description changed. Replaced

“floating” with “unconnected”

15

98

Soldering information in ABSOLUTE MAXIMUM RATINGS table updated

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Maxim is a registered trademark of Maxim Integrated Products, Inc.

121 of 121


型号：	DS26334
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul Line Interface Unit
文件：	总121页 (文件大小：1186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS26334 [MAXIM]

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