DS2720CU/T&R [MAXIM]
Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC;
| 型号： | DS2720CU/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC |
| 文件： | 总21页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2720
Efficient, Addressable Single-Cell
Rechargeable Lithium Protection IC
www.maxim-ic.com
FEATURES
PIN CONFIGURATION
CꢀRechargeable Lithium-Ion (Li+) Safety
Circuit
PLS
PS
1
2
3
4
8
7
6
5
CP
DC
CC
VDD
- Overvoltage Protection
- Overcurrent/Short-Circuit Protection
- Undervoltage Protection
DQ
VSS
- Overtemperature Protection
CꢀControls High-Side N-Channel Power
MOSFETs Driven from 9V Charge Pump
CꢀSystem Power Management and Control
Feature Support
DS2720U
ꢀSOP
CꢀEight Bytes of Lockable EEPROM
CꢀDallas 1-Wire® Interface with Unique 64-Bit
Device Address
PIN DESCRIPTION
PLS - Battery-Pack Positive Terminal Input
- Power-Switch Sense Input
PS
Cꢀ8-Pin ꢀꢁSOP Package
DQ - Data Input/Output
CꢀLow Power Consumption:
- Active Current: 12.5ꢁA typ
VSS - Device Ground
VDD - Power-Supply Input
CP - Reservoir Capacitor
CC - Charge Control Output
DC - Discharge Control Output
- Sleep Current:
1.5ꢁA typ
DESCRIPTION
The DS2720 single-cell rechargeable Li+ protection IC provides electronic safety functions required for
rechargeable Li+ applications including protecting the battery during charge, protection of the circuit
from damage during periods of excess current flow and maximization of battery life by limiting the level
of cell depletion. Protection is facilitated by electronically disconnecting the charge and discharge
conduction path with switching devices such as low-cost N-channel power MOSFETs.
Since the DS2720 provides high-side drive to external N-channel protection MOSFETs from a 9V charge
pump, superior on-resistance performance results compared to common low-side protector circuits using
the same FETs. The FET on-resistance actually decreases as the battery discharges.
Adding to the uniqueness of the DS2720 is the ability of the system to control the FETs from either the
data interface or a dedicated input thereby eliminating the power-switch control redundancy of
rechargeable Li+ battery systems.
Through its 1-Wire interface, the DS2720 gives the host system read/write access to status and control
registers, instrumentation registers, and general-purpose data storage. Each device has a factory-
programmed 64-bit net address that allows it to be individually addressed by the host system.
1-Wire is a registered trademark of Dallas Semiconductor.
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080205
DS2720
Two types of user-memory are provided on the DS2720 for battery information storage: EEPROM and
lockable EEPROM. EEPROM memory saves important battery data in true nonvolatile (NV) memory
that is unaffected by severe battery depletion, accidental shorts, or ESD events. Lockable EEPROM
becomes ROM when locked to provide additional security for unchanging battery data.
ORDERING INFORMATION
PART
DS2720AU+
DS2720AU+T&R
DS2720BU+
DS2720BU+T&R
DS2720CU+
DS2720CU+T&R
DS2720AU
DS2720AU/T&R
DS2720BU
DS2720BU/T&R
DS2720CU
DS2720CU/T&R
DESCRIPTION
DS2720+ in 8-Lead ꢀSOP in Bulk with VOVA = 4.275V
DS2720+ in 8-Lead ꢀSOP in Tape-and-Reel with VOVA = 4.275V
DS2720+ in 8-Lead ꢀSOP in Bulk with VOVB = 4.35V
DS2720+ in 8-Lead ꢀSOP in Tape-and-Reel with VOVB = 4.35V
DS2720+ in 8-Lead ꢀSOP in Bulk with VOVC = 4.30V
DS2720+ in 8-Lead ꢀSOP in Tape-and-Reel with VOVC = 4.30V
DS2720 in 8-Lead ꢀSOP in Bulk with VOVA = 4.275V
DS2720 in 8-Lead ꢀSOP in Tape-and-Reel with VOVA = 4.275V
DS2720 in 8-Lead ꢀSOP in Bulk with VOVB = 4.35V
DS2720 in 8-Lead ꢀSOP in Tape-and-Reel with VOVB = 4.35V
DS2720 in 8-Lead ꢀSOP in Bulk with VOVC = 4.30V
DS2720 in 8-Lead ꢀSOP in Tape-and-Reel with VOVC = 4.30V
+ Denotes lead-free package.
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DS2720
Figure 1. BLOCK DIAGRAM
1-WIRE INTERFACE
64-BIT ROM
LOCKABLE EEPROM
STATUS/CONTROL
DQ
AND CONTROL
PS
TEMP SENSOR
(Tdevice)
+
+
OUTPUT BUFFER
CP
TMAX
Q
S
VDD
CC
+
+
+
DELAY
tOVD
+
+
R
VOV
VCE
VUV
DC
Q
S
+
VSS
L
O
G
I
DELAY
tUVD
R
(1)
(2)
C
+
+
DELAY
tOCD
+
RTST
VOC
+
+
VCH
VSC
PLS
+
DELAY
tSCD
1) Normally open, closed to enable test current, ITST
2) Normally open, closed to enable test current, ITST, and recovery charge
(See Rechargeable Li+ Protection Circuitry section for more information.)
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DS2720
Table 1. DETAILED PIN DESCRIPTION
SYMBOL DESCRIPTION
Battery-Pack Positive Terminal Input. The device monitors the state of the battery
pack’s positive terminal through this pin in order to detect events such as the attachment
of a charger or the removal of a short circuit. Connect PLS to the pack positive terminal
through a 100ꢂ resistor.
PLS
Power-Switch Sense Input. The device wakes up from sleep mode when it senses the
closure of a switch to VSS on this pin. PS has a high-impedance internal pullup.
PS
Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the
DATA terminal of the battery pack. DQ has an internal 0.5ꢁA pull-down.
Device Ground. Connect directly to the negative terminal of the battery cell.
DQ
VSS
VDD
Power Supply Input. Connect VDD to the positive terminal of the battery cell through a
decoupling network.
Charge Pump Output. The internal charge pump regulates CP to 9V which supplies
the ON state drive to the protection FETs. Connect a 0.1ꢁF reservoir capacitor from CP
to VSS.
CP
Charge Protection Control Output. Controls an external N-channel high-side charge
CC
DC
protection FET.
Discharge Protection Control Output. Controls an external N-channel high-side
discharge protection FET.
Figure 2. APPLICATION EXAMPLE
102
102
PACK+
100
102
1k
1k
DS2720
330
330
PLS
CP
DC
CC
1-CELL Li+
10
PS
PS
DQ
VSS VDD
104
104
PACK-
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DS2720
POWER MODES
The DS2720 has two power modes: active and sleep. While in active mode, the DS2720 continuously
performs safety monitoring. In sleep mode, the DS2720 ceases monitoring activities and drives both the
charge and discharge protection FETs to an “off state”. Upon returning to the active mode from the sleep
mode, DS2720 resumes safety monitoring and conditionally turns on the protection FETs.
Table 2. POWER MODE TRANSITION CONDITIONS
Active J Sleep
Sleep J Active(1)
VDD < VUV
pulled to V or
PS
VPLS > VDD + SVSCH
(1) DS2720 does not transition to Active Mode if VDD < VSC.
RECHARGEABLE Li+ PROTECTION CIRCUITRY
During active mode, the DS2720 constantly monitors cell voltage and voltage drop across the FETs to
protect the battery from overcharge (overvoltage), overdischarge (undervoltage), and excessive discharge
currents (overcurrent, short circuit). Conditions and DS2720 responses are described in the sections
below and summarized in Table 3 and Figure 3.
Table 3. PROTECTION CONDITIONS AND DS2720 RESPONSES
CONDITION
NAME
ACTIVATION
DELAY
RELEASE
THRESHOLD
VDD < VCE or
THRESHOLD
RESPONSE
(1)
Overvoltage
VDD > VOV
tOVD
CC = VOLCC
VDD - VPLS > VOC
CC = VOLCC
DC = VOLDC
VPLS > VDD + VCH and
Undervoltage
VSC < VDD < VUV
tUVD
VDD > VUV
(charger connected)
VDD < VSC or
(while in active
mode) VDD < VCE
Recovery Charge
RTST enabled(2)
VDD O VCE
CC = VOLCC
DC = VOLCC
CC = VOLCC
DC = VOLDC
CC = VOLCC
DC = VOLDC
(3)
Overcurrent
VDD - VPLS > VOC
VDD < VSC
tOCD
tSCD
VPLS > VDD - VOC
(3)
Short Circuit
VPLS > VDD - VOC
Overtemperature
Tdevice > TMAX
Tdevice < TMAX
All voltages are with respect to VSS.
(1) During transition from sleep to active, tOVD = 0.
(2) Recovery charge current is limited by RTST and forward voltage of blocking diode, which prevents discharging through
R
TST when recovery charge enabled.
(3) With test current ITST flowing from VDD to PLS (pullup on PLS).
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DS2720
Overvoltage. If the cell voltage sensed at VDD exceeds overvoltage threshold VOV for a period longer
than overvoltage delay tOVD, the DS2720 shuts off the external charge FET and sets the OV flag in the
protection register. Discharging remains enabled during overvoltage. The charge FET is re-enabled
(unless another protection condition prevents it), when the cell voltage falls below charge enable
threshold VCE, or a discharge causes VDD - VPLS > VOC.
Undervoltage. If the cell voltage sensed at VDD drops below undervoltage threshold VUV for a period
longer than undervoltage delay tUVD, the DS2720 shuts off the charge and discharge FETs, sets the UV
flag in the protection register, and enters sleep mode. The DS2720 turns on both the charge and discharge
FETs after the cell voltage rises above VUV and a charger is present.
Short Circuit. If the cell voltage sensed at VDD drops below depletion threshold VSC for a period of tSCD
,
the DS2720 shuts off the charge and discharge FETs and sets the DOC flag in the protection register. The
current path through the charge and discharge FETs is not re-established until the voltage on PLS rises
above VDD - VOC. The DS2720 provides a test current through internal resistor RTST from VDD to PLS to
pull up PLS when VDD rises above VSC. The test current allows the DS2720 to detect the removal of the
offending low-impedance load. Additionally, a recovery charge path through RTST from PLS to VDD is
enabled.
Overcurrent. If the voltage across the protection FETs (VDD - VPLS) is greater than VOC for a period
longer than tOCD, the DS2720 shuts off the external charge and discharge FETs and sets the DOC flag in
the protection register. The current path is not re-established until the voltage on PLS rises above VDD
-
VOC. The DS2720 provides a test current through internal resistor RTST from VDD to PLS to detect the
removal of the offending low-impedance load.
Overtemperature. If the device temperature exceeds TMAX, the DS2720 immediately shuts off the
external discharge and charge FETs. The FETs are not turned back on until the cell temperature drops
below TMAX AND the host resets the OT bit.
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DS2720
Figure 3. Li+ PROTECTION CIRCUITRY EXAMPLE WAVEFORMS
VOV
VCE
VDD
VUV
VSC
VCH
0
VPLS - VDD
-VOC
CHARGE
ICELL
RECOVERY CHARGED THROUGH
0
-IOC
-ISC
DISCHARGE
VOHCP
VOLCC
CC
tUVD
tUVD
tOVD
tON
tON
tON
VOHCP
VOLDC
DC
tSCD
tUVD
tOCD
tUVD
ACTIVE
SLEEP
POWER
MODE
OVER-
CURRENT OR
SHORT TEST
ACTIVE
INACTIVE
ENABLED
DISABLED
RECOVERY
CHARGE
SHORT-CIRCUIT
EVENT
OVERCURRENT
EVENT
UNDERVOLTAGE
EVENT
OVERVOLTAGE
UNDERVOLTAGE
SEVERE
DEPLETION
EVENT
EVENT
Notes:
IOC = Current that produces a voltage drop across FETs equal to VOC threshold.
I
SC = Current drawn from the battery during short-circuit event. (Collapses the cell terminal voltage to VSC.)
Above example assumes FET on-resistance values such that the overcurrent threshold, VOC, is reached before the
short-circuit threshold, VSC.
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DS2720
MEMORY
The DS27xx family of products is organized into a 256-byte linear address space with registers for
instrumentation, status, and control in the lower 32 bytes, with lockable EEPROM memory occupying
portions of the remaining address space. All EEPROM memory is general purpose except address 31h,
which should be written with the default values for the status register.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory in fact access the shadow RAM. In unlocked EEPROM blocks, the write data
command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The
copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM
but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROM
to shadow RAM regardless of whether the block is locked or not.
Table 4. MEMORY MAP
ADDRESS (hex)
DESCRIPTION
READ/WRITE
00
01
Protection Register
Status Register
Reserved
R/W
R
02–06
07
08
09–1F
20–23
24–2F
30–33
—
R
EEPROM Register
Special Feature Register
Reserved
R/W
—
EEPROM, Block 0
Reserved
R/W (1)
—
EEPROM, Block 1
(31 = Status Register Initialization)
Reserved
R/W (1)
34–FF
—
(1)
Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The format of
the protection register is shown in Figure 4. The function of each bit is described in detail in the following
paragraphs.
Figure 4. PROTECTION REGISTER FORMAT
Address 00
Bit 7
OV
Bit 6
UV
Bit 5
0
Bit 4
Bit 3
CC
Bit 2
DC
Bit 1
CE
Bit 0
DE
DOC
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DS2720
OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage
condition. This bit does not clear itself after the overvoltage state is corrected, and thus must be reset by
the host system. A reset of this bit should be issued after the battery voltage falls below VCE in order to
detect future events. The OV bit is a volatile R/W bit, initialized to 0 upon power-on-reset (POR).
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit does not clear itself after the undervoltage state is corrected, and thus
should be reset by the host system in order to detect future events. The UV bit is a volatile R/W bit,
initialized to 1 upon POR.
DOC—Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced an
overcurrent (or short-circuit) condition. This bit does not clear itself after the over/shortcurrent state is
corrected, and thus should be reset by the host system in order to detect future events. The DOC bit is a
volatile R/W bit, initialized to 1 upon POR.
CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin. The CC bit is a 1 when the
CC pin is driven high (VOHCC). The CC bit is a 0 when the CC pin is driven low (VOLCC).
DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin. The DC bit is a 1 when
the DC pin is driven high (VOHDC). The DC bit is a 0 when the DC pin is driven low (VOLDC).
CE—Charge Enable. Writing a 0 to this bit disables charging (CC output low, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2720 automatically sets this bit to 1 when it transitions
from sleep mode to active mode. The CE bit is a volatile R/W bit, initialized to 1 upon POR.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (DC output low, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2720 automatically sets this bit to 1 when it
transitions from sleep mode to active mode. The DE bit is a volatile R/W bit, initialized to 1 upon POR.
STATUS REGISTER
The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of
address 31h. A recall data command for EEPROM block 1 recalls the default values into the status
register bits. The format of the status register is shown in Figure 5. The function of each bit is described
in detail in the following paragraphs.
Figure 5. STATUS REGISTER FORMAT
Address 01
Bit 7
X
Bit 6
X
Bit 5
0
Bit 4
Bit 3
0
Bit 2
X
Bit 1
X
Bit 0
X
RNAOP
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DS2720
BIT 5—This bit is read only. The value of this bit is set by bit 5 of address 31h and is factory set to 0.
The value of address 31h bit 5 must not be changed.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address
command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h. The factory default for RNAOP is 0.
BIT 3—This bit is read only. The value of this bit is set by bit 3 of address 31h and is factory set to 0.
The value of address 31h bit 3 must not be changed.
X—Reserved Bits.
EEPROM REGISTER
The format of the EEPROM register is shown in Figure 6. The function of each bit is described in detail
in the following paragraphs.
Figure 6. EEPROM REGISTER FORMAT
Address 07
Bit 7
EEC
Bit 6
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
BL1
Bit 0
BL0
LOCK
EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress.
While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data can be
written to unlocked EEPROM blocks if the DS2720 is in the active mode of operation.
LOCK—EEPROM Lock Enable. When this bit is 0, the lock command is ignored. Writing a 1 to this bit
enables the lock command. After the lock command is executed, the LOCK bit is reset to 0. The LOCK
bit is a volatile R/W bit, initialized to 0 upon POR.
BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses
30 to 33h) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write).
BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses
20 to 23h) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write).
X—Reserved Bits.
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DS2720
SPECIAL FEATURE REGISTER
The format of the special feature register is shown in Figure 7. The function of each bit is described in
detail in the following paragraphs.
Figure 7. SPECIAL FEATURE REGISTER FORMAT
Address 08
Bit 7
PSF
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
OT
PSF— PS Flag. This bit is reset to 0 when the DS2720 detects the PS pin is pulled to VSS. This bit does
not set itself to a 1 after the PS pin returns to a high logic level, and thus must be set by the host system
to detect future events. This bit is initialized to a 1 upon POR.
OT—Overtemperature Flag. When set to 1, this bit indicates the battery pack has experienced an
overtemperature condition. This bit does not clear itself after the overtemperature state is corrected, and
thus must be reset by the host system after the temperature decreases below TMAX to re-enable the charge
and discharge FETs. Writing a 1 to this bit disables the FETs, but this is not recommended. The OT bit is
a volatile R/W bit, initialized to 0 upon POR.
X—Reserved Bits.
INPUT PIN
PS
The PS pin is internally pulled to VDD through a high-value resistance. PS is continuously monitored for
a low-impedance connection to VSS. Connecting PS to VSS wakes up the DS2720 if it was in sleep mode.
If the DS2720 was in active mode, PS has no effect.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-
Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2720
is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this
bus system consists of four topics: 64-bit net address, hardware configuration, transaction sequence, and
1-Wire signaling.
64-BIT NET ADDRESS
Each DS2720 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first
eight bits are the 1-Wire family code (31h for DS2720). The next 48 bits are a unique serial number. The
last eight bits are a CRC of the first 56 bits (see Figure 8). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2720 to communicate through the 1-Wire protocol detailed in
the 1-Wire Bus System section of this data sheet.
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DS2720
Figure 8. 1-WIRE NET ADDRESS FORMAT
8-Bit CRC
MSb
48-Bit Serial Number
8-Bit Family
Code (31h)
LSb
CRC GENERATION
The DS2720 has an 8-bit cyclic redundancy check (CRC) stored in the most significant byte of its 1-Wire
net address. To ensure error-free transmission of the address, the host system can compute a CRC value
from the first 56 bits of the address and compare it to the CRC from the DS2720. The host system is
responsible for verifying the CRC value and taking action as a result. The DS2720 does not compare
CRC values and does not prevent a command sequence from proceeding as a result of a CRC mismatch.
Proper use of the CRC can result in a communication channel with a very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as
shown in Figure 9, or it can be generated in software. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27, Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products.
In the circuit in Figure 9, the shift register bits are initialized to 0. Then, starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value.
Figure 9. 1-WIRE CRC GENERATION BLOCK DIAGRAM
INPUT
MSb
LSb
XOR
XOR
XOR
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2720 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 10. If a bidirectional pin is not available on the bus
master, separate output and input pins can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5kꢂ. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120ꢀs, slave devices on the bus begin to
interpret the low period as a reset pulse, effectively terminating the transaction.
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DS2720
Figure 10. 1-WIRE BUS INTERFACE CIRCUITRY
+VPULLUP
(2.0V TO 5.5V)
BUS MASTER
DS2720 1-WIRE PORT
4.7kꢁ
Rx
Rx
Tx
0.5ꢀA
(typ)
Tx
Rx = RECEIVE
Tx = TRANSMIT
100ꢁ
MOSFET
TRANSACTION SEQUENCE
The protocol for accessing the DS2720 through the 1-Wire port is as follows:
CꢀInitialization
CꢀNet Address Command
CꢀFunction Command
CꢀTransaction/Data
The sections that follow describe each of these steps in detail.
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse
transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2720
and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on
the bus and ready to operate. For more details, see the 1-Wire Signaling section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the ROM
commands described in the following paragraphs. The name of each net address command is followed by
the 8-bit opcode for that command in square brackets. Figure 11 presents a transaction flowchart of the
ROM commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2720’s 1-Wire net
address. This command can only be used if there is a single slave on the bus. If more than one slave is
present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a
wired-AND result). The RNAOP bit in the status register selects the opcode for this command, with
RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2720 on
the 1-Wire bus. Only the addressed DS2720 responds to any subsequent function command. All other
slave devices ignore the function command and wait for a reset pulse. This command can be used with
one or more slave devices on the bus.
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DS2720
Skip Net Address [CCh]. This command saves time when there is only one 1-Wire device on the bus by
allowing the bus master to issue a function command without specifying the address of the slave. If more
than one slave device is present on the bus, a subsequent function command can cause a data collision
when all slaves transmit data at the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to
identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple three-step routine on each bit location of the net
address. After one complete pass through all 64 bits, the bus master knows the address of one device. The
remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book
of DS19xx iButton® Standards for a comprehensive discussion of a net address search, including an actual
example.
Resume Command [A5H]. In a typical application the DS2720 can be accessed several times to
complete control adjustment. To maximize data throughput in a multidrop environment, the resume
command has been implemented. This function checks the status of an internal flag. If it is set, it directly
transfers control in similar fashion to the skip net address command. The only way to set the internal flag
is through successfully executing the match net address or search net address. Once the flag has been set,
the device can be repeatedly accessed through the resume command. Accessing another device on the bus
clears the flag, thus preventing two or more devices from simultaneously responding to the resume
command function.
FUNCTION COMMANDS
After successfully completing one of the net address commands, the bus master can access the features of
the DS2720 with any of the function commands described in the following paragraphs. The name of each
function is followed by the 8-bit opcode for that command in square brackets. The function commands
are summarized in Table 5.
Read Data [69h, XX]. This command reads data from the DS2720 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb
of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX.
If the bus master continues to read beyond address FFh, data is read starting at memory address 00 and
the address is automatically incremented until a reset pulse occurs. Addresses labeled “Reserved” in the
memory map contain undefined data. The read data command can be terminated by the bus master with a
reset pulse at any bit boundary.
Write Data [6Ch, XX]. This command writes data to the DS2720 starting at memory address XX. The
LSb of the data to be stored at address XX can be written immediately after the MSb of address has been
entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb
to be stored at address XX + 1 can be written immediately after the MSb to be stored at address XX. If
the bus master continues to write beyond address FFh, the data starting at address 00 is overwritten.
Writes to read-only addresses, reserved addresses and locked EEPROM blocks are ignored. Incomplete
bytes are not written. Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM.
See the Memory section for more details.
Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 4-byte
EEPROM block containing address XX. Copy data commands that address locked blocks are ignored.
While the copy data command is executing, the EEC bit in the EEPROM register is set to 1 and writes to
iButton is a registered trademark of Dallas Semiconductor.
14 of 21
DS2720
EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while the
copy is in progress. The copy data command takes tEEC time to execute, starting on the next falling edge
after the address is transmitted. The copy data command is ignored by the DS2720 while in the sleep
mode.
Recall Data [B8h, XX]. This command recalls the contents of the 4-byte EEPROM block containing
address XX to shadow RAM.
Lock [6Ah, XX]. This command locks (write-protects) the 4-byte block of EEPROM memory containing
memory address XX. The LOCK bit in the EEPROM register must be set to l before the lock command is
executed. To help prevent unintentional locks, one must issue the lock command immediately after
setting the LOCK bit (EEPROM register, address 07h, bit 06) to a 1. If the LOCK bit is 0 or if setting the
lock bit to 1 does not immediately precede the lock command, the lock command has no effect. The lock
command is permanent; a locked block can never be written again. The lock command is ignored by the
DS2720 while in the sleep mode.
Table 5. FUNCTION COMMANDS
COMMAND
PROTOCOL
BUS STATE
AFTER
COMMAND
PROTOCOL
COMMAND
DESCRIPTION
BUS DATA
Reads data from
memory starting at
address XX
Up to 256 bytes
of data
Read Data
Write Data
Copy Data
Master Rx
Master Tx
69h, XX
6Ch, XX
Writes data to memory
starting at address XX
Copies shadow RAM
data to EEPROM block
containing address XX
Recalls EEPROM
Up to 256 bytes
of data
48h, XX
B8h, XX
Master Reset
None
None
None
Recall Data
Lock
block containing
Master Reset
Master Reset
address XX to RAM
Permanently locks the
block of EEPROM
containing address XX
6Ch, 07h, 4Xh
6Ah, XX
15 of 21
DS2720
Figure 11. NET ADDRESS COMMAND FLOW CHART
MASTER Tx
RESET PULSE
DS2720 Tx
PRESENCE PULSE
MASTER Tx
NET ADDRESS
COMMAND
33h/39h
READ
NO
55h
MATCH
NO
F0h
SEARCH
NO
NO
CCh
SKIP
YES
YES
YES
YES
MASTER Tx
BIT 0
DS2720 Tx
FAMILY CODE
1 BYTE
DS2720 Tx BIT 0
DS2720 Tx BIT 0
MASTER Tx BIT 0
A5h
NO
NO
RESUME
DS2720 Tx
SERIAL NUMBER
6 BYTES
YES
BIT 0
MATCH ?
NO NO
BIT 0
MATCH ?
RESUME
FLAG SET?
DS2720 Tx
CRC
1 BYTE
YES
YES
YES
MASTER Tx
BIT 1
DS2720 Tx BIT 1
DS2720 Tx BIT 1
MASTER Tx BIT 1
CLEAR RESUME
FLAG
CLEAR RESUME
FLAG
BIT 1
MATCH ?
NO NO
BIT 1
MATCH ?
MASTER Tx
FUNCTION
COMMAND
YES
YES
MASTER Tx
BIT 63
DS2720 Tx BIT 63
DS2720 Tx BIT 63
MASTER Tx BIT 63
YES
BIT 63
MATCH ?
Set Resume
Flag
NO
MASTER Tx
FUNCTION
COMMAND
CLEAR RESUME
FLAG
16 of 21
DS2720
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2720 are the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read
data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2720 is shown in Figure 12.
A presence pulse following a reset pulse indicates the DS2720 is ready to accept a net address command.
The bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into
receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the
rising edge on the DQ pin, the DS2720 waits for tPDH and then transmits the presence pulse for tPDL
.
Figure 12. 1-WIRE INITIALIZATION SEQUENCE
tRSTL
tRSTH
tPDH
tPDL
VDQ
VSS
DQ
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
DS2720 ACTIVE LOW
BOTH BUS MASTER AND
DS2720 ACTIVE LOW
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be tSLOT (60ꢀs to 120ꢀs) in duration with a 1ꢀs minimum recovery time, tREC, between cycles. The
DS2720 samples the 1-Wire bus line between 15ꢀs and 60ꢀs after the line falls. If the line is high when
sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see Figure 13). For the bus
master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15ꢀs after the start of the write time slot. For the host to generate a write 0 time
slot, the bus line must be pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a
logic-low level. The bus master must keep the bus line low for at least 1ꢀs and then release it to allow the
DS2720 to present valid data. The bus master can then sample the data tRDV (15ꢀs) from the start of the
read-time slot. By the end of the read-time slot, the DS2720 releases the bus line and allows it to be
pulled high by the external pullup resistor. All read-time slots must be tSLOT (60ꢀs to 120ꢁs) in duration
with a 1ꢀs minimum recovery time, tREC, between cycles. See Figure 13 for more information.
17 of 21
DS2720
Figure 13. 1-WIRE WRITE- AND READ-TIME SLOTS
WRITE 0 SLOT
WRITE 1 SLOT
tSLOT
tSLOT
tLOW1
t
tREC
VDQ
DQ
VSS
DS2720 SAMPLE WINDOW
15ꢀs
DS2720 SAMPLE WINDOW
15ꢀs
>1ꢀs
15ꢀs
30ꢀs
15ꢀs
30ꢀs
READ 0 SLOT
READ 1 SLOT
tSLOT
tSLOT
tREC
VDQ
VSS
DQ
MASTER SAMPLE WINDOW
LINE TYPE LEGEND:
>1ꢀs
MASTER SAMPLE WINDOW
tRDV
tRDV
BUS MASTER ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND
DS2720 ACTIVE LOW
18 of 21
DS2720
ABSOLUTE MAXIMUM RATINGS*
Voltage on PLS, Relative to VSS
-0.3V to +18V
Voltage on CC, DC, and CP Pins, Relative to VSS
Voltage on any Other Pin, Relative to VSS
Operating Temperature Range
-0.3V to +12V
-0.3V to +6V
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC-STD-020A
Storage Temperature Range
Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC
OPERATING CONDITIONS
(-20LC to +70LC, 2.5V ? VDD ? 5.5V)
PARAMETER
Supply Voltage
Data Pin
SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
VDD
DQ
2.5
5.5
5.5
V
V
1
1
-0.3
DC ELECTRICAL CHARACTERISTICS
(-20LC to +70LC, 2.5V ? VDD ? 4.5V)
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
DQ = VDD
12.5
20
25
2
2
ꢁA
ꢁA
ꢁA
V
Active Current
IACTIVE
0LC ? TA ? 50LC
DQ = VDD
DQ = 0V,
Sleep Mode Current
Input Logic High: DQ
ISLEEP
VIH1
1.5
2.5
floating
PS
1.5
1
VDD
-
VIH2
V
1, 6
Input Logic High:
PS
0.2V
Input Logic Low: DQ
VIL1
VIL2
0.4
0.2
V
V
1
1
Input Logic Low:
PS
Output Logic High:
VOHCP
VOLCC
VOLDC
VOL1
8.5
9.0
VDD
VPLS
9.5
V
V
V
V
1
RLOAD > 10Mꢂ
RLOAD > 10Mꢂ
CC, DC
Output Logic Low:
CC
VDD
0.1
VPLS
0.1
+
+
1
Output Logic Low:
DC
R
LOAD > 10Mꢂ
VPLS ? 10V
1, 7
1
Output Logic Low:
DQ
IOL = 4mA
0.4
2.5
DQ Input Pulldown
IPD
IPS
VDQ = 0.4V
VPS = 0.4V
0.1
0.5
100
1.2
ꢁA
nA
kꢂ
Current
Pullup Current
PS
CC Pulldown
RCCPD
4
Resistance
DC Pulldown
Resistance
RDCPD
12
16
kꢂ
19 of 21
DS2720
ELECTRICAL CHARACTERISTICS:
PROTECTION CIRCUITRY
(0LC to +50LC, 2.5V ? VDD ? 4.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VOVA
VOVB
VOVC
4.250
4.325
4.275
Typ -
75mV
Typ -
120mV
70
140
2.0
0.75
90
4.275
4.350
4.300
4.300
4.375
4.325
Typ +
75mV
Typ +
120mV
110
260
2.6
1.25
160
Overvoltage Detect
V
1, 3
Charge Enable
VCE
VOV/1.022
V
V
1, 3
1, 3
Undervoltage Detect
VUV
VOV/1.55
Overtemperature Detect
Overcurrent Detect
Short-Circuit Detect
Overvoltage Delay
Undervoltage Delay
Overcurrent Delay
TMAX
VOC
VSC
tOVD
tUVD
tOCD
tSCD
90
200
2.3
1.0
125
16
3
1, 3
1
LC
mV
V
s
3
ms
ms
ꢀs
3
12
50
3
20
150
11
3
Short-Circuit Delay
Test Resistance, ITST Active
Test Resistance, Recovery
Charging
100
RTST1
5
5
kꢂ
RTST2
VCH
5
15
kꢂ
Charger Detect Voltage
20
60
120
mV
ELECTRICAL CHARACTERISTICS:
1-WIRE INTERFACE
(-20LC to +70LC, 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
tSLOT
tREC
MIN
60
1
TYP
MAX
UNITS
ꢀs
NOTES
Time Slot
120
Recovery Time
ꢀs
Write 0 Low Time
Write 1 Low Time
Read Data Valid
Reset Time High
Reset Time Low
Presence Detect High
Presence Detect Low
Active Transition to
CC/DC Engage
tLOW0
tLOW1
tRDV
60
1
120
15
15
ꢀs
ꢀs
ꢀs
tRSTH
tRSTL
tPDH
480
480
15
ꢀs
960
60
240
ꢀs
ꢀs
tPDL
60
ꢀs
tON
100
25
ms
pF
4
DQ Capacitance
CDQ
20 of 21
DS2720
EEPROM RELIABILITY
SPECIFICATION:
(-20LC to +70LC, 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Copy to EEPROM Time
EEPROM Copy Endurance
EEPROM Data Retention
tEEC
NEEC
tEEDR
1
5
ms
cycles
years
25,000
4
NOTES
1. All voltages are referenced to VSS.
2. Specified with no resistive load on CC, DC, or CP.
3. Contact the factory for different voltage trip points and delay periods.
4. Typical load capacitance on CC, DC is 1000pF CP (charge pump reservoir cap) = 0.1ꢁF. DC load
total on CC, DC, CP > 10Mꢂ.
5. RTST = |VPLS - VDD| / I measured, with VPLS = 3.2V, VDD = 3.6V when test current, ITST, active for
R
TST1 ; and VPLS = 4.0V, VDD = 2.5V when recovery charging for RTST2.
6. Maximum high-to-low fall time is 5ꢁs.
7. Internal 10V clamp on DC pin limits DC output logic low when PLS > 10V
8. Short-circuit delay tested with VDD ramped from 3.1V to 1.9V in 5ꢁs. Delay measured from VDD
=
2.5V to DC pin fall to 7V from VOHCP
.
21 of 21
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