DS2745U+ [MAXIM]
Low-Cost I2C Battery Monitor; 低成本I²C电池监视器
| 型号： | DS2745U+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Cost I2C Battery Monitor |
| 文件： | 总14页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2745
Low-Cost I2
www.maxim-ic.com
PIN CONFIGURATION
FEATURES
16-Bit Bidirectional Current Measurement
1.56ꢀV LSB, ±51.2mV Dynamic Range
7
6
VDD
VIN
CTG
VSS
SCL
SDA
PIO
104ꢀA LSB, ±3.4A Dynamic Range (RSNS =
2
15mꢁ)
3
Current Accumulation Register Resolution
4
SNS
6.25ꢀVhr LSB, ±204.8mVh Range
0.417mAhr LSB, ±13.65Ah Range
(RSNS = 15mꢁ)
ꢀMAX
11-Bit Voltage Measurement
4.88mV LSB, 0V to 5V Input Range
11-Bit Temperature Measurement
0.125ºC Resolution, -20ºC to +70ºC
Industry Standard I2C* Interface
Low Power Consumption:
Active Current:
See Table 1 for Ordering Information.
DESCRIPTION
The DS2745 provides current-flow, voltage, and
temperature measurement data to support battery-
capacity monitoring in cost-sensitive applications. The
DS2745 can be mounted on either the host side or
pack side of the application. Current measurement
and coulomb counting is accomplished by monitoring
the voltage drop across an external sense resistor,
voltage measurement is accomplished through a
separate voltage-sense input, and temperature
measurement takes place on-chip. A standard I2C
interface with software programmable address gives
the controlling microprocessor access to all data and
status registers inside the DS2745. A low-power sleep
mode state conserves energy when the cell pack is in
storage.
70ꢀA typical, 100ꢀA max
Sleep Current:
1ꢀA typical, 3ꢀA max
BLOCK DIAGRAM
PACK+
VDD
Fuel Gauge
Algorithm
µP
DS2745
SDA
SCL
VIN
COMM
PACK-
APPLICATIONS
Cellular
SNS
VSS
GPS
PDAs
Handheld Products
Sense
Li+
Protector
Table 1. ORDERING INFORMATION
PART
MARKING
2745
PIN-PACKAGE
ꢀMAX package
DS2745U+
2745
DS2745U+/T&R
DS2745U+ in Tape-and-Reel
+Denotes lead-free package.
*I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated
Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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091405
DS2745 Low-Cost I2C Battery Monitor
ABSOLUTE MAXIMUM RATINGS*
Voltage on All Pins Relative to VSS
Operating Temperature Range
Storage Temperature Range
-0.3V to +6V
-40°C to +85°C
-55°C to +125°C
Soldering Temperature
See IPC/JEDECJ-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(2.5V ? VDD ? 5.5V; TA = 0LC to +70LC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
2.5
-0.3
-0.3
-0.3
-0.3
TYP
MAX
5.5
UNITS
Supply Voltage
VDD
(Note 1)
V
V
V
V
V
Serial Data I/O Pin
Serial Clock Pin
Programmable I/O Pin
VIN Pin
SDA
(Note 1)
(Note 1)
(Note 1)
(Note 1)
+5.5
SCL
+5.5
PIO
+5.5
VIN
VDD +0.3
DC ELECTRICAL CHARACTERISTICS
(2.5V ? VDD ? 4.5V; TA = 0LC to +70LC, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
70
MAX UNITS
100
Active Current
IACTIVE
ꢀA
VDD = 5.5V
105
SCL = SDA = VSS,
PIO = VSS
Sleep-Mode Current
Current Resolution
Current Full-Scale
Magnitude
ISLEEP
1
3
ꢀA
ILSB
IFS
1.56
51.2
ꢀV/R
mV/R
ꢀV/R
(Note 1)
(Note 2)
Current Offset
IOERR
IGERR
qCA
- 7.82
- 1.0
+ 12.5
+1.0
% of
Current Gain Error
reading
Accumulated Current
Resolution
Accumulated Current
Offset
6.25
4.88
ꢀVh/R
µVh/R
qOERR
VSNS = VSS, (Notes 4, 5)
- 188
+ 0
per day
Voltage Resolution
Voltage Full-Scale
Voltage Error
VLSB
VFS
mV
V
0
4.992
+ 25
VGERR
TLSB
TERR
fSAMP
tERR
(Note 12)
- 25
mV
°C
Temperature Resolution
0.125
18.6
Temperature Error
Current Sample Clock
Frequency
- 3
+ 3
±1
ºC
kHz
%
Timebase Accuracy
VDD = 3.8V, TA = +25°C
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DS2745 Low-Cost I2C Battery Monitor
±2
-20°C ≤ TA ≤ +70°C,
2.5V ≤ VDD ≤ 5.5V
±3
Input Resistance, VIN
RIN
VIH
15
Mꢁ
V
Input Logic High:
SCL, SDA
(Note 1)
1.5
Input Logic Low:
SCL, SDA
VIL
(Note 1)
0.6
0.4
V
Output Logic Low:
SDA, PIO
VOL
IPD
IOL = 4mA (Note 1)
V
Pulldown Current: SCL,
SDA
0.25
ꢀA
pF
S
Input Capacitance: SCL,
SDA
CBUS
tSLEEP
VIH
50
SLEEP Timeout
(Note 3)
(Note 1)
(Note 1)
2.2
Input Logic High:
PIO
VDD x 0.7
V
Input Logic Low:
PIO
VIL
VDD x 0.3
V
2-WIRE INTERFACE TIMING SPECIFICATIONS
(VDD = 2.5V to 5.5V, TA = -20LC to +70LC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
f
SCL Clock Frequency
(Note 6)
0
400
KHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
SCL
Bus Free Time Between a
t
1.3
0.6
BUF
STOP and START Condition
Hold Time (Repeated)
START Condition
t
(Note 7)
HD:STA
t
Low Period of SCL Clock
1.3
LOW
t
High Period of SCL Clock
0.6
HIGH
Setup Time for a Repeated
START Condition
t
0.6
SU:STA
t
Data Hold Time
(Note 8, 9)
(Note 8)
0
0.9
HD:DAT
t
Data Setup Time
100
SU:DAT
Rise Time of Both SDA and
SCL Signals
t
20 + 0.1CB
20 + 0.1CB
300
300
R
Fall Time of Both SDA and
t
F
SCL Signals
Setup Time for STOP
Condition
t
0.6
0
SU:STO
Spike Pulse Widths
Suppressed by Input Filter
Capacitive Load for Each
Bus
t
(Note 10)
(Note 11)
50
400
60
SP
C
B
pF
pF
Line
SCL, SDA Input
Capacitance
CBIN
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DS2745 Low-Cost I2C Battery Monitor
Note 1:
Note 2:
Note 3:
All voltages are referenced to VSS.
Offset specified after auto-calibration cycle and Current Offset Bias register (COBR) set to 00h.
To properly enter sleep mode, SMOD=1, and the application should hold SDA and SCL low for longer
than the maximum tSLEEP
.
Note 4:
NBEN = 0, Current Offset Bias Register (COBR) set to 00h, and Accumulation Bias Register (ABR)
set to 00h.
Note 5:
Note 6:
Parameters guaranteed by design.
Timing must be fast enough to prevent the DS2745 from entering sleep mode due to SDA,SCL low
for period >
tSLEEP
.
Note 7:
Note 8:
fSCL must meet the minimum clock low time plus the rise/fall times.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL
signal.
Note 9:
This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the
VIHmin of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
CBZtotal capacitance of one bus line in pF.
Note 10:
Note 11:
Note 12:
The first voltage measurement after writing the ACR or after device POR is not valid.
Figure 1. I2C Bus Timing Diagram
SDA
tF
tF
tSP
tR
tBUF
tSU;DAT
tHD;STA
tLOW
tR
SCL
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
S
Sr
P
S
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DS2745 Low-Cost I2C Battery Monitor
PIN DESCRIPTION
PIN
SYMBOL
FUNCTION
Serial Clock Input. 2-Wire clock line. Input only. Connect this pin to the CLOCK
terminal of the battery pack. Pin has an internal pulldown (IPD) for sensing
disconnection.
Serial Data Input/Output. 2-Wire data line. Open-drain output driver. Connect this pin
to the DATA terminal of the battery pack. Pin has an internal pulldown (IPD) for sensing
disconnection.
SCL
SDA
1
2
General Purpose Input/Output. Open-drain output driver with input sense. Connect
PIO
SNS
VSS
3
4
5
to a pull up resistor for bidirectional operation.
Sense Resistor Connection. Connect to the negative terminal of the battery pack.
Connect the sense resistor between VSS and SNS.
Device Ground. Connect to the negative terminal of the Li+ cell outside the cell
protection FETs. Connect the sense resistor between VSS and SNS.
Connect to Ground. Connect to the negative terminal of the Li+ cell outside the cell
CTG
6
7
8
protection FETs.
Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin.
VIN
VDD
Power-Supply Input. Connect to the positive terminal of the Li+ cell through a
decoupling network.
Figure 2. BLOCK DIAGRAM
VDD
BIAS
TIMEBASE
THERMAL
SENSE
VOLTAGE
REFERENCE
TEMPERATURE
M
U
ADC1
ADC2
VOLTAGE
CURRENT
ACR
VIN
X
SCL
SDA
2-WIRE
INTERFACE
STATUS
PIO
1kꢀ
1kꢀ
-
+
SNS
VSS
ꢀ
chip
ground
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DS2745 Low-Cost I2C Battery Monitor
DETAILED DESCRIPTION
Current is measured bidirectionally over a dynamic range of ±51.2mV with a resolution of 1.56ꢀV. Assuming a
15mꢁ sense resistor, the current sense range is ±3.4A, with a 1 LSB resolution of 104ꢀA. Current measurements
are performed at regular intervals and accumulated with each measurement to support accurate “coulomb
counting”. Each current measurement is reported with sign and magnitude in the two-byte Current register. The
Accumulated Current register (ACR) reports the coulomb count and supports a wide range of battery sizes. Battery
voltage measurements are reported in the two-byte Voltage register with 11-bit (4.88mV) resolution, and
Temperature is reported in the two-byte Temperature register with 0.125C resolution.
The DS2745 measurements can be used directly to provide accurate fuel gauging in typical use conditions, or
along with FuelPack™ algorithms to form a complete and accurate solution for estimating remaining capacity over
wide temperature and operating conditions.
Through its two wire I2C interface, the DS2745 allows a host system read/write access to the Status, Configuration
and Measurement registers. Additionally, the I2C slave address can be changed from the default after power up.
Figure 3. APPLICATION EXAMPLE
PACK+
500ꢀ
1kꢀ
DS2745
PIO
VSS
VIN
CTG
SNS
SCL
SDA
CLOCK
DATA
150ꢀ
150ꢀ
1 Cell Li+
VDD
5.6V
(1)
5.6V 5.6V
(1) (1)
Protection IC
(Li+/Polymer)
103
RSNS
PACK -
2.5V
(1)
102
102
(1) Optional for 8kV/15kV ESD
FuelPack is a trademark of Dallas Semiconductor.
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DS2745 Low-Cost I2C Battery Monitor
POWER MODES
The DS2745 operates in one of two power modes: active and sleep. While in active mode, the DS2745 operates as
a high-precision battery monitor with voltage, temperature, current and accumulated current measurements
acquired continuously and the resulting values updated in the measurement registers. Read and write access is
allowed to all registers.
In sleep mode, the DS2745 operates in a low-power mode with no measurement activity. Serial access to current,
accumulated current, and status/control registers is allowed in sleep mode if VDD > 2V.
The DS2745 operating mode transitions from SLEEP to ACTIVE when:
SDA > VIH OR SCL > VIH
The DS2745 operating mode transitions from ACTIVE to SLEEP when:
SMOD = 1 AND (SDA < VIL AND SCL < VIL) for tSLEEP
.
CAUTION: If SMOD = 1, pull-up resistors are required on SCL and/or SDA in order to ensure that the DS2745
transitions from SLEEP to ACTIVE mode when the battery is charged. If the bus is not pulled up, the DS2745
remains in SLEEP and cannot accumulate the charge current. This caution statement applies particularly to on a
battery that is charged on a standalone charger.
VOLTAGE MEASUREMENT
Battery voltage is measured at the VIN input with respect to VSS over a range of 0V to 4.992V and with a
resolution of 4.88mV. The result is updated every 440ms and placed in the VOLTAGE register in two’s compliment
form. Voltages above the maximum register value are reported as 7FFFh.
Figure 4. VOLTAGE REGISTER FORMAT
MSB—Address 0C
28 27 26
LSB—Address 0D
20
S
29
25
24
23
22
21
X
X
X
X
X
MSb
LSb
MSb
LSb
Units: 4.88mV
“S”: sign bit(s), “X”: reserved
The input impedance of VIN is sufficiently large (>15Mꢁ) to be connected to a high impedance voltage divider in
order to support multiple cell applications. The pack voltage should be divided by the number of series cells to
present a single cell average voltage to the VIN input. Note that the first voltage measurement made after the
DS2745 is powered or after the ACR register is written will not be valid. The host should wait one measurement
cycle after either of these two conditions occur before reading voltage.
TEMPERATURE MEASUREMENT
The DS2745 uses an integrated temperature sensor to measure battery temperature with a resolution of 0.125°C.
Temperature measurements are updated every 440ms and placed in the Temperature Register in two’s
complement form.
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DS2745 Low-Cost I2C Battery Monitor
Figure 5. TEMPERATURE REGISTER FORMAT
MSB—Address 0A
LSB—Address 0B
20
S
29
28
27
26
25
24
23
22
21
X
X
X
X
X
MSb
LSb
MSb
LSb
Units: 0.125LC
“S”: sign bit, “X”: reserved
CURRENT MEASUREMENT
In the active mode of operation, the DS2745 continually measures the current flow into and out of the battery by
measuring the voltage drop across a low-value current-sense resistor, RSNS, connected between the SNS and VSS
pins. The voltage sense range between SNS and VSS is ±51.2mV. Note that positive current values occur when
V
SNS is less than VSS, and negative current values occur when VSNS is greater than VSS. Peak signal amplitudes up
to 102mV are allowed at the input as long as the continuous or average signal level does not exceed ±51.2mV over
the conversion cycle period. The ADC samples the input differentially at with an 18.6kHz sample clock and updates
the current register at the completion of each conversion cycle. Figure 6 describes the current measurement
register format and resolution. Charge currents above the maximum register value are reported at the maximum
value (7FFFh = +51.2mV). Discharge currents below the minimum register value are reported at the minimum
value (8000h = -51.2mV).
Figure 6. CURRENT REGISTER FORMATS
MSB—Address 0E
LSB—Address 0F
25 24 23
Units:
S
214 213 212 211 210 29
28
27
26
22
21 20
LSb
MSb
LSb
MSb
20 = 1.5625ꢀV/Rsns
“S”: sign bit
Table 2. CURRENT RESOLUTION FOR VARIOUS RSNS VALUES
CURRENT RESOLUTION (1 LSB)
CONVERSION
RSNS
TIME
|VSS - VSNS
|
20mꢁ
78.13ꢀA
15mꢁ
104.2ꢀA
10mꢁ
156.3ꢀA
5mꢁ
312.5ꢀA
3.5s
1.5625ꢀV
Table 3. CURRENT RANGE FOR VARIOUS RSNS VALUES
CURRENT INPUT RANGE
RSNS
VSS - VSNS
20mꢁ
15mꢁ
10mꢁ
5mꢁ
±51.2mV
±2.56A
±3.41A
±5.12A
±10.24A
Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset correction occurs
approximately once per hour. The resulting correction factor is applied to the subsequent 1023 measurements.
During the offset correction conversion, the ADC does not measure the SNS to VSS signal. A maximum error of
1/1024 in the accumulated current register (ACR) is possible, however, to reduce the error, the current
measurement just prior to the offset conversion is displayed in the current register and is substituted for the
dropped current measurement in the current accumulation process. The error due to offset correction is typically
much less than 1/1024.
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DS2745 Low-Cost I2C Battery Monitor
CURRENT ACCUMULATION
The Accumulated Current register (ACR) serves as an up/down counter holding a running count of charge stored in
the battery. Current measurement results, plus a programmable bias value are internally summed, or accumulated,
at the completion of each current measurement conversion period with the results displayed in the ACR. The ACR
has a range of 0mVh to +409.6mVh with an LSb of 6.25µVhAdditional registers hold fractional results of each
accumulation, however, these bits are not user accessible. The ACR count clamps at FFFFh when accumulating
charge values and at 0000h when accumulating discharge values.
Read and write access is allowed to the ACR. Whenever the ACR is written, fractional accumulation results are
cleared. A write to the ACR also forces the ADC to measure its offset and update the offset correction factor.
Current measurement and accumulation resume (using the new offset correction) with the second conversion
following the write to the ACR. Figure 7 describes the ACR address, format, and resolution.
Figure 7. ACCUMULATED CURRENT REGISTER FORMAT
MSB—Address 10
LSB—Address 11
S
214 213 212 211 210 29
28
27
26
25
24
23
22
21 20
LSb
6.25ꢀVh/Rsns
MSb
LSb
MSb
“S”: sign bit
Units:
Table 4. ACCUMULATED CURRENT RANGE FOR VARIOUS RSNS VALUES
ACR RANGE
RSNS
VSS - VSNS
20mꢀ
15mꢀ
10mꢁ
5mꢁ
409.6mVh
20.48Ah
27.31Ah
40.96Ah
81.92Ah
CURRENT OFFSET BIAS
The Current Offset Bias register (COBR) allows a programmable offset value to be added to raw current
measurements. The result of the raw current measurement plus the COBR value is displayed as the current
measurement result in the CURRENT register, and is used for current accumulation. The COBR value can be used
to correct for a static offset error, or can be used to intentionally skew the current results and therefore the current
accumulation.
Read and write access is allowed to COBR. Whenever the COBR is written, the new value is applied to all
subsequent current measurements. COBR can be programmed in 1.56ꢀV steps to any value between +198.1ꢀV
and -199.7ꢀV. The COBR value is stored as a two’s complement value in volatile memory, and must be initialized
via the interface on power-up. Figure 8 describes the COBR address, format, and resolution.
Figure 8. CURRENT OFFSET BIAS REGISTER FORMAT
Address 61
S
26
25
24
23
22
21 20
LSb
MSb
“S”: sign bit
Units: 1.56ꢀV/Rsns
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DS2745 Low-Cost I2C Battery Monitor
CURRENT BLANKING
The Current Blanking feature modifies current measurement result prior to being accumulated in the ACR. Current
Blanking occurs conditionally when a current measurement (raw current + COBR) falls in one of two defined
ranges. The first range prevents charge currents less than 100ꢀV from being accumulated. The second range
prevents discharge currents less than 25ꢀV in magnitude from being accumulated. Charge current blanking is
always performed, however, discharge current blanking must be enabled by setting the NBEN bit in the
Status/Config register. See the register description for additional information.
ACCUMULATION BIAS
The Accumulation Bias register (ABR) allows a programmable offset value to be added to the current accumulation
process. The new ACR value results from the addition of the Current register value plus ABR plus the previous
ACR value. ABR can be used to intentionally skew the current accumulation to estimate system stand-by currents
that are too small to measure. ABR value is not subject to the Current Blanking thresholds.
Read and write access is allowed to the ABR. Whenever the ABR is written, the new value is applied to all
subsequent current measurements. ABR can be set to any value between +198.1ꢀV and -199.7ꢀV in 1.56ꢀV
steps. The ABR value is stored as a two’s complement value in volatile memory, and must be initialized via the
interface on power-up. Figure 9 describes the ABR address, format, and resolution.
Figure 9. ACCUMULATION BIAS REGISTER FORMAT
Address 62
S
26
25
24
23
22
21 20
LSb
MSb
“S”: sign bit
Units: 1.56ꢀV/Rsns
MEMORY
The DS2745 has memory space with registers for instrumentation, status, and control. When the MSB of a two-
byte register is read, both the MSB and LSB are latched and held for the duration of the read data command to
prevent updates during the read and ensure synchronization between the two register bytes. For consistent results,
always read the MSB and the LSB of a two-byte register during the same read data command sequence.
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DS2745 Low-Cost I2C Battery Monitor
Table 5. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
POR DEFAULT
00
01
02 to 08
09 to 0D
0A
Reserved
Status/Config Register
Reserved
—
R/W
—
—
R
R
R
R
R
11000000b
Reserved
Temperature Register MSB
Temperature Register LSB
Voltage Register MSB
Voltage Register LSB
Current Register MSB
Current Register LSB
Accumulated Current Register MSB
Accumulated Current Register LSB
Reserved
0B
0C
0D
0E
0F
10
11
R
No Change
No Change
R/W
R/W
—
R/W
R/W
—
12 to 61
61
00h
00h
Offset Bias Register
Accumulation Bias Register
Reserved
62
63 to FF
STATUS/CONFIG REGISTER
The Status/Config register is read/write with individual bits designated as read only. Bit values indicate status as
well as program or select device functionality.
Figure 10. STATUS/CONFIG REGISTER FORMAT
ADDRESS 01
BIT 7
X
BIT 6
PORF
BIT 5
SMOD
BIT 4
NBEN
BIT 3
PIO
BIT 2
A2
BIT 1
A1
BIT 0
A0
X — Reserved.
PORF — The Power-On-Reset Flag is set to indicate initial power-up. PORF is not cleared internally. The user
must write this flag value to a 0 in order to use it to indicate subsequent power-up events. If PORF indicates a
power-on-reset, the ACR could be misaligned with the actual battery state of charge. The system can request a
charge to full in order to synchronize the ACR with the battery charge state. PORF is read/write-to-zero.
SMOD — SLEEP Mode Enable. A value of 1 allows the DS2745 to enter sleep mode when both SDA and SCL
pins is low for 2s. A value of 0 disables the transition to sleep mode. The power-up default of SMOD = 0.
NBEN — Negative Blanking Enable. A value of 1 enables blanking of negative current values up to 25ꢀV. A value
of 0 disables blanking of negative currents. The power-up default of NBEN = 0.
PIO — Programmable Input/Output. PIO provides both control of the PIO open-drain output driver and readback of
the PIO pin logic level. Writing a 0 to PIO drives PIO pin low. Writing a 1 deactivates the PIO output and allows
readback of an external signal. Reading PIO returns the logic state on the pin. PIO is RESET on POR.
A2:A0 — I2C Slave Address bits. A2:A0 set the lower 3 bits of the I2C slave address. When modified from the
power-up default slave address of 1001000b, accessing the DS2745 requires the modified slave address following
a start or repeated start.
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DS2745 Low-Cost I2C Battery Monitor
2-WIRE BUS SYSTEM
The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi-
master system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire
interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional
communication between the DS2745 slave device and a master device at speeds up to 400kHz. The DS2745’s
SDA pin operates bidirectionally, that is, when the DS2745 receives data, SDA operates as an input, and when the
DS2745 returns data, SDA operates as an open-drain output, with the host system providing a resistive pull-up.
The DS2745 always operates as a slave device, receiving and transmitting data under the control of a master
device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and
STOP bits which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and
then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any
change in SDA when SCL is high is interpreted as a START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one
transaction and begin another without returning the bus to the idle state. In multimaster systems, a Repeated
START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities
in which the SDA transitions when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the
master and the DS2745 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL
returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of
the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is
busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re-
attempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is
followed by the Acknowledge bit. DS2745 registers composed of multi-byte values are ordered most significant
byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a Slave
Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2745 continuously monitors for a
START condition followed by its slave address. When the DS2745 receives a slave address that matches the value
in its Status/Config register, it responds with an Acknowledge bit during the clock period following the R/W bit. The
default Slave Address at power-up is 1001000. The lower three bits of the slave address can be re-programmed,
refer to the Status/Config register description for details.
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DS2745 Low-Cost I2C Battery Monitor
Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read
transaction, with the following bytes being read from the stave by the master.
Bus Timing
The DS2745 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2745. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
Table 3. 2-Wire Protocol Key
KEY
DESCRIPTION
KEY
Sr
DESCRIPTION
S
START bit
Repeated START
SAddr
FCmd
MAddr
Data
A
Slave Address (7-bit)
W
R/W bit = 0
Function Command byte
Memory Address byte
R
R/W bit = 1
P
STOP bit
Data byte written by master
Acknowledge bit - Master
No Acknowledge - Master
Data
A
Data byte returned by slave
Acknowledge bitZSlave
No AcknowledgeZSlave
N
N
Basic Transaction Formats
Write:
S SAddr W A MAddr A Data0 A P
A write transaction transfers one or more data bytes to the DS2745. The data transfer begins at the memory
address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction,
except for the Acknowledge cycles.
Read:
S SAddr W A MAddr A Sr SAddr R A Data0 N P
Write Portion Read Portion
A read transaction transfers one or more bytes from the DS2745. Read transactions are composed of two parts, a
write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write portion
communicates the starting point for the read operation. The read portion follows immediately, beginning with a
Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2745 beginning with
the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2745 throughout the
transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding
to the last byte it requires with a No Acknowledge. This signals the DS2745 that control of SDA is to remain with
the master following the Acknowledge clock.
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DS2745 Low-Cost I2C Battery Monitor
Write Data Protocol
The write data protocol is used to write to register and shadow RAM data to the DS2745 starting at memory
address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and
DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by
sending a STOP or Repeated START after receiving the last acknowledge bit.
S SAddr W A MAddr A Data0 A Data1 A … DataN A P
The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is
received by the DS2745, the msb of the data at address MAddr + 1 is can be written immediately after the
acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write transaction
beyond address FFh, the DS2745 ignores the data. Data is also ignored on writes to read-only addresses and
reserved addresses. Incomplete bytes and bytes that are Not Acknowledged by the DS2745 are not written to
memory.
Read Data Protocol
The Read Data protocol is used to read register and shadow RAM data from the DS2745 starting at memory
address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data
from MAddr + 1 and DataN represents the last byte read by the master.
S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A … DataN N P
Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is
automatically incremented after the least significant bit (lsb) of each byte is returned, the msb of the data at
address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If
the bus master continues to read beyond address FFh, the DS2745 outputs data values of FFh. Addresses labeled
“Reserved” in the memory map return undefined data. The bus master terminates the read transaction at any byte
boundary by issuing a No Acknowledge followed by a STOP or Repeated START.
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
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