DS2777GR [MAXIM]
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication; 2节，独立式， Li +电池电量计IC，提供保护电路和SHA -1认证
| 型号： | DS2777GR |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication |
| 文件： | 总46页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4688; Rev 4; 6/11
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
General Description
Features
The DS2775–DS2778 report available capacity for
rechargeable lithium-ion (Li+) and Li+ polymer (Li-Poly)
batteries in mAh and as a percentage of full. Safe oper-
ation is ensured by the integrated Li+ protector. The
DS2776/DS2778 support SHA-1-based challenge-
response authentication in addition to all other DS2775/
DS2777 features.
♦ High-Side nFET Drivers and Protection Circuitry
♦ Precision Voltage, Temperature, and Current
Measurement System
♦ Cell-Capacity Estimation from Coulomb Count,
Discharge Rate, Temperature, and Cell
Characteristics
Precision measurements of voltage, temperature, and
current, along with a cell characteristics table and
application parameters, are used for capacity estima-
tion calculations. The capacity registers report a con-
servative estimate of the amount of charge that can be
removed given the current temperature, discharge rate,
stored charge, and application parameters.
♦ Estimates Cell Aging Between Learn Cycles
♦ Uses Low-Cost Sense Resistor
♦ Allows Calibration of Gain and Temperature
Coefficient
♦ Programmable Thresholds for Overvoltage and
The DS2775–DS2778 operate from +4.0V to +9.2V for
direct integration into battery packs with two Li+ or Li-
Poly cells.
Overcurrent
♦ Pack Authentication Using SHA-1 Algorithm
(DS2776/DS2778)
In addition to nonvolatile storage for cell compensation
and application parameters, the DS2775–DS2778 offer
16 bytes of EEPROM for use by the host system and/or
pack manufacturer to store battery lot and date tracking
information. The EEPROM can also be used for non-
volatile storage of system and/or battery usage statis-
♦ 32-Byte Parameter EEPROM
♦ 16-Byte User EEPROM
♦ Maxim 1-Wire Interface with 64-Bit Unique ID
(DS2775/DS2776)
®
tics. A Maxim 1-Wire (DS2775/DS2776) or 2-wire
♦ 2-Wire Interface with 64-Bit Unique ID
(DS2777/DS2778) interface provides serial communica-
tion to access measurement and capacity data regis-
ters, control registers, and user memory. The
DS2776/DS2778 use the SHA-1 hash algorithm in a
challenge-response pack authentication protocol for
battery-pack verification.
(DS2777/DS2778)
♦ 3mm x 5mm, 14-Pin TDFN Lead-Free Package
Ordering Information
PART
DS2775G+
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
TOP MARK
D2775
D2775
D2776
D2776
D2777
D2777
D2778
D2778
Applications
Low-Cost Notebooks
UMPCs
DS2775G+T&R
DS2776G+
DS776G+T&R
DS2777G+
DSLR Cameras
Video Cameras
DS2777G+T&R
DS2778G+
Commercial and Military Radios
Portable Medical Equipment
DS2778G+T&R
Note: All devices are specified over the -20°C to +70°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Selector Guide appears at end of data sheet.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
ABSOLUTE MAXIMUM RATINGS
Voltage Range on PLS, CP, CC, DC Pins
Continuous Sink Current, PIO, DQ......................................20mA
Continuous Sink Current, CC, DC.......................................10mA
Operating Temperature Range ...........................-20°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Relative to V .....................................................-0.3V to +18V
SS
Voltage Range on V , V , V , SRC Pins
DD IN1 IN2
Relative to V ....................................................-0.3V to +9.2V
SS
Voltage Range on All Other Pins Relative to V ..-0.3V to +6.0V
SS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
A A
PARAMETER
SYMBOL
CONDITIONS
Sleep mode, T ꢀ +50°C
MIN
TYP
MAX
5
UNITS
μA
3
A
I
DD0
Sleep mode, T > +50°C
A
10
Supply Current
I
I
Active mode
80
135
300
+3
DD1
Active mode during SHA-1 computation
120
DD2
Temperature Accuracy
T
-3
°C
ERR
2.0V ꢀ V
4.6V, 0°C ꢀ T ꢀ +50°C
ꢀ 4.6V, 2.0V ꢀ (V
- V ) ꢀ
IN1
IN1
IN2
IN2
-35
+35
A
Voltage Accuracy
mV
2.0V ꢀ V
ꢀ 4.6V, 2.0V ꢀ (V
– V ) ꢀ
IN1
IN1
-22
22
4.6V, T = +25°C
A
2.0V ꢀ V ꢀ 4.6V, 2.0V ꢀ (V - V ) ꢀ 4.6V
-50
15
+50
IN1
IN2
IN1
Input Resistance (V , V
)
Mꢁ
μV
IN1 IN2
Current Resolution
Current Full Scale
Current Gain Error
Current Offset
I
1.56
LSB
56/DS278
I
FS
-51.2
-1
+51.2
+1
mV
I
I
% FS
μVh
GERR
OERR
0°C ꢀ T ꢀ +70°C (Note 1)
-9.375
-255
-2
9.375
0
A
Accumulated Current Offset
q
OERR
0°C ꢀ T ꢀ +70°C (Note 1)
μVh/Day
A
0°C ꢀ T ꢀ +50°C
+2
A
Time-Base Error
t
%
ERR
-3
+3
CP Output Voltage (V - V
CP
)
V
I = 0.9μA
OUT
4.4
4.7
5
V
ms
V
SRC
GS
CP Startup Time
t
CE = 0, DE = 0, C = 0.1μF, active mode
200
SCP
CP
Output High: CC, DC
Output Low: CC
V
OHCP
V
OLCC
V
OLDC
I
I
I
= 100μA (Note 2)
= 100μA
V
- 0.4
OH
OL
OL
CP
V
V
+ 0.1
+ 0.1
V
SRC
Output Low: DC
= 100μA
V
SRC
DQ, PIO Voltage Range
-0.3
1.5
+5.5
V
DQ, PIO, SDA, SCL Input
Logic-High
V
V
V
IH
DQ, PIO, SDA, SCL Input
Logic-Low
V
0.6
IL
OVD Input Logic-High
OVD Input Logic-Low
V
V
BAT
- 0.2
V
V
IH
V
V
+ 0.2
SS
IL
2
_______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
A A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
V
DQ, PIO, SDA Output Logic-Low
DQ, PIO Pullup Current
V
I
= 4mA
OL
OL
PU
I
Sleep mode, V
= (V - 0.4V)
30
30
100
100
50
200
nA
PIN
DD
DQ, PIO, SDA, SCL Pulldown
Current
I
Active mode, V
= 0.4V
PIN
200
9
nA
PD
DQ Input Capacitance
DQ Sleep Timeout
C
DQ
pF
s
t
DQ < V
2
SLEEP
IL
PIO, DQ Wake Debounce
t
Sleep mode
100
ms
WDB
SHA-1 COMPUTATION TIMING (DS2776/DS2778 ONLY)
(V
DD
= +4.0V to +9.2V, T = 0°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
A A
PARAMETER
Computation Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
30
ms
COMP
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT
(V
DD
= +4.0V to +9.2V, T = 0°C to +50°C, unless otherwise noted. Typical values are at T = +25°C.)
A A
PARAMETER
SYMBOL
CONDITIONS
= 1110111b
MIN
4.438
4.242
TYP
4.473
4.277
-100
MAX
4.508
4.312
UNITS
V
V
OV
OV
Overvoltage Detect
Charge-Enable Voltage
Undervoltage Detect
V
OV
V
CE
V
UV
V
mV
V
= 1100011b
Relative to V
OV
Programmable in Control register 0x60h,
UV[1:0] = 10
2.415
2.450
2.485
OC = 11b
OC = 00b
OC = 11b
OC = 00b
SC =1b
-60
-12.5
80
-75
-25
100
38
-90
-38
Overcurrent Detect: Charge
Overcurrent Detect: Discharge
Short-Circuit Current Detect
V
V
mV
mV
mV
COC
DOC
120
50
25
240
120
600
600
8
300
150
360
180
1400
1400
12
V
SC
SC = 0b
(Note 3)
Overvoltage Delay
Undervoltage Delay
Overcurrent Delay
Short-Circuit Delay
Charger-Detect Hysteresis
Test Threshold
t
ms
ms
ms
μs
OVD
t
(Note 3)
UVD
t
10
120
50
OCD
t
80
160
SCD
V
V
condition
UV
mV
V
CD
V
COC, DOC condition
DOC condition
COC condition
Sleep mode
0.4
20
1.0
40
1.2
80
TP
Test Current
I
μA
μA
TST
-45
200
-60
400
-95
630
PLS Pulldown Current
Recovery Current
I
PPD
V
condition, max: V
= 15V, V = 1.4V;
PLS DD
= 2V
DD
UV
I
3.3
8
13
mA
RC
min: V
= 4.2V, V
PLS
_______________________________________________________________________________________
3
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
EEPROM RELIABILITY SPECIFICATION
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ms
EEPROM Copy Time
t
10
EEC
EEPROM Copy Endurance
N
T
A
= +50°C
50,000
Cycles
EEC
ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE, STANDARD (DS2775/DS2776 ONLY)
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
60
1
TYP
MAX
UNITS
μs
Time Slot
t
120
SLOT
Recovery Time
t
μs
REC
Write-Zero Low Time
Write-One Low Time
Read Data Valid
t
t
60
1
120
15
μs
LOW0
LOW1
μs
t
15
μs
RDV
Reset Time High
Reset Time Low
t
480
480
15
μs
RSTH
t
960
60
μs
RSTL
Presence-Detect High
Presence-Detect Low
t
μs
PDH
t
60
240
μs
PDL
ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE, OVERDRIVE (DS2775/DS2776 ONLY)
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C.)
A
56/DS278
PARAMETER
SYMBOL
CONDITIONS
MIN
6
TYP
MAX
UNITS
μs
Time Slot
t
16
SLOT
Recovery Time
t
1
μs
REC
Write-Zero Low Time
Write-One Low Time
Read Data Valid
t
t
6
16
2
μs
LOW0
LOW1
1
μs
t
2
μs
RDV
Reset Time High
Reset Time Low
t
48
48
2
μs
RSTH
t
80
6
μs
RSTL
Presence-Detect High
Presence-Detect Low
t
μs
PDH
t
8
24
μs
PDL
4
_______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (DS2777/DS2778 ONLY)
(V
DD
= +4.0V to +9.2V, T = -20°C to +70°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 4)
(Note 5)
0
400
kHz
SCL
Bus-Free Time Between a STOP
and START Condition
t
1.3
0.6
μs
μs
BUF
Hold Time (Repeated) START
Condition
t
t
HD:STA
Low Period of SCL Clock
High Period of SCL Clock
t
1.3
0.6
μs
μs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
μs
SU:STA
Data Hold Time
Data Setup Time
t
t
(Notes 6, 7)
(Note 6)
0
0.9
μs
ns
HD:DAT
SU:DAT
100
Rise Time of Both SDA and SCL
Signals
20 +
t
300
300
ns
R
0.1C
B
Fall Time of Both SDA and SCL
Signals
20 +
t
ns
μs
ns
F
0.1C
B
Setup Time for STOP Condition
t
0.6
SU:STO
Spike Pulse Widths Suppressed
by Input Filter
t
(Note 8)
(Note 9)
0
50
SP
Capacitive Load for Each Bus
Line
C
400
60
pF
pF
B
SCL, SDA Input Capacitance
C
BIN
Note 1: Accumulation bias and offset bias registers set to 00h. NBEN bit set to 0.
Note 2: Measurement made with V = +8V, V driven with external +4.5V supply.
SRC
GS
Note 3: Overvoltage (OV) and undervoltage (UV) delays (t
, t
) are reduced to zero seconds if the OV or UV condition is
OVD UVD
detected within 100ms of entering active mode.
Note 4: Timing must be fast enough to prevent the DS2777/DS2778 from entering sleep mode due to bus low for period > t
.
SLEEP
Note 5: f
must meet the minimum clock low time plus the rise/fall times.
SCL
Note 6: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V
of the SCL signal) to
IHMIN
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 9: C is total capacitance of one bus line in pF.
B
_______________________________________________________________________________________
5
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
DISCHARGE-OVERCURRENT
PROTECTION DELAY
CC FET GATE TURN-OFF DURING
CHARGE-OVERCURRENT EVENT
DS2775/6/7/8 toc01
DS2775/6/7/8 toc02
CC FET
GATE
2V/div
0V
2V/div
0V
DC FET
GATE
CC FET
SOURCE
2V/div
0V
2V/div
0V
DC FET
SOURCE
1V/div
0V
1V/div
0V
V
V
CC FET
GS
V
GS
25mΩ
SNS
20mV/div
0V
V
25mΩ
SNS
0V
20mV/div
SENSE RESISTOR
WITH CHARGE-
OVERCURRENT
SENSE RESISTOR
WITH DISCHARGE-
OVERCURRENT
THRESHOLD = 25mV
0
2
4
6
8
10 12 14 16 18 20
0
5
10 15 20 25 30 35 40 45 50
THRESHOLD = 38mV
TIME (ms)
TIME (μs)
SHORT-CIRCUIT PROTECTION
DELAY
DC FET GATE TURN-OFF DURING
SHORT-CIRCUIT EVENT
DS2775/6/7/8 toc04
DS2775/6/7/8 toc03
2V/div
0V
2V/div
0V
DC FET
GATE
DC FET
GATE
2V/div
0V
2V/div
0V
DC FET
SOURCE
DC FET
SOURCE
1V/div
0V
1V/div
0V
V
V
DC FET
GS
V
V
DC FET
GS
56/DS278
25mΩ
SNS
25mΩ
SNS
100mV/div
0V
SENSE RESISTOR
WITH SHORT-CIRCUIT
THRESHOLD = 150mV
50mV/div
0V
SENSE RESISTOR
WITH SHORT-CIRCUIT
THRESHOLD = 150mV
0
20 40 60 80 100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20
TIME (μs)
TIME (μs)
VOLTAGE MEASUREMENT
ACCURACY
CHARGE-PUMP STARTUP EXITING SLEEP
MODE (V = 8V NO LOAD ON PK+)
DD
DS2775/6/7/8 toc06
20
18
16
14
12
10
8
8
7
12.6V
6
-20°C
+70°C
5
4
+25°C
3
2.75V
6
2
4
0
2
0
-2
0
1
2
3
4
0
10 20 30 40 50 60 70 80 90 100
TIME (ms)
V
(V)
INX
6
_______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
CURRENT MEASUREMENT
CURRENT MEASUREMENT OFFSET
vs. TEMPERATURE
I
RC
vs. V
DD
ACCURACY
125
7
6
5
4
3
2
1
0
2
1
1kΩ RESISTOR FROM PLS TO PK+
75
-20°C
0
+25°C
25
-1
-2
-3
-4
-5
-25
+70°C
-75
-125
-0.052 -0.032 -0.012 0.008 0.028 0.048
0
1
2
3
4
5
6
-20
0
20
40
60
V
(mV)
V
DD
(V)
TEMPERATURE (°C)
SNS
_______________________________________________________________________________________
7
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Pin Configuration
TOP VIEW
CC
1
2
3
4
5
6
7
14 CP
+
V
DD
13 SRC
DC
12 SCL/OVD
11 SDA/DQ
10 PLS
DS2775
DS2776
DS2777
DS2778
V
IN2
V
IN1
VB
9
8
PIO
EP
V
SS
SNS
TDFN
(3mm × 5mm)
Pin Description
PIN
1
NAME
FUNCTION
CC
Charge Control. Charge FET control output.
Chip-Supply Input. Bypass with 0.1μF to V .
SS
2
V
DD
3
DC
Discharge Control. Discharge FET control output.
Battery Voltage Sense Input 2. Connect to highest voltage potential positive cell terminal through
decoupling network.
4
5
V
IN2
IN1
Battery Voltage Sense Input 1. Connect to lowest voltage potential positive cell terminal through
decoupling network.
V
56/DS278
6
7
8
9
VB
Regulated Operating Voltage. Bypass with 0.1μF to V
.
SS
V
Device Ground. Chip ground and battery-side sense resistor input.
Sense Resistor Connection. Pack-side sense resistor sense input.
Programmable I/O. Can be configured as wake input.
SS
SNS
PIO
Pack Plus Terminal Sense Input. Used to detect the removal of short-circuit, discharge overcurrent, and
charge overcurrent conditions.
10
11
12
PLS
Data Input/Output. Serial data I/O, includes weak pulldown to detect system disconnect and can be
configured as wake input for 1-Wire devices.
SDA/DQ
SCL/OVD
Serial Clock Input/Overdrive Select. Communication clock for 2-wire devices/overdrive select pin for
1-Wire devices.
13
14
—
SRC
CP
Protection MOSFET Source Connection. Used as a reference for the charge pump.
Charge Pump Output. Generates gate drive voltage for protection FETs. Bypass with 0.47μF to SRC.
Exposed Pad. Connect to ground or leave unconnected.
EP
8
_______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Block Diagram
VOLTAGE
V
V
IN2
10-BIT + SIGN
ADC/MUX
POWER-MODE
CONTROL
IN1
TEMPERATURE
CURRENT
Li+
PLS
PROTECTOR
SNS
15-BIT + SIGN
ADC
PRECISION ANALOG
OSCILLATOR
FuelPack™
ALGORITHM
VREF
V
SS
CC
DC
FET DRIVERS
CONTROL AND
STATUS REGISTERS
CP
PIN
DRIVERS
AND
POWER
SWITCH
CONTROL
SDA/DQ
SCL/OVD
PIO
PIO LOGIC
CHARGE
PUMP
V
DD
32-BYTE
PARAMETER
EEPROM
COMMUNICATION
INTERFACE
VOLTAGE
REGULATOR
16-BYTE USER
EEPROM
VB
DS2775–DS2778
VB INTERNAL
FuelPack is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
9
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
DS2775/DS2776 Typical Application Circuit
PK+
1kΩ
150Ω
1kΩ
470Ω
1kΩ
1kΩ
CC
SRC
DC
PLS
DQ
V
DD
IN2
IN1
150Ω
DATA
V
V
1kΩ
DS2775
DS2776
PIO
VB
CP
0.47μF
5.1V
SNS
V
SS
OVD
0.1μF
0.1μF
SRC
R
SNS
PK-
DS2777/DS2778 Typical Application Circuit
PK+
56/DS278
1kΩ
150Ω
1kΩ
470Ω
1kΩ
1kΩ
CC
SRC
DC
PLS
SDA
SCL
PIO
VB
V
DD
IN2
IN1
150Ω
SDA
SCL
V
V
1kΩ
DS2777
DS2778
150Ω
5.1V
CP
0.47μF
SNS
V
SS
0.1μF
5.1V
0.1μF
SRC
R
SNS
PK-
10 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
serve power by disabling measurement and capacity
Detailed Description
estimation functions, but preserve register contents.
The DS2775–DS2778 function as an accurate fuel
Gate drive to the protection FETs is disabled in sleep;
the SHA-1 authentication feature is not operational.
gauge, Li+ protector, and SHA-1-based authentication
token (SHA-1-based authentication available only on
The IC enters sleep mode under two different condi-
tions: bus low and undervoltage. An enable bit makes
entry into sleep optional for each condition. Sleep mode
the DS2776/DS2778). The fuel gauge provides accu-
rate estimates of remaining capacity and reports timely
voltage, temperature, and current measurement data.
Capacity estimates are calculated from a piecewise lin-
ear model of the battery performance over load and
temperature along with system parameters for charge
and end-of-discharge conditions. The algorithm para-
meters are user programmable and can be modified
within the pack. Critical capacity and aging data are
periodically saved to EEPROM in case of short-circuit
or deep-depletion events.
is not entered if a charger is connected (V
> V
+
PLS
DD
V
) or if a charge current of 1.6mV/R
measured
CD
SNS
from SNS to V . The DS2775–DS2778 exit sleep mode
SS
upon charger connection or a low-to-high transition on
any communication line. The bus-low condition, where
all communication lines are low for t
, indicates
SLEEP
pack removal or system shutdown in which the bus
pullup voltage, V , is not present. The power
PULLUP
mode (PMOD) bit must be set to enter sleep when a
bus-low condition occurs. After the DS2775–DS2778
enter sleep due to a bus-low condition, it is assumed
that no charge or discharge current flows and that
coulomb counting is unnecessary.
The Li+ protection function ensures safe, high-perfor-
mance operation. nFET protection switches are driven
with a charge pump that maintains gate drive as the
cell voltage decreases. The high-side topology pre-
serves the ground path for serial communication while
eliminating the parasitic charge path formed when the
fuel-gauge IC is located inside the protection FETs in a
low-side configuration. The thresholds for overvoltage,
undervoltage, overcurrent, and short-circuit current are
user programmable for customization to each cell and
application.
The second condition to enter sleep is an undervoltage
condition, which reduces battery drain due to the
DS2775–DS2778 supply current and prevents overdis-
charging the cell. The DS2775–DS2778 transition to
sleep mode if the V
or V
voltage is less than V
IN2 UV
IN1
and the undervoltage enable (UVEN) bit is set. The
communication bus must be in a static state, that is,
with DQ (SDA and SCL for 2-wire) either high or low for
The 32-bit-wide SHA-1 engine with 64-bit secret and
64-bit challenge words resists brute force and other
attacks with financial-level HMAC security. The chal-
lenge of managing secrets in the supply chain is
addressed with the compute next secret feature. The
unique serial number or ROM ID can be used to assign
a unique secret to each battery.
t
. The DS2775–DS2778 transition from sleep
SLEEP
mode to active mode when DQ (SDA and SCL for
2-wire) changes logic state. See Figures 1 and 2 for
more information on sleep-mode state.
The DS2775–DS2778 have a “power switch” capability
for waking the device and enabling the protection FETs
when the host system is powered down. A simple dry
contact switch on the PIO pin or DQ pin can be used to
wake up the battery pack. The power-switch function is
enabled using the PSPIO and PSDQ configuration bits
in the Control register.
Power Modes
The DS2775–DS2778 have two power modes: active
and sleep. On initial power-up, the DS2775–DS2778
default to active mode. In active mode, the DS2775–
DS2778 are fully functional with measurements and
capacity estimation registers continuously updated.
The protector circuit monitors battery pack, cell volt-
ages, and battery current for safe conditions. The pro-
tection FET gate drivers are enabled when conditions
are deemed safe. Also, the SHA-1 authentication func-
tion is available in active mode. When an SHA-1 com-
putation is performed, the supply current increases to
When PSPIO or PSDQ are set and sleep mode is
entered through the PMOD condition*, the PIO and DQ
pins pull high, respectively. Sleep mode is exited upon
the detection of a low-going transition on PIO or DQ.
PIO has a 100ms debounce period to filter out glitches
that can be caused when a sleeping battery is inserted
into a system.
I
for t
. In sleep mode, the DS2775–DS2778 con-
DD2
SHA
*The “power switch” feature is disabled if sleep mode is
entered because of a UV condition.
______________________________________________________________________________________ 11
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
ACTIVE
PMOD = 0
UVEN = 0
SLEEP
PSPIO = 0
PSDQ = X
RISING EDGE ON SDA OR SCL
CHARGER DETECT
ACTIVE
PMOD = 0
UVEN = 0
SLEEP
PSPIO = 0
PSDQ = 0
RISING EDGE ON DQ
CHARGER DETECT
V
IN1
OR V < V
IN2 UV
PULL DQ LOW
ACTIVE
PMOD = 0
UVEN = 1
SLEEP
PSPIO = 0
PSDQ = X
RISING EDGE ON SDA OR SCL
CHARGER DETECT
ACTIVE
PMOD = 0
UVEN = 1
SLEEP
PSPIO = 0
PSDQ = 1
V
IN1
OR V < V
IN2 UV
CHARGER DETECT
PULL PIO LOW
PULL PIO LOW
ACTIVE
PMOD = 1
UVEN = 0
SLEEP
PSPIO = 1
PSDQ = X
RISING EDGE ON SDA OR SCL
ACTIVE
PMOD = 1
UVEN = 0
SLEEP
PSPIO = 1
PSDQ = 0
PULL DQ LOW FOR t
SLEEP
CHARGER DETECT
RISING EDGE ON DQ
CHARGER DETECT
PULL SDA AND SCL LOW
FOR t
SLEEP
V
IN1
OR V < V
IN2 UV
PULL PIO LOW
PULL PIO LOW
PULL DQ LOW FOR t
SLEEP
ACTIVE
PMOD = 1
UVEN = 1
SLEEP
PSPIO = 1
PSDQ = X
ACTIVE
PMOD = 1
UVEN = 1
SLEEP
PSPIO = 1
PSDQ = 1
V
IN1
OR V < V
IN2
RISING EDGE ON SDA OR SCL
UV
CHARGER DETECT
PULL DQ LOW
CHARGER DETECT
56/DS278
PULL SDA AND SCL LOW
FOR t
SLEEP
Figure 1. Sleep-Mode State Diagram for DS2775/DS2776
Figure 2. Sleep-Mode State Diagram for DS2777/DS2778
Overvoltage (OV)
- V ) or (V - V
Li+ Protection Circuitry
If either of the voltages on (V
)
SS
IN2
IN1
IN1
During active mode, the DS2775–DS2778 constantly
exceeds the overvoltage threshold, V , for a period
OV
monitor SNS, V , V , and PLS to protect the battery
IN1 IN2
longer than overvoltage delay, t
, the CC pin is dri-
OVD
from overvoltage (overcharge), undervoltage (overdis-
charge), and excessive charge and discharge currents
(overcurrent, short circuit). Table 1 summarizes the
conditions that activate the protection circuit, the
response of the DS2775–DS2778, and the thresholds
that release the DS2775–DS2778 from a protection
state. Figure 3 shows Li+ protection circuitry example
waveforms.
ven low to shut off the external charge FET. The DC out-
put remains high during overvoltage to allow
discharging. When (V
- V ) and (V
- V ) falls
IN1 SS
IN2
IN1
below the charge-enable threshold, V , the
CE
DS2775–DS2778 turn the charge FET on by driving CC
high. The DS2775–DS2778 drive CC high before
[(V
- V ) and (V
- V )] < V
if a discharge
CE
IN2
IN1
IN1
SS
condition persists with V
≥ 1.2mV and [(V
- V
)
IN1
SNS
IN2
and (V
- V )] < V
.
IN1
SS
OV
12 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Table 1. Li+ Protection Conditions and DS2775/DS2776 Responses
ACTIVATION
CONDITION
RELEASE THRESHOLD
Both V < V or
THRESHOLD
DELAY
RESPONSE
CELL
CE
Overvoltage (OV) (Note 1)
V
V
> V
< V
t
t
CC Off
(V
V
ꢀ 1.2mV and both
SNS
CELL
CELL
OV
UV
OVD
< V ) (Note 1)
OV
CELL
V
> V
(charger connected)
IN2
PLS
CC Off, DC Off,
Sleep Mode (Note 2)
or (both V
> V and
UV
Undervoltage (UV) (Note 1)
Overcurrent, Charge (COC)
CELL
UVD
UVEN = 0) (Note 3)
V
< V – V
PLS
DD
TP
V
V
< V
t
t
CC Off, DC Off
SNS
SNS
COC
DOC
OCD
(charger removed) (Note 4)
Overcurrent, Discharge
(DOC)
V
PLS
> V – V
DD
TP
> V
DC Off
DC Off
OCD
(load removed) (Note 5)
V > V – V (Note 5)
PLS
Short Circuit (SC)
V
> V
t
SNS
SC
SCD
DD
TP
Note 1: V
is defined as (V
- V ) or (V
- V ).
IN2 IN1
CELL
IN1
SS
Note 2: Sleep mode is only entered if UVEN = 1.
Note 3: If V < V when a charger connection is detected, release is delayed until V
≥ V . The recovery charge path pro-
CELL
UV
CELL
UV
vides an internal current limit (I ) to safely charge the battery.
RC
Note 4: With test current I
Note 5: With test current I
flowing from PLS to V (pulldown on PLS) enabled.
PPD
TST
SS
flowing from V
to PLS (pullup on PLS).
DD
V
OV
V
CE
V
IN
V
UV
DISCHARGE
V
V
0
SC
DOC
V
SNS
-V
COC
OHCC
CP
CHARGE
CC
V
V
t
t
t
t
t
OVD
OVD
OCD
UVD
V
DD
V
V
CP
DC
t
t
OCD
SCO
UVD
PLS
ACTIVE
SLEEP*
POWER
MODE
*IF UVEN = 1.
Figure 3. Li+ Protection Circuitry Example Waveforms
______________________________________________________________________________________ 13
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
The DS2775–DS2778 provide a test current of value
from V to PLS, pulling PLS up, in order to detect
Undervoltage (UV)
If the average of the voltages on (V - V ) or
I
TST
DD
IN2
IN1
the removal of the offending low-impedance load.
(V
- V ) drops below the undervoltage threshold,
IN1
SS
V
, for a period longer than undervoltage delay, t
UV
,
UVD
Short Circuit (SC)
the DS2775–DS2778 shut off the charge and discharge
FETs. If UVEN is set, the DS2775–DS2778 also enter
If V
exceeds short-circuit threshold, V , for a
SC
SNS
period longer than short-circuit delay, t
, the
SCD
sleep mode. When a charger is detected and V
>
PLS
DS2775–DS2778 shut off the external discharge FET.
The discharge current path is not reestablished until
V
, the DS2775–DS2778 provide a current-limited
IN2
recovery charge path (I ) from PLS to V
to gently
DD
RC
the voltage on PLS rises above (V
- V ). The
DD
TP
charge severely depleted cells. The recovery charge
path is enabled when 0 ≤ [(V - V ) and (V
DS2775–DS2778 provide a test current of value I
TST
-
IN1
IN2
IN1
IN2 IN1
from V
to PLS, pulling PLS up, in order to detect the
DD
V
)] < V . The FETs remain off until (V
- V ) and
SS
CE
removal of the short circuit.
(V
IN1
- V ) exceed V
.
SS
UV
All the protection conditions described are logic
ANDed to affect the CC and DC outputs.
Overcurrent, Charge Direction (COC)
Charge current develops a negative voltage on V
SNS
CC = (overvoltage) AND (undervoltage) AND
(overcurrent, charge direction) AND (Protection register
bit CE = 0)
with respect to V . If V
is less than the charge
SS
SNS
overcurrent threshold, V
, for a period longer than
COC
overcurrent delay, t
, the DS2775–DS2778 shut off
OCD
DC = (undervoltage) AND (overcurrent, either direction)
AND (short circuit) AND (Protection register bit
DE = 0)
both external FETs. The charge current path is not re-
established until the voltage on the PLS pin drops
below (V
- V ). The DS2775–DS2778 provide a test
TP
DD
current of value I
from PLS to V , pulling PLS
SS
PPD
Voltage Measurements
Cell voltages are measured every 440ms. The lowest
down, in order to detect the removal of the offending
charge current source.
potential cell, V , is measured with respect to V
.
SS
IN1
Overcurrent, Discharge Direction (DOC)
The highest potential cell, V
, is measured with
IN2
Discharge current develops a positive voltage on V
SNS
respect to V . Battery voltages are measured with a
IN1
with respect to V . If V
exceeds the discharge
SS
SNS
range of -5V to +4.9951V and a resolution of 4.8828mV
and placed in the Result register in two’s complement
form. Voltages above the maximum register value are
reported as 7FE0h.
overcurrent threshold, V
, for a period longer than
DOC
t
, the DS2775–DS2778 shut off the external dis-
OCD
charge FET. The discharge current path is not reestab-
56/DS278
lished until the voltage on PLS rises above (V
- V ).
TP
DD
MSB - ADDRESS 0Ch, V
- V
LSB - ADDRESS 0Dh, V
- V
SS
IN1
SS
IN1
MSB - ADDRESS 1Ch, V
- V
5
LSB - ADDRESS 1Dh, V
1 0
- V
X
IN2
IN1
IN2
IN1
9
8
7
6
4
3
2
S
2
2
2
2
2
2
2
2
2
2
X
X
X
X
MSb
LSb
MSb
UNITS: 4.883mV
LSb
“S”: SIGN BIT(S), “X”: RESERVED
Figure 4. Voltage Register Format
14 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
1.5625µV. The input linearly converts peak signal ampli-
Temperature Measurement
tudes up to 102.4mV as long as the continuous signal
The DS2775–DS2778 use an integrated temperature
level (average over the conversion cycle period) does
sensor to measure battery temperature with a resolution
not exceed 51.2mV. The ADC samples the input differ-
of 0.125°C. Temperature measurements are updated
entially at 18.6kHz and updates the Current register at
every 440ms and placed in the Temperature register in
the completion of each conversion cycle (3.52s). Charge
two’s complement form.
currents above the maximum register value are reported
as 7FFFh. Discharge currents below the minimum regis-
Current Measurement
In active mode, the DS2775–DS2778 continuously mea-
ter value are reported as 8000h.
The Average Current register reports an average cur-
rent level over the preceding 28.16s. The register value
is updated every 28.16s in two’s complement form and
represents an average of the eight preceding Current
register values.
sure the current flow into and out of the battery by mea-
suring the voltage drop across a low-value current-sense
resistor, R
. The voltage-sense range between SNS
SNS
and V is 51.2mV with a least significant bit (LSb) of
SS
MSB—ADDRESS 0Ah
LSB—ADDRESS 0Bh
9
8
7
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
2
2
2
X
X
X
X
X
MSb
LSb
MSb
UNITS: 0.125°C
LSb
“S”: SIGN BIT(S), “X”: RESERVED
Figure 5. Temperature Register Format
MSB—ADDRESS 0Eh
LSB—ADDRESS 0Fh
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 1.5625μV/R
LSb
“S”: SIGN BIT(S)
SNS
Figure 6. Current Register Format
MSB—ADDRESS 08h
LSB—ADDRESS 09h
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 1.5625μV/R
LSb
“S”: SIGN BIT(S)
SNS
Figure 7. Average Current Register Format
______________________________________________________________________________________ 15
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Current Offset Correction
Current Blanking
Every 1024th conversion, the ADC measures its input
offset to facilitate offset correction. Offset correction
occurs approximately once per hour. The resulting cor-
rection factor is applied to the subsequent 1023 mea-
surements. During the offset correction conversion, the
ADC does not measure the sense resistor signal. A
maximum error of 1/1024 in the Accumulated Current
register (ACR) is possible; however, to reduce the error,
the current measurement made just prior to the offset
conversion is retained in the Current register and is
substituted for the dropped current measurement in the
current accumulation process. Therefore the accumu-
lated current error due to offset correction is typically
much less than 1/1024.
The current blanking feature modifies current measure-
ment result prior to being accumulated in the ACR.
Current blanking occurs conditionally when a current
measurement (raw current and COBR) falls in one of
two defined ranges. The first range prevents charge
currents less than 100µV from being accumulated. The
second range prevents discharge currents less than
25µV in magnitude from being accumulated. Charge
current blanking is always performed; however, dis-
charge current blanking must be enabled by setting the
NBEN bit in the Control register. See the Control
Register Format description for additional information.
Current Measurement Gain
The DS2775–DS2778’s current measurement gain can
be adjusted through the RSGAIN register, which is facto-
ry calibrated to meet the data sheet specified accuracy.
RSGAIN is user accessible and can be reprogrammed
after module or pack manufacture to improve the current
measurement accuracy. Adjusting RSGAIN can correct
for variation in an external sense resistor’s nominal value
and allows the use of low-cost, nonprecision current-
sense resistors. RSGAIN is an 11-bit value stored in 2
bytes of the parameter EEPROM memory block. The
RSGAIN value adjusts the gain from 0 to 1.999 in steps
of 0.001 (precisely 2–10). The user must use caution
when programming RSGAIN to ensure accurate current
measurement. When shipped from the factory, the gain
calibration value is stored in two separate locations in the
parameter EEPROM block, RSGAIN, which is reprogram-
mable and FRSGAIN, which is read-only. RSGAIN deter-
mines the gain used in the current measurement. The
Current Offset Bias
The current offset bias value (COB) allows a program-
mable offset value to be added to raw current measure-
ments. The result of the raw current measurement plus
COB is displayed as the current measurement result in
the Current register and is used for current accumula-
tion. COB can be used to correct for a static offset error
or can be used to intentionally skew the current results
and therefore the current accumulation. Read and write
access is allowed to COB. Whenever the COB is writ-
ten, the new value is applied to all subsequent current
measurements. COB can be programmed in 1.56µV
steps to any value between -199.7µV and +198.1µV.
The COBR value is stored as a two’s complement value
in volatile memory and must be initialized through the
interface on power-up. The factory default value is 00h.
56/DS278
ADDRESS 7Bh
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
MSb
LSb
UNITS: 1.56μV/R
“S”: SIGN BIT(S)
SNS
Figure 8. Current Offset Bias Register Format
MSB—ADDRESS 78h
LSB—ADDRESS 79h
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
X
SC0
OC1
OC0
X
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 2–10
LSb
“X”: RESERVED
Figure 9. RSGAIN Register
16 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
FRSGAIN value is provided to preserve the factory cali-
bration value only and is not used to calibrate the current
measurement. The 16-bit FRSGAIN value is readable
from addresses B0h and B1h.
with the results displayed in the Accumulated Current
register (ACR). The accuracy of the ACR is dependent
on both the current measurement and the conversion
time base. The ACR has a range of 0 to +409.6mVh
with an LSb of 6.25µVh. Additional registers hold frac-
tional results of each accumulation to avoid truncation
errors. The fractional result bits are not user accessible.
Accumulation of charge current above the maximum
register value is reported at the maximum value; con-
versely, accumulation of discharge current below the
minimum register value is reported at the minimum
value.
Sense-Resistor Temperature
Compensation
The DS2775–DS2778 can temperature compensate the
current-sense resistor to correct for variation in a sense
resistor’s value over temperature. The DS2775–DS2778
are factory programmed with the sense-resistor temper-
ature coefficient, RSTC, set to zero, which turns off the
temperature compensation function. RSTC is user
accessible and can be reprogrammed after module or
pack manufacture to improve the current accuracy
when using a high-temperature coefficient current-
sense resistor. RSTC is an 8-bit value stored in the
parameter EEPROM memory block. The RSTC value
sets the temperature coefficient from 0 to +7782ppm/°C
in steps of 30.5ppm/°C. The user must program RSTC
cautiously to ensure accurate current measurement.
Charge currents (positive Current register values) less
than 100µV are not accumulated in order to mask the
effect of accumulating small positive offset errors over
long periods. This effect limits the minimum charge cur-
rent, for coulomb counting purposes, to 5mA for R
SNS
= 0.020Ω and 20mA for R
= 0.005Ω (see Table 2 for
SNS
more details).
Read and write access is allowed to the ACR. The
ACR must be written most significant byte (MSB) first,
then LSB. Whenever the ACR is written, the fractional
accumulation result bits are cleared. The write must
be completed in 3.5s. A write to the ACR forces the
ADC to perform an offset correction conversion and
update the internal offset correction factor. The cur-
rent measurement and accumulation begin with the
second conversion following a write to the ACR. To
preserve the ACR value in case of power loss, the
ACR value is backed up to EEPROM. The ACR value
is recovered from EEPROM on power-up. See the
Memory Map for specific address location and back-
up frequency.
Temperature compensation adjustments are made when
the Temperature register crosses 0.5°C boundaries. The
temperature compensation is most effective with the
resistor placed as close as possible to the V terminal
SS
to optimize thermal coupling of the resistor to the on-chip
temperature sensor. If the current shunt is constructed
with a copper PCB trace, run the trace under the
DS2775–DS2778 package whenever possible.
Current Accumulation
Current measurements are internally summed, or accu-
mulated, at the completion of each conversion period
MSB—ADDRESS 10h
LSB—ADDRESS 11h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 6.25μV/R
LSb
SNS
Figure 10. Accumulated Current Register Format
Table 2. Resolution and Range vs. Sense Resistor
R
SNS
TYPE OF RESOLUTION/RANGE
V
- V
SS SNS
20mꢀ
78.13μA
2.56A
15mꢀ
10mꢀ
156.3μA
5.12A
5mꢀ
Current Resolution
Current Range
ACR Resolution
ACR Range
1.5625μV
51.2mV
104.2μA
3.41A
312.5μA
10.2A
6.25μVh
409.6mVh
312.5μAh
20.48Ah
416.7μAh
27.30Ah
625μAh
1.250mAh
81.92Ah
40.96Ah
______________________________________________________________________________________ 17
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Accumulation Bias
Modeling Cell Characteristics
In some designs a systematic error or an application
preference requires the application of an arbitrary bias
to the current accumulation process. The Current
Accumulation Bias register (CAB) allows a user-pro-
grammed constant positive or negative polarity bias to
be included in the current accumulation process. The
value in CAB can be used to estimate battery currents
that do not flow through the sense resistor, estimate
battery self-discharge, or estimate current levels below
the current measurement resolution. The user-pro-
grammed two’s complement value, with bit weighting
the same as the current register, is added to the ACR
once per current conversion cycle. CAB is loaded on
power-up from EEPROM memory.
To achieve reasonable accuracy in estimating remain-
ing capacity, the cell performance characteristics over
temperature, load current, and charge-termination point
must be considered. Since the behavior of Li+ cells is
nonlinear, these characteristics must be included in the
capacity estimation to achieve an acceptable level of
accuracy in the capacity estimation. The FuelPack
method used in the DS2775–DS2778 is described in
general in Application Note 131: Lithium-Ion Cell Fuel
Gauging with Maxim Battery Monitor ICs. To facilitate
efficient implementation in hardware, a modified version
of the method outlined in Application Note 131 is used
to store cell characteristics in the DS2775–DS2778. Full
and empty points are retrieved in a lookup process that
retraces a piecewise linear model consisting of three
model curves named full, active empty, and standby
empty. Each model curve is constructed with five line
segments, numbered 1 through 5. Above +40°C, the
segment 5 model curves extend infinitely with zero
slope, approximating the nearly flat change in capacity
of Li+ cells at temperatures above +40°C. Segment 4 of
each model curves originates at +40°C on its upper end
and extends downward in temperature to the junction
with segment 3. Segment 3 joins with segment 2, which
in turn joins with segment 1. Segment 1 of each model
curve extends from the junction with segment 2 to infi-
nitely colder temperatures. The three junctions or break-
points that join the segments (labeled TBP12, TBP23,
and TBP34 in Figure 14) are programmable in 1°C
increments from -128°C to +40°C. The slope or deriva-
tive for segments 1, 2, 3, and 4 are also programmable
over a range of 0 to 15,555ppm in steps of 61ppm.
Cycle Counter
The cycle counter is an absolute count of the cumula-
tive discharge cycles. This register is intended to act as
a “cell odometer.” The LSb is two cycles, which allows
a maximum count of 510 discharge cycles. The register
does not loop. Once the maximum value is reached,
the register is clamped. This register is read and write
accessible while the parameter EEPROM memory block
(block 1) is unlocked. The Cycle Count register
becomes read-only once the EEPROM block is locked.
Capacity Estimation Algorithm
Remaining capacity estimation uses real-time mea-
sured values and stored parameters describing the cell
characteristics and application operating limits. Figure
13 describes the algorithm inputs and outputs.
56/DS278
ADDRESS 61h
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
MSb
LSb
UNITS: 6.25μV/R
“S”: SIGN BIT(S)
SNS
Figure 11. Current Accumulation Bias Register Format
ADDRESS 1Eh
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
MSb
LSb
UNITS: 2 cycles
Figure 12. Cycle Counter Register Format
18 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
VOLTAGE
(R)
(R)
(R)
FULL
FULL(T)
AE(T)
(R)
(R)
(R)
TEMPERATURE
CURRENT
ACTIVE EMPTY
CAPACITY LOOKUP
AVAILABLE CAPACITY CALCULATION
ACR HOUSEKEEPING
STANDBY EMPTY SE(T)
ACCUMULATED
CURRENT (ACR) (RW)
REMAINING ACTIVE-ABSOLUTE
CAPACITY (RAAC) mAh
(R)
AGE ESTIMATOR
REMAINING STANDBY-ABSOLUTE
CAPACITY (RSAC) mAh
(R)
LEARN FUNCTION
AVERAGE CURRENT
(R)
REMAINING ACTIVE-RELATIVE
CAPACITY (RARC) %
(R)
(R)
REMAINING STANDBY-RELATIVE
CAPACITY (RSRC) %
CELL MODEL PARAMETERS
(EEPROM)
USER MEMORY (EEPROM)
16 BYTES
AGING CAPACITY (AC)
(2 BYTES EE)
AGE SCALAR (AS)
(1 BYTE EE)
CYCLE COUNTER (EEPROM)
SENSE-RESISTOR PRIME (RSNSP)
(1 BYTE EE)
CHARGE VOLTAGE (VCHG)
(1 BYTE EE)
MINIMUM CHARGE CURRENT (IMIN)
(1 BYTE EE)
ACTIVE-EMPTY VOLTAGE (VAE)
(1 BYTE EE)
ACTIVE-EMPTY CURRENT (IAE)
(1 BYTE EE)
Figure 13. Top-Level Algorithm Diagram
Full
Active Empty
The active-empty curve defines the variation of the
active-empty point over temperature. The active-empty
point is defined as the minimum voltage required for
system operation at a discharge rate based on a high-
level load current (one that is sustained during a high-
power operating mode). This load current is
programmed as the active-empty current (IAE), and
should be a 3.5s average value to correspond to values
The full curve defines how the full point of a given cell
depends on temperature for a given charge termina-
tion. The application’s charge termination method
should be used to determine the table values. The
DS2775–DS2778 reconstruct the full line from cell char-
acteristic table values to determine the full capacity of
the battery at each temperature. Reconstruction occurs
in one-degree temperature increments.
______________________________________________________________________________________ 19
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
SEGMENT 1
SEGMENT 2
SEGMENT 3
SEGMENT 4
SEGMENT 5
100%
FULL
DERIVATIVE
(ppm/°C)
CELL
CHARACTERIZATIONDATA
ACTIVE
EMPTY
STANDBY
EMPTY
TBP12
TBP23
TBP34
+40°C
Figure 14. Cell Model Example Diagram
56/DS278
read from the Current register. The specified minimum
voltage, or active-empty voltage (VAE), should be a
110ms average value to correspond to the values read
from the voltage register. The VAE value represents the
thus the standby voltage is set by the minimum DRAM
voltage-supply requirements. In other applications,
standby empty can represent the point that the battery
can no longer support a subset of the full application
operation, such as games or organizer functions. The
standby-load current and voltage are used for deter-
mining the cell characteristics but are not programmed
into the DS2775–DS2778. The DS2775–DS2778 recon-
struct the standby-empty line from the cell characteris-
tic table to determine the standby-empty capacity of
the battery at each temperature. Reconstruction occurs
in one-degree temperature increments.
average of the two cell’s voltages, V
and V . The
IN2
IN1
DS2775–DS2778 reconstruct the active-empty line from
the cell characteristic table to determine the active-
empty capacity of the battery at each temperature.
Reconstruction occurs in one-degree temperature
increments.
Standby Empty
The standby-empty curve defines the variation of the
standby-empty point over temperature. The standby-
empty point is defined as the minimum voltage required
for standby operation at a discharge rate dictated by
the application standby current. In typical handheld
applications, standby empty represents the point that
the battery can no longer support DRAM refresh and
Cell Model Construction
The model is constructed with all points normalized to
the fully charged state at +40°C. All values are stored in
the cell parameter EEPROM block. The +40°C full value
is stored in µVh with an LSb of 6.25µVh. The +40°C
active-empty value is stored as a percentage of +40°C
20 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
-10
full with a resolution of 2 . Standby empty at +40°C is,
Application Parameters
by definition, zero and therefore no storage is required.
In addition to cell model characteristics, several appli-
The slopes (derivatives) of the four segments for each
cation parameters are needed to detect the full and
model curve are stored in the cell parameter EEPROM
empty points, as well as calculate results in mAh units.
block as ppm/°C. The breakpoint temperatures of each
segment are stored there also (refer to Application Note
Sense Resistor Prime (RSNSP)
3584: Storing Battery Fuel Gauge Parameters in
DS2780 for more details on how values are stored). An
example of data stored in this manner is shown in
Table 3.
RSNSP stores the value of the sense resistor for use in
computing the absolute capacity results. The value is
stored as a 1-byte conductance value with units of
mhos (1/Ω). RSNSP supports resistor values of 1Ω to
3.922mΩ. RSNSP is located in the parameter EEPROM
block.
RSNSP = 1/R
(units of mhos; 1/Ω)
SNS
CELL MODEL
PARAMETERS
FULL(T)
AE(T)
Charge Voltage (VCHG)
LOOKUP
FUNCTION
VCHG stores the charge voltage threshold used to
detect a fully charged state. The voltage is stored as a
1-byte value with units of 19.5mV and can range from 0
to 4.978V. VCHG should be set marginally less than the
average cell voltage at the end of the charge cycle to
ensure reliable charge termination detection. VCHG is
located in the parameter EEPROM block.
(EEPROM)
SE(T)
TEMPERATURE
Figure 15. Lookup Function Diagram
Table 3. Example Cell Characterization Table (Normalized to +40°C)
Manufacturer’s Rated Cell Capacity: 1000mAh
Charge Voltage: 4.2V
Active Empty (V): 3.0V
Sense Resistor: 0.020ꢀ
Termination Current: 50mA
Standby Empty (I): 300mA
SEGMENT BREAKPOINTS
TBP12 = -12°C
TBP23 = 0°C
TBP34 = 18°C
+40°C NOMINAL
(mAh)
SEGMENT 1
(ppm/°C)
SEGMENT 2
(ppm/°C)
SEGMENT 3
(ppm/°C)
SEGMENT 4
(ppm/°C)
CALCULATED VALUE
Full
1051
3601
2380
1404
3113
1099
427
1163
671
854
305
183
Active Empty
Standby Empty
244
______________________________________________________________________________________ 21
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
time of pack manufacture to allow the learning of a larg-
er capacity on batteries that have an initial capacity
greater than the rated cell capacity programmed in the
cell characteristic table. The AS is modified by aging
estimation introduced under aging capacity and by the
learn function.
Minimum Charge Current (IMIN)
IMIN stores the charge-current threshold used to detect
a fully charged state. It is stored as a 1-byte value with
units of 50µV (IMIN x R
) and can range from 0 to
SNS
12.75mV. Assuming R
= 20mΩ, IMIN can be pro-
SNS
grammed from 0 to 637.5mA in 2.5mA steps. IMIN
should be set marginally greater than the charge cur-
rent at the end of the charge cycle to ensure reliable
charge termination detection. IMIN is located in the
parameter EEPROM block.
Batteries are typically considered worn out when the full
capacity reaches 80% of the rated capacity; therefore,
the AS value is not required to range to 0%. It is
clamped to 50% (64 decimal or 40h). If a value of 50%
is read from the AS, the host should prompt the user to
initiate a learning cycle.
Active-Empty Voltage (VAE)
VAE stores the voltage threshold used to detect the
active-empty point. The value is stored in 1 byte with
units of 19.5mV and can range from 0 to 4.978V. VAE is
stored as an average of the cell’s voltages. VAE is locat-
ed in the parameter EEPROM block. See the Modeling
Cell Characteristics section for more information.
The host system has read and write access to the AS;
however, caution should be exercised when writing it to
ensure that the cumulative aging estimate is not over-
written with an incorrect value. The AS is automatically
saved to EEPROM. The EEPROM value is recalled on
power-up.
Active-Empty Current (IAE)
IAE stores the discharge-current threshold used to
detect the active-empty point. The unsigned value rep-
resents the magnitude of the discharge current and is
stored in 1 byte with units of 200µV and can range from
Capacity Estimation Operation
Cycle-Count-Based Aging Estimation
As previously discussed, the AS register value is
adjusted occasionally based on cumulative discharge.
As the ACR register decrements during each discharge
cycle, an internal counter is incremented until equal to
32 times the AC. The AS is then decremented by one,
resulting in a decrease of the scaled full battery capaci-
ty by 0.78% (approximately 2.4% per 100 cycles). The
internal counter is reset in the event of a learn cycle.
See the Aging Capacity (AC) section for recommenda-
tions on customizing the age estimation rate.
0 to 51.2mV. Assuming R
= 20mΩ, IAE can be pro-
SNS
grammed from 0 to 2550mA in 10mA steps. IAE is locat-
ed in the parameter EEPROM block. See the Modeling
Cell Characteristics section for more information.
Aging Capacity (AC)
AC stores the rated cell capacity, which is used to esti-
mate the decrease in battery capacity that occurs dur-
ing normal use. The value is stored in 2 bytes in the
same units as the ACR (6.25µVh). When set to the man-
ufacturer’s rated cell capacity, the aging estimation rate
is approximately 2.4% per 100 cycles of equivalent full
capacity discharges. Partial discharge cycles are
added to form equivalent full capacity discharges. The
default aging estimation results in 88% capacity after
500 equivalent cycles. The aging estimation rate can
be adjusted by setting the AC to a value other than the
cell manufacturer’s rating. Setting AC to a lower value
accelerates the aging estimation rate. Setting AC to a
higher value retards the aging estimation rate. The AC
is located in the parameter EEPROM block.
56/DS278
Learn Function
Because Li+ cells exhibit charge efficiencies near unity,
the charge delivered to a Li+ cell from a known empty
point to a known full point is a dependable measure of
the cell’s capacity. A continuous charge from empty to
full results in a learn cycle. First, the active-empty point
must be detected. The learn flag (LEARNF) is set at this
point. Then, once charging starts, the charge must con-
tinue uninterrupted until the battery is charged to full.
Upon detecting full, the LEARNF is cleared, the charge-
to-full (CHGTF) flag is set, and the AS is adjusted
according to the learned capacity of the cell.
Age Scalar (AS)
AS adjusts the cell capacity estimation results down-
ward to compensate for aging. The AS is a 1-byte value
that has a range of 49.2% to 100%. The LSb is weight-
Full capacity estimation based on the learn function is
more accurate than the cycle-count-based estimation
introduced under aging capacity. The learn function
reflects the current performance of the cell. Cycle-
count-based estimation is an approximation derived
from the manufacturer’s recommendation for a typical
cell. Therefore, the internal counter used for cycle-
-7
ed at 0.78% (precisely 2 ). A value of 100% (128 deci-
mal or 80h) represents an unaged battery. A value of
95% is recommended as the starting AS value at the
22 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
count-based estimation is reset after a learn cycle. The
cycle-count-based estimation is used only in the
absence of a learn cycle.
level with the discharge rate ensures that the active-
empty point is not detected at loads much lighter than
those used to construct the model. Also, the active-
empty point must not be detected when a deep dis-
charge at a very light load is followed by a load greater
than IAE. Either case would cause a learn cycle on the
following charge to include part of the standby capacity
in the measurement of the active capacity. Active-
empty point detection sets the learn flag (LEARNF) bit
in the Status register.
ACR Housekeeping
The ACR value is adjusted occasionally to maintain the
coulomb count within the model curve boundaries. When
the battery is charged to full (CHGTF set), the ACR is set
equal to the age-scaled full lookup value at the present
temperature. If a learn cycle is in progress, correction of
the ACR value occurs after the AS is updated. When an
empty condition is detected (LEARNF and/or AEF set),
the ACR adjustment is conditional:
Note: Do not confuse the active-empty point with the
active-empty flag. The active-empty flag is set only
when the VAE threshold is passed.
• If the AEF is set and the LEARNF is not set, the
active-empty point was not detected. The battery is
likely below the active-empty capacity of the model.
The ACR is set to the active-empty model value at
present temperature only if it is greater than the
active-empty model value at present temperature.
Result Registers
The DS2775–DS2778 process measurement and cell
characteristics on a 3.5s interval and yield seven result
registers. The result registers are sufficient for direct
display to the user in most applications. The host sys-
tem can produce customized values for system use or
user display by combining measurement, result, and
user EEPROM values.
• If the AEF is set, the LEARNF is not set, and the ACR
is below the active-empty model value at present
temperature, the ACR is not updated.
• If the LEARNF is set, the battery is at the active-
empty point and the ACR is set to the active-empty
model value.
FULL(T)
The full capacity of the battery at the present tempera-
ture is reported normalized to the +40°C full value. This
15-bit value reflects the cell model full value at the
given temperature. The FULL(T) register reports values
between 100% and 50% with a resolution of 61ppm
Full Detect
Full detection occurs when the average of V
IN2
and
IN1
V
voltage registers remain continuously above the
-14
(precisely 2 ). Though the register format permits val-
charge voltage (VCHG) threshold for the duration of two
average current (IAVG) readings, and both IAVG read-
ings are below terminating current (IMIN). The two con-
secutive IAVG readings must also be positive and
nonzero (>16 LSB). This ensures that removing the bat-
tery from the charger does not result in a false detec-
tion of full. Full detect sets the charge to full (CHGTF)
bit in the Status register.
ues greater than 100%, the register value is clamped to
a maximum value of 100%.
Active Empty, AE(T)
The active-empty capacity of the battery at the present
temperature is reported normalized to the +40°C full
value. This 13-bit value reflects the cell model active-
empty value at the given temperature. The AE(T) regis-
ter reports values between 0% and 49.8% with a
Active-Empty Point Detect
-14
resolution of 61ppm (precisely 2 ).
Active-empty point detection occurs when the average
of V
and V
voltage registers drops below the VAE
IN2
IN1
Standby Empty, SE(T)
The standby-empty capacity of the battery at the pre-
sent temperature is reported normalized to the +40°C
full value. This 13-bit value reflects the cell model
standby-empty value at the current temperature. The
SE(T) register reports values between 0% and 49.8%
threshold and the two previous current readings are
above IAE. This captures the event of the battery reach-
ing the active-empty point. Note that the two previous
current readings must be negative and greater in mag-
nitude than IAE (i.e., a larger discharge current than
specified by the IAE threshold). Qualifying the voltage
-14
with a resolution of 61ppm (precisely 2 ).
______________________________________________________________________________________ 23
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
MSB—ADDRESS 02h
LSB—ADDRESS 03h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 1.6mAh
LSb
Figure 16. Remaining Active Absolute Capacity (RAAC) [mAh]
The RAAC register reports the capacity available under the current temperature conditions to the the active-empty
point in absolute units of milliamps/hour (mAh). RAAC is 16 bits.
MSB—ADDRESS 04h
LSB—ADDRESS 05h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
UNITS: 1.6mAh
LSb
Figure 17. Remaining Standby Absolute Capacity (RSAC) [mAh]
The RSAC register reports the remaining battery capacity available under the current temperature conditions to the
standby-empty point capacity in absolute units of milliamps/hour (mAh). RSAC is 16 bits.
MSB–ADDRESS 06h
15
14
13
12
11
10
9
8
2
2
2
2
2
2
2
2
MSb
LSb
UNITS: 1%
Figure 18. Remaining Active Relative Capacity (RARC) [%]
56/DS278
The RARC register reports the remaining battery capacity available under the current temperature conditions to the
active-empty point in relative units of percent (%). RARC is 8 bits.
MSB–ADDRESS 07h
15
14
13
12
11
10
9
8
2
2
2
2
2
2
2
2
MSb
LSb
UNITS: 1%
Figure 19. Remaining Standby Relative Capacity (RSRC) [%]
The RSRC register reports the remaining battery capacity available under the current temperature conditions to the
standby-empty point capacity in relative units of percent (%). RSRC is 8 bits.
Calculation of Results
RAAC [mAh] = (ACR[mVh] - AE(T) x FULL40[mVh]) x RSNSP [mhos]*
RSAC [mAh] = (ACR[mVh] - SE(T) x FULL40[mVh]) x RSNSP [mhos]*
RARC [%] = 100% x (ACR[mVh] - AE(T) x FULL40[mVh])/{(AS x FULL(T) - AE(T)) x FULL40[mVh]}
RSRC [%] = 100% x (ACR[mVh] - SE(T) x FULL40[mVh])/{(AS x FULL(T) - SE(T)) x FULL40[mVh]}
*RSNSP = 1/R
SNS
24 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Protection, Status, and Control Registers
Protection Register Format
The Protection register reports events detected by the Li+ safety circuit on bits [3:2]. Bits 0 and 1 are used to disable
the charge and discharge FET gate drivers. Bits [3:2] are set by internal hardware only. Bits 2 and 3 are cleared by
hardware only. Bits 0 and 1 are set on power-up and a transition from sleep to active modes. While in active mode,
these bits can be cleared to disable the FET gate drive of either or both FETs. Setting these bits only turns on the
FETs if there are no protection faults.
Protection Register (00h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
CC
DC
CE
DE
Bits 7 to 4: Reserved.
Bit 3: Charge Control Flag (CC). CC indicates the logic state of the CC pin driver. The CC flag is set to indicate CC
high and is cleared to indicate CC low. The CC flag is read-only.
Bit 2: Discharge Control Flag (DC). DC indicates the logic state of the DC pin driver. DC flag is set to indicate DC
high and is cleared to indicate DC low. DC flag is read-only.
Bit 1: Charge-Enable Bit (CE). CE must be set to allow the CC pin to drive the charge FET to the on state. CE acts
as an enable input to the safety circuit. If all safety conditions are met and CE is set, the CC pin drives to V . If CE
CP
is cleared, the CC pin is driven low to disable the charge FET. The power-up default state of CE is 1.
Bit 0: Discharge-Enable Bit (DE). DE must be set to allow the DC pin to drive the discharge FET to the on state. DE
acts as an enable input to the safety circuit. If all safety conditions are met and DE is set, the DC pin drives to V . If
CP
DE is cleared, the DC pin is driven low to disable the discharge FET. The power-up default state of DE is 1.
______________________________________________________________________________________ 25
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Status Register Format
The Status register contains bits that report the device status. All bits are set internally. The CHGTF, AEF, SEF, and
LEARNF bits are read-only.
Status Register (01h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CHGTF
AEF
SEF
LEARNF
X
X
X
X
Bit 7: Charge-Termination Flag (CHGTF). CHGTF is set to indicate that the average of the voltages on V
IN2
and
IN1
V
and the Average Current register values have persisted above the VCHG and below the IMIN thresholds suffi-
ciently long enough to detect a fully charged condition. CHGTF is cleared when RARC is less than 90%. CHGTF is
read-only.
Bit 6: Active-Empty Flag (AEF). AEF is set to indicate that the battery is at or below the active-empty point. AEF is
set when the average of the voltages on V
greater than 5%. AEF is read-only.
and V
is less than the VAE threshold. AEF is cleared when RARC is
IN2
IN1
Bit 5: Standby-Empty Flag (SEF). SEF is set to indicate RSRC is less than 10%. SEF is cleared when RSRC is
greater than 15%. SEF is read-only.
Bit 4: Learn Flag (LEARNF). LEARNF indicates that the current-charge cycle can be used to learn the battery
capacity. LEARNF is set when the active-empty point is detected. This occurs when the average of the voltages on
V
and V
drops below the VAE threshold and the two previous current register values were negative and
IN2
IN1
greater in magnitude than the IAE threshold. See the Active-Empty Point Detect section for additional information.
LEARNF is cleared when any of the following occur:
1) Learn cycle completes (CHGTF set).
2) Current register value becomes negative indicating discharge current flow.
3) ACR = 0.
4) ACR value is written or recalled from EEPROM.
5) Sleep mode is entered.
56/DS278
LEARNF is read-only.
Bit 3 to 0: Reserved.
26 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Control Register Format
All Control register bits are read and write accessible. The Control register is recalled from parameter EEPROM
memory at power-up. Register bit values can be modified in shadow RAM after power-up. Power-up default values
are saved by using the Copy Data command.
Control Register (60h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NBEN
UVEN
PMOD
RNAOP
VUV1
VUV0
PSPIO
PSDQ
Bit 7: Negative Blanking Enable (NBEN). A value of 1 enables blanking of negative current values up to 25µV. A
value of 0 disables blanking of negative currents. The power-up default of NBEN = 0.
Bit 6: Undervoltage Enable (UVEN). A value of 1 allows the DS2775–DS2778 to enter sleep mode when the aver-
age of the voltages on V
and V
is less than V
and DQ is stable at either logic level for t
. A value of 0
IN1
IN2
UV
SLEEP
disables transitions to sleep mode during an undervoltage condition.
Bit 5: Power-Mode Enable (PMOD). A value of 1 allows the DS2775–DS2778 to enter sleep mode when DQ is low
for t . A value of 0 disables DQ-related transitions to sleep mode.
SLEEP
Bit 4: Read Net Address Op Code (RNAOP). A value of 0 selects 33h as the op code value for the Read Net
Address command. A value of 1 selects 39h as the op code value for the Read Net Address command.
Bit 3 and 2: Undervoltage Threshold (VUV[1:0]). Sets the voltage at which the part detects an undervoltage condi-
tion according to Table 4.
Bit 1: Power-Switch PIO Enable (PSPIO). A value of 1 enables the PIO pin as a power-switch input. A value of 0
disables the power-switch input function on PIO pin. This control is independent of the PSDQ state.
Bit 0: Power-Switch DQ Enable (PSDQ). A value of 1 enables the DQ pin as a power-switch input. A value of 0 dis-
ables the power-switch input function on DQ pin. This control is independent of the PSPIO state. This bit has no
effect in the DS2777/DS2778.
Table 4. Undervoltage Threshold
VUV[1:0] BIT FIELD
V
(V)
UV
0 0
0 1
1 0
1 1
2.00
2.30
2.45
2.60
______________________________________________________________________________________ 27
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Overvoltage Threshold Register Format
The 8-bit Overvoltage Threshold register (VOV) sets the overvoltage threshold for the protection circuitry. An over-
voltage condition is detected if either of the voltages on V
or V
exceeds the OV threshold for t
. The LSB of
IN1
IN2
OVD
the VOV register is 2 x 5V/1024 = 31.25mV. The V set point can be calculated by the following formula.
OV
V
OV
= (678 + 2 x Overvoltage_Threshold_Register_Value) x 5V/1024
Example:
Overvoltage Threshold register = 1110110b = 118D
V
OV
= (678 + 2 x 118) x 5V/1024 = 4.46289V
Overvoltage Threshold Register (7Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
VOV6
VOV5
VOV4
VOV3
VOV2
VOV1
VOV0
Table 5. VOV Register Programmability
VOV[6:0] BIT FIELD
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 0
0 0 0 0 0 1 1
0 0 0 0 1 0 0
0 0 0 0 1 0 1
0 0 0 0 1 1 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 0 1 0 0 1
0 0 0 1 0 1 0
0 0 0 1 0 1 1
0 0 0 1 1 0 0
0 0 0 1 1 0 1
0 0 0 1 1 1 0
0 0 0 1 1 1 1
...
V
(V)
VOV[6:0] BIT FIELD
1 1 1 0 0 0 0
1 1 1 0 0 0 1
1 1 1 0 0 1 0
1 1 1 0 0 1 1
1 1 1 0 1 0 0
1 1 1 0 1 0 1
1 1 1 0 1 1 0
1 1 1 0 1 1 1
1 1 1 1 0 0 0
1 1 1 1 0 0 1
1 1 1 1 0 1 0
1 1 1 1 0 1 1
1 1 1 1 1 0 0
1 1 1 1 1 0 1
1 1 1 1 1 1 0
1 1 1 1 1 1 1
V
(V)
OV
OV
3.311
3.320
3.330
3.340
3.350
3.359
3.369
3.379
3.389
3.398
3.408
3.418
3.428
3.438
3.447
3.457
...
4.404
4.414
4.424
4.434
4.443
4.453
4.463
4.473
4.482
4.492
4.502
4.512
4.521
4.531
4.541
4.551
56/DS278
28 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Overcurrent Thresholds
The overcurrent thresholds are set in the upper nibble of the RSGAIN register. The OC1 and OC0 bits set the over-
current thresholds for the charge and discharge thresholds. The short-circuit threshold is set by the SC0 bit (see
Tables 6 and 7, respectively, for overcurrent and short-circuit threshold values). The DS2775–DS2778 have a built-in
fixed delay of t
for overcurrent events and t
for short-circuit events. This means that the current ADC must
OCD
SCD
read a value greater than the overcurrent threshold for longer than t
and greater than the short-circuit threshold
OCD
for longer than t
are ignored.
before turning off the FET. Overcurrent and short-circuit events less than their respective delays
SCD
ADDRESS 78h
0
-1
-2
X
SC0
OC1
OC0
X
2
2
2
MSb
LSb
“X”: RESERVED
Figure 20. Overcurrent and Short-Circuit Threshold Bits Format
Table 6. COC, DOC Programmability
Table 7. SC Programmability
SC0 BIT FIELD
V
(mV)
SC
OC[1:0] BIT FIELD
V
(mV)
V
(mV)
DOC
COC
0
1
150
300
0 0
0 1
1 0
1 1
-25
38
-38
-50
-75
50
75
100
Special Feature Register Format
All register bits are read and write accessible with default values specified in each bit definition.
Special Feature Register (15h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
X
X
SHA_IDLE
PIOB
Bits 7 to 2: Reserved.
Bit 1: SHA Idle Bit (SHA_IDLE). For the DS2777/DS2778, this bit reads logic 1 while an SHA calculation is in
progress and reads logic 0 when the calculation is complete.
Bit 0: PIO Pin Sense and Control Bit (PIOB). Writing a 0 to the PIOB bit activates the PIO pin open-drain output
driver, forcing the PIO pin low. Writing a 1 to PIOB disables the output driver, allowing the PIO pin to be pulled high
or used as an input. Reading PIOB returns the logic level forced on the PIO pin. Note that if the PIO pin is left uncon-
nected with PIOB set, a weak pulldown current source pulls the PIO pin to V . PIOB is set to a 1 on power-up.
SS
PIOB is also set in sleep mode to ensure the PIO pin is high-impedance in sleep mode. Note: Do not write PIOB to 0
if PSPIO is enabled.
______________________________________________________________________________________ 29
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
EEPROM Register
The EEPROM register provides access control of the EEPROM blocks. EEPROM blocks can be locked to prevent
alteration of data within the block. Locking a block disables write access to the block. Once a block is locked, it can-
not be unlocked. Read access to EEPROM blocks is unaffected by the lock/unlock status.
EEPROM Register Format (1Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EEC
LOCK
X
X
X
X
BL1
BL0
Bit 7: EEPROM Copy Flag (EEC). A 1 in this read-only bit indicates that a Copy Data command is in progress.
While this bit is high, writes to EEPROM addresses are ignored. A 0 value in this bit indicates that data can be written
to unlocked EEPROM.
Bit 6: EEPROM Lock Enable (LOCK). When the LOCK bit is 0, the Lock command is ignored. Writing a 1 to this bit
enables the Lock command. After setting the LOCK bit, the Lock command must be issued as the next command,
else the LOCK bit is reset to 0. After the lock operation is completed, the LOCK bit is reset to 0. The LOCK bit is a
volatile R/W bit, initialized to 0 upon POR.
Bits 5 to 2: Reserved.
Bit 1: Parameter EEPROM Block 1 Lock Flag (BL1). A 1 in this read-only bit indicates that EEPROM block 1
(addresses 60h to 80h) is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).
Bit 0: User EEPROM Block 0 Lock Flag (BL0). A 1 in this read-only bit indicates that EEPROM block 0 (addresses
20h to 2Fh) is locked (read-only), while a 0 indicates block 0 is unlocked (read/write).
56/DS278
30 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
the shadow RAM and then read from the shadow. After
Memory
issuing the Copy Data command, access to the EEP-
The DS2775–DS2778 have a 256-byte linear memory
ROM block is not available until the EEPROM copy
space with registers for instrumentation, status, and
completes (see t
Specification table).
in the EEPROM Reliability
EEC
control, as well as EEPROM memory blocks to store
parameters and user information. Byte addresses des-
ignated as “reserved” typically return FFh when read.
These bytes should not be written. Several byte regis-
ters are paired into 2-byte registers to store 16-bit val-
ues. The MSB of the 16-bit value is located at the even
address and the LSB is located at the next address
(odd) byte. When the MSB of a 2-byte register is read,
the MSB and LSB are latched simultaneously and held
for the duration of the Read Data command to prevent
updates to the LSB during the read. This ensures syn-
chronization between the two register bytes. For consis-
tent results, always read the MSB and the LSB of a
2-byte register during the same Read Data sequence.
User EEPROM—Block 0
A 16-byte user EEPROM memory (block 0, addresses
20h to 2Fh) provides nonvolatile memory that is uncom-
mitted to other DS2775–DS2778 functions. Accessing
the user EEPROM block does not affect the operation of
the DS2775–DS2778. User EEPROM is lockable and,
once locked, write access is not allowed. The battery
pack or host system manufacturer can program lot
codes, date codes, and other manufacturing or warran-
ty or diagnostic information and then lock it to safe-
guard the data. User EEPROM can also store
parameters for charging to support different size batter-
ies in a host device as well as auxiliary model data
such as time to full-charge estimation parameters.
EEPROM memory consists of nonvolatile EEPROM cells
overlaying volatile shadow RAM. The Read Data and
Write Data commands allow the 1-Wire interface to
directly accesse the shadow RAM (Figure 21). The
Copy Data and Recall Data commands transfer data
between the EEPROM cells and the shadow RAM. In
order to modify the data stored in the EEPROM cells,
data must be written to the shadow RAM and then
copied to the EEPROM. To verify the data stored in the
EEPROM cells, the EEPROM data must be recalled to
Parameter EEPROM—Block 1
Model data for the cells as well as application operating
parameters are stored in the parameter EEPROM mem-
ory (block 1, addresses 60h to 80h). The ACR (MSB
and LSB) and AS registers are automatically saved to
EEPROM when the RARC result crosses 4% bound-
aries (see Table 8 for more information).
COPY
EEPROM
WRITE
RECALL
SERIAL
INTERFACE
SHADOW RAM
READ
Figure 21. EEPROM Access Through Shadow RAM
______________________________________________________________________________________ 31
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Table 8. Parameter EEPROM Memory Block
ADDRESS
(HEX)
ADDRESS
(HEX)
DESCRIPTION
DESCRIPTION
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
Control Register
71h
72h
73h
74h
75h
76h
77h
78h
79h
AE Segment 3 Slope Register
Accumulation Bias Register (AB)
Aging Capacity Register MSB (AC)
Aging Capacity Register LSB (AC)
Charge Voltage Register (VCHG)
Minimum Charge Current Register (IMIN)
Active-Empty Voltage Register (VAE)
Active-Empty Current Register (IAE)
Active-Empty 40 Register
AE Segment 2 Slope Register
AE Segment 1 Slope Register
SE Segment 4 Slope Register
SE Segment 3 Slope Register
SE Segment 2 Slope Register
SE Segment 1 Slope Register
Sense-Resistor Gain Register MSB (RSGAIN)
Sense-Resistor Gain Register LSB (RSGAIN)
Sense Resistor Prime Register (RSNSP)
Full 40 MSB Register
Sense-Resistor Temperature Coefficient Register
(RSTC)
7Ah
Full 40 LSB Register
7Bh
7Ch
7Dh
7Eh
7Fh
80h
Current Offset Bias Register (COB)
TBP34 Register
Full Segment 4 Slope Register
Full Segment 3 Slope Register
Full Segment 2 Slope Register
Full Segment 1 Slope Register
AE Segment 4 Slope Register
TBP23 Register
TBP12 Register
Protector Threshold Register
2-Wire Slave Address Register
Table 9. Memory Map
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
Protection Register
Status Register
R/W
R/W
R
56/DS278
RAAC Register MSB
RAAC Register LSB
RSAC Register MSB
RSAC Register LSB
RARC Register
R
R
R
R
RSRC Register
R
Average Current Register MSB
Average Current Register LSB
Temperature Register MSB
Temperature Register LSB
R
R
R
R
Voltage Register MSB, V
- V
R
IN1
IN1
SS
Voltage Register LSB, V
Current Register MSB
Current Register LSB
- V
R
SS
R
R
Accumulated Current Register MSB
Accumulated Current Register LSB
Accumulated Current Register LSB - 1
R/W*
R/W*
R
32 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Table 9. Memory Map (continued)
ADDRESS (HEX)
13h
DESCRIPTION
Accumulated Current Register LSB - 2
Age Scalar Register
READ/WRITE
R
R/W*
R/W
R
14h
15h
Special Feature Register
Full Register MSB
16h
17h
Full Register LSB
R
18h
Active-Empty Register MSB
Active-Empty Register LSB
Standby-Empty Register MSB
Standby-Empty Register LSB
R
19h
R
1Ah
R
1Bh
R
1Ch
Voltage Register MSB, V
- V
R
IN2
IN2
IN1
1Dh
Voltage Register LSB, V
Cycle Counter Register
EEPROM Register
- V
R
IN1
1Eh
R/W*
R/W
R/W
—
1Fh
20h to 2Fh
30h to 5Fh
60h to 80h
81h to AFh
B0h
User EEPROM Register, Lockable, Block 0
Reserved
Parameter EEPROM Register, Lockable, Block 1
Reserved
R/W
—
Factory Gain RSGAIN Register MSB
Factory Gain RSGAIN Register LSB
Reserved
R
B1h
R
B2h to FDh
FEh
—
2-Wire Command Register
Reserved
W
FFh
—
*Register value is automatically saved to EEPROM during active-mode operation and recalled from EEPROM on power-up.
challenge, and 384 bits of constant data. Optionally,
64-Bit Net Address (ROM ID)
the 64-bit net address replaces 64 of the 384 bits of
Each DS2775–DS2778 has a unique, factory-pro-
constant data used in the hash operation. Contact
Maxim for details of the message block organization.
grammed ROM ID that is 64 bits. The first 8 bits of the
net address are the product family code (3Dh). The
The host and the DS2776/DS2778 both calculate the
result based on the mutually known secret. The result
data, known as the message authentication code
(MAC) or message digest, is returned by the
DS2776/DS2778 for comparison to the host’s result.
Note that the secret is never transmitted on the bus and
thus cannot be captured by observing bus traffic. Each
authentication attempt is initiated by the host system by
providing a 64-bit random challenge through the Write
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits
(see Figure 22).
Authentication
The DS2776/DS2778 have an authentication feature
that is performed using a FIPS 180-compliant SHA-1
one-way hash algorithm on a 512-bit message block.
The message block consists of a 64-bit secret, a 64-bit
8-BIT FAMILY
CODE (3Dh)
8-BIT CRC
MSb
Figure 22. 1-Wire Net Address Format (ROM ID)
______________________________________________________________________________________ 33
48-BIT SERIAL NUMBER
LSb
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Challenge command. The host then issues the Compute
MAC or Compute MAC with ROM ID command. The
MAC is computed per FIPS 180, and then returned as a
160-bit serial stream, beginning with the LSb.
Table 10 summarizes SHA-1-related commands used
while authenticating a battery or peripheral device. The
Secret Management Function Commands section
describes four additional commands for clearing, com-
puting, and locking of the secret.
DS2776/DS2778 Authentication
Commands
Secret Management Function
Commands
Table 11 summarizes all the secret management func-
tion commands.
Write Challenge [0Ch]
This command writes the 64-bit challenge to the
DS2776/DS2778. The LSB of the 64-bit data argument
can begin immediately after the MSB of the command
has been completed. If more than 8 bytes are written,
the final value in the Challenge register is indetermi-
nate. The Write Challenge command must be issued
prior to every Compute MAC or Compute Next Secret
command for reliable results.
Clear Secret [5Ah]
This command sets the 64-bit secret to all 0s (0000
0000 0000 0000h). The host must wait for t
for the
EEC
DS2776/DS2778 to write the new secret value to
EEPROM. See Figure 28 for command timing.
Compute Next Secret Without
ROM ID [30h]
Compute MAC Without ROM ID [36h]
This command initiates an SHA-1 computation without
including the ROM ID in the message block. Because
the ROM ID is not used, this command allows the use
of a master secret and MAC response independent of
the ROM ID. The DS2776/DS2778 computes the MAC
This command initiates an SHA-1 computation of the
MAC and uses a portion of the resulting MAC as the
next or new secret. The MAC computation is performed
with the current 64-bit secret and the 64-bit challenge.
Logical 1s are loaded in place of the ROM ID. The out-
put MAC’s 64 bits are used as the new secret value.
in t
after receiving the last bit of this command.
SHA
After the MAC computation is complete, the host must
write eight write-zero time slots and then issue 160 read
time slots to receive the 20-byte MAC. See Figure 25 for
command timing.
The host must allow t
after issuing this command for
SHA
the SHA calculation to complete, then wait t
for the
EEC
DS2776/DS2778 to write the new secret value to
EEPROM. See Figure 26 for command timing.
Compute MAC with ROM ID [35h]
This command is structured the same as the Compute
MAC without ROM ID, except that the ROM ID is includ-
ed in the message block. With the ROM ID unique to
each DS2776/DS2778 included in the MAC computation,
use of a unique secret in each token and a master secret
in the host device is allowed. Refer to Application Note
1099: White Paper 4: Glossary of 1-Wire SHA-1 Terms for
more information. See Figure 25 for command timing.
Compute Next Secret with ROM ID [33h]
This command initiates an SHA-1 computation of the
MAC and uses a portion of the resulting MAC as the
next or new secret. The MAC computation is performed
with the current 64-bit secret, the 64-bit ROM ID, and
the 64-bit challenge. The output MAC’s 64 bits are used
56/DS278
as the new secret value. The host must allow t
after
SHA
issuing this command for the SHA calculation to com-
plete, then wait t for the DS2776/DS2778 to write
EEC
Table 10. Authentication Function Commands
COMMAND
HEX
FUNCTION
Writes 64-bit challenge for SHA-1 processing. Required prior to issuing
Compute MAC and Compute Next Secret commands.
Write Challenge
0Ch
Compute MAC without ROM ID (and
Return MAC for the DS2776 only)
Computes hash of the message block with logical 1s in place of the ROM
ID. (Returns the 160-bit MAC for the DS2776 only.)
36h
35h
Compute MAC with ROM ID (and Return
MAC for the DS2776 only)
Computes hash of the message block including the ROM ID. (Returns the
160-bit MAC for the DS2776 only.)
Read ROM ID (DS2778 only)
Read MAC (DS2778 only)
39h
3Ah
Returns the ROM ID (DS2778 only).
Returns the 160-bit MAC (DS2778 only).
34 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Table 11. Secret Management Function Commands
COMMAND
HEX
5Ah
30h
33h
60h
FUNCTION
Clears the 64-bit secret to 0000 0000 0000 0000h.
Generates new global secret.
Clear Secret
Compute Next Secret without ROM ID
Compute Next Secret with ROM ID
Lock Secret
Generates new unique secret.
Sets lock bit to prevent changes to the secret.
the new secret value to EEPROM. See Figure 26 for
command timing.
The host system is responsible for verifying the CRC
value and taking action as a result. The DS2775/
DS2776 do not compare CRC values and do not pre-
vent a command sequence from proceeding as a result
of a CRC mismatch. Proper use of the CRC can result
in a communication channel with a very high level of
integrity.
Lock Secret [60h]
This command write protects the 64-bit secret to pre-
vent accidental or malicious overwrite of the secret
value. The secret value stored in EEPROM becomes
"final." The host must wait t
for the DS2776/DS2778
EEC
The CRC can be generated by the host using a circuit
consisting of a Shift register and XOR gates as shown
in Figure 23, or it can be generated in software using
to write the lock secret bit to EEPROM. See Figure 28
for command timing.
8
5
4
the polynomial X + X + X + 1. Additional information
about the Maxim 1-Wire CRC is available in Application
Note 27: Understanding and Using Cyclic Redundancy
1-Wire Bus System
(DS2775/DS2776 Only)
The 1-Wire bus is a system that has a single bus master
and one or more slaves. A multidrop bus is a 1-Wire
bus with multiple slaves, while a single-drop bus has
only one slave device. In all instances, the DS2775/
DS2776 are slave devices. The bus master is typically a
microprocessor in the host system. The discussion of
this bus system consists of five topics: 64-bit net
address, CRC generation, hardware configuration,
transaction sequence, and 1-Wire signaling.
®
Checks with Maxim iButton Products.
In the circuit in Figure 23, the Shift register bits are ini-
tialized to 0. Then, starting with the LSb of the family
code, one bit at a time is shifted in. After the 8th bit of
the family code has been entered, then the serial num-
ber is entered. After the 48th bit of the serial number has
been entered, the Shift register contains the CRC value.
During some command sequences, the DS2775/
DS2776 also generate an 8-bit CRC and provide this
value to the bus master to facilitate validation for the
transfer of command, address, and data from the bus
master to the DS2775/DS2776. The DS2775/DS2776
compute an 8-bit CRC for the command and address
bytes received from the bus master for the Read
Memory, Read Status, and Read/Generate CRC com-
mands to confirm that these bytes have been received
correctly. The CRC generator on the DS2775/DS2776 is
CRC Generation
The DS2775/DS2776 have an 8-bit CRC stored in the
MSB of its 64-bit net address and generates a CRC
during some command protocols. To ensure error-free
transmission of the address, the host system can com-
pute a CRC value from the first 56 bits of the address
and compare it to the CRC from the DS2775/DS2776.
INPUT
MSb
XOR
XOR
LSb
XOR
Figure 23. 1-Wire CRC Generation Block Diagram
iButton is a registered trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________ 35
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
also used to provide verification of error-free data trans-
fer as each EEPROM page is sent to the master during
a Read Data/Generate CRC command and for the
8 bytes of information in the status memory field.
the low period as a reset pulse, effectively terminating
the transaction.
Transaction Sequence
The protocol for accessing the DS2775/DS2776
through the 1-Wire port is as follows:
In each case where a CRC is used for data transfer val-
idation, the bus master must calculate the CRC value
using the same polynomial function and compare the
calculated value to the CRC either stored in the
DS2775/DS2776 net address or computed by the
DS2775/DS2776. The comparison of CRC values and
decision to continue with an operation are determined
entirely by the bus master. There is no circuitry in the
DS2775/DS2776 that prevents a command sequence
from proceeding if the stored or calculated CRC from
the DS2775/DS2776 and the calculated CRC from the
host do not match.
• Initialization
• Net Address Commands
• Function Command(s)
• Data Transfer (not all commands have data transfer)
Initialization
All transactions of the 1-Wire bus begin with an initial-
ization sequence consisting of a reset pulse transmitted
by the bus master, followed by a presence pulse simul-
taneously transmitted by the DS2775/DS2776 and any
other slaves on the bus. The presence pulse tells the
bus master that one or more devices are on the bus
and ready to operate. For more details, see the 1-Wire
Signaling section.
Hardware Configuration
Because the 1-Wire bus has only a single line, it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must connect to the bus with
open-drain or three-state output drivers. The DS2775/
DS2776 use an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 24. If a
bidirectional pin is not available on the bus master,
separate output and input pins can be connected
together.
Net Address Commands
Once the bus master has detected the presence of one
or more slaves, it can issue one of the net address
commands described in the following sections. The
name of each Net Address command (ROM command)
is followed by the 8-bit op code for that command in
square brackets.
The 1-Wire bus must have a pullup resistor at the bus
master end. A value of between 2kΩ and 5kΩ is recom-
mended. The idle state for the 1-Wire bus is high. If, for
any reason, a bus transaction must be suspended, the
bus must be left in the idle state to properly resume the
transaction later. Note that if the bus is left low for more
Read Net Address [33h]
This command allows the bus master to read the
DS2775/DS2776’s 1-Wire net address. This command
can only be used if there is a single slave on the bus. If
more than one slave is present, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result).
56/DS278
than t
, slave devices on the bus begin to interpret
LOW0
V
PULLUP
(2.0V TO 5.5V)
BUS MASTER
DS2775/DS2776 1-Wire PORT (DQ)
4.7kΩ
Rx
Tx
Rx
100nA
(TYP)
Tx
100Ω MOSFET
Rx = RECEIVE
Tx = TRANSMIT
Figure 24. 1-Wire Bus Interface Circuitry
36 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Match Net Address [55h]
This command allows the bus master to specifically
address one DS2775/DS2776 on the 1-Wire bus. Only
the addressed DS2775/DS2776 responds to any sub-
sequent function command. All other slave devices
ignore the function command and wait for a reset pulse.
This command can be used with one or more slave
devices on the bus.
ing at memory address 00h and the address is auto-
matically incremented until a reset pulse occurs.
Addresses labeled Reserved in the Memory Map con-
tain undefined data values (see Table 9). The Read
Data command can be terminated by the bus master
with a reset pulse at any bit boundary. Reads from EEP-
ROM block addresses return the data in the shadow
RAM. A Recall Data command is required to transfer
data from the EEPROM to the shadow. See the Memory
section for more details.
Skip Net Address [CCh]
This command saves time when there is only one
DS2775/DS2776 on the bus by allowing the bus master
to issue a function command without specifying the
address of the slave. If more than one slave device is
present on the bus, a subsequent function command
can cause a data collision when all slaves transmit data
at the same time.
Write Data [6Ch, XXh]
This command writes data to the DS2775/DS2776 start-
ing at memory address XXh. The LSb of the data to be
stored at address XXh can be written immediately after
the MSb of the address has been entered. Because the
address is automatically incremented after the MSb of
each byte is written, the LSb to be stored at address
XXh + 1 can be written immediately after the MSb to be
stored at address XXh. If the bus master continues to
write beyond address FFh, the data starting at address
00 is overwritten. Writes to read-only addresses,
reserved addresses, and locked EEPROM blocks are
ignored. Incomplete bytes are not written. Writes to
unlocked EEPROM block addresses modify the shadow
RAM. A Copy Data command is required to transfer
data from the shadow to the EEPROM. See the Memory
section for more details.
Search Net Address [F0h]
This command allows the bus master to use a process
of elimination to identify the 1-Wire net addresses of all
slave devices on the bus. The search process involves
the repetition of a simple three-step routine: read a bit,
read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple
three-step routine on each bit location of the net
address. After one complete pass through all 64 bits,
the bus master knows the address of one device. The
remaining devices can then be identified on additional
iterations of the process. See Chapter 5 in Application
Note 937: Book of iButton Standards for a comprehen-
sive discussion of a net address search, including an
actual example.
Copy Data [48h, XXh]
This command copies the contents of the EEPROM
shadow RAM to EEPROM cells for the EEPROM block
containing address XXh. Copy Data commands that
address locked blocks are ignored. While the Copy
Data command is executing, the EEC bit in the EEPROM
register is set to 1 and writes to EEPROM addresses are
ignored. Reads and writes to non-EEPROM addresses
can still occur while the copy is in progress. The Copy
Function Commands
After successfully completing one of the net address
commands, the bus master can access the features of
the DS2775/DS2776 with any of the function commands
described in the following paragraphs. The name of
each function is followed by the 8-bit op code for that
command in square brackets. The function commands
are summarized in Table 12. Table 13 details the
requirements for using the function commands.
Data command takes t
time to execute, starting on
EEC
the next falling edge after the address is transmitted.
See Figure 27 for more information.
Recall Data [B8h, XXh]
This command recalls the contents of the EEPROM
cells to the EEPROM shadow memory for the EEPROM
block containing address XXh.
Read Data [69h, XXh]
This command reads data from the DS2775/DS2776
starting at memory address XXh. The LSb of the data in
address XXh is available to be read immediately after
the MSb of the address has been entered. Because the
address is automatically incremented after the MSb of
each byte is received, the LSb of the data at address
XXh + 1 is available to be read immediately after the
MSb of the data at address XXh. If the bus master con-
tinues to read beyond address FFh, data is read start-
Lock [6Ah, XXh]
This command locks (write protects) the block of
EEPROM memory containing memory address XXh.
The LOCK bit in the EEPROM register must be set to 1
before the Lock command is executed. To help pre-
vent unintentional locks, one must issue the Lock com-
mand immediately after setting the LOCK bit (EEPROM
______________________________________________________________________________________ 37
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
register, address 1Fh, bit 6) to a 1. If the LOCK bit is 0
or if setting the LOCK bit to 1 does not immediately
precede the Lock command, the Lock command has
no effect. The Lock command is permanent; a locked
block can never be written again.
Table 12. All Function Commands
COMMAND
HEX
DESCRIPTION
Writes 64-bit challenge for SHA-1 processing. Required immediately prior
to all Compute MAC and Compute Next Secret commands.
Write Challenge
0Ch
Compute MAC without ROM ID (and
Return MAC for the DS2776 only)
Computes hash of the message block with logical 1s in place of ROM ID.
(Returns the 160-bit MAC for the DS2776 only.)
36h
35h
Compute MAC with ROM ID (and Return
MAC for the DS2776 only)
Computes hash of the message block using the ROM ID. (Returns the
160-bit MAC for the DS2776 only.)
Clear Secret
5Ah
30h
33h
39h
3Ah
60h
Clears the 64-bit secret to 0000 0000 0000 0000h.
Generates new global secret.
Compute Next Secret without the ROM ID
Compute Next Secret with ROM ID
Read ROM ID (DS2778 only)
Read MAC (DS2778 only)
Lock Secret
Generates new unique secret.
Returns the ROM ID (DS2778 only).
Returns the 160-bit MAC (DS2778 only).
Sets lock bit to prevent changes to the secret.
Read Data
69h, XXh Reads data from memory starting at address XXh.
Write Data
6Ch, XXh Writes data to memory starting at address XXh.
Copy Data
48h, XXh Copies shadow RAM data to EEPROM block containing address XXh.
B8h, XXh Recalls EEPROM block containing address XXh to RAM.
6Ah, XXh Permanently locks the block of EEPROM containing address XXh.
Recall Data
Lock
Reset
BBh
Resets DS2775/DS2776 (software POR).
56/DS278
Table 13. Guide to Function Command Requirements
ISSUE MEMORY ADDRESS
COMMAND
ISSUE 00h BEFORE READ
READ/WRITE TIME SLOTS
(BITS)
Write Challenge
—
—
—
—
8
—
Yes
—
Write: 64
Compute MAC
Read: Up to 160
Compute Next Secret
Clear/Lock Secret, Set/Clear
—
—
—
Read Data
Write Data
Copy Data
Recall Data
Lock
—
Read: Up to 2048
8
—
Write: Up to 2048
8
—
—
—
—
—
8
—
8
—
Reset
—
—
38 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
t
SHA
WAIT FOR MAC
COMPUTATION
1-Wire
RESET
SKIP-ROM
COMMAND
UP TO 160 READ TIME SLOTS
(READ 20-BYTE MAC)
PRESENCE
PULSE
COMPUTE
MAC COMMAND
8 WRITE-ZERO
TIME SLOTS
Figure 25. Compute MAC Command
t
t
EEC
SHA
WAIT FOR MAC
COMPUTATION
WAIT FOR EEPROM
PROGRAMMING
1-Wire
RESET
SKIP-ROM
COMMAND
PRESENCE
PULSE
COMPUTE
NEXT SECRET COMMAND
Figure 26. Compute Next Secret Command
t
EEC
WAIT FOR EEPROM
PROGRAMMING
1-Wire
RESET
SKIP-ROM
COMMAND
COPY DATA
COMMAND
8 WRITE
TIME SLOTS
PRESENCE
PULSE
Figure 27. Copy Data Command
______________________________________________________________________________________ 39
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
t
EEC
1-Wire
RESET
SKIP-ROM
COMMAND
CLEAR/LOCK
SECRET COMMAND
OR SET/CLEAR
WAIT FOR EEPROM
COPY TIME
OVERDRIVE COMMAND
PRESENCE
PULSE
Figure 28. Clear/Lock Secret, Set/Clear Overdrive Commands
t
t
RSTH
RSTL
t
t
PDL
PDH
PK+
PK-
DQ
56/DS278
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
RESISTOR PULLUP
DS2775/DS2776 ACTIVE LOW
Figure 29. 1-Wire Initialization Sequence
Figure 29 shows the initialization sequence required to
begin any communication with the DS2775/DS2776. A
presence pulse following a reset pulse indicates that
the DS2775/DS2776 are ready to accept a Net Address
command. The bus master transmits (Tx) a reset pulse
1-Wire Signaling
The 1-Wire bus requires strict signaling protocols to
ensure data integrity. The four protocols used by the
DS2775/DS2776 are as follows: the initialization
sequence (reset pulse followed by presence pulse),
write-zero, write-one, and read data. The bus master
initiates all these types of signaling except the pres-
ence pulse.
for t
. The bus master then releases the line and
RSTL
goes into receive mode (Rx). The 1-Wire bus line is
then pulled high by the pullup resistor. After detecting
the rising edge on the DQ pin, the DS2775/DS2776 wait
for t
and then transmit the presence pulse for t
.
PDH
PDL
40 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
trol of a master device. The master initiates all transac-
Write Time Slots
tions on the bus and generates the SCL signal as well
A write time slot is initiated when the bus master pulls
as the START and STOP bits which begin and end
the 1-Wire bus from a logic-high (inactive) level to a
each transaction.
logic-low level. There are two types of write time slots:
write-one and write-zero. All write time slots must be
Bit Transfer
t
t
in duration with a 1µs minimum recovery time,
SLOT
REC
One data bit is transferred during each SCL clock cycle
with the cycle defined by SCL transitioning low-to-high
and then high-to-low. The SDA logic level must remain
stable during the high period of the SCL clock pulse.
Any change in SDA when SCL is high is interpreted as
a START (S) or STOP (P) control signal.
, between cycles. The DS2775/DS2776 sample the
1-Wire bus line between t
and t
LOW0_MIN
LOW1_MAX
after the line falls. If the line is high when sampled, a
write-one occurs. If the line is low when sampled, a
write-zero occurs. Figure 30 illustrates the sample win-
dow. For the bus master to generate a write-one time
slot, the bus line must be pulled low and then released,
Bus Idle
allowing the line to be pulled high less than t
after
RDV
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
the start of the write time slot. For the host to generate a
write-zero time slot, the bus line must be pulled low and
held low for the duration of the write time slot.
Read Time Slots
START and STOP Conditions
A read time slot is initiated when the bus master pulls the
1-Wire bus line from a logic-high level to a logic-low
level. The bus master must keep the bus line low for at
least 1µs and then release it to allow the DS2775/
DS2776 to present valid data. The bus master can then
The master initiates transactions with a START condi-
tion by forcing a high-to-low transition on SDA while
SCL is high. The master terminates a transaction with a
STOP condition, a low-to-high transition on SDA while
SCL is high. A repeated START condition (Sr) can be
used in place of a STOP then START sequence to ter-
minate one transaction and begin another without
returning the bus to the idle state. In multimaster sys-
tems, a repeated START allows the master to retain
control of the bus. The START and STOP conditions are
the only bus activities in which the SDA transitions
when SCL is high.
sample the data t
from the start of the read time slot.
By the end of the read time slot, the DS2775/DS2776
release the bus line and allow it to be pulled high by the
RDV
external pullup resistor. All read time slots must be t
in duration with a 1µs minimum recovery time, t
SLOT
,
REC
between cycles. See Figure 30 and the timing specifica-
tions in the Electrical Characteristics: 1-Wire Interface,
Standard/Overdrive tables for more information.
Acknowledge Bits
2-Wire Bus System
Each byte of a data transfer is acknowledged with an
acknowledge bit (A) or a not acknowledge bit (N). Both
the master and the DS2777/DS2778 slave generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (9th
pulse) and keep it low until SCL returns low. To gener-
ate a not acknowledge (also called NACK), the receiver
releases SDA before the rising edge of the acknowl-
edge-related clock pulse and leaves SDA high until
SCL returns low. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer can occur if a receiving
device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master
should reattempt communication.
The 2-wire bus system supports operation as a slave-
only device in a single or multislave and single or multi-
master system. Up to 128 slave devices can share the
bus by uniquely setting the 7-bit slave address. The
2-wire interface consists of a serial data line (SDA) and
serial clock line (SCL). SDA and SCL provide bidirec-
tional communication between the DS2777/DS2778
slave device and a master device at speeds up to
400kHz. The DS2777/DS2778’s SDA pin operates bidi-
rectionally, that is, when the DS2777/DS2778 receive
data, SDA operates as an input, and when the
DS2777/DS2778 return data, SDA operates as an open-
drain output with the host system providing a resistive
pullup. The DS2777/DS2778 always operate as a slave
device, receiving and transmitting data under the con-
______________________________________________________________________________________ 41
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
WRITE-ZERO SLOT
WRITE-ONE SLOT
t
t
SLOT
SLOT
t
t
LOW1
LOW0
t
REC
V
PULLUP
GND
> 1μs
DEVICE SAMPLE WINDOW
TYP MAX
DEVICE SAMPLE WINDOW
MIN TYP MAX
MIN
MODE:
15μs
2μs
15μs
30μs
3μs
15μs
2μs
15μs
30μs
3μs
STANDARD
1μs
1μs
OVERDRIVE
READ-ZERO SLOT
READ-ONE SLOT
t
t
SLOT
SLOT
t
REC
t
t
RDV
RDV
V
PULLUP
GND
56/DS278
> 1μs
MASTER SAMPLE WINDOW
MASTER SAMPLE WINDOW
MODE:
15μs
2μs
15μs
2μs
STANDARD
OVERDRIVE
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
SLAVE ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND
SLAVE ACTIVE LOW
Figure 30. 1-Wire Write and Read Time Slots
42 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
selects a read transaction, with the subsequent bytes
Data Order
being read from the slave by the master.
A byte of data consists of 8 bits ordered MSb first. The
LSb of each byte is followed by the acknowledge bit.
Bus Timing
The DS2777/DS2778 registers composed of multibyte
The DS2777/DS2778 are compatible with any bus tim-
values are ordered MSB first. The MSB of multibyte reg-
ing up to 400kHz. No special configuration is required
isters is stored on even data memory addresses.
to operate at any speed.
Slave Address
2-Wire Command Protocols
A bus master initiates communication with a slave
The command protocols involve several transaction for-
device by issuing a START condition followed by a
mats. The simplest format consists of the master writing
slave address (SAddr) and the read/write (R/W) bit.
the START bit, slave address, R/W bit, and then moni-
When the bus is idle, the DS2777/DS2778 continuously
toring the acknowledge bit for presence of the
monitor for a START condition followed by its slave
DS2777/DS2778. More complex formats such as the
address. When the DS2777/DS2778 receive a slave
Write Data, Read Data, and function command proto-
address that matches the value in its Programmable
cols write data, read data, and execute device-specific
Slave Address register, they respond with an acknowl-
operations. All bytes in each command format require
edge bit during the clock period following the R/W bit.
the slave or host to return an acknowledge bit before
The 7-bit Programmable Slave Address register is fac-
continuing with the next byte. Each function command
tory programmed to 1011001. The slave address can
definition outlines the required transaction format. Table
be reprogrammed. See the Programmable Slave
14 applies to the transaction formats.
Address section for details.
Basic Transaction Formats
Write: S SAddr W A MAddr A Data0 A P
Programmable Slave Address
The 2-wire slave address of the DS2777/DS2778 is
A write transaction transfers one or more data bytes to
the DS2777/DS2778. The data transfer begins at the
memory address supplied in the MAddr byte. Control of
the SDA signal is retained by the master throughout the
transaction, except for the acknowledge cycles.
stored in the parameter EEPROM block, address 80h.
Programming the slave address requires a write to 80h
with the desired slave address. The new slave address
value is effective following the write to 80h and must be
used to address the DS2777/DS2778 on subsequent
bus transactions. The slave address value is not stored
to EEPROM until a Copy EEPROM Block 1 command is
executed. Prior to executing the Copy Data command,
power cycling the DS2777/DS2778 restores the original
slave address value. The data format of the slave
address value in address 80h is shown in the Slave
Address Format (80h) section.
Read: S SAddr W A MAddr A Sr SAddr R A Data0 N P
Write Portion
Read Portion
A read transaction transfers one or more bytes from the
DS2777/DS2778. Read transactions are composed of
two parts with a write portion followed by a read portion
and are, therefore, inherently longer than a write trans-
action. The write portion communicates the starting
point for the read operation. The read portion follows
immediately, beginning with a repeated START, and
slave address with R/W set to a 1. Control of SDA is
Read/Write Bit
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W
= 0 selects a write transaction, with the subsequent
bytes being written by the master to the slave. R/W = 1
Slave Address Format (80h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
A6
A5
A4
A3
A2
A1
A0
X
Bits 7 to 1: Slave Address (A[6:0]). A[6:0] contains the 7-bit slave address of the DS2777/DS2778. The factory
default is 1011001b.
Bit 0: Reserved.
______________________________________________________________________________________ 43
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Table 14. 2-Wire Protocol Key
KEY
S
DESCRIPTION
START Bit
KEY
Sr
DESCRIPTION
Repeated START
SAddr
FCmd
MAddr
Data
A
Slave Address (7-bit)
W
R/W Bit = 0
Function Command Byte
Memory Address Byte
R
R/W Bit = 1
P
STOP bit
Data Byte Written by Master
Acknowledge Bit (Master)
Not Acknowledge (Master)
Data
A
Data Byte Returned by Slave
Acknowledge Bit (Slave)
Not Acknowledge (Slave)
N
N
assumed by the DS2777/DS2778 beginning with the
slave address acknowledge cycle. Control of the SDA
signal is retained by the DS2777/DS2778 throughout
the transaction, except for the acknowledge cycles.
The master indicates the end of a read transaction by
responding to the last byte it requires with a no
acknowledge. This signals the DS2777/DS2778 that
control of SDA is to remain with the master following the
acknowledge clock.
Read-Data Protocol
The read-data protocol is used to read register and
shadow RAM data from the DS2777/DS2778 starting at
a memory address specified by MAddr. Data0 repre-
sents the data byte in memory location MAddr, Data1
represents the data from MAddr + 1, and DataN repre-
sents the last byte read by the master.
S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A
… DataN N P
Write-Data Protocol
Data is returned beginning with the MSb of the data in
MAddr. Because the address is automatically incre-
mented after the LSb of each byte is returned, the MSb
of the data at address MAddr + 1 is available to the
host immediately after the acknowledgement of the
data at address MAddr. If the bus master continues to
read beyond address FFh, the DS2777/DS2778 output
data values of FFh. Addresses labeled reserved in the
Memory Map return undefined data. The bus master
terminates the read transaction at any byte boundary
by issuing a not acknowledge followed by a STOP or
repeated START.
The write-data protocol is used to write to register and
shadow RAM data to the DS2777/DS2778 starting at
memory address MAddr. Data0 represents the data
written to MAddr, Data1 represents the data written to
MAddr + 1 and DataN represents the last data byte,
written to MAddr + N. The master indicates the end of a
write transaction by sending a STOP or repeated
START after receiving the last acknowledge bit.
56/DS278
S SAddr W A MAddr A Data0 A Data1 A … DataN A P
The MSb of the data to be stored at address MAddr
can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically
incremented after the LSb of each byte is received by
the DS2777/DS2778, the MSb of the data at address
MAddr + 1 is written immediately after the acknowl-
edgement of the data at address MAddr. If the bus
master continues an autoincremented write transaction
beyond address 4Fh, the DS2777/DS2778 ignore the
data. Data is also ignored on writes to read-only
addresses and reserved addresses, locked EEPROM
blocks, as well as a write that auto-increments to the
Function Command register (address FEh). Incomplete
bytes and bytes that are not acknowledged by the
DS2777/DS2778 are not written to memory. As noted in
the Memory section, writes to unlocked EEPROM
blocks modify the shadow RAM only.
Function Command Protocol
The function command protocol executes a device-
specific operation by writing one of the function com-
mand values (FCmd) to memory address FEh. Table 15
lists the DS2777/DS2778 FCmd values and describes
the actions taken by each. A 1-byte write protocol is
used to transmit the function command, with the MAddr
set to FEh and the data byte set to the desired FCmd
value. Additional data bytes are ignored. Data read
from memory address FEh is undefined.
S SAddr W A MAddr = 0FEh A FCmd A P
44 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
56/DS278
Table 15. Function Commands
TARGET
EEPROM
BLOCK
FUNCTION
COMMAND
FCmd
VALUE
DESCRIPTION
This command copies the shadow RAM to the target EEPROM block. Copy data
commands that target locked blocks are ignored. While the Copy Data command is
executing, the EEC bit in the EEPROM register is set to 1, and write data commands
with MAddr set to any address within the target block are ignored. Read data and
write data commands with MAddr set outside the target block are processed while
0
1
42h
44h
Copy Data
the copy is in progress. The Copy Data command execution time, t
, is 2ms
EEC
typical and starts after the FCmd byte is acknowledged. Subsequent copy or lock
commands must be delayed until the EEPROM programming cycle completes.
0
1
B2h
B4h
This command recalls the contents of the targeted EEPROM block to its shadow
RAM.
Recall Data
Lock
This command locks (write protects) the targeted EEPROM block. The LOCK bit in
the EEPROM register must be set to 1 before the Lock command is executed. If the
LOCK bit is 0, the Lock command has no effect. The Lock command is permanent;
a locked block can never be written again. The Lock command execution time,
0
63h
t
, is 2ms typical and starts after the FCmd byte is acknowledged. Subsequent
EEC
1
66h
39h
copy or lock commands must be delayed until the EEPROM programming cycle
completes.
This command initiates a read of the unique 64-bit ROM ID. After the Read ROM ID
command is sent, the ROM ID can be read with the following sequence:
S SAddr R Data0 A Data1 A ... Data7 N P.
Read ROM
ID
—
Selector Guide
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
DS2775G+
INTERFACE
SHA-1
No
1-Wire
1-Wire
1-Wire
1-Wire
2-Wire
2-Wire
2-Wire
2-Wire
DS2775G+T&R
DS2776G+
No
Yes
Yes
No
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
DS2776G+T&R
DS2777G+
14 TDFN-EP
T1435N+1
21-0253
90-0246
DS2777G+T&R
DS2778G+
No
Yes
Yes
DS2778G+T&R
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
______________________________________________________________________________________ 45
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
10/08
3/09
0
1
2
Initial release
—
27
42
Corrected values in the VOV Register Programmability table (Table 5)
7/09
Corrected the 2-wire slave address default value to 1011001
2, 7, 11, 13,
24, 25, 45
3
5/10
Clarified ESD sensitivity to avoid confusion
Updated the DS2775/DS2776 Typical Application Circuit and DS2777/DS2778
Typical Application Circuit; corrected the product family code from 32h to 3Dh in
the 64-Bit Net Address (ROM ID) section and Figure 22
4
6/11
10, 33
56/DS278
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
46 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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