DS28C36 [MAXIM]
DeepCover Secure Authenticator;
| 型号： | DS28C36 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | DeepCover Secure Authenticator |
| 文件： | 总7页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ABRIDGED DATA SHEET
EVALUATION KIT AVAILABLE
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DS28C36
DeepCover Secure Authenticator
General Description
The DS28C36 is a DeepCover secure authenticator
Benefits and Features
● ECC-256 Compute Engine
®
• FIPS 186 ECDSA P256 Signature and Verification
• ECDH Key Exchange with Authentication Prevents
Man-in-the-Middle Attacks
• ECDSA Authenticated R/W of Configurable
Memory
that provides a core set of cryptographic tools derived
from integrated asymmetric (ECC-P256) and symmetric
(SHA-256) security functions. In addition to the security
services provided by the hardware implemented crypto
engines, the device integrates a FIPS/NIST true random
number generator (RNG), 8Kb of secured EEPROM, a
decrement-only counter, two pins of configurable GPIO,
and a unique 64-bit ROM identification number (ROM ID).
● FIPS 180 SHA-256 Compute Engine
• HMAC
● SHA-256 OTP (One-Time Pad) Encrypted R/W of
The ECC public/private key capabilities operate from
the NIST defined P-256 curve and include FIPS 186
compliant ECDSA signature generation and verification
to support a bidirectional asymmetric key authentication
model. The SHA-256 secret-key capabilities are compli-
ant with FIPS 180 and are flexibly used either in conjunc-
tion with ECDSA operations or independently for multiple
HMAC functions.
Configurable Memory Through ECDH Established Key
● Two GPIO Pins with Optional Authentication Control
• Open-Drain, 4mA/0.4V
• Optional SHA-256 or ECDSA Authenticated On/Off
and State Read
• Optional ECDSA Certificate to Set On/Off after
Multiblock Hash for Secure Boot
● RNG with NIST SP 800-90B Compliant Entropy
Two GPIO pins can be independently operated under
command control and include configurability supporting
authenticated and nonauthenticated operation including
an ECDSA-based crypto-robust mode to support secure-
boot of a host processor.
Source with Function to Read Out
● Optional Chip Generated Pr/Pu Key Pairs for ECC
Operations
● 17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
DeepCover embedded security solutions cloak sensitive
data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
● 8Kbits of EEPROM for User Data, Keys, and
Certificates
● Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
• Optional Input Data Component to Crypto and Key
Operations
Applications
● IoT Node Crypto-Protection
● Accessory and Peripheral Secure Authentication
2
● I C Communication Up to 1MHz
● Operating Range: 2.2V to 3.63V, -40°C to +85°C
● 6-Pin TDFN Package
● Secure Storage of Cryptographic Keys for a Host
Controller
● Secure Boot or Download of Firmware and/or System
Ordering Information appears at end of data sheet.
Parameters
Typical Application Circuit appears at end of data sheet.
DeepCover is a registered trademark of Maxim Integrated
Products, Inc.
19-8564; Rev 3; 12/20
ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+125°C
Storage Temperature Range............................ -55°C to +125°C
Lead temperature (soldering, 10s)..................................+300°C
Soldering Temperature (reflow)...................................... +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
6 TDFN-EP
Package Code
T633+2
21-0137
90-0058
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
55°C/W
9°C/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
42°C/W
9°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T = -40°C to +85°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.97
2.2
TYP
MAX
UNITS
DS28C36
Supply Voltage
V
3.3
3.63
V
CC
DS28C36B
(Note 2)
Active Supply Current
Standby Supply Current
Computation Current
GPIO
I
300
250
7.5
µA
µA
CC
I
CCS
I
(Note 3)
mA
CMP
Output Low
PIOV
0.4
V
V
OL
V
CC
0.3
x
Input Low
PIOV
-0.3
IL
V
CC
0.7
x
V
+
CC
0.3
Input High
PIOV
V
IH
DS28C36
-10
-1
+10
+1
Leakage current
I
µA
L
DS28C36B
ECC ENGINE
Generate ECDSA Signature Time
Generate ECC Key Pair
t
t
50
ms
ms
GES
100
GKP
Verify ECDSA Signature or Compute
ECDH Time
t
150
ms
VES
SHA-256 ENGINE
Computation Time (HMAC or RNG)
t
CMP
3
ms
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ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Electrical Characteristics (continued)
(T = -40°C to +85°C.) (Note 1)
A
PARAMETER
EEPROM
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
W/E Endurance
NCY
(Note 4)
100K
—
ms
Read Memory Time
Write Memory Time
Data Retention
t
1
RM
t
15
ms
WM
t
10
years
T
= +85°C (Note 5)
DR
A
2
I C SCL AND SDA PINS (Note 6)
0.3 ×
Low-Level Input Voltage
V
-0.3
V
V
V
V
IL
V
CC
0.7 ×
V
+
CC
0.3
High-Level Input Voltage
V
IH
V
CC
0.05 ×
Hysteresis of Schmitt Trigger Inputs
V
(Note 7)
(Note 7)
HYS
V
CC
Low-Level Output Voltage at 4mA Sink
Current
V
0.4
50
OL
Output Fall Time from V
to
IH(MIN)
V
with a Bus Capacitance from
t
30
10
ns
IL(MAX)
OF
10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
t
(Note 7)
ns
SP
II
DS28C36
-10
-1
+10
+1
Input Current with an Input Voltage
Between 0.1VCCmax and 0.9VCCmax
µA
DS28C36B (Note 8)
(Note 7)
Input Capacitance
CI
pF
DS28C36
DS28C36B
DS28C36
DS28C36B
DS28C36
DS28C36B
DS28C36
DS28C36B
DS28C36
DS28C36B
DS28C36
DS28C36B
0
0
0.4
1
SCL Clock Frequency
f
(Note 9)
MHz
SCL
0.6
0.45
1.3
0.65
0.6
0.35
0.6
0.35
Hold Time (Repeated) START Condition
Low Period of the SCL Clock
t
t
µs
µs
µs
µs
HD:STA
t
(Note 10)
LOW
High Period of the SCL Clock
t
HIGH
Setup Time for a Repeated START
Condition
SU:STA
HD:DAT
0.9
0.35
Data Hold Time
t
(Notes 7, 10, 11)
(Notes 10, 12)
µs
ns
µs
Data Setup Time
t
100
SU:DAT
t
SU:STO
DS28C36
DS28C36B
DS28C36
DS28C36B
0.6
0.35
1.3
Setup Time for STOP Condition
Bus Free Time Between a STOP and
START Condition
t
µs
pF
ms
BUF
0.6
Capacitive Load for Each Bus Line
C
(Notes 9, 13)
(Note 14)
400
B
DS28C36
DS28C36B
0.25
1.0
Warm-Up Time
t
OSCWUP
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ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Electrical Characteristics (continued)
(T = -40°C to +85°C.) (Note 1)
A
Note 1: Limits are 100% production tested at T = +25°C and/or T = +85°C. Limits over the operating temperature range and
A
A
relevant supply voltage range are guaranteed by design and characterization. Typical values at +25°C.
Note 2: Operating current continuously reading memory at 400kHz with < 25ns rise and fall times on SDA and SCL.
Note 3: Average current drawn from V during EEPROM read, EEPROM write, RNG calculation, SHA-256 calculation, or ECDSA calculation.
CC
Note 4: Write-cycle endurance is tested in compliance with JESD47H.
Note 5: Data retention is rested in compliance with JESD47H.
2
Note 6: All I C timing values are referred to V
and V
levels.
IH(MIN)
IL(MAX)
Note 7: Guaranteed by design and/or characterization only. Not production tested.
Note 8: I/O pins of the DS28C36B do not obstruct the SDA and SCL lines if V
Note 9: System requirement.
is switched off.
CC
Note 10:
t
min = t
max + t
max + t
min, where t
is rise or fall time. For the DS28C36, t max = 300ns;
LOW
HD:DAT
EDGE
SU:DAT
EDGE
EDGE
for the DS28C36B, t
max = 200ns. Values greater than these can be accommodated by extending t
accordingly.
of the SCL signal) to bridge
EDGE
LOW
Note 11: The DS28C36 provides a hold time of at least 100ns for the SDA signal (referred to the V
IH(MIN)
the undefined region of the falling edge of SCL. The master can provide a hold time of 0ns when writing to the device.
2
Note 12: The DS28C36 can be used in a standard-mode I C bus system, but the requirement t
≥ 250ns must then be met
SU:DAT
2
(I C bus specification Rev. 03, 19 June 2007).
Note 13: C = total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending
B
2
on the actual operating voltage and frequency of the application (I C bus specification Rev. 03, 19 June 2007).
2
Note 14: I C communication should not take place for max t
time following a power-on reset.
OSCWUP
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ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Pin Configuration
TOP VIEW
SCL
1
2
3
6
5
4
V
CC
PIOA
PIOB
SDA
GND
DS28C36
EP*
TDFN-EP
(3mm x 3mm)
Pin Description
PIN
1
NAME
SCL
FUNCTION
2
I C CLK. Connect to V
with a pullup resistor.
with a pullup resistor.
CC
2
2
SDA
I C Data. Connect to V
Ground
CC
3
GND
PIOB
PIOA
4
General-Purpose IO
General-Purpose IO
Supply Voltage
5
6
V
CC
Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to Application
Note 3273: Exposed Pads: A Brief Introduction for additional information.
—
EP
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ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Typical Application Circuit
3.3V
R
P3
R
P2
R
R
P4
P1
V
CC
V
CC
DS28C36
2
I C
IO
SDA
SCL
PIOA
PIOB
PORT
IO
µC
GND
GND
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
6 TDFN-EP*
-40°C to +85°C
DS28C36Q+T†
(2.5k pcs)
6 TDFN-EP*
-40°C to +85°C
DS28C36BQ+T
(2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T= Tape and reel.
*EP = Exposed pad.
†Not recommended for new designs.
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ABRIDGED DATA SHEET
DS28C36
DeepCover Secure Authenticator
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/16
Initial release
—
Updated Electrical Characteristics and Notes, Typical Operating Conditions,
authenticated SHA2 Write Memory HMAC input tables, and general corrections
1
10/18
1–63
Added indications of GPIO volatility in the Memory Resources section, Table 1,
and power-up states in Table 5
2
3
1/19
7, 10
2
12/20
Updated Package Information
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2020 Maxim Integrated Products, Inc.
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