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DS28E36

DeepCover Secure Authenticator

General Description

Beneﬁts and Features

● ECC-256 Compute Engine

®

The DS28E36 is a DeepCover secure authenticator

that provides a core set of cryptographic tools derived

from integrated asymmetric (ECC-P256) and symmetric

(SHA-256) security functions. In addition to the security

services provided by the hardware implemented crypto

engines, the device integrates a FIPS/NIST true random

number generator (RNG), 8Kb of secured EEPROM, a

decrement-only counter, two pins of configurable GPIO,

and a unique 64-bit ROM identification number (ROM

ID). This unique ROM ID is used as a fundamental input

parameter for cryptographic operations and also serves

as an electronic serial number within the application. The

• FIPS 186 ECDSA P256 Signature and Veriﬁcation

• ECDH Key Exchange with Authentication Prevents

Man-in-the-Middle Attacks

• ECDSA Authenticated R/W of Conﬁgurable

Memory

● SHA-256 Compute Engine

• FIPS 180 MAC for Secure Download/Boot

Operations

• FIPS 198 HMAC for Bidirectional Authentication

and Optional GPIO Control

● Two GPIO Pins with Optional Authentication Control

• Open-Drain, 4mA/0.4V

®

DS28E36 communicates over the single-contact 1-Wire

bus at overdrive speed. The communication follows the

1-Wire protocol with the ROM ID acting as node address

in the case of a multidevice 1-Wire network.

• Optional SHA-256 or ECDSA Authenticated On/Oﬀ

and State Read

• Optional Set On/Oﬀ after Multiblock Hash for

Secure Boot/Download

The ECC public/private key capabilities operate from

the NIST defined P-256 curve and include FIPS 186

compliant ECDSA signature generation and verification

to support a bidirectional asymmetric key authentication

model. The SHA-256 secret-key capabilities are compli-

ant with FIPS 180 and are flexibly used either in conjunc-

tion with ECDSA operations or independently for multiple

HMAC functions.

● RNG with NIST SP 800-90B Compliant Entropy

Source with Function to Read Out

● Optional Chip Generated Pr/Pu Key Pairs for ECC

Operations

● 17-Bit One-Time Settable, Nonvolatile Decrement-

Only Counter with Authenticated Read

Two GPIO pins can be independently operated under

command control and include configurability supporting

authenticated and nonauthenticated operation including

an ECDSA-based crypto-robust mode to support secure-

boot of a host processor.

● 8Kbits of EEPROM for User Data, Keys, and

Certificates

● Unique and Unalterable Factory Programmed 64-Bit

Identification Number (ROM ID)

• Optional Input Data Component to Crypto and Key

Operations

DeepCover embedded security solutions cloak sensitive

data under multiple layers of advanced security to provide

the most secure key storage possible. To protect against

device-level security attacks, invasive and noninvasive

countermeasures are implemented including active die

shield, encrypted storage of keys, and algorithmic methods.

● Single-Contact 1-Wire Interface Communication with

Host at 11.7kbps and 62.5kbps

● Operating Range: 3.3V ±10%, -40°C to +85°C

● 6-Pin TDFN-EP Package (3mm x 3mm)

Applications

● IoT Node Crypto-Protection

Ordering Information and Typical Application Circuit appear

at end of data sheet.

● Accessory and Peripheral Secure Authentication

● Secure Storage of Cryptographic Keys for a Host

Controller

● Secure Boot or Download of Firmware and/or System

Parameters

1-Wire and DeepCover are registered trademarks of Maxim

Integrated Products, Inc.

19-100170; Rev 3; 3/20

DS28E36

DeepCover Secure Authenticator

Absolute Maximum Ratings

Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V

Maximum Current into Any Pin...........................................20mA

Operating Temperature Range........................... -40°C to +85°C

Junction Temperature......................................................+125°C

Storage Temperature Range............................ -55°C to +125°C

Lead temperature (soldering, 10s)..................................+300°C

Soldering Temperature (reflow)...................................... +260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

6 TDFN-EP

PACKAGE CODE

T633+2

Outline Number

21-0137

90-0058

Land Pattern Number

Thermal Resistance, Single-Layer Board:

Junction to Ambient (θ

)

55ºC/W

9ºC/W

JA

Junction to Case (θ

)

JC

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θ

)

42ºC/W

9ºC/W

JA

Junction to Case (θ

)

JC

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial

Electrical Characteristics

Limits are 100% production tested at T = +25°C and T = +85°C. Typical values are at T = +25°C. Limits over the operating tem-

A

perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are

guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and

are not production tested.

PARAMETER

IO PIN: GENERAL DATA

1-Wire Pullup Voltage

1-Wire Pullup Resistance

Input Capacitance

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

R

(Note 1)

2.97

300

3.3

3.63

V

PUP

(Notes 1, 2)

(Note 3)

1000

Ω

PUP

C

0.1 + Cx

nF

µA

IO

Capacitor External

C

(Note 1)

399.5

470

6

540.5

250

X

Input Load Current

I

IO pin at V

PUP

L

During t , t

(Note 20)

, t

or t

RM WM CMP VES GKP GES

Computation Current

Computation Voltage

I

7.5

mA

V

SPU

Voltage at IO pin during t , t

, t

,

RM WM CMP

V

2.2

SPU

t

, t

, or t

(Note 20)

VES GKP

GES

High-to-Low Switching

Threshold

0.65 x

V

(Notes 4, 5, 6)

(Note 7)

V

TL

V

PUP

0.10 x

Input Low Voltage

V

IL

V

PUP

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DS28E36

DeepCover Secure Authenticator

Electrical Characteristics (continued)

Limits are 100% production tested at T = +25°C and T = +85°C. Typical values are at T = +25°C. Limits over the operating tem-

A

perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are

guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and

are not production tested.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Low-to-High Switching

Threshold

0.75 x

V

(Notes 4, 5, 8)

(Notes 4, 5, 9)

V

TH

V

PUP

Switching Hysteresis

Output Low Voltage

V

0.3

V

HY

I

= 4mA (Note 10)

0.4

OL

Standard speed, R

= 1000Ω

25

10

Recovery Time

(Notes 1, 11, 12)

PUP

t

µs

REC

REH

Overdrive speed, R

PUP

Rising-Edge Hold-oﬀ Time

(Notes 4, 13)

t

Applies to standard speed only

1

Standard speed

Overdrive speed

85

16

Time Slot Duration (Notes 1, 14)

t

SLOT

IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE

Standard speed

480

48

640

80

Reset Low Time

(Note 1)

t

µs

RSTL

Overdrive speed

Standard speed

Overdrive speed

Standard speed

Overdrive speed

Standard speed

Overdrive speed

480

48

Reset High Time (Notes 1, 15)

t

RSTH

1.25

0.15

Presence Detect Fall Time

(Notes 4, 16)

t

FPD

MSP

65

7

75

10

Presence-Detect Sample Time

(Notes 1, 17)

t

IO PIN: 1-Wire WRITE

Standard speed

Overdrive speed

Standard speed

Overdrive speed

60

6

120

16

15

2

Write-Zero Low Time

(Notes 1, 18)

t

µs

W0L

W1L

0.25

Write-One Low Time

(Notes 1, 18)

IO PIN: 1-Wire READ

Standard speed

Overdrive speed

Standard speed

Overdrive speed

0.25

15 - δ

2 - δ

15

Read Low Time

(Notes 1, 19)

t

µs

RL

t

+ δ

Read Sample Time

(Notes 1, 19)

RL

t

MSR

+ δ

2

PIOA AND PIOB PINS

Output Low

PIOV

PIOI = 4mA (Note 10)

0.4

V

OL

0.15 x

Input Low

PIOV

-0.3

0.7 x

IL

V

PUP

V

PUP

Input High

PIOV

PIOI

V

IH

V

PUP

-1

+ 0.3

+1

Leakage Current

µA

L

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DS28E36

DeepCover Secure Authenticator

Electrical Characteristics (continued)

Limits are 100% production tested at T = +25°C and T = +85°C. Typical values are at T = +25°C. Limits over the operating tem-

A

perature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are

guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and

are not production tested.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STRONG PULLUP OPERATION

Generate ECDSA Signature Time

Generate ECC Key Pair

t

(Note 1)

50

ms

GES

100

GKP

Verify ECDSA Signature or

Compute ECDH Time

t

(Note 1)

150

3

ms

VES

Computation Time (HMAC or RNG)

EEPROM

t

CMP

Read Memory Time

Write Memory Time

Write/Erase Cycles (Endurance)

Data Retention

t

(Note 1)

(Note 21)

1

ms

RM

t

15

WM

N

100k

10

—

CY

DR

t

T

= +85°C (Note 22)

Years

A

POWER-UP

Power-Up Time

t

(Notes 1, 23)

2

ms

OSCWUP

Note 1: System requirement.

Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 3: Value represents the internal parasite capacitance when V

is first applied. Once the parasite capacitance is charged, it does

PUP

not affect normal communication. Typically, during normal communication, the internal parasite capacitance is effectively ~100pF.

Note 4: Guaranteed by design and/or characterization only. Not production tested.

Note 5: V , V , and V

are a function of the internal supply voltage, which is a function of V

, R

, 1-Wire timing, and

TL TH

HY

PUP PUP

capacitive loading on IO. Lower V

, higher R

, shorter t

, and heavier capacitive loading all lead to lower values of

PUP

REC

V

, V , and V

.

TL TH

HY

Note 6: Voltage below which, during a falling edge on IO, a logic-zero is detected.

Note 7: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.

ILMAX

Note 8: Voltage above which, during a rising edge on IO, a logic-one is detected.

Note 9: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V

to be detected as logic-zero.

TH

HY

Note 10: The I-V characteristic is linear for voltages less than 1V.

Note 11: Applies to a single device attached to a 1-Wire line.

Note 12: t

min covers operation at worst-case temperature V

, R

, C , t

, t

, and t . t

can be significantly

REC

PUP PUP

X

RSTL WOL

RL RECMIN

reduced under less extreme conditions. Contact the factory for more information.

Note 13: The earliest recognition of a negative edge is possible at t after V has been previously reached.

REH

TH

Note 14: Defines maximum possible bit rate. Equal to 1/(t

+ t

).

W0LMIN

RECMIN

Note 15: An additional reset of communication sequence sequence cannot begin until the reset high time has expired.

Note 16: Time from V = 80% of V and V = 20% of V at the negative edge on IO at the beginning of the Presence

(IO)

PUP

(IO)

PUP

Detect pulse.

Note 17: Interval after t

during which a bus master can read a logic 0 on IO if there is a DS28E36 present.

RSTL

Note 18: ε in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V

.

IL

TH

Note 19: δ in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high

IL

threshold of the bus master.

Note 20: I

is the current drawn from IO during a strong pullup (SPU) operation. The pullup circuit on IO during the SPU operation

SPU

should be such that the voltage at IO is greater than or equal to V

. A low-impedance bypass of R

activated

SPUMIN

PUP

during the SPU operation is the recommended way to meet this requirement.

Note 21: Write-cycle endurance is tested in compliance with JESD47H.

Note 22: Data retention is tested in compliance with JESD47H.

Note 23: 1-Wire communication should not take place for at least t

after V

reaches V

min.

OSCWUP

PUP

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DS28E36

DeepCover Secure Authenticator

Pin Conﬁguration

Pin Description

1

NAME

N.C.

FUNCTION

No Connection

TOP VIEW

2

IO

1-Wire IO

N.C.

IO

1

2

3

6 CEXT

3

GND

PIOB

PIOA

CEXT

Ground

4

General-Purpose IO

Input for External Capacitor

PIOA

5

DS28E36

5

6

*EP

PIOB

4

GND

Exposed Pad (TDFN Only). Solder

evenly to the board’s ground plane for

proper operation. Refer to Application

Note 3273: Exposed Pads: A Brief

Introduction for additional information.

TDFN-EP

(3mm x 3mm)

—

EP

operated under command control and include configu-

rability supporting authenticated and nonauthenticated

operation including an ECDSA-based crypto-robust mode

to support secure-boot of a host processor.

Detailed Description

The DS28E36 is a secure authenticator that supports

multiple asymmetric (ECC-P256) and symmetric (SHA-

256) security functions. In addition to the security services

provided by the hardware implemented ECC and SHA-

256 engines, the device integrates a FIPS/NIST true ran-

dom number generator (RNG), 8Kb of secured EEPROM,

a decrement-only counter, two pins of configurable GPIO,

and a unique 64-bit serial number. The ECC public/private

key capabilities operate from the NIST defined P-256

curve and include FIPS 186 compliant ECDSA signature

generation and verification for bidirectional asymmetric

key authentication. Additionally, through FIPS/NIST 800-

56B ECDH-based key agreement, the device supports

secure storage and host communication of sensitive

data, such as application-specific crypto keys that would

be used independently by a host processor. The SHA-

256 secret-key capabilities are compliant with FIPS 180

and are flexibly used either in conjunction with ECDSA

operations or independently for multiple MAC and HMAC

functions. Through the integrated RNG, the device further

enhances system crypto functionality with the ability to

supply FIPS-grade random numbers to a host processor

along with internal-only functions including nonce values

for ECDSA operation and optional generation of its ECC

private keys. Two pins of GPIO can be independently

The DS28E36 integrates an 8Kb secured EEPROM array

to store keys, certificates, general-purpose data and

control registers. Multiple user-programmable protec-

tion modes exist for the general-purpose memory space

including open, ECDSA R/W authentication protection,

SHA-256 HMAC R/W authentication protected, and SHA-

256 one-time-pad (OTP) R/W encryption in conjunction

with an ECDH established key. With these options, gen-

eral-purpose memory can be flexibly configured to store

end application data ranging from nonsensitive calibration

constants to critically sensitive host-system crypto keys.

The DS28E36 also provides a dedicated 17-bit counter

that operates in a decrement-only mode to support appli-

cations where limited use requirements exist and must be

tracked. Once set and upon command, the device decre-

ments the counter value by 1. After the counter reaches a

value of 0, no additional changes are possible. To prevent

reply attacks, a read of the counter is performed with user-

selectable ECDSA or SHA-256 HMAC authentication.

The block diagram in Figure 1 shows the relationships

between the circuit elements of the DS28E36.

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DS28E36

DeepCover Secure Authenticator

CX

PARASITE

POWER

Cext

DS28E36

64-BIT ROM ID

BUFFER

IO

1-Wire FUNCTION

CONTROL

And

ECC (256)

SHA-256

COMMAND

RNG

USER MEMORY

KEYS

DECREMENT COUNTER

COMPUTE

CONTROL

PIOA

PIOB

AUTHENTICATED

GPIO

Figure 1. Simplified Block Diagram

follow the state flow diagrams of Figure 2 and Figure 3.

Within these flow diagrams, the data transfer is verified

when writing and reading by a CRC of 16-bit type (CRC-

16). The CRC-16 is computed as described in Maxim’s

Application Note 27.

Design Resource Overview

Operation of the DS28E36 involves use of device

EEPROM and execution of device function commands.

The following provides an overview including the dec-

rement counter and GPIO pins. Refer to the DS28E36

Security Guide for full details.

Decrement Counter

The 17-bit decrement only counter can be written/initial-

ized one time. If unwritten, it reads as random data and

cannot be authenticated with a read. A dedicated device

function command is used to decrement the count value

by one with each call. Once the count value reaches a

value of 0, no additional decrements are possible.

Memory

A secured 8kbit EEPROM array is divided into two 4kbit

regions. One 4kbit space for user-programmable and

configurable memory, the other 4kbit space for registers

including ECC and SHA-256 keys, the decrement-only

counter, and programmable device control functions.

Depending on the register function, there are either

default or user-programmable protection modes.

GPIO Control

State setting and/or reads of the two open-drain GPIO

pins is controlled in accordance with user-programmable

protection settings. Multiple protection options exist based

on ECDSA, ECDH key establishment, or SHA256-HMAC.

Function Commands

After a 1-Wire Reset/Presence cycle and ROM function

command sequence is successful, a device function com-

mand can be accepted. These commands, in general,

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DS28E36

DeepCover Secure Authenticator

N

MASTER Tx MEMORY

FUNCTION COMMAND

READ MEMORY

COMMAND

N

MASTER Tx MEMORY

EX CMD

FUNCTION COMMAND

DATA WRITE

Y

FROM ROM FUNCTIONS

FLOW CHART (FIGURE 7)

Y

MASTER Tx

PARAMETER(S)

FROM ROM FUNCTIONS

FLOW CHART (FIGURE 7)

MASTER Tx

PARAMETER(S)

MASTER Rx CRC-16 OF CMD

AND PARAMETER(S)

MASTER Rx CRC-16 OF CMD

AND PARAMETER(S)

N

MASTER Tx

DATA BYTE(S)

MASTER Tx

RELEASE?

Y

N

MASTER Rx

RELEASE?

DELAY WITH STRONG PULLUP

Y

MASTER Rx MEMORY

DATA BYTES

DELAY WITH STRONG PULLUP

MASTER Tx RESULT BYTE

(AAh FOR SUCCESS)

MASTER Rx CRC-16 OF

DATA BYTE

MASTER Rx CRC-16 OF RESULT

BYTE

N

MASTER

Rx 1s

MASTER Tx

RESET?

N

MASTER

Rx 1s

MASTER Tx

RESET?

Y

FROM ROM FUNCTIONS

FLOW CHART (FIGURE 7)

Y

FROM ROM FUNCTIONS

FLOW CHART (FIGURE 7)

Figure 3. 1-Wire Device Data Read Flow Chart

Figure 2. 1-Wire Device Execute Command or Data Write

Flow Chart

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DS28E36

DeepCover Secure Authenticator

The idle state for the 1-Wire bus is high. If for any reason

a transaction needs to be suspended, the bus must be

left in the idle state if the transaction is to resume. If this

does not occur and the bus is left low for more than 16μs

(overdrive speed) or more than 120μs (standard speed),

one or more devices on the bus could be reset.

1-Wire Bus System

The 1-Wire bus is a system that has a single bus master

and one or more slaves. In all instances, the DS28E36 is

a slave device. The bus master is typically a microcon-

troller. The discussion of this bus system is broken down

into three topics: hardware configuration, transaction

sequence, and 1-Wire signaling (signal types and timing).

The 1-Wire protocol defines bus transactions in terms of

the bus state during specific time slots, which are initiated

on the falling edge of sync pulses from the bus master.

Transaction Sequence

The protocol for accessing the DS28E36 through the

1-Wire port is as follows:

● Initialization

Hardware Conﬁguration

● ROM function command

● Memory function command

● Transaction/data

The 1-Wire bus has only a single line by definition; it is

important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device

attached to the 1-Wire bus must have open-drain or three-

state outputs. The 1-Wire port of the DS28E36 is open

drain with an internal circuit equivalent to that shown in

Figure 4.

Initialization

All transactions on the 1-Wire bus begin with an initializa-

tion sequence. The initialization sequence consists of a

reset pulse transmitted by the bus master followed by

presence pulse(s) transmitted by the slave(s). The pres-

ence pulse lets the bus master know that the DS28E36 is

on the bus and is ready to operate. For more details, see

the 1-Wire Signaling and Timing section.

A multidrop bus consists of a 1-Wire bus with multiple

slaves attached. The DS28E36 supports both a standard

and overdrive communication speed of 11.7kbps (max)

and 62.5kbps (max), respectively. The value of the pullup

resistor primarily depends on the network size and load

conditions. The DS28E36 requires a pullup resistor of

1kΩ (max) at any speed.

V

PUP

*SEE NOTE

1-WIRE SLAVE PORT

BUS MASTER

C

X

Tx

PIOX

PIOY

CTL

Rx

R

PUP

Rx

Tx

DATA

I

L

Tx

Rx = RECEIVE

Tx = TRANSMIT

BIDIRECTIONAL

OPEN-DRAIN PORT

100Ω

MOSFET

*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY

Figure 4. Hardware Configuration

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DS28E36

DeepCover Secure Authenticator

remains in overdrive mode. If the device is in overdrive

1-Wire Signaling and Timing

mode and t

is between 80μs and 480μs, the device

RSTL

The DS28E36 requires strict protocols to ensure data

integrity. The protocol consists of four types of signaling

on one line: reset sequence with reset pulse and presence

pulse, write-zero, write-one, and read-data. Except for the

presence pulse, the bus master initiates all falling edges.

The DS28E36 can communicate at two speeds: standard

and overdrive. If not explicitly set into the overdrive mode,

the DS28E36 communicates at standard speed. While in

overdrive mode, the fast timing applies to all waveforms.

resets, but the communication speed is undetermined.

After the bus master has released the line, it goes into

receive mode. Now, the 1-Wire bus is pulled to V

PUP

through the pullup resistor or, in the case of a special

driver chip, through the active circuitry. Now, the 1-Wire

bus is pulled to V

the threshold V

through the pullup resistor. When

is crossed, the DS28E36 waits and

PUP

TH

then transmits a presence pulse by pulling the line low. To

detect a presence pulse, the master must test the logical

To get from idle to active, the voltage on the 1-Wire line

state of the 1-Wire line at t

.

MSP

needs to fall from V

below the threshold V . To get

PUP

TL

Immediately after t

RSTH

has expired, the DS28E36 is

from active to idle, the voltage needs to rise from V

ILMAX

ready for data communication. In a mixed population net-

work, t should be extended to a minimum 480μs at

past the threshold V . The time it takes for the voltage

to make this rise is seen in Figure 6 as ε, and its dura-

TH

RSTH

standard speed and a 48μs at overdrive speed to accom-

modate other 1-Wire devices.

tion depends on the pullup resistor (R

) used and the

PUP

capacitance of the 1-Wire network attached. The voltage

is relevant for the DS28E36 when determining a

V

ILMAX

Read/Write Time Slots

logical level, not triggering any events.

Data communication with the DS28E36 takes place in

time slots that carry a single bit each. Write time slots

transport data from bus master to slave. Read time slots

transfer data from slave to master. Figure 6 illustrates the

definitions of the write and read time slots.

Figure 5 shows the initialization sequence required to

begin any communication with the DS28E36. A reset pulse

followed by a presence pulse indicates that the DS28E36

is ready to receive data, given the correct ROM and

memory function command. If the bus master uses slew-

rate control on the falling edge, it must pull down the line

All communication begins with the master pulling the data

line low. As the voltage on the 1-Wire line falls below

for t

+ t to compensate for the edge. A t dura-

RSTL

F

RSTL

the threshold V , the DS28E36 starts its internal timing

TL

tion of 480μs or longer exits the overdrive mode, returning

the device to standard speed. If the DS28E36 is in over-

generator that determines when the data line is sampled

during a write time slot and how long data is valid during

a read time slot.

drive mode and t

is no longer than 80μs, the device

RSTL

MASTER TX “RESET PULSE”

MASTER RX “PRESENCE PULSE”

t

MSP

ε

V

PUP

V

IHMASTER

V

TH

V

TL

V

ILMAX

0V

t

REC

F

RSTL

t

RSTH

MASTER

1-WIRE SLAVE

RESISTOR (R

)

PUP

Figure 5. Initialization Procedure: Reset and Presence Pulse

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DS28E36

DeepCover Secure Authenticator

WRITE-ONE TIME SLOT

t

W1L

V

PUP

V

IHMASTER

V

TH

V

TL

V

ILMAX

0V

t

ε

F

t

SLOT

MASTER

RESISTOR (R

)

PUP

WRITE-ZERO TIME SLOT

t

W0L

V

PUP

V

IHMASTER

V

TH

V

TL

V

ILMAX

0V

t

ε

F

t

REC

t

SLOT

MASTER

RESISTOR (R

)

PUP

READ-DATA TIME SLOT

t

MSR

t

RL

V

PUP

V

IHMASTER

V

TH

MASTER SAMPLING

WINDOW

V

TL

V

ILMAX

0V

δ

t

F

t

REC

t

SLOT

MASTER

1-WIRE SLAVE

RESISTOR (R

)

PUP

Figure 6. Read/Write Timing Diagrams

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DS28E36

DeepCover Secure Authenticator

Master-to-Slave

Read ROM [33h]

For a write-one time slot, the voltage on the data line

The Read ROM command allows the bus master to read

the DS28E36’s 8-bit family code, unique 48-bit serial

number, and 8-bit CRC. This command can only be used

if there is a single slave on the bus. If more than one

slave is present on the bus, a data collision occurs when

all slaves try to transmit at the same time (open drain

produces a wired-AND result). The resultant family code

and 48-bit serial number result in a mismatch of the CRC.

must have crossed the V

threshold before the write-

TH

one low time t

is expired. For a write-zero time

W1LMAX

slot, the voltage on the data line must stay below the V

TH

threshold until the write-zero low time t

is expired.

W0LMIN

For the most reliable communication, the voltage on the

data line should not exceed V during the entire

ILMAX

t

or t

window. After the V

threshold has been

W0L

W1L

TH

crossed, the DS28E36 needs a recovery time t

it is ready for the next time slot.

before

REC

Match ROM [55h]

The Match ROM command, followed by a 64-bit ROM

sequence, allows the bus master to address a specific

DS28E36 on a multidrop bus. Only the DS28E36 that

exactly matches the 64-bit ROM sequence responds to

the subsequent memory function command. All other

slaves wait for a reset pulse. This command can be used

with a single device or multiple devices on the bus.

Slave-to-Master

A read-data time slot begins like a write-one time slot.

The voltage on the data line must remain below V until

TL

the read low time t

is expired. During the t window,

RL

when responding with a 0, the DS28E36 starts pulling

the data line low; its internal timing generator determines

when this pulldown ends and the voltage starts rising

again. When responding with a 1, the DS28E36 does not

hold the data line low at all, and the voltage starts rising

Search ROM [F0h]

When a system is initially brought up, the bus master

might not know the number of devices on the 1-Wire bus

or their ROM ID numbers. By taking advantage of the

wired-AND property of the bus, the master can use a pro-

cess of elimination to identify the ID of all slave devices.

For each bit in the ID number, starting with the least sig-

nificant bit, the bus master issues a triplet of time slots.

On the first slot, each slave device participating in the

search outputs the true value of its ID number bit. On the

second slot, each slave device participating in the search

outputs the complemented value of its ID number bit. On

the third slot, the master writes the true value of the bit

to be selected. All slave devices that do not match the

bit written by the master stop participating in the search.

If both of the read bits are zero, the master knows that

slave devices exist with both states of the bit. By choos-

ing which state to write, the bus master branches in the

search tree. After one complete pass, the bus master

knows the ROM ID number of a single device. Additional

passes identify the ID numbers of the remaining devices.

Refer to Application Note 187: 1-Wire Search Algorithm

for a detailed discussion, including an example.

as soon as t is over.

RL

The sum of t + δ (rise time) on one side and the internal

RL

timing generator of the DS28E36 on the other side define

the master sampling window (t

to t

), in

MSRMIN

MSRMAX

which the master must perform a read from the data line.

For the most reliable communication, t should be as

RL

short as permissible, and the master should read close

to but no later than t . After reading from the data

MSRMAX

line, the master must wait until t

guarantees sufficient recovery time t

is expired. This

for the DS28E36

SLOT

REC

to get ready for the next time slot. Note that t

speci-

REC

fied herein applies only to a single DS28E36 attached to a

1-Wire line. For multidevice configurations, t must be

REC

extended to accommodate the additional 1-Wire device

input capacitance. Alternatively, an interface that performs

active pullup during the 1-Wire recovery time such as the

special 1-Wire line drivers can be used.

1-Wire ROM Function Commands

Once the bus master has detected a presence, it can

issue one of the seven ROM function commands that the

DS28E36 supports. All ROM function commands are 8

bits long. A list of these commands follows (see the flow-

chart in Figure 7-1 and Figure 7-2).

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DS28E36

DeepCover Secure Authenticator

overdrive speed until a reset pulse of minimum 480μs

duration resets all devices on the bus to standard speed

(OD = 0).

Skip ROM [CCh]

This command can save time in a single-drop bus sys-

tem by allowing the bus master to access the memory

functions without providing the 64-bit ROM ID. If more

than one slave is present on the bus and, for example,

a read command is issued following the Skip ROM com-

mand, data collision occurs on the bus as multiple slaves

transmit simultaneously (open-drain pulldowns produce a

wired-AND result).

When issued on a multidrop bus, this command sets all

overdrive-supporting devices into overdrive mode. To

subsequently address a specific overdrive-supporting

device, a reset pulse at overdrive speed must be issued

followed by a Match ROM or Search ROM command

sequence. This speeds up the time for the search pro-

cess. If more than one slave supporting overdrive is pres-

ent on the bus and the Overdrive-Skip ROM command

is followed by a read command, data collision occurs on

the bus as multiple slaves transmit simultaneously (open-

drain pulldowns produce a wired-AND result).

Resume [A5h]

To maximize the data throughput in a multidrop environ-

ment, the Resume command is available. This command

checks the status of the RC bit and, if it is set, directly

transfers control to the memory function commands, simi-

lar to a Skip ROM command. The only way to set the RC

bit is by successfully executing the Match ROM, Search

ROM, or Overdrive-Match ROM command. Once the RC

bit is set, the device can repeatedly be accessed through

the Resume command. Accessing another device on the

bus clears the RC bit, preventing two or more devices from

simultaneously responding to the Resume command.

Overdrive-Match ROM [69h]

The Overdrive-Match ROM command followed by a 64-bit

ROM sequence transmitted at overdrive speed allows the

bus master to address a specific DS28E36 on a multi-

drop bus and to simultaneously set it in overdrive mode.

Only the DS28E36 that exactly matches the 64-bit ROM

sequence responds to the subsequent memory function

command. Slaves already in overdrive mode from a previ-

ous Overdrive-Skip ROM or successful Overdrive-Match

ROM command remain in overdrive mode. All overdrive-

capable slaves return to standard speed at the next reset

pulse of minimum 480μs duration. The Overdrive-Match

ROM command can be used with a single device or mul-

tiple devices on the bus.

Overdrive-Skip ROM [3Ch]

On a single-drop bus this command can save time by

allowing the bus master to access the memory functions

without providing the 64-bit ROM ID. Unlike the normal

Skip ROM command, the Overdrive-Skip ROM command

sets the DS28E36 into the overdrive mode (OD = 1). All

communication following this command must occur at

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DS28E36

DeepCover Secure Authenticator

BUS MASTER Tx

RESET PULSE

FROM ROM FUNCTION FLOW PART 2

FROM DEVICE FUNCTIONS

FLOW CHART

N

OD

OD = 0

RESET PULSE?

Y

BUS MASTER Tx

SLAVE Tx

ROM FUNCTION COMMAND

PRESENCE PULSE

33h

55h

F0h

N

CCh

N

READ ROM

COMMAND?

MATCH ROM

COMMAND?

SEARCH ROM

COMMAND?

SKIP ROM

COMMAND?

TO ROM FUNCTION

FLOW PART 2

Y

RC = 0

SLAVE Tx BIT 0

MASTER Tx BIT 0

SLAVE Tx

FAMILY CODE

(1 BYTE)

MASTER Tx BIT 0

N

BIT 0 MATCH?

Y

BIT 0 MATCH?

Y

SLAVE Tx BIT 1

MASTER Tx BIT 0

SLAVE Tx

SERIAL NUMBER

(6 BYTES)

MASTER Tx BIT 1

Y

N

BIT 1 MATCH?

Y

BIT 1 MATCH?

Y

SLAVE Tx BIT 63

MASTER Tx BIT 63

SLAVE Tx

CRC BYTE

MASTER Tx BIT 63

N

BIT 63 MATCH?

RC = 1

BIT 63 MATCH?

RC = 1

TO ROM FUNCTION

FLOW PART 2

FROM ROM FUNCTION FLOW PART 2

Figure 7-1. ROM Functions Flow Chart

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DS28E36

DeepCover Secure Authenticator

TO ROM FUNCTION FLOW PART 1

FROM ROM

FUNCTION

FLOW PART 1

A5h

3Ch

69h

N

RESUME

COMMAND?

OVERDRIVE-

SKIP ROM?

OVERDRIVE-

MATCH ROM?

Y

RC = 0; OD = 1

N

RC = 1?

MASTER Tx BIT 0

Y

N

MASTER Tx

RESET?

BIT 0 MATCH?

Y

OD = 0

N

MASTER Tx BIT 1

Y

MASTER Tx

RESET?

N

BIT 1 MATCH?

Y

OD = 0

SLAVE Tx BIT 63

N

BIT 63 MATCH?

RC = 1

OD = 0

FROM ROM FUNCTION

FLOW PART 1

TO ROM FUNCTION FLOW PART 1

TO DEVICE FUNCTIONS

FLOW CHART

Figure 7-2. ROM Functions Flow Chart (continued)

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DS28E36

DeepCover Secure Authenticator

The DS28E36’s 1-Wire front-end has the following features:

Improved Network Behavior

(Switchpoint Hysteresis)

● The falling edge of the presence pulse has a con-

trolled slew rate to reduce ringing. The slew rate con-

In a 1-Wire environment, line termination is possible only

during transients controlled by the bus master (1-Wire

driver). 1-Wire networks, therefore, are susceptible to

noise of various origins. Depending on the physical size

and topology of the network, reflections from end points

and branch points can add up or cancel each other to

some extent. Such reflections are visible as glitches or

ringing on the 1-Wire communication line. Noise coupled

onto the 1-Wire line from external sources can also result

in signal glitching. A glitch during the rising edge of a time

slot can cause a slave device to lose synchronization with

the master and, consequently, result in a Search ROM

command coming to a dead end or cause a device-spe-

cific function command to abort. For better performance

in network applications, the DS28E36 uses a 1-Wire front-

end that is less sensitive to noise.

trol is specified by t

.

FPD

● There is a hysteresis at the low-to-high switching

threshold V . If a negative glitch crosses V , but

TH

does not go below V - V , it is not recognized

(Figure 8, Case A). The hysteresis is effective at any

1-Wire speed.

TH

HY

● There is a time window specified by the rising edge

hold-off time t

during which glitches are ignored,

REH

even if they extend below the V - V

(Figure 8, Case B, t < t

or glitches that appear late after crossing the V

threshold and extend beyond the t

not be filtered out and are taken as the beginning of

a new time slot (Figure 8, Case C, t ≥ t ).

threshold

). Deep voltage drops

TH

HY

GL

REH

TH

window can-

REH

GL

REH

t

REH

t

REH

V

PUP

V

TH

V

HY

CASE A

CASE B

CASE C

0V

t

GL

Figure 8. Noise Suppression Scheme

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DS28E36

DeepCover Secure Authenticator

Typical Application Circuit

V

CC

100kΩ

R

P

R

PUP

Q1

1kΩ

V

CC

PIOX

IO

X

PIOA

PIOB

IO

*PMV65XP

BIDIRECTIONAL

OPEN-DRAIN PORT

DS28E36

µC

PIOY

GND

IO

C

EXT

C

GND

*NOTE: USE A Q1 LOW-IMPEDANCE BYPASS

OR EQUALLY DRIVE LOGIC 1 WITH PIOY

Package Information

Ordering Information

For the latest package outline information and land pat-

terns (footprints), go to www.maximintegrated.com/

packages. Note that a “+”, “#”, or “-” in the package code

indicates RoHS statusonly. Package drawings may show

a different suffix character, but the drawing pertains to the

package regardless of RoHS status.

PART

TEMP RANGE

PIN-PACKAGE

6 TDFN-EP*

(2.5k pcs)

DS28E36Q+T†

-40°C to +85°C

6 TDFN-EP*

(2.5k pcs)

DS28E36BQ+T

-40°C to +85°C

+Denotes a lead(Pb)-free/RoHS-compliant package.

T= Tape and reel.

*EP = Exposed pad.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

†Not recommended for new designs.

6 TDFN-EP*

T633+2

21-0137

90-0058

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DS28E36

DeepCover Secure Authenticator

Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

10/17

11/18

3/20

0

1

2

3

Initial release

—

2

Updated Package Information section

Updated Ordering Information section

Updated Typical Application Circuit

16

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2018 Maxim Integrated Products, Inc.

│ 17


型号：	DS28E36
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	DeepCover Secure Authenticator
文件：	总17页 (文件大小：447K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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