DS3234S [MAXIM]
Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM; 超高精度， SPI总线RTC，集成晶体和SRAM
| 型号： | DS3234S |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM |
| 文件： | 总20页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 2/06
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
General Description
Features
♦ Accuracy ±2ppm from 0°C to +40°C
The DS3234 is a low-cost, extremely accurate SPI™ bus
real-time clock (RTC) with an integrated temperature-
compensated crystal oscillator (TCXO) and crystal. The
DS3234 incorporates a precision, temperature-compen-
sated voltage reference and comparator circuit to moni-
♦ Accuracy ±3.5ppm from -40°C to +85°C
♦ Battery Backup Input for Continuous
Timekeeping
♦ Operating Temperature Ranges
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
tor V . When V
PF
drops below the power-fail voltage
CC
CC
(V ), the device asserts the RST output and also dis-
ables read and write access to the part when V drops
CC
♦ Low-Power Consumption
below both V and V
. The RST pin is monitored as
BAT
PF
♦ Real-Time Clock Counts Seconds, Minutes,
Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2099
a pushbutton input for generating a reset externally. The
device switches to the backup supply input and main-
tains accurate timekeeping when main power to the
device is interrupted. The integration of the crystal res-
onator enhances the long-term accuracy of the device
as well as reduces the piece-part count in a manufactur-
ing line. The DS3234 is available in commercial and
industrial temperature ranges, and is offered in an
industry-standard 300-mil, 20-pin SO package.
♦ Two Time-of-Day Alarms
♦ Programmable Square-Wave Output
♦ 4MHz SPI Bus Supports Modes 1 and 3
♦ Digital Temp Sensor Output: ±3°C Accuracy
♦ Register for Aging Trim
♦ RST Input/Output
♦ 300-Mil, 20-Pin SO Package
The DS3234 also integrates 256 bytes of battery-backed
SRAM. In the event of main power loss, the contents of
the memory are maintained by the power source con-
♦ Underwriters Laboratory (UL) Recognized
nected to the V
pin. The RTC maintains seconds,
BAT
Ordering Information
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically adjust-
ed for months with fewer than 31 days, including correc-
tions for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator. Two
programmable time-of-day alarms and a programmable
square-wave output are provided. Address and data are
transferred serially by an SPI bidirectional bus.
PIN-
TOP
PART
TEMP RANGE
PACKAGE
MARK
DS3234S#
0°C to +70°C
20 SO
20 SO
DS3234S
DS3234SN#
-40°C to +85°C
DS3234SN
# Denotes a RoHS-compliant device that may include lead that
is exempt under the RoHS requirements. Lead finish is JESD97
Category e3, and is compatible with both lead-based and
lead-free soldering processes. A "#" anywhere on the top mark
denotes a RoHS-compliant device.
Applications
Utility Power Meters
GPS
Servers
Telematics
Pin Configuration
Typical Operating Circuit
TOP VIEW
V
V
PU
CC
CS
N.C.
1
2
3
4
5
6
7
8
9
20 SCLK
19 DOUT
18 SCLK
17 DIN
V
CC
V
CC
CS
SS
32kHz
SCLK
MOSI
MISO
RST
SCLK
DIN
DOUT
INT/SQW
32kHz
V
CC
INT/SQW
RST
16
15 GND
14
V
BAT
DS3234
V
RST
BAT
CPU
N.C.
N.C.
N.C.
N.C.
N.C.
DS3234
N.C.
N.C.
N.C.
N.C.
PUSH-
BUTTON
RESET
N.C.
13 N.C.
12 N.C.
11 N.C.
N.C.
N.C.
GND
N.C.
N.C. 10
SO
SPI is a trademark of Motorola, Inc.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground......-0.3V to +6.0V
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Junction Temperature......................................................+125°C
Storage Temperature Range...............................-40°C to +85°C
Soldering Temperature
(leads, 10s) ...........................................................+260°C/10s
Soldering Temperature (reflow, 2 times max) .......See IPC/JEDEC
J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.0
TYP
3.3
MAX
5.5
UNITS
V
CC
V
V
2.0
3.0
3.8
BAT
0.7 x
V
+
CC
0.3
Logic 1 Input CS, SCLK, DIN
V
V
IH
V
CC
+0.2 x
2.0V ≤ V
≤ 3.63V
-0.3
-0.3
CC
Logic 0 Input CS, SCLK, DIN,
RST
V
V
CC
V
V
IL
3.63V < V
≤ 5.5V
+0.7
5.5
CC
Pullup Voltage INT/SQW
V
V
= 0V
CC
PU
ELECTRICAL CHARACTERISTICS
(V
3.3V, V
= 2.0V to 5.5V, V
= active supply (see Table 1), T = -40°C to +85°C, unless otherwise noted.) (Typical values are at V
=
CC
CC
CC
A
A
= 3.0V, and T = +25°C, unless otherwise noted. TCXO operation guaranteed from 2.3V to 5.5V on V
and 2.3V to 3.8V on
BAT
CC
V .) (Notes 1, 2)
BAT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
400
UNITS
V
V
= 3.63V
= 5.5V
CC
CC
SCLK = 4MHz, BSY = 0
Active Supply Current
I
µA
CCA
(Notes 3, 4)
700
CS = V , 32kHz output off,
SQW output off
(Note 4)
V
V
= 3.63V
= 5.5V
120
160
IH
CC
CC
Standby Supply Current
I
µA
µA
CCS
V
V
= 3.63V
= 5.5V
500
600
2.70
100
CC
CC
SPI bus inactive, 32kHz
output off, SQW output off
Temperature Conversion Current
Power-Fail Voltage
I
CCSCONV
V
2.45
2.575
25
V
PF
V
Leakage Current
I
nA
BAT
BATLKG
(V
= 2.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Notes 1 and 2)
A
CC
Logic 1 Output, 32kHz
V
> 3.63V,
CC
I
I
I
= -500µA
= -250µA
= -125µA
3.63V > V
> 2.7V,
OH
OH
OH
CC
V
0.85 x V
V
OH
CC
2.7V > (V
or V
) > 2.0V
BAT
CC
(BB32kHz = 1)
2
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
ELECTRICAL CHARACTERISTICS (continued)
(V
3.3V, V
= 2.0V to 5.5V, V
=
CC
CC
CC
A
A
= 3.0V, and T = +25°C, unless otherwise noted. TCXO operation guaranteed from 2.3V to 5.5V on V
BAT
V .) (Notes 1, 2)
BAT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 0 Output, 32kHz
Logic 1 Output, DOUT
V
I
I
I
I
= 1mA
0.4
V
V
V
V
OL
OL
OH
OL
OL
V
= -1.0mA
= 3mA
0.85 x V
OH
CC
Logic 0 Output, DOUT, INT/SQW
Logic 0 Output, RST
V
V
0.4
0.4
OL
OL
= 1.0mA
Output Leakage Current 32kHz,
INT/SQW, DOUT
I
Output high impedance
-1
0
+1
µA
LO
Input Leakage DIN, CS, SCLK
RST Pin I/O Leakage
I
-1
+1
µA
µA
LI
I
RST high impedance (Note 5)
-200
+10
OL
TCXO (V
= 2.3V to 5.5V, V = 2.3V to 3.8V, T = -40°C to +85°C, unless otherwise noted.) (Notes 1 and 2)
BAT A
CC
Output Frequency
f
V
= 3.3V or V
= 3.3V or
= 3.3V
BAT
32.768
kHz
ppm
OUT
CC
0°C to +40°C
-2
+2
Frequency Stability vs.
Temperature
V
V
CC
∆f/f
OUT
-40°C to 0°C and
+40°C to +85°C
= 3.3V
BAT
-3.5
+3.5
Frequency Stability vs. Voltage
∆f/V
1
ppm/V
-40°C
+25°C
+70°C
+85°C
0.7
0.1
0.4
0.8
Trim Register Frequency
Sensitivity per LSB
∆f/LSB
Specified at:
After reflow,
ppm
Temperature Accuracy
Crystal Aging
Temp
-3
+3
°C
First year
1.0
5.0
∆f/f
ppm
OUT
not production tested
0–10 years
ELECTRICAL CHARACTERISTICS
(V
= 0V, V = 2.0V to 3.8V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
BAT A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
= 3.4V
= 3.8V
1.5
2.3
BAT
BAT
Battery Current
(Note 4)
I
EOSC = 0, BBSQW = 0
µA
BAT
1.5
2.5
Temperature Conversion Current
Data-Retention Current
I
EOSC = 0, BBSQW = 0
EOSC = 1
400
100
µA
nA
TC
I
BATTC
_____________________________________________________________________
3
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
AC ELECTRICAL CHARACTERISTICS
(V
= 2.0V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
CC
PARAMETER
SYMBOL
CONDITIONS
≤ 5.5V
MIN
TYP
MAX
UNITS
2.7V ≤ V
4
2
CC
SCLK Clock Frequency
f
MHz
SCL
2.0V ≤ V < 2.7V
CC
Data to SCLK Setup
SCLK to Data Hold
SCLK to CS Setup
t
30
30
30
ns
ns
ns
DC
t
CDH
t
CCS
2.7V ≤ V
≤ 5.5V
80
CC
SCLK to Data Valid (Note 6)
SCLK Low Time
t
ns
ns
ns
CDD
2.0V ≤ V < 2.7V
160
CC
2.7V ≤ V
≤ 5.5V
110
220
110
220
CC
t
CL
2.0V ≤ V < 2.7V
CC
2.7V ≤ V
≤ 5.5V
CC
SCLK High Time
t
CH
2.0V ≤ V < 2.7V
CC
SCLK Rise and Fall
t , t
200
ns
ns
R
F
CS to SCLK Setup
t
400
100
200
CC
2.7V ≤ V
≤ 5.5V
CC
SCLK to CS Hold
t
ns
CCH
2.0V ≤ V < 2.7V
CC
CS Inactive Time
t
400
40
ns
ns
CWH
CS to Output High Impedance
Pushbutton Debounce
t
(Note 7)
(Note 8)
CDZ
PBDB
250
250
100
125
ms
ms
ms
ms
Reset Active Time
t
RST
Oscillator Stop Flag (OSF) Delay
Temperature Conversion Time
t
OSF
t
200
CONV
POWER-SWITCH CHARACTERISTICS
(T = -40°C to +85°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Fall Time; V
to
to
CC
PF(MAX)
t
300
µs
VCCF
PF(MIN)
V
V
Rise Time; V
PF(MIN)
PF(MAX)
CC
t
0
µs
VCCR
Recovery at Power-Up
t
(Note 9)
125
300
ms
REC
CAPACITANCE
(T = +25°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
10
UNITS
pF
Capacitance on All Input Pins
Capacitance on All Output Pins
C
C
(Note 10)
IN
IO
Outputs high impedance (Note 10)
10
pF
4
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Pushbutton Reset Timing
RST
PB
DB
t
RST
Power-Switch Timing
V
CC
V
PF(MAX)
V
PF
V
PF
V
PF(MIN)
t
t
VCCR
VCCF
t
REC
RST
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: Measured at V = 0.8 x V
or V = 0.2 x V , 10ns rise/fall time, DOUT = no load.
IH
CC
IL CC
Note 4: Current is the averaged input current, which includes the temperature conversion current. CRATE1 = CRATE0 = 0.
Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to V
.
CC
Note 6: Measured at V
= 0.8 x V
or V = 0.2 x V . Measured from the 50% point of SCLK to the V
minimum of DOUT.
OH
CC
OL
CC
OH
Note 7: With 50pF load.
Note 8: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
OSF
0V ≤ V
≤ V
and 2.3V ≤ V
≤ V
.
CC
CC(MAX)
BAT
BAT(MAX)
Note 9: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, t
goes high.
is bypassed and RST immediately
REC
Note 10: Guaranteed by design and not production tested.
_____________________________________________________________________
5
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Timing Diagram—SPI Read Transfer
t
CS
CCS
t
t
t
F
CC
R
SCLK
t
CDZ
t
CL
t
CH
t
CDH
t
CDD
t
DC
DIN
A6
W/R
A0
DOUT
HIGH IMPEDANCE
D7
D0
WRITE ADDRESS BYTE
READ DATA BYTE
NOTE: SCLK CAN BE EITHER POLARITY, SHOWN FOR CPOL = 1.
Timing Diagram—SPI Write Transfer
t
CWH
CS
t
t
CCH
CC
t
R
t
F
SCLK
t
CL
t
CH
t
CDH
t
DC
DIN
A6
W/R
D7
D0
A0
WRITE ADDRESS BYTE
WRITE DATA BYTE
HIGH IMPEDANCE
DOUT
6
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
BATTERY CURRENT
vs. SUPPLY VOLTAGE
150
125
100
75
2600
2350
2100
1850
INPUTS = GND
RST ACTIVE
V
= 0V
CC
BBSQW = 1
BB32kHz = 0
1600
1350
50
1100
850
25
BBSQW = 0
600
0
2.3
3.3
2.8
SUPPLY VOLTAGE (V )
BAT
2.3
3.3
3.8
2.8
4.3
4.8
5.3
3.8
V
(V)
CC
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING VALUE
BATTERY CURRENT
vs. TEMPERATURE
850
800
750
700
650
65
55
45
35
25
15
AGING = -128
V
= 0V
CC
V
= 3.4V
BAT
BB32kHz = 0
BBSQW = 0
AGING = -33
AGING = 0
V
= 3.0V
BAT
5
-5
-15
-25
AGING = 127
AGING = 32
-35
-45
600
40
TEMPERATURE (°C)
-40
0
20
60
-20
80
20
TEMPERATURE (°C)
-40
0
-20
40
60
80
I
vs. DOUT LOAD
CCA
500
450
400
SCLK = 4MHz
350
300
250
200
20
CAPACITANCE (pF)
40
0
30
10
_____________________________________________________________________
7
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Pin Description
PIN
1
NAME
CS
FUNCTION
Active-Low Chip Select Input. Used to select or deselect the device.
No Connection. Not connected internally. Must be connected to ground.
2, 7–14
N.C.
32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin will be
low.
3
4
32kHz
V
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1µF to 1.0µF capacitor.
CC
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can be
left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register
(0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2
and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the
alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1
when power is first applied, the pin defaults to an interrupt output with alarms disabled.
5
6
INT/SQW
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V
relative to the
CC
V
specification. As V
falls below V , the RS T pin is driven low. When V
exceeds V , for t
, the RS T
RST
PF
CC
PF
CC
PF
pin is driven high impedance. The active-low, open-drain output is combined with a debounced pushbutton input
function. This pin can be activated by a pushbutton reset request. It has an internal 50kΩ nominal value pullup
RST
resistor to V . No external pullup resistors should be connected. If the crystal oscillator is disabled, t
CC
is
RST
bypassed and RST immediately goes high.
15
16
GND
Ground
Backup Power-Supply Input. If V
pin and the battery can cause improper operation. UL recognized to ensure against reverse charging when
used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul.
is not used, connect to ground. Diodes placed in series between the V
BAT
BAT
V
BAT
17
DIN
SPI Data Input. Used to shift address and data into the device.
SPI Clock Input. Used to control timing of data into and out of the device. Either clock polarity can be used. The
clock polarity is determined by the device based on the state of SCLK when CS goes low. Pins 18 and 20 are
electrically connected together internally.
18, 20
19
SCLK
DOUT
SPI Data Output. Data is output on this pin when the device is in read mode; CMOS push-pull driver.
8
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Block Diagram
V
CC
X1
X2
RST
OSCILLATOR AND
CAPACITOR ARRAY
PUSHBUTTON RESET;
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
N
CONTROL LOGIC/
DIVIDER
32kHz
DS3234
V
CC
CONTROL AND STATUS
REGISTERS
V
BAT
TEMPERATURE
SENSOR
POWER CONTROL
INT/SQW
GND
N
SRAM
CS
SCLK
SCLK
DIN
SPI INTERFACE AND
ADDRESS REGISTER
DECODE
CLOCK AND CALENDAR
REGISTERS
USER BUFFER
(7 BYTES)
DOUT
consumption by temperature sensor sampling. The user
should select a sample rate based upon the expected
temperature rate of change, with faster sample rates for
applications where the ambient temperature changes
significantly over a short time. The TCXO provides a sta-
ble and accurate reference clock, and maintains the
RTC to within 2 minutes per year accuracy from -40°C
to +85°C. The TCXO frequency output is available at the
32kHz pin. The RTC is a low-power clock/calendar with
Detailed Description
The DS3234 is a TCXO and RTC with integrated crystal
and 256 bytes of SRAM. An integrated sensor periodi-
cally samples the temperature and adjusts the oscillator
load to compensate for crystal drift caused by tempera-
ture variations. The DS3234 provides user-selectable
sample rates. This allows the user to select a tempera-
ture sensor sample rate that allows for various tempera-
ture rates of change, while minimizing current
_____________________________________________________________________
9
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
two programmable time-of-day alarms and a program-
mable square-wave output. The INT/SQW provides either
an interrupt signal due to alarm conditions or a square-
wave output. The clock/calendar provides seconds, min-
utes, hours, day, date, month, and year information. The
date at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections for
leap year. The clock operates in either the 24-hour or 12-
hour format with AM/PM indicator. Access to the internal
registers is possible through an SPI bus interface.
both V
and V
, the internal clock registers are
BAT
PF
blocked from any access. If V is less than V
, the
PF
BAT
device power is switched from V
to V
when V
BAT CC
CC
drops below V . If V
is greater than V , the
BAT
PF
PF
device power is switched from V
to V
when V
BAT CC
CC
drops below V
. After V
returns above both V
CC PF
BAT
and V
, read and write access is allowed after RST
BAT
goes high (Table 1).
Table 1. Power Control
A temperature-compensated voltage reference and
READ/WRITE ACTIVE
comparator circuit monitors the level of V
to detect
SUPPLY CONDITION
RST
CC
ACCESS
SUPPLY
power failures and to automatically switch to the backup
supply when necessary. When operating from the back-
up supply, access is inhibited to minimize supply cur-
rent. Oscillator, time and date, and TCXO operations can
continue while the backup supply powers the device.
The RST pin provides an external pushbutton function
and acts as an indicator of a power-fail event.
V
V
V
V
< V , V
< V
> V
< V
> V
No
V
Active
Active
CC
CC
CC
CC
PF CC
BAT
BAT
BAT
BAT
BAT
< V , V
Yes
V
PF CC
CC
> V , V
Yes
V
Inactive
Inactive
PF CC
CC
> V , V
Yes
V
PF CC
CC
To preserve the battery, the first time V
the device, the oscillator does not start up until V
crosses V . After the first time V
PF
oscillator starts up and the V
oscillator during power-down and keeps the oscillator
running. When the DS3234 switches to V
lator may be disabled by setting the EOSC bit.
is applied to
BAT
Operation
CC
is ramped up, the
The block diagram shows the main elements of the
DS3234. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described sep-
arately in the following sections.
CC
source powers the
BAT
, the oscil-
BAT
Pushbutton Reset Function
32kHz TCXO
The temperature sensor, oscillator, and control logic form
the TCXO. The controller reads the output of the on-chip
temperature sensor and uses a lookup table to determine
the capacitance required, adds the aging correction in
the AGE register, and then sets the capacitance selection
registers. New values, including changes to the AGE reg-
ister, are loaded only when a change in the temperature
value occurs. The temperature is read on initial applica-
The DS3234 provides for a pushbutton switch to be con-
nected to the RST output pin. When the DS3234 is not in
a reset cycle, it continuously monitors the RST signal for a
low going edge. If an edge transition is detected, the
DS3234 debounces the switch by pulling the RST low.
After the internal timer has expired (PB ), the DS3234
DB
continues to monitor the RST line. If the line is still low, the
DS3234 continuously monitors the line looking for a rising
edge. Upon detecting release, the DS3234 forces the
tion of V
and once every 64 seconds (default, see the
CC
RST pin low and holds it low for t
.
description for CRATE1 and CRATE0 in the Control/Status
Register section) afterwards.
RST
The same pin, RST, is used to indicate a power-fail con-
dition. When V is lower than V , an internal power-fail
CC
PF
Power Control
The power control function is provided by a tempera-
ture-compensated voltage reference and a comparator
signal is generated, which forces the RST pin low. When
returns to a level above V , the RST pin is held low
V
CC
for t
PF
to allow the power supply to stabilize. If the
REC
circuit that monitors the V
level. The device is fully
CC
EOSC bit is set to logic 1 (to disable the oscillator in bat-
accessible and data can be written and read when V
CC
tery-backup mode), the reset signal is kept active for
is greater than V . However, when V
falls below
PF
CC
t
plus the startup time of the oscillator (typ 1 second).
REC
10
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
SCLK and DIN/DOUT pins. Multiple byte transfers are
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automati-
cally adjusted for months with fewer than 31 days, includ-
ing corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
supported within one CS low period. The SPI on the
DS3234 interface is accessible whenever V
is above
CC
either V
or V
.
PF
BAT
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3234 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12-
hour mode, bit 5 is the AM/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the second 10-hour bit
(20–23 hours). The century bit (bit 7 of the month regis-
ter) is toggled when the years register overflows from
99 to 00.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
SRAM
The DS3234 provides 256 bytes of general-purpose bat-
tery-backed read/write memory. The SRAM can be writ-
ten or read whenever V
is above either V or V
.
PF
BAT
CC
Address Map
Figure 1 shows the address map for the DS3234 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(13h read, 93h write), it wraps around to the beginning
(00h read, 80h write). The DS3234 does not respond to a
read or write to any reserved address, and the internal
address pointer does not increment. Address pointer
operation when accessing the 256-byte SRAM data is
covered in the description of the SRAM address and data
registers. On the falling edge of CS, or during a multibyte
access when the address pointer increments to location
00h, the current time is transferred to a second set of reg-
isters. The time information is read from these secondary
registers, while the internal clock registers continue to
increment normally. If the time and date registers are
read using a multibyte read, this eliminates the need to
reread the registers in case the main registers update
during a read.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date
registers, the user buffers are synchronized to the internal
registers on the falling edge of CS or and when the regis-
ter pointer rolls over to zero. The time information is read
from these secondary registers, while the clock continues
to run. This eliminates the need to reread the registers in
case the main registers update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowl-
edge from the DS3234. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer.
SPI Interface
The DS3234 operates as a slave device on the SPI seri-
al bus. Access is obtained by selecting the part by the
CS pin and clocking data into/out of the part using the
____________________________________________________________________ 11
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Figure 1. Address Map for DS3234 Timekeeping Registers and SRAM
ADDRESS
READ/WRITE
MSB
BIT 7
LSB
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FUNCTION
RANGE
00h
01h
80h
81h
0
0
10 Seconds
10 Minutes
AM/PM
10 hr
Seconds
Seconds
Minutes
00–59
00–59
Minutes
Hour
1-12 +AM /PM
02h
82h
0
12/24
10 hr
0
Hours
00-23
03h
04h
83h
84h
0
0
0
0
0
0
Day
Day
1-7
10 Date
Date
Month
Year
Date
01-31
Month/
Century
05h
06h
07h
85h
86h
87h
Century
0
0
10 Mo
01-12 + Century
00-99
10 Year
Year
Alarm 1
Seconds
A1M1
A1M2
10 Seconds
10 Minutes
Seconds
Minutes
00-59
Alarm 1
Minutes
08h
09h
88h
89h
00-59
AM/PM
Alarm 1
Hours
1-12 +AM /PM
A1M3
12/24
10 hr
Hour
00-23
10 hr
0
Day
Date
Alarm 1 Day
Alarm 1 Date
1-7
01-31
0Ah
0Bh
0Ch
8Ah
8Bh
8Ch
A1M4
A2M2
A2M3
DY/DT
10 Date
Alarm 2
Minutes
10 Minutes
Minutes
Hour
00-59
AM/PM
Alarm 2
Hours
1-12 +AM /PM
12/24
10 hr
00-23
10 hr
0
Day
Date
Alarm 2 Day
Alarm 2 Date
1-7
01-31
0Dh
0Eh
0Fh
8Dh
8Eh
8Fh
A2M4
EOSC
OSF
DY/DT
10 Date
BBSQW
CONV RS2
RS1
INTCN
A2IE
A2F
A1IE
A1F
Control
—
Control/
Status
BB32kHz CRATE1 CRATE0 EN32kHz
BSY
—
Crystal Aging
Offset
10h
90h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
—
11h
12h
91h
92h
SIGN
DATA
DATA
DATA
DATA
0
DATA
0
DATA
0
DATA
0
DATA
0
DATA
0
Temp MSB
Temp LSB
Read Only
Read Only
Disable
Temp
13h
93h
0
0
0
0
0
0
0
BB_TD
—
Conversions
14h–17h 94h–97h
—
A7
D7
—
A6
D6
—
A5
D5
—
A4
D4
—
A3
D3
—
A2
D2
—
A1
D1
—
A0
D0
Reserved
—
—
—
SRAM
Address
18h
98h
19h
99h
SRAM Data
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied. Bits defined as 0 cannot be written
to 1 and will always read 0.
12
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
The DY/DT bits (bit 6 of the alarm day/date registers)
Alarms
control whether the alarm value stored in bits 0 to 5 of
The DS3234 contains two time-of-day/date alarms. Alarm
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
1 can be set by writing to registers 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the alarm enable and INTCN
bits of the control register) to activate the INT/SQW output
on an alarm match condition. Bit 7 of each of the time-of-
day/date alarm registers are mask bits (Table 2). When all
the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers
match the corresponding values stored in the time-of-
day/date alarm registers. The alarms can also be pro-
grammed to repeat every second, minute, hour, day, or
date. Table 2 shows the possible settings. Configurations
not listed in the table will result in illogical operations.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition activates
the INT/SQW signal. The match is tested on the once-
per-second update of the time and date registers.
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
X
X
X
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A2M4
A2M3
A2M2
X
X
X
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
Alarm when hours and minutes match
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
____________________________________________________________________ 13
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Control Register (0Eh/8Eh)
BIT 7
EOSC
0
BIT 6
BBSQW
0
BIT 5
CONV
0
BIT 4
RS2
1
BIT 3
RS1
1
BIT 2
INTCN
1
BIT 1
A2IE
0
BIT 0
A1IE
0
NAME:
POR*:
*POR is defined as the first application of power to the device, either V
or V
.
CC
BAT
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
Special-Purpose Registers
The DS3234 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.
Control Register (0Eh/8Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3234 switches to battery
power. This bit is clear (logic 0) when power is first
applied. When the DS3234 is powered by V , the
CC
oscillator is always on regardless of the status of the
SQUARE-WAVE OUTPUT FREQUENCY
SQUARE-WAVE OUTPUT
RS2
RS1
FREQUENCY
0
0
1
1
0
1
0
1
1Hz
1.024kHz
4.096kHz
8.192kHz
EOSC bit.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1, this bit enables the
square-wave or interrupt output when V
is absent and
BAT
CC
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, a match between the time-
keeping registers and either of the alarm registers acti-
vates the INT/SQW (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of
the state of the INTCN bit. The INTCN bit is set to logic
1 when power is first applied.
the DS3234 is being powered by the V
pin. When
BBSQW is logic 0, the INT/SQW pin goes high imped-
ance when V
falls below the power-fail trip point. This
CC
bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO exe-
cution. A user-initiated temperature conversion does
not affect the internal 64-second (default interval)
update cycle. This bit is disabled (logic 0) when power
is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
14
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Control/Status Register (0Fh/8Fh)
BIT 7
OSF
1
BIT 6
BB32kHz
0
BIT 5
CRATE1
0
BIT 4
CRATE0
0
BIT 3
EN32kHz
1
BIT 2
BSY
0
BIT 1
A2F
0
BIT 0
A1F
0
NAME:
POR*:
*POR is defined as the first application of power to the device, either V
or V
.
CC
BAT
Bit 3: Enable 32kHz Output (EN32kHz). This bit indi-
cates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin is
low. The initial power-up state of this bit is logic 1, and a
32.768kHz square-wave signal appears at the 32kHz pin
after a power source is applied to the DS3234. This bit is
enabled (logic 1) when power is first applied.
Control/Status Register (0Fh/8Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.
1) The first time power is applied.
2) The voltages present on both V
insufficient to support oscillation.
and V
are
BAT
CC
3) The EOSC bit is turned off in battery-backed mode.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit and INTCN bit are set to logic 1, the
INT/SQW pin is driven low while A2F is active. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 6: Battery-Backed 32kHz Output (BB32kHz). This
bit enables the 32kHz output when powered from V
(provided EN32kHz is enabled). If BB32kHz = 0, the
32kHz output is low when the part is powered by V
This bit is disabled (logic 0) when power is first applied.
BAT
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit and the INTCN bit are set to logic 1,
the INT/SQW pin is driven low while A1F is active. A1F
is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
.
BAT
Bits 5 and 4: Conversion Rate (CRATE1 and
CRATE0). These two bits control the sample rate of the
TCXO. The sample rate determines how often the tem-
perature sensor makes a conversion and applies com-
pensation to the oscillator. Decreasing the sample rate
decreases the overall power consumption by decreas-
ing the frequency at which the temperature sensor
operates. However, significant temperature changes
that occur between samples may not be completely
compensated for, which reduce overall accuracy.
These bits are set to logic 0 when power is first applied.
SAMPLE RATE
CRATE1
CRATE0
(seconds)
0
0
1
1
0
1
0
1
64
128
256
512
____________________________________________________________________ 15
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Aging Offset (10h/90h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT 5
DATA
0
BIT 4
DATA
0
BIT 3
DATA
0
BIT 2
DATA
0
BIT 1
DATA
0
BIT 0
DATA
0
NAME:
POR*:
Temperature Register (MSB) (11h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT 5
DATA
0
BIT 4
DATA
0
BIT 3
DATA
0
BIT 2
DATA
0
BIT 1
DATA
0
BIT 0
DATA
0
NAME:
POR*:
Temperature Register (LSB) (12h)
BIT 7
DATA
0
BIT 6
DATA
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
POR*:
0
0
0
0
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either V
or V
.
CC
BAT
The change in ppm per LSB is different at different tem-
peratures. The frequency vs. temperature curve is shift-
ed by the values used in this register. At +25°C, one
LSB typically provides about 0.1ppm change in fre-
quency. These bits are all set to logic 0 when power is
first applied.
Aging Offset Register (10h/90h)
The aging offset register provides an 8-bit code to add
to or subtract from the oscillator capacitor array. The
data is encoded in two’s complement, with bit 7 repre-
senting the SIGN bit. One LSB represents the smallest
capacitor to be switched in or out of the capacitance
array at the crystal pins. The offset register is added to
the capacitance array during a normal temperature
conversion, if the temperature changes from the previ-
ous conversion, or during a manual user conversion
(setting the CONV bit). To see the effects of the aging
register on the 32kHz output frequency immediately, a
manual conversion should be performed after each
aging offset register change.
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format, with bit 7 in the MSB representing the SIGN bit.
The upper 8 bits are at location 11h and the lower 2 bits
are in the upper nibble at location 12h. Upon power
reset, the registers are set to a default temperature of
0°C and the controller starts a temperature conversion.
New temperature readings are stored in this register.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
16
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Temperature Control (13h/93h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BB_TD
0
0
0
NAME:
POR*:
0
0
0
0
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either V
or V
.
CC
BAT
SRAM Address (18h/98h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
A7
A6
A5
A4
A2
A1
A1
A0
SRAM Data (19h/99h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
D7
D6
D5
D4
D2
D1
D1
D0
Note: These registers do not default to any specific value.
Temperature Control
Register (13h/93h)
SPI Serial Data Bus
The DS3234 provides a 4-wire SPI serial data bus to com-
municate in systems with an SPI host controller. The
DS3234 supports both single byte and multiple byte data
transfers for maximum flexibility. The DIN and DOUT pins
are the serial data input and output pins, respectively.
The CS input is used to initiate and terminate a data
transfer. The SCLK pin is used to synchronize data move-
ment between the master (microcontroller) and the slave
devices (see Table 3). The shift clock (SCLK), which is
generated by the microcontroller, is active only during
address and data transfer to any device on the SPI bus.
Input data (DIN) is latched on the internal strobe edge
and output data (DOUT) is shifted out on the shift edge
(Figure 2). There is one clock for each bit transferred.
Address and data bits are transferred in groups of eight.
Bit 0: Battery-Backed Temperature Conversion
Disable (BB_TD). The battery-backed tempconv dis-
able bit prevents automatic temperature conversions
when the device is powered by the V
supply. This
BAT
reduces the battery current at the expense of frequen-
cy accuracy.
SRAM Address Register
(18h/98h)
The SRAM address register provides the 8-bit address
of the 256-byte memory array. The desired memory
address should be written to this register before the
data register is accessed. The contents of this register
are incremented automatically if the data register is
accessed more than once during a single transfer.
When the contents of the address register reach 0FFh,
the next access causes the register to roll over to 00h.
CS
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
SRAM Data Register (19h/99h)
The SRAM data register provides the data to be written
to or the data read from the 256-byte memory array.
During a read cycle, the data in this register is that
found in the memory location in the SRAM address reg-
ister (18h/98h). During a write cycle, the data in this reg-
ister is placed in the memory location in the SRAM
address register (18h/98h). When the SRAM data regis-
ter is read or written, the internal register pointer
remains at 19h/99h and the SRAM address register
increments after each byte that is read or written, allow-
ing multibyte transfers.
SCLK WHEN CPOL = 0
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
SCLK WHEN CPOL = 1
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2: CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER.
NOTE 3: DOUT REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE
SHIFTED OUT DURING A READ.
Figure 2. Serial Clock as a Function of Microcontroller Clock-
Polarity Bit
____________________________________________________________________ 17
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Address and data bytes are shifted MSB first into the
serial data input (DIN) and out of the serial data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write opera-
tion (Figures 3 and 4).
The address byte is always the first byte entered after
CS is driven low. The most significant bit of this byte
determines if a read or write takes place. If the MSB is
0, one or more read cycles occur. If the MSB is 1, one
or more write cycles occur.
Table 3. SPI Pin Function
MODE
SCLK
DIN
DOUT
CS
Input Disabled
Input Disabled
High Impedance
Disable
Write
H
*CPOL = 1, SCLK Rising
CPOL = 0, SCLK Falling
CPOL = 1, SCLK Falling
CPOL = 0, SCLK Rising
Don’t Care
Data Bit Latch
High Impedance
L
X
Next Data Bit Shift**
High Impedance
Read
L
L
Don’t Care
Read Invalid Location
*CPOL is the clock-polarity bit set in the control register of the host microprocessor.
**DOUT remains at high impedance until 8 bits of data are ready to be shifted out during a read.
CS
SCLK
DIN
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
HIGH IMPEDANCE
Figure 3. SPI Single-Byte Write
CS
SCLK
DIN
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
DOUT
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. SPI Single-Byte Read
18
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
CS
SCLK
DIN
WRITE
ADDRESS
BYTE
DATA BYTE 0
DATA BYTE 1
DATA BYTE N
DIN
ADDRESS
BYTE
READ
DOUT
HIGH IMPEDANCE
DATA
DATA
DATA
BYTE 0
BYTE 1
BYTE N
Figure 5. SPI Multiple-Byte Burst Transfer
Data transfers can occur one byte at a time or in multi-
ple-byte burst mode. After CS is driven low, an address
is written to the DS3234. After the address, one or more
data bytes can be written or read. For a single-byte
transfer, one byte is read or written and then CS is dri-
ven high. For a multiple-byte transfer, however, multiple
bytes can be read or written after the address has been
written (Figure 5). Each read or write cycle causes the
RTC register address to automatically increment, which
continues until the device is disabled. The address
wraps to 00h after incrementing to 13h (during a read)
and wraps to 80h after incrementing to 93h (during a
write). An updated copy of the time is loaded into the
user buffers upon the falling edge of CS and each time
the address pointer increments from 13h to 00h.
Because the internal and user copies of the time are
only synchronized on these two events, an alarm condi-
tion can occur internally and activate the INT/SQW pin
independently of the user data.
If the SRAM is accessed by reading (address 19h) or
writing (address 99h) the SRAM data register, the con-
tents of the SRAM address register are automatically
incremented after the first access, and all data cycles
will use the SRAM data register.
Handling, PC Board Layout,
and Assembly
The DS3234 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shock and vibration are avoided. Ultrasonic cleaning
should be avoided to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connect-
ed to ground.
____________________________________________________________________ 19
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Chip Information
TRANSISTOR COUNT: 48,000
Thermal Information
Theta-J : +55°C/W
A
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Theta-J : +24°C/W
C
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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