DS34T101 [MAXIM]
Single/Dual/Quad/Octal TDM-Over-Packet Chip; 单/双/四/八通道的TDM-over -Packet时芯片
| 型号： | DS34T101 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single/Dual/Quad/Octal TDM-Over-Packet Chip |
| 文件： | 总74页 (文件大小：804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev: 072707
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-Over-Packet Chip
General Description
Features
The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
draft-compliant DS34T108 allows up to eight T1/E1
links or frame-based serial HDLC links to be
transported transparently through a switched IP or
MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261,
and TDM specifications. This eliminates the need for
remote timing sources in cabinets and pedestals.
♦
♦
Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-
Packet
Supports Adaptive Clock Recovery, Common
Clock (Using RTP), External Clock, and
Loopback Timing Modes
♦
♦
♦
Selectable 32-Bit or 16-Bit Processor Bus
Clock Rate Adapter for T1/E1 Master Clock
10/100 Ethernet MAC That Supports
MII/RMII/SSMII
The Ethernet side of the DS34T108 provides high
QoS capabilities to its MII/RMII/SSMII port, while the
WAN side supports full-featured T1/E1 framers and
LIUs. This takes the solution all the way through
analog, while preserving options to make use of TDM
streams at key intermediate points. The high level of
integration that the DS34T108 brings minimizes cost,
board space, and time to market.
♦
♦
♦
Fully Compatible with IEEE 802.3 Standard
VLAN Support According to 802.1 p&Q
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, and Metro
Ethernet
♦
End-to-End TDM Synchronization Through
the IP/MPLS Domain by Eight Independent
On-Chip TDM Clock Recovery Mechanisms
Applications
♦
♦
♦
Single Serial Support for RS-530 and V.35
Single DS3/E3/STS-1 to Ethernet
TDM Circuit Extension Over PSN
o
o
o
o
Leased—Line Services Over PSN
TDM Over G/E—PON
TDM Over Cable
Packet Loss Compensation and Handling of
Misordered Packets
TDM Over WiMAX
♦
♦
♦
♦
64 Independent Bundle/Connections
Glueless SDRAM Buffer Management
1.8V Core, 3.3V I/O
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC—Based Traffic Transport Over PSN
Complies with IETF PWE3 RFCs and Drafts
for CESoPSN, SAToP, TDMoIP, and HDLC
Functional Diagram
Features continued in Section 7.
CPU
Bus
Ordering Information
DS34T108
Octal
T1/E1/J1
Transceiver
Framers
PIN-
PACKAGE
PART
PORTS TEMP RANGE
Circuit
Emulation
Engine
10/100
Ethernet
xMII
DS34T108GN
DS34T108GN+
DS34T104GN*
DS34T104GN+*
DS34T102GN*
DS34T102GN+*
DS34T101GN*
DS34T101GN+*
8
8
4
4
2
2
1
1
484 HSBGA
484 HSBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
MAC
BERT
& CAS
Buffer
Manager
LIUs
CLAD
TDM
Access
SDRAM
Interface
Clock Inputs
+Denotes a lead-free package.
*Future product—Contact factory for availability.
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about
device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim
Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
Table of Contents
1.
INTRODUCTION ..............................................................................................................................6
ACRONYMS AND GLOSSARY.......................................................................................................7
STANDARDS COMPLIANCE ..........................................................................................................9
DETAILED DESCRIPTION ............................................................................................................12
APPLICATION EXAMPLES...........................................................................................................14
2.
3.
4.
5.
5.1.1
Other Possible Applications................................................................................................................. 15
6.
7.
BLOCK DIAGRAM.........................................................................................................................16
FEATURE HIGHLIGHTS................................................................................................................17
7.1 GLOBAL FEATURES .......................................................................................................................17
7.2 LINE INTERFACE............................................................................................................................17
7.3 CLOCK SYNTHESIZER ....................................................................................................................18
7.4 JITTER ATTENUATOR .....................................................................................................................18
7.5 FRAMER/FORMATTER....................................................................................................................18
7.6 FRAMER SYSTEM PORTS...............................................................................................................19
7.7 TDM-OVER-PACKET ENGINE .........................................................................................................19
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
TDM-over-Packet User Interfaces ....................................................................................................... 20
Network Port ........................................................................................................................................ 20
Bundles ................................................................................................................................................ 20
Clock Recovery.................................................................................................................................... 20
Delay Variation Compensation ............................................................................................................ 21
CAS Support ........................................................................................................................................ 21
7.8 TEST AND DIAGNOSTICS ................................................................................................................21
7.9 CONTROL PORT ............................................................................................................................22
8.
9.
OVERVIEW OF MAJOR OPERATIONAL MODES .......................................................................23
8.1 INTERNAL MODE CONFIGURED AS ONE-CLOCK MODE ....................................................................23
8.2 INTERNAL MODE CONFIGURED AS TWO-CLOCK MODE....................................................................25
8.3 EXTERNAL MODE ..........................................................................................................................26
FUNCTIONAL DESCRIPTION AND DEVICE REGISTERS..........................................................27
10. PIN DESCRIPTION ........................................................................................................................28
10.1
10.2
SHORT PIN DESCRIPTIONS .........................................................................................................28
DETAILED PIN DESCRIPTIONS.....................................................................................................35
11. JTAG INFORMATION....................................................................................................................49
11.1
11.2
11.3
JTAG DESCRIPTION...................................................................................................................49
JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ...........................................................50
JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ....................................................................52
11.3.1 SAMPLE/PRELOAD ............................................................................................................................ 52
11.3.2 EXTEST ............................................................................................................................................... 52
11.3.3 BYPASS............................................................................................................................................... 52
11.3.4 IDCODE ............................................................................................................................................... 53
11.3.5 HIGHZ.................................................................................................................................................. 53
11.3.6 CLAMP................................................................................................................................................. 53
11.4
JTAG TEST REGISTERS.............................................................................................................53
11.4.1 Bypass Register................................................................................................................................... 53
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11.4.2 Identification Register........................................................................................................................... 53
11.4.3 Boundary Scan Register...................................................................................................................... 53
12. DC ELECTRICAL CHARACTERISTICS .......................................................................................54
13. AC TIMING CHARACTERISTICS..................................................................................................55
14. PIN ASSIGNMENTS ......................................................................................................................56
14.1
14.2
14.3
14.4
14.5
BOARD DESIGN FOR THE DS34T108 FAMILY OF PRODUCTS .......................................................56
DS34T108 PIN ASSIGNMENT .....................................................................................................67
DS34T104 PIN ASSIGNMENT .....................................................................................................68
DS34T102 PIN ASSIGNMENT .....................................................................................................69
DS34T101 PIN ASSIGNMENT .....................................................................................................70
15. PACKAGE INFORMATION ...........................................................................................................71
15.1
15.2
484-BALL HSBGA (56-G6038-002) ..........................................................................................71
484-BALL TEBGA (56-G6038-001)...........................................................................................72
16. THERMAL INFORMATION............................................................................................................73
17. DOCUMENT REVISION HISTORY................................................................................................74
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List of Figures
Figure 1-1. Block Diagram........................................................................................................................................... 6
Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network................................................................ 14
Figure 5-2. Cellular 2/3G Backhaul Over Packet-Switched Networks....................................................................... 15
Figure 6-1. DS34T108 Functional Block Diagram..................................................................................................... 16
Figure 8-1. Internal Mode .......................................................................................................................................... 24
Figure 8-2. Internal One-Clock Mode ........................................................................................................................ 25
Figure 8-3. Internal Two-Clock Mode (Framed) ........................................................................................................ 26
Figure 8-4. Internal Two-Clock Mode (Unframed)..................................................................................................... 26
Figure 11-1. JTAG Block Diagram............................................................................................................................. 49
Figure 11-2. JTAG TAP Controller State Machine .................................................................................................... 50
Figure 14-1. DS34T108 Pin Assignment (HSBGA Package).................................................................................... 67
Figure 14-2. DS34T104 Pin Assignment (TEBGA Package) .................................................................................... 68
Figure 14-3. DS34T102 Pin Assignment (TEBGA Package) .................................................................................... 69
Figure 14-4. DS34T101 Pin Assignment (TEBGA Package) .................................................................................... 70
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List of Tables
Table 3-1. T1-Related Telecommunications Specifications ........................................................................................ 9
Table 3-2. E1-Related Telecommunications Specifications...................................................................................... 10
Table 3-3. TDM-over-Packet Related Specifications................................................................................................. 11
Table 10-1. DS34T108 Short Pin Descriptions.......................................................................................................... 28
Table 10-2. Detailed Pin Descriptions ....................................................................................................................... 35
Table 11-1. JTAG Instruction Codes ......................................................................................................................... 52
Table 11-2. JTAG ID Code ........................................................................................................................................ 52
Table 12-1. Recommended DC Operating Conditions.............................................................................................. 54
Table 12-2. DC Electrical Characteristics.................................................................................................................. 54
Table 14-1. Common Board Design Connections..................................................................................................... 56
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1.
Introduction
The DS34T108/DS34T104/DS34T102/DS34T101 (DS34T10x) family of products combines LIU, framer, and
Pseudo Wire Emulation Edge-to-Edge (PWE3) circuit emulation technology into one die. Dedicated payload-type
engines are included for TDMoIP (AAL1, AAL2), CESoPSN, SAToP, and HDLC.
Products in the DS34T10x family provide a transport technology for simple conversion of T1/E1/J1/T3/E3/STS-1
serial TDM to IP, MPLS, or pure Ethernet Layer 2 networks. They carry from the line E1/T1/J1 or they provide a
carrier for E3, T3, or STS1 services and serial data across a packet-switched network, transparent to all protocols
and signaling. These products enable service providers to migrate to next-generation networks while continuing to
provide all their revenue-generating legacy voice and data services. They also benefit data carriers by enabling
them to offer lucrative leased-line services and increase revenues from their packet-switched infrastructure by
selling voice as well as data services. Finally, they enable enterprises to run voice and video over the same
IP/Ethernet-based network that is currently used to run only LAN traffic, thereby minimizing network maintenance
and operating costs.
Packet-switched networks, such as IP networks, were not designed to transport TDM data and have no inherent
clock distribution mechanism. Hence, when transporting TDM over packet-switched networks, the receiver needs
to reconstruct the transmitter's TDM clock. The DS34T10x family ensures that jitter and wander levels of the
recovered clock conform to ITU-T G.823/824 and G.8261, even for networks that introduce significant packet delay
variation and packet loss.
The Circuit Emulation technology in the DS34T10x products that makes this possible is called TDM-over-Packet
(TDMoP) and complements VoIP in those cases where VoIP is not applicable or where VoIP price/performance is
not sufficient. Most importantly, TDMoP technology provides higher voice quality with lower latency than VoIP.
Unlike VoIP, TDMoP can support all applications that run over E1/T1/J1 circuits, not just voice. TDMoP can provide
traditional leased-line services over IP and is transparent to protocols and signaling. Because TDMoP provides an
evolutionary, as opposed to revolutionary, approach, investment protection is maximized.
Figure 1-1. Block Diagram
CPU
Bus
32 bit or 16 bit
DS34T108
Control
BERT
T1/E1/J1
T1/E1/J1
Framer
LIU
10/100
Ethernet
MAC
T1/E1/J1
LIU
T1/E1/J1
Framer
MII/RMII
T1/E1/J1
LIU
T1/E1/J1
Framer
Octal
T1
E1
J1
(analog)
T1/E1/J1
LIU
T1/E1/J1
Framer
CLAD
Circuit Emulation
Engine
T1/E1/J1
LIU
T1/E1/J1
Framer
T1/E1/J1
LIU
T1/E1/J1
Framer
SDRAM
Interface
T1/E1/J1
LIU
T1/E1/J1
Framer
T1/E1/J1
LIU
T1/E1/J1
Framer
32 bit
SDRAM
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2.
Acronyms and Glossary
Listed below are the terms used in this data sheet.
2.5G
2.5 Generation
2G
Second Generation
3G
Third Generation
AAL1
ATM Adaptation Layer 1
AAL2
ATM Adaptation Layer 2
ATM
BGA
Asynchronous Transfer Mode
Ball Grid Array
Bridge
Bundle
BW
Bridge
Bundle
Bandwidth
CAS
CCS
CE
Channel Associated Signaling
Common Channel Signaling
Customer Edge
CESoP
CESoPSN
Circuit Switching
CLAD
CLEC
CPE
CSMA
CSMA/CD
DS0
Circuit Emulation Service over Packet
Circuit Emulation Services over Packet Switched Network
Circuit Switching
Clock Rate Adapter
Competitive Local Exchange Carrier
Customer Premises Equipment
Carrier Sense Multiple Access
Carrier Sense Multiple Access with Collision Detection
Digital Signal Level 0
DS1
Digital Signal 1
DS3
Digital Signal 3
HDLC
IEEE 802.3
IEEE 802.X
IETF
ILEC
IP
High-Level Data Link Control
Institute of Electrical and Electronics Engineers 802.3
Institute of Electrical and Electronics Engineers 802.X
Internet Engineering Task Force
Incumbent Local Exchange Carrier
Internet Protocol
IP Address
IWF
Internet Protocol Address
Interworking Function
LAN
Local Area Network
LEC
Local Exchange Carrier
LIU
Line Interface Unit
MAC
Media Access Control
MAN
Message Switching
MII
MPLS
OC-3
Metropolitan Area Network
Message Switching
Medium Independent Interface
Multiprotocol Label Switching
Optical Carrier Level 3
OCXO
OFE
Oven-Controlled Crystal Oscillator
Optical Front-End
OSI
OSI-RM
PAD
PBX
PCI
PCI Express
PCI-X
PDV
Open Systems Interconnection
Open Systems Interconnection—Reference Model
Packet Assembler/Disassembler
Private Branch Exchange
Peripheral Component Interconnect
Peripheral Component Interconnect Express
Peripheral Component Interconnect Extended
Packet Delay Variation
PE
Provider Edge
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PLCC
PQFP
PSN
Plastic Leaded Chip Carrier
Plastic Quad Flat Pack
Packet Switched Network
PSTN
PWE3
QoS
Public Switched Telephone Network
Pseudo-Wire Edge-to-Edge Emulation
Quality of Service
RMII
RPR
Reduced Medium Independent Interface
Resilient Packet Ring
SAToP
SDH
SMII
SONET
SS7
Structure-Agnostic TDM over Packet
Synchronous Digital Hierarchy
Serial Media Independent Interface
Synchronous Optical Network
Signal System 7
SSMII
STM-1
TDM
Source Synchronous Serial Media Independent Interface
Synchronous Transfer Module -1
Time Division Multiplexing
TDMoIP
TDMoP
TLS
Time Division Multiplexing over Internet Protocol
Time Division Multiplexing over Packet
Transport Layer Security
UDP
User Datagram Protocol
VoIP
Voice over IP
VPLS
WAN
Virtual Private LAN Services
Wide Area Network
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
3.
Standards Compliance
The DS34T108 meets all the latest relevant telecommunications specifications. Table 3-1 and Table 3-2 provide
the T1 and E1 specifications and sections that are applicable to the DS34T108. The TDM-over-Packet
specifications and sections relevant for the DS34T108 are described in Table 3-3.
Table 3-1. T1-Related Telecommunications Specifications
ANSI T1.102- Digital Hierarchy Electrical Interface.
AMI Coding.
B8ZS Substitution Definition.
DS1 Electrical Interface. Line rate ±32ppm; pulse amplitude between 2.4V to 3.6V peak; power level between 12.6dBm to
17.9dBm; the T1 pulse mask is provided that we comply. DSX-1 for cross-connects the return loss is greater than -26dB. The
DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cables of 1000 feet.
ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition.
ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100Ω. Pulse shape and template compliance according to T1.102;
Power level 12.4dBm to 19.7dBm when all ones is transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB and -15dB. Line rate is ±32ppm. Pulse Amplitude is 2.4V to
3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS34T108 will function with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different, specifically at times 0.61, -0.27, -34, and 0.77. The
DS34T108 is complaint to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.
(ANSI) “Digital Hierarchy – Electrical Interfaces”
(ANSI) “Digital Hierarchy – Formats Specification”
(ANSI) “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces – DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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Table 3-2. E1-Related Telecommunications Specifications
ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate—2048 ±50ppm; The transmission media are 75Ω coax or 120Ω twisted pair; peak to peak space
voltage is ±0.237V; Nominal pulse width is 244ns.
Return loss 51 to 102Hz is 6dB, 102 to 3072Hz is 8dB, 2048 to 3072Hz is 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse template for E1 is defined in G.703.
ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048Kbit/s
The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITUT G.775
A LOS detection criterion is defined.
ITUT G.823 The control of jitter and wander within digital networks which are based on 2.048Kbit/s hierarchy
G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and 100kHz.
ETSI 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.
(ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels”
(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in
Recommendation G.704”
(ITU) “Characteristics of primary PCM Multiplex Equipment Operating at 2048Kbit/s”
(ITU) Characteristics of a synchronous digital multiplex equipment operating at 2048Kbit/s”
(ITU) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
(ITU) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048Kbit/s Hierarchy”
(ITU) “Primary Rate User-Network Interface – Layer 1 Specification”
(ITU) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”
(ITU) “In-service code violation monitors for digital systems”
(ETSI) “Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1/ Layer 1 specification”
(ETSI) “Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using
the 2048Kbit/s-based plesiochronous or synchronous digital hierarchies”
(ETSI) “Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate”
(ETSI) “Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN
using ISDN primary rate access”
(ETSI) “Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048Kbit/s digital
unstructured leased lines (D2048U) attachment requirements for terminal equipment interface”
(ETSI) “Business Telecommunications (BTC); 2048Kbit/s digital structured leased lines (D2048S); Attachment requirements for
terminal equipment interface”
(ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels”
(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in
Recommendation G.704”
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Table 3-3. TDM-over-Packet Related Specifications
Y.1413 TDM-MPLS network interworking – User plane interworking
TDMoMPLS will meet standards for network interworking that covers the Transport label, Interworking label, Common
interworking indicators, and Optional timing information. The Common interworking indicators include a Control Field, a
Fragmentation Field, Length Indicator and the Sequence number.
TDMoMPLS shall meet standards for Structure Agnostic transport.
TDMoMPLS shall meet standards for Structure Aware transport that contains Structure-locked encapsulation and Structure-
indicated encapsulation.
Y.1414 Voice Service – MPLS network interworking
The recommendation focuses on the required functions and procedures necessary for support of narrow-band voice services
by MPLS networks. Details of the encapsulation of encoded audio streams in MPLS packets are specified. Clause 10 draft
recommendation shall be met.
Y.1452 (Y.VTOIP) Voice trunking over IP
This recommendation specifies a method for transporting multiplexed voice services over UDP/IP.
Y.1453 (Y.TDMIP) TDM-IP interworking – User plane interworking
This recommendation specifies methods for transporting low-rate TDM (T1, E1, T3, E3) over UDP/IP. Y.1453 is a direct
extension of Y.1413.
PWE3-CESoPSN Structure-aware TDM Circuit Emulation Service over Packet Switched Network
May 2006 ‘draft-ietf-pwe3-cesopsn-07.txt’ revision shall be supported.
The TDM-over-Packet shall meet Basic NxDS0 service, and "Trunk-specific" NxDS0 service with CAS.
The TDM-over-Packet shall meet CESoPSN packet format for an IPv4/IPv6 PSN, CESoPSN Packet Format for an MPLS PSN.
Shall also meet CESoPSN Payload Layer.
PWE3-SAToP Structure-Agnostic TDM over Packet
June 2006 ‘rfc4553.txt’ revision shall be supported.
The TDM-over-Packet shall meet Basic SAToP Packet format, SAToP Packet format for an IPv4/IPv6, SAToP Packet format
for a MPLS PSN, and SAToP Payload Layer. SATop Control Word.
PWE3-TDMoIP
December 2006 ‘draft-ietf-pwe3-tdmoip-06.txt’ revision shall be supported.
PWE3-HDLC
September 2006 ‘rfc4618.txt’ revision shall be supported. (excluding clause 4.3 – PPP)
IEEE 802.3
This standard covers the MAC interface to a PHY for MII.
MPLS-Frame Relay Alliance Implementation Agreements 4.1
The purpose of this Implementation Agreement (IA) is to define network interworking between TDM circuits (n x 64 kbps,
E1/T1/E3/T3) over MPLS Label Switched Paths (LSPs) by using AAL1 encapsulation.
MPLS-Frame Relay Alliance Implementation Agreements 5.1
This specification defines MPLS support for the transport of AAL type 2 CPS-Packets. Frame formats and
procedures required for this transport are described in this Implementation Agreement. This specification addresses the
transport of any AAL type 2 CPS-Packets regardless of the application data that is transported.
MPLS-Frame Relay Alliance Implementation Agreements 8.0.0
This document describes a method for encapsulating TDM signals belonging to the PDH hierarchy (T1, E1, T3, E3, Nx64kbps)
as pseudo-wires over a MPLS network.
MEF 8 – Metro Ethernet Forum 8 - Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet
Networks
This document provides an implementation agreement for the emulation of PDH services across a Metro Ethernet Network.
Specifically it covers emulation of Nx64kbps, DS1, E1, DS3 and E3 circuits. Generically this is referred to as Circuit Emulation
Services over Ethernet (CESoETH).
G.823/G.824 Jitter & Wander Requirements
G.8261/Y.1361 (G.pactiming) Timing and Synchronization Aspects in Packet Networks
This recommendation defines synchronization aspects in packet networks and specifies the maximum network limits of jitter
and wander that shall not be exceeded and the minimum equipment tolerance to jitter and wander than shall be provided at the
boundary of these packet networks at TDM interfaces. It also outlines the minimum requirements for the synchronization
function of network elements.
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4.
Detailed Description
The DS34T108 is an 8-port device featuring independent transceivers that can be software configured for T1/J1 or
E1. The DS34T104/DS34T102/DS34T101 have the same functionality as the DS34T108, the product reference
throughout this document, but with fewer ports. Each transceiver, composed of an LIU, framer, HDLC controller,
elastic store, connects to the TDM-over-Packet (TDMoP) block for a complete monolithic solution to IP or MPLS or
Ethernet Layer 2 networks. The internal MAC supports connectivity to a single 10/100Mbps, MII//RMII/SSMII. The
DS34T108 is controlled via a 16-bit or 32-bit parallel port or via an SPI serial port.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. Internal impedance matching
is provided for both transmit and receive paths, reducing external component count. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes
for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator can be placed in either the transmit or the receive data paths and requires only a T1/J1 or E1 clock rate,
a SONET/SDH reference frequency of 19.44/38.88/77.76MHz, or a GPS reference frequency of 10MHz for both
T1/J1 and E1 applications.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane
interface section.
Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives
data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot or to FDL
(T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to
manage the flow of data.
The TDM-over-Packet (TDMoP) core is the building block for circuit emulation and other network applications. It
performs transparent transport of legacy TDM traffic over Packet Switched Networks (PSNs). The TDMoP core
implements payload methods such as AAL1 for circuit emulation, AAL2-like method for loop emulation, HDLC
method, structure-agnostic SAToP method, and the structure-aware CESoPSN method.
The AAL1 payload-type machine converts E1/T1/E3/T3/STS-1/serial data flows into IP, MPLS or Ethernet packets,
and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1, and the IETF PWE3 TDMoIP draft. It
supports E1/T1 structured mode with/without CAS, using a time slot size of 8 bits, or unstructured mode (carrying
serial interfaces, unframed E1/T1 or E3/T3/STS-1 traffic).
The AAL2 payload-type machine converts E1/T1 data flows into IP, MPLS or Ethernet packets, and vice versa,
implementing dynamic time slot allocation. It supports E1/T1 structured mode with/without CAS with 8-bit time slot
resolution, according to ITU-T Y.1414 (clause 10), Y.1452, MFA 5.1 and the IETF PWE3 TDMoIP draft.
The HDLC payload-type machine converts and terminates HDLC-based E1/T1/serial flow into IP/MPLS packets
and vice versa, according to the IETF RFC 4618 (excluding clause 5.3—PPP) and TDMoIP draft. It supports 2-, 7-
and 8-bit time slot resolution (i.e., 16kbps, 56kbps, and 64kbps, respectively), as well as N × 64 kbps bundles
(n = 1 to 32). Supported applications of this machine include trunking of HDLC-based traffic (such as frame relay)
implementing dynamic bandwidth allocation over IP/MPLS networks, and HDLC-based signaling interpretation
(such as ISDN D-channel signaling termination—BRI or PRI, V5.1/2, or GR-303).
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
The SAToP payload-type machine converts unframed E1/T1/E3/T3 data flows into IP, MPLS, or Ethernet packets,
and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0, and IETF RFC 4553. It supports
E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing it to be the simplest
way of making payload. The size of the payload is programmable for different services. This emulation suits
applications where the provider edges have no need to interpret TDM data or to participate in the TDM signaling.
The PSN network must have almost no packet loss and a very low PDV for this method.
The CESoPSN payload-type machine converts structured E1/T1/E3/T3 data flows into IP, MPLS or Ethernet
packets, and vice versa, with static assignment of time slots inside a bundle according to ITU-T Y.1413, Y.1453,
MEF 8, MFA 8.0.0, and the IETF PWE3 CESoPSN draft. It supports E1/T1/E3/T3 while taking into account the
TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e.,
frame, multiframe). This method is less sensitive to PSN impairments, but lost packets could still cause service
interruption. The payload is simply encapsulated into 24 bytes for T1 and 32 bytes for E1.
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5.
Application Examples
In Figure 5-1, DS34T108 is used to allow TDM services over a packet-switched metropolitan network, using
various access methods (G/E PON, fiber optic, wireless, cable).
Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network
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Figure 5-2. Cellular 2/3G Backhaul Over Packet-Switched Networks
5.1.1 Other Possible Applications
5.1.1.1 Point-to-Multipoint TDM Connectivity over IP/Ethernet
The TDM-over-Packet chip supports DS0-level multiple bundles/connections with and without CAS (Channel
Associated Signaling). There is no need for an external TDM cross-connect, as the packet domain can be used as
a virtual cross-connect; any bundle of time slots can be directed to another remote location on the packet domain.
5.1.1.2 HDLC Transport over IP/MPLS
TDM traffic streams often contain HDLC-based control and data traffic. These data streams, when transported over
a packet domain, should be treated differently than the time-sensitive TDM payload. The DS34T108 includes
HDLC controller capability, which enables termination of the HDLC frames. HDLC-based control protocols, such as
ISDN BRI and PRI, SS7, etc., and other frame-based traffic, can be managed and transported.
5.1.1.3 Using a Packet Backplane for Multiservice Concentrators
A communications device with all the above-mentioned capabilities can use a packet-based backplane instead of
the more expensive TDM bus option. This enables a cost-effective and future-proof design of communication
platforms with full support for both legacy and next-generation services.
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6.
Block Diagram
Figure 6-1. DS34T108 Functional Block Diagram
E1CLK
T1CLK
E1CLK
T1CLK
RESREF
JITTER ATTENUATOR
RCLKn/
RCLKFn
RDATFn
TDATFn
TCLKOn
TCLKFn
F
S y s t e m I
F
/
S y s t e m I
/
RLOF/RLOSn
RSYSCLKn
BACKPLANE INTERFACE
RSERn
RSYNCn
RF/RMSYNCn
TDMn_TCLK
TDMn_TX_SYNC
TDMn_TX_MF_CD
TDMn_RX
TDMn_RCLK
TDMn_RX_SYNC
TDMn_RSIG_RTS
TSERn
TSYNC/TSSYNCn
TSYSCLKn /ECLKn
TDMn_TX
TDMn_ACLK
TDMn_TSIG_CTS
CLK_CMN
H_D[31:0]
H_A[24:1]
H_CS_N
CLK_HIGH
MCLK
H_ R_W_N
H_WR_BE3..0_N
H_READY_N
H_INT[1:0]
DATA_31_16_N
Reserved
SD_D[31: 0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
JTMS
Data
JTCLK
JTDI
Byte Enable Mask
Address
Bank Select
Control
JTDO
SD_CLK
JTRST_EN
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
HIZ_EN
SCEN
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
RST_SYS_N
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7.
Feature Highlights
The following sections describe the features provided by the 8-port DS34T108.
7.1
Global Features
•
The DS34T108 chip offers:
Eight E1/T1 LIUs/framers/TDMoP interfaces or
One E3/DS3/STS-1 TDMoP interface or
One serial TDMoP interface for V.35 and RS530
•
Ethernet interface
One 10/100Mbps, MII/RMII/SSMII
Half/full duplex
VLAN support according to 802.1 p&Q
Fully compatible with IEEE 802.3 standard
•
•
End-to-end TDM synchronization through the IP/MPLS domain by eight independent on-chip TDM clock
recovery mechanisms, on a per-port basis
64 independent bundles/connections, each with its own:
Transmit and receive queues
Configurable jitter-buffer depth
Connection level redundancy, with traffic duplication option
64 Internal bundle cross-connect capability, with DS0 resolution
Any framer receiver port to any TDM interface receiver to maintain bundle connectivity
Any transmit TDM interface to any framer transmit port to maintain bundle connectivity
Packet loss compensation and handling of misordered packets
Glueless SDRAM interface
Complies with MPLS-Frame Relay Alliance Implementation Agreements 4.1, 5.1, and 8.0
Meets ITU standards Y.1413 and Y.1414
Complies with Metro Ethernet Forum 3 & 8
•
•
•
•
•
•
•
•
•
•
•
•
Conforms to drafts submitted to IETF
23mm x 23 mm, 484-pin HSBGA package (1mm pitch)
IEEE 1146.1 JTAG boundary scan
1.8V and 3.3V Operation with 5.0V tolerant I/O
7.2
Line Interface
•
Requires a single 38.88Mz, 19.44MHz, 77.76MHz, or 10MHz clock high synthesis (CLK_HIGH) input for both
E1 and T1 operation. Optionally, a 1.544MHz or 2.048MHz master clock (MCLK) also can be used for LIU
clock recovery
•
•
•
Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB,
0dB to 30dB, 0dB to 20dB, and 0dB to -15dB for T1
•
Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB
increments
•
•
•
•
•
•
Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
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•
•
•
•
•
•
•
•
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
Analog loss of signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current limit exceeded indication
Transmit open-circuit-detected indication
7.3
Clock Synthesizer
•
Internal clock synthesis for the E1 and T1 from an input of 38.88Mz, 19.44MHz, 77.76MHz, or 10MHz clock
source.
7.4
Jitter Attenuator
•
•
32-bit or 128-bit crystal-less jitter attenuator
Can be placed in either the receive or transmit path or disabled
•
Limit trip indication
7.5
Framer/Formatter
•
•
•
•
•
•
•
•
•
•
•
•
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe
Transmit side synchronizer
Transmit midpath CRC recalculate (E1)
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
T1: BPV, CV, CRC6, and framing bit errors
E1: BPV, CV, CRC4, E-bit, and frame alignment errors
Timed or manual update modes
DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
•
•
User-defined code generation
Digital milliwatt code generation
•
•
•
•
•
•
•
•
•
•
•
ANSI T1.403-1999 Support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
Three independent generators and detectors
Patterns from 1 to 8 bits or 16 bits in Length
Bit oriented code (BOC) support
Software or hardware based signaling support
Interrupt generated on change of signaling data
Optional receive signaling freeze on loss of frame, loss of signal, or frame slip
Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock (LOTC), or
signaling freeze condition
•
Automatic RAI generation to ETS 300 011 specifications
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•
•
•
•
•
•
•
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1 to E1 conversion
7.6
Framer System Ports
•
•
•
•
•
•
•
•
•
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Supports T1 to CEPT (E1) conversion
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
Hardware signaling capability
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
BERT testing to the system interface
7.7
TDM-over-Packet Engine
TDM-over-Packet enables transport of legacy TDM services – E1/T1, E3/T3, STS-1, or serial data (on the user
side) over packet switched networks – IP, MPLS or Ethernet (on the network side). This module implements the
following payload methods of TDM transfer over IP, MPLS or Ethernet networks:
•
•
•
•
•
SAToP (Structure-Agnostic TDM over Packet)
Structure-aware format for structured E1/T1 with or without CAS (CESoPSN)
AAL1 format (constant rate/static allocation of time slots)
AAL2 format (dynamic allocation of time slots)
HDLC termination for efficient transfer of frame-based traffic.
A dedicated payload type engine implements each per the following method:
•
SAToP hardware engine converts unframed E1/T1/E3/T3/STS-1 or serial data flows into IP, MPLS, or Ethernet
packets and vice versa according to ITU-T Y.1413, MEF 8, MFA 8.0.0 and the IETF PWE3 SAToP draft.
CESoPSN hardware engine converts structured E1/T1 data flows into IP, MPLS or Ethernet packets and vice
versa with static assignment of time slots inside a bundle according to ITU-T Y.1413, MEF 8, MFA 8.0.0, and
the IETF PWE3 CESoPSN draft.
•
•
AAL1 hardware engine converts E1/T1/E3/T3/STS-1 or serial data flows into IP, MPLS or Ethernet packets,
and vice versa, according to ITU-T Y.1413, MEF 8, MFA 4.1 and the IETF PWE3 TDMoIP draft. For E1/T1 it
supports structured mode with/without CAS using 8-bit time slot resolution, while implementing static time slot
allocation. For E1/T1, E3/T3/STS-1 or serial interface it supports unstructured mode.
•
•
AAL2 hardware engine converts E1/T1 data flows into IP/MPLS/Ethernet packets, and vice versa, while
implementing dynamic time slot allocation. It supports E1/T1 structured mode with/without CAS using 8-bit time
slot resolution, according to ITU-T Y.1414 (clause 10), MFA 5.1 and the IETF PWE3 TDMoIP draft.
HDLC hardware engine converts and terminates HDLC-based E1/T1/serial flow into IP/MPLS/Ethernet packets
and vice versa. It supports 2-, 7- and 8-bit time slot resolution (i.e., 16kbps, 56kbps, and 64kbps, respectively),
as well as N x 64kbps bundles. This is useful in applications where HDLC-based signaling interpretation is
required (such as ISDN D channel signaling termination, V.51/2, or GR-303), or for trunking packet-based
applications (such as Frame Relay), according to the IETF PWE3 HDLC draft.
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7.7.1 TDM-over-Packet User Interfaces
The user side consists of either a single high-speed E3, T3 or STS-1, or eight I/Fs, each independently supporting
E1, T1 or serial data transfer.
For the E3/T3/STS-1 option, the AAL1 or SAToP method is used.
For the E1/T1 option, the module supports the following operation modes:
•
•
•
Unframed—E1/T1 pass-through mode (AAL1, SAToP, or HDLC payload type method)
Structured—fractional E1/T1 support (all payload type methods)
Structured with CAS—fractional E1/T1 with CAS support (CESoPSN, AAL1, or AAL2 payload type method)
The serial interface option supports synchronous data transfer (for interfaces such as V.35) over the
IP/MPLS/Ethernet network for legacy data services (such as frame relay or arbitrary continuous bit stream).
The serial port option supports the following synchronous serial data formats:
•
•
Arbitrary continuous bit stream (using AAL1 or SAToP payload type method)
In single-interface high-speed mode, the first interface operates at up to STS-1 rate (51.84Mbps) and the
other interfaces are disabled. In this mode, the whole traffic is transferred using a single bundle/connection.
In eight-interface low-speed mode each interface can operate at the rate of N x 64kbps, where N = 1 to 63,
with an aggregate rate of 18.6Mbps.
HDLC-based traffic (such as frame relay transferred using HDLC payload type method). Only the eight-
interface low-speed mode is available (N x 64kbps, where N = 1 to 63, with an aggregate rate of
18.6Mbps).
•
•
All serial interface modes can work with a gapped clock.
7.7.2 Network Port
The chip features one 10/100 Ethernet port with the option of MII/RMII/SSMII. The port can work in half/full-duplex
mode and supports VLAN tagging and priority labeling according to 802.1 p&Q, including VLAN stacking.
7.7.3 Bundles
A bundle is defined as a stream of bits that have originated from the same physical interface and that are
transmitted from a TDM-over-Packet source device to a TDM-over-Packet destination device. For example,
bundles can comprise any number of 64kbps time slots originating from a single E1 or an entire T3 or E3. Bundles
are single-direction streams, frequently coupled with bundles in the opposite direction to enable full-duplex
communications. More than one bundle can be transmitted between two TDM-over-Packet edge devices.
The chip supports up to 64 bundles; each can be assigned to any port. The bundles are configured independently,
each with its own:
•
•
•
Transmit and receive queues
Configurable receive-buffer depth
Optional connection level redundancy (SAToP, AAL1, CESoPSN only)
The bundles can be assigned to one of the payload type machines or to the CPU. For E1/T1, the chip provides
internal bundle cross-connect functionality, with DS0 resolution.
7.7.4 Clock Recovery
Sophisticated TDM clock recovery mechanisms, one for each E1/T1 interface, allow end-to-end TDM clock
synchronization, despite packet delay variation of IP/MPLS/Ethernet network.
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TDM-over-Packet supports the following clock recovery modes:
•
•
•
•
Adaptive clock recovery
Common clock (using RTP)
External clock
Loopback clock
The clock recovery mechanisms provide both fast frequency acquisition and highly accurate phase tracking.
•
Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or
synchronization interfaces. For adaptive clock recovery, the recovered clock performance depends on
packet network characteristics.
•
Short-term frequency accuracy (1 second) is better than 16ppb (using OCXO reference) or 100ppb (using
TCXO reference)
•
•
•
Capture range is ±90ppm
Internal synthesizer resolution of 0.5ppb
High resilience to the packet loss and misordering, up to 2% of packet loss/misordering without
degradation of clock recovery performance
•
•
Robust to sudden significant constant delay changes
Automatic transition to hold-over is performed upon link-break events.
7.7.5 Delay Variation Compensation
The TDM-over-Packet module provides large configurable jitter buffers, on a per-bundle basis, that compensate for
the delay variation introduced by the IP/MPLS/Ethernet network, with the following depths:
•
•
•
•
•
•
•
E1: Up to 256ms
T1 Unframed: Up to 340ms
T1 Framed: Up to 256ms
T1 Framed with CAS: Up to 192ms
E3: Up to 60ms
T3: Up to 45ms
STS-1: Up to 40ms
For the SAToP and CESoPSN bundles, TDM-over-Packet performs packet reordering within the range of the jitter
buffer.
Packet loss is compensated by inserting either a preconfigured conditioning value or the last received value.
7.7.6 CAS Support
A CAS handler terminates the E1/T1 CAS when using AAL1/AAL2/CESoPSN in structured-with-CAS mode. This
eliminates the need for CPU intervention.
7.8
Test and Diagnostics
•
•
•
•
•
•
•
•
IEEE 1149.1 Support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 & E1 frame in the transmit path
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•
•
•
•
•
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
MBIST
7.9
Control Port
The CPU interface provides a connection to a host with a 16/32-bit data bus. This allows configuration of chip
control registers and statistics collection using the chip counters and status registers. It also provides access to the
CPU transmit and received buffers allocated in the SDRAM, used for packets that are directed to/originate from the
CPU (such as ARP, SNMP, etc.).
•
•
•
•
32- or 16-bit parallel control port
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
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8.
Overview of Major Operational Modes
This section provides a high-level overall description of the DS34T108 and its functional interfaces and capabilities.
8.1
Internal Mode Configured as One-Clock Mode
The default mode of the DS34T108 is internal mode and one-clock mode. Internal mode is used to internally
connect the framer and the TDM-over-Packet blocks. Internal mode additionally sets many unused output
port/interface pins to drive low. Unused input port/interface pins become inactive. This is due to the signals now
being connected internally. Figure 8-1 represents the block diagram of this mode.
One-clock mode refers to both the transmit and the receive interfaces using a single recovery clock for the framer
port and TDM-over-Packet interface. Transmit and the receiver are therefore synchronized together. This mode
requires the elastic store of the receiver framer to be enabled. Registers additionally allow the selection of any one
clock and transmit synchronization pulse to connect to any port. Figure 8-2 represents the internal connections for
a single port/interface.
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Figure 8-1. Internal Mode
RESREF
E1CLK
T1CLK
E1CLK
T1CLK
JITTER ATTENUATOR
RCLKn
RCLKFn
RDATFn
TCLKOn
TDATFn
F
S y s t e m I
F
/
S y s t e m I
/
BACKPLANE INTERFACE
H_D[31:0]
H_A[24:1]
CLK_HIGH
MCLK
H_CS_N
H_R_W_N
H_WR_BE3..0_N
H_READY_N
H_INT[1:0]
DATA_31_16_N
Reserved
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
JTMS
JTCLK
Data
Byte Enable Mask
Address
JTDI
JTDO
Bank Select
Control
SD_CLK
JTRST_EN
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
HIZ_EN
SCEN
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
RST_SYS_N
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Figure 8-2. Internal One-Clock Mode
"One Clock Mode (Framed/Multiframed)"
RCLK[8..1]
ACLK[8.. 1]
E1CLK
ECLK[8..1] pin
T1CLK
CLKCNTL
bits
TDMoPacket X 8
Framer X8
ACLKn
RCLKn
TDMn_ACLK
TDMn_TCLK
TDMn_RCLK
TDMn_TSIG
TDMn_RSIG
TDMn_TX
TCLKn
RSYSCLKn
TSIGn
rclkn
rposn
rnegn
RSIGn
TSERn
RSERn
RSYNCn
TSYNCn
TDMn_RX
Connected to LIU
TDMn_RX_SYNC
TDMn_TX_SYNC
TDMn_TX_MF*
tclkon
tposn
tnegn
TSYNC
SYNCNTL
bits
TSYNC[8..1]
*Note: The internal signal input "TDMn_TX_MF" is a don 't care when configured in framer mode
.
8.2
Internal Mode Configured as Two-Clock Mode
Internal two-clock mode configures the port/interfaces to have separate clocking between transmit and receive
port/interfaces.
Figure 8-3 represent a single internal two-clock mode port/interface connection for framed and multiframed
applications. In this mode, the elastic store should not be enabled. The receive frame synchronization pulse or
receive multiframe synchronization are delivered from the framer to the TDM-over-Packet block based on RCLKFn.
The transmit synchronization pulse also comes from the framer with TSYNC configured for framer pulses or
multiframe pulses based on the TCLKF input.
The user may not need to use the framer during particular applications. If this is the case, the user should set the
GCR1.UNFRMMODE bit. This selects internal two-clock mode for unframed applications as shown in Figure 8-4.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
Figure 8-3. Internal Two-Clock Mode (Framed)
"Two Clock Mode, (Framed)"
RCLK[8..1]
ACLK[8..1]
ECLK[8.. 1] pin
E1CLK
T1CLK
CLKCNTL
bits
TDMoPacket X 8
Framer X8
ACLKn
TDMn_ACLK
TDMn_TCLK
TDMn_RCLK
TDMn_TSIG
TDMn_RSIG
TDMn_TX
RCLKn
TCLKFn
RCLKn
RCLKFn
RPOSn
RNEGn
TSIGn
RSIGn
TSERn
RSERn
TDMn_RX
Connected to LIU
TDMn_RX_SYNC
TDMn_TX_SYNC
TDMn_TX_MF
RF/RMSYNCn
TCLKOn
TPOSn
TNEGn
TSYNCn
SYNCNTL
bits
SYNCNTL
bits
RF/RMSYNC[8..1]
TSYNC[8..1]
*Note: The internal signal input "TDMn_TX_MF" is a don 't care when configured in framer mode
.
Figure 8-4. Internal Two-Clock Mode (Unframed)
"Two Clock Mode, (Unframmed)"
RCLK[8..1]
ACLK[8..1]
ECLK[8..1] pin
E1CLK
T1CLK
CLKCNTL
bits
TDMoPacket X 8
Framer X8
(Bypassed mode)
ACLKn
TDMn_ACLK
TDMn_TCLK
TDMn_RCLK
RCLKn
TCLKFn
RCLKn
RCLKFn
RPOSn
RNEGn
TDMn_TX
TDMn_RX
TSERn
RSERn
Connected to LIU
TCLKOn
TPOSn
TNEGn
8.3
External Mode
External mode activates all the port interface pins for utilization of when the user wants to custom wire the
connections between the framer and TDM-over-Packet externally. Many applications that require a network
processor would need wiring like this to be applied between these two points. Refer to the full data sheet for more
information.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
9.
Functional Description and Device Registers
Refer to the full data sheet for this information.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
10. Pin Description
10.1 Short Pin Descriptions
In the type column, of the short pin description, the following abbreviations are used: I (Input), Ipu (Input with
Pullup), Ipd (Input with Pulldown), Ia (Analog Input), O (Output), Oz (Output Tri-Stateable), Oa (Analog Output),
IO (Bidirectional Inout), IOpd (Bidirectional with Pulldown), and IOpu (Bidirectional with Pullup).
Table 10-1. DS34T108 Short Pin Descriptions
NAME
SD_D[31:0]
TYPE
IO
FUNCTION
Synchronous DRAM Data Bus
Byte Enable Mask
SD_DQM[3:0]
SD_A[11:0]
O
O
SDRAM Address Bus
SDRAM Bank Select
SDRAM Clock
SD_BA[1:0]
O
SD_CLK
O
SD_CS_N
O
SDRAM Chip Select (Active Low)
SDRAM Write Enable (Active Low)
SDRAM Row Address Strobe Enable (Active Low)
SDRAM Column Address Strobe (Active Low)
TDM1 Transmit
SD_WE_N
O
SD_RAS_N
O
SD_CAS_N
O
TDM1_TX
O
TDM1_RX
Ipu
Ipu
Ipu
O
TDM1 Receive
TDM1_TCLK
TDM1_RCLK
TDM1_ACLK
TDM1_TX_SYNC
TDM1_TX_MF_CD
TDM1_RX_SYNC
TDM1_TSIG_CTS
TDM1_RSIG_RTS
TDM2_TX
TDM1 Transmit Clock
TDM1 Receive Clock
TDM1 Recovery Clock
Ipd
IOpd
Ipd
O
TDM1 Transmit/Receive Sync Pulse
TDM1 Transmit Multiframe Sync Pulse/Carrier Detect
TDM1 Receive Multiframe Sync Pulse/Sync Pulse
TDM1 Transmit Signaling/Clear to Send
TDM1 Receive Signaling/Request To Send
TDM2 Transmit
Ipu
O
TDM2_RX
Ipu
Ipu
Ipu
O
TDM2 Receive
TDM2_TCLK
TDM2_RCLK
TDM2_ACLK
TDM2_TX_SYNC
TDM2_TX_MF_CD
TDM2_RX_SYNC
TDM2_TSIG_CTS
TDM2_RSIG_RTS
TDM3_TX
TDM2 Transmit Clock
TDM2 Receive Clock
TDM2 Recovery Clock
Ipd
IOpd
Ipd
O
TDM2 Transmit/Receive Sync Pulse
TDM2 Transmit Multiframe Sync Pulse/Carrier Detect
TDM2 Receive Multiframe Sync Pulse/Sync Pulse
TDM2 Transmit Signaling/Clear to Send
TDM2 Receive Signaling/Request To Send
TDM3 Transmit
Ipu
O
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
Ipu
Ipu
Ipu
O
FUNCTION
TDM3_RX
TDM3 Receive
TDM3_TCLK
TDM3Transmit Clock
TDM3 Receive Clock
TDM3 Recovery Clock
TDM3_RCLK
TDM3_ACLK
TDM3_TX_SYNC
TDM3_TX_MF_CD
TDM3_RX_SYNC
TDM3_TSIG_CTS
TDM3_RSIG_RTS
TDM4_TX
Ipd
IOpd
Ipd
O
TDM3 Transmit/Receive Sync Pulse
TDM3 Transmit Multiframe Sync Pulse/Carrier Detect
TDM3 Receive Multiframe Sync Pulse/Sync Pulse
TDM3 Transmit Signaling/Clear to Send
TDM3 Receive Signaling/Request To Send
TDM4 Transmit
Ipu
O
TDM4_RX
Ipu
Ipu
Ipu
O
TDM4 Receive
TDM4_TCLK
TDM4Transmit Clock
TDM4_RCLK
TDM4 Receive Clock
TDM4_ACLK
TDM4 Recovery Clock
TDM4_TX_SYNC
TDM4_TX_MF_CD
TDM4_RX_SYNC
TDM4_TSIG_CTS
TDM4_RSIG_RTS
TDM5_TX
Ipd
IOpd
Ipd
O
TDM4 Transmit/Receive Sync Pulse
TDM4 Transmit Multiframe Sync Pulse/Carrier Detect
TDM4 Receive Multiframe Sync Pulse/Sync Pulse
TDM4 Transmit Signaling/Clear to Send
TDM4 Receive Signaling/Request To Send
TDM5 Transmit
Ipu
O
TDM5_RX
Ipu
Ipu
Ipu
O
TDM5 Receive
TDM5_TCLK
TDM5Transmit Clock
TDM5_RCLK
TDM5 Receive Clock
TDM5_ACLK
TDM5 Recovery Clock
TDM5_TX_SYNC
TDM5_TX_MF_CD
TDM5_RX_SYNC
TDM5_TSIG_CTS
TDM5_RSIG_RTS
TDM6_TX
Ipd
IOpd
Ipd
O
TDM5 Transmit/Receive Sync Pulse
TDM5 Transmit Multiframe Sync Pulse/Carrier Detect
TDM5 Receive Multiframe Sync Pulse/Sync Pulse
TDM5 Transmit Signaling/Clear to Send
TDM5 Receive Signaling/Request To Send
TDM6 Transmit
Ipu
O
TDM6_RX
Ipu
Ipu
Ipu
O
TDM6 Receive
TDM6_TCLK
TDM6Transmit Clock
TDM6_RCLK
TDM6 Receive Clock
TDM6_ACLK
TDM6 Recovery Clock
TDM6_TX_SYNC
TDM6_TX_MF_CD
TDM6_RX_SYNC
TDM6_TSIG_CTS
TDM6_RSIG_RTS
Ipd
IOpd
Ipd
O
TDM6 Transmit/Receive Sync Pulse
TDM6 Transmit Multiframe Sync Pulse/Carrier Detect
TDM6 Receive Multiframe Sync Pulse/Sync Pulse
TDM6 Transmit Signaling/Clear to Send
TDM6 Receive Signaling/Request To Send
Ipu
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TDM7_TX
TYPE
O
FUNCTION
TDM7 Transmit
TDM7_RX
Ipu
Ipu
Ipu
O
TDM7 Receive
TDM7_TCLK
TDM7_RCLK
TDM7_ACLK
TDM7_TX_SYNC
TDM7_TX_MF_CD
TDM7_RX_SYNC
TDM7_TSIG_CTS
TDM7_RSIG_RTS
TDM8_TX
TDM7Transmit Clock
TDM7 Receive Clock
TDM7 Recovery Clock
Ipd
IOpd
Ipd
O
TDM7 Transmit/Receive Sync Pulse
TDM7 Transmit Multiframe Sync Pulse/Carrier Detect
TDM7 Receive Multiframe Sync Pulse/Sync Pulse
TDM7 Transmit Signaling/Clear to Send
TDM7 Receive Signaling/Request To Send
TDM8 Transmit
Ipu
O
TDM8_RX
Ipu
Ipu
Ipu
O
TDM8 Receive
TDM8_TCLK
TDM8_RCLK
TDM8_ACLK
TDM8_SYNC
TDM8_TX_MF_CD
TDM8_RX_MF
TDM8_TSIG_CTS
TDM8_RSIG_RTS
CLK_MII_RX
MII_RXD[0]
TDM8Transmit Clock
TDM8 Receive Clock
TDM8 Recovery Clock
Ipd
IOpd
Ipd
O
TDM8 Transmit/Receive Sync Pulse
TDM8 Transmit Multiframe Sync Pulse/Carrier Detect
TDM8 Receive Multiframe Sync Pulse
TDM8 Transmit Signaling/Clear to Send
TDM8 Receive Signaling/Request To Send
Clock Media Independent Interface Receive
Media Independent Interface Receive Data 0
Media Independent Interface Receive Data 1
Media Independent Interface Receive Data 2
Media Independent Interface Receive Data 3
Media Independent Interface Receive Data Valid
Media Independent Interface Receive Error
Media Independent Interface Collision
Media Independent Interface carrier sense.
Clock Media Independent Interface Transmit
Clock Source Synchronous Serial Media Independent Interface Transmit
Media Independent Interface Transmit Data 0
Media Independent Interface Transmit Data 1
Media Independent Interface Transmit Data 2
Media Independent Interface Transmit Data 3
Media Independent Interface Transmit Enable
Media Independent Interface Transmit Error
Management Data Input/Output
Ipu
I
I
MII_RXD[1]
I
MII_RXD[2]
I
MII_RXD[3]
I
MII_RX_DV
I
MII_RX_ERR
MII_COL
I
I
MII_CRS
I
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[0]
I
O
O
MII_TXD[1]
O
MII_TXD[2]
O
MII_TXD[3]
O
MII_TX_EN
O
MII_TX_ERR
MDIO
O
IOpu
O
MDC
Management Data Clock
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
Oa
Transmit Bipolar Tip for Channels 1–8
TTIP6
TTIP7
TTIP8
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
TRING8
Oa
I
Transmit Bipolar Ring for Channels 1–8
Transmit Enable for All Channels 1–8
Receive Bipolar Tip for Channels 1–8
TXENABLE
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
Ia
RTIP6
RTIP7
RTIP8
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
RRING8
Ia
I
Receive Bipolar Ring for Channels 1–8
Receive Termination Selection
RXTSEL
RCLKF1/RCLK1
RCLKF2/RCLK2
RCLKF3/RCLK3
RCLKF4/RCLK4
RCLKF5/RCLK5
RCLKF6/RCLK6
RCLKF7/RCLK7
RCLKF8/RCLK8
TCLKF1
IO
Receive Framer Clock/Receive Clock
TCLKF2
TCLKF3
TCLKF4
TCLKF5
I
Transmit Clock Input for the Formatter
TCLKF6
TCLKF7
TCLKF8
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TCLKO5
TCLKO6
TCLKO7
TCLKO8
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
TDATF1
TDATF2
TDATF3
TDATF4
TDATF5
TDATF6
TDATF7
TDATF8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
O
Transmit Clock Output
Receive Serial Data Output
Transmit Data Formatter Output
Receive Sync
O
O
IO
I
RSYNC8
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RSYSCLK5
RSYSCLK6
RSYSCLK7
RSYSCLK8
RF/RMSYNC1
RF/RMSYNC2
RF/RMSYNC3
RF/RMSYNC4
RF/RMSYNC5
RF/RMSYNC6
RF/RMSYNC7
RF/RMSYNC8
Receive System Clock
O
Frame Synchronization/Receive Multiframe Synchronization
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
RLOF/RLOS1
RLOF/RLOS2
RLOF/RLOS3
RLOF/RLOS4
RLOF/RLOS5
RLOF/RLOS6
RLOF/RLOS7
RLOF/RLOS8
TSER1
O
Receive Loss of Frame/Receive Loss of Signal
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
RDATF1
RDATF2
RDATF3
I
I
Transmit Serial Data
RDATF4
RDATF5
Receive Data Framer Input/Transmit Signaling
Transmit Synchronization/Transmit System Synchronization In
Transmit System Clock
RDATF6
RDATF7
RDATF8
TSYNC/TSSYNC1
TSYNC/TSSYNC2
TSYNC/TSSYNC3
TSYNC/TSSYNC4
TSYNC/TSSYNC5
TSYNC/TSSYNC6
TSYNC/TSSYNC7
TSYNC/TSSYNC8
TSYSCLK1/ECLK1
TSYSCLK2/ECLK2
TSYSCLK3/ECLK3
TSYSCLK4/ECLK4
TSYSCLK5/ECLK5
TSYSCLK6/ECLK6
TSYSCLK7/ECLK7
TSYSCLK8/ECLK8
IO
I
CLK_SYS_S
CLK_SYS
I
System Clock Selection
System Clock
I
CLK_HIGH
MCLK
I
I
Clock High Synthesis
Master Clock
CLK_CMN
I
Common Clock
Host Data Bus
H_D[31:1]
IO
IO
I
H_D[0]/SPI_MISO
H_AD[24:1]
H_CS_N
Host Data LSB
Host Address Bus
Host Chip Select
Host Read/Write
I
H_R_W_N/SPI_CP
I
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
H_D[7:0] Write Enable, Active Low
H_WR_BE0_N/
SPI_CLK
I
H_WR_BE1_N/
SPI_MOSI
I
I
I
H_D[15:8] Write Enable, Active Low
H_D[23:16] Write Enable, Active Low
H_D[31:24] Write Enable, Active Low
H_WR_BE2_N/
SPI_SEL_N
H_WR_BE3_N/
SPI_CI
H_READY_N
Oz
O
Host Ready
H_INT[1]
H_INT[0]
Host Interrupt
DAT_32_16_N
H_CPU_SPI_N
RST_SYS_N
RESREF
JTMS
Ipu
Ipu
Ipu
I
Data 32/16-Bit Select
CPU or SPI Mode
System Reset
Resistance Reference
Ipu
Ipd
Ipu
Oz
Ipu
Ipd
Ipd
I
JTAG Test Mode Select
JTCLK
JTAG Test Clock
JTDI
JTAG Test data In
JTDO
JTAG Test Data Out
JTRST
JTAG Test Reset
SCEN
Used for factory tests.
STMD
Used for factory tests.
HIZ_N
Used for factory tests.
MBIST_EN
MBIST_DONE
MBIST_FAIL
TEST_CLK
TST_CLD
TST_TA
TST_TB
TST_TC
TST_RA
TST_RB
TST_RC
DVSS
I
Used for factory tests.
O
Used for factory tests.
O
Used for factory tests
O
Used for factory tests.
I
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Used for factory tests. DS34T104 only.
Digital Core Ground for Framers and TDM-over-Packet (31 pins)
1.8V Core Supply Voltage for Framers and TDM-over-Packet (17 pins)
3.3V Supply Voltage for I/O (16 pins)
3.3V Supply Voltage for LIUs (2 pins)
Digital Ground for the LIUs (2 pins)
3.3V Power Supply for the Transmitter (8 pins)
O
O
O
O
O
O
—
—
—
—
—
—
DVDDC
DVDDIO
DVDDLIU
DVSSLIU
ATVDDn
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
—
FUNCTION
Analog Ground for Transmitters (8 pins)
ATVSSn
ARVDDn
ARVSSn
ACVDD2
ACVSS2
ACVDD1
ACVSS1
—
3.3V Analog Receive Power Supply (8 pins)
Analog Receive GND (8 pins)
Analog CLAD 1.8V Supply 2
Analog CLAD GND 2
—
—
—
—
Analog CLAD 1.8V Supply 1
Analog CLAD GND 1
—
Note: Pins with names ending in an asterisk (*) or “_N” are active low.
10.2 Detailed Pin Descriptions
In the detailed pin description table, the type column defines the drive current for any type of output pin. Also in the
detailed pin description table, the type column uses the following abbreviations: I (Input), Ipu (Input with Pullup), Ipd
(Input with Pulldown), Ia (Analog Input), O (Output), Oz (Output Tri-Stateable), Oa (Analog output), IO (Bidirectional
Inout), IOpd (Bidirectional with Pulldown), and IOpu (Bidirectional with Pullup).
Table 10-2. Detailed Pin Descriptions
NAME
TYPE
FUNCTION
SDRAM PINS
IO
8mA
Synchronous DRAM Data Bus
SD_D[31:0]: Data bus towards SDRAM. MSB is SD_D[31].
SD_D[31:0]
Byte Enable Mask
O
8mA
SD_DQM[3:0]: Byte enable towards SDRAM. Serves as a mask. SD_DQM[0] is
connected to the least significant byte at SDRAM, while SD_DQM[3] is connected
to the most significant byte at SDRAM.
SD_DQM[3:0]
O
8mA
SDRAM Address Bus
SD_A[11:0]: Address bus towards SDRAM. MSB is SD_A[11].
SD_A[11:0]
SD_BA[1:0]
SDRAM Bank Select
SD_BA[1:0]: SDRAM bank select. Selects one bank out of four banks at
SDRAM.
O
8mA
O
8mA
SDRAM Clock
SD_CLK: Drives the SDRAM clock towards the SDRAM.
SD_CLK
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
O
8mA
SDRAM Chip Select (Active Low)
SD_CS_N: SDRAM chip select towards SDRAM.
O
8mA
SDRAM Write Enable (Active Low)
SD_WE_N: Write enable towards SDRAM.
O
8mA
SDRAM Row Address Strobe Enable (Active Low)
SD_RAS_N: Row address strobe towards SDRAM.
O
8mA
SDRAM Column Address Strobe (Active Low)
SD_CAS_N: Column address strobe towards SDRAM.
TDM-OVER-PACKET INTERFACE PINS
TDM1 Transmit
O
8mA
TDM1_TX
TDM1_RX
TDM1_TX: First interface serial transmit line. Also used in high-speed
E3/T3/STS1 mode.
TDM1 Receive
Ipu
TDM1_RX: First interface serial receive line. This pin is active in external mode
only. Also used in high-speed E3/T3/STS1 mode.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TDM1 Transmit Clock
TDM1_TCLK: Used for clocking TDM1_TX and TDM1_RX lines in one-clock
mode, or TDM1_TX in two-clock mode. This pin is active in external mode only.
Also used in high-speed E3/T3/STS1 mode.
TDM1_TCLK
Ipu
TDM1 Receive Clock
TDM1_RCLK: Used for clocking TDM1_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only. Also used in high-speed
E3/T3/STS1 mode.
TDM1 Recovery Clock
TDM1_ACLK: First interface recovered clock. Also used in high-speed
E3/T3/STS1 mode.
TDM1_RCLK
TDM1_ACLK
Ipu
O
8mA
TDM1 Transmit/Receive Sync Pulse
TDM1_TX_SYNC: First interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM1 Transmit Multiframe Sync Pulse/Carrier Detect
TDM1_TX_MF_CD: First interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM1_TX_SYNC
TDM1_TX_MF_CD
Ipd
IOpd
Ipd
TDM1 Receive Multiframe Sync Pulse
TDM1_RX_SYNC: First interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM1 Transmit Signaling/Clear to Send
TDM1_TSIG_CTS: First interface transmit signaling, or Clear To Send in case of
serial interface.
TDM1_RX_SYNC
TDM1_TSIG_CTS
O
8mA
TDM1 Receive Signaling/Request To Send
TDM1_RSIG_RTS
TDM2_TX
Ipu
TDM1_RSIG_RTS: First interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
TDM2 Transmit
O
8mA
TDM2_TX: Second Interface serial transmit line.
TDM2 Receive
TDM2_RX
Ipu
Ipu
Ipu
TDM2_RX: Second interface serial receive line. This pin is active in external
mode only. This pin is active in external mode only.
TDM2 Transmit Clock
TDM2_TCLK: Used for clocking TDM2_TX and TDM2_RX lines in one-clock
mode, or TDM2_TX in two-clock mode. This pin is active in external mode only.
This pin is active in external mode only.
TDM2_TCLK
TDM2 Receive Clock
TDM2_RCLK
TDM2_ACLK
TDM2_RCLK: Used for clocking TDM2_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM2 Recovery Clock
O
8mA
TDM2_ACLK: Second interface recovered clock.
TDM2 Transmit/Receive Sync Pulse
TDM2_TX_SYNC: Second interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM2 Transmit Multiframe Sync Pulse/Carrier Detect
TDM2_TX_MF_CD: Second interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM2_TX_SYNC
TDM2_TX_MF_CD
Ipd
IOpd
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TDM2 Receive Multiframe Sync Pulse
TDM2_RX_SYNC: Second interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM2 Transmit Signaling/Clear to Send
TDM2_TSIG_CTS: Second interface transmit signaling, or Clear to Send in case
of serial interface.
TDM2_RX_SYNC
Ipd
O
8mA
TDM2_TSIG_CTS
TDM2 Receive Signaling/Request To Send
TDM2_RSIG_RTS
TDM3_TX
Ipu
TDM2_RSIG_RTS: Second interface serial Rx signaling input or Request To
Send input in case of serial interface. This pin is active in external mode only.
TDM3 Transmit
O
8mA
TDM3_TX: Third Interface serial transmit line.
TDM3 Receive
TDM3_RX
Ipu
Ipu
Ipu
TDM3_RX: Third interface serial receive line. This pin is active in external mode
only.
TDM3 Transmit Clock
TDM3_TCLK: Used for clocking TDM3_TX and TDM3_RX lines in one-clock
mode, or TDM3_TX in two-clock mode. This pin is active in external mode only.
TDM3 Receive Clock
TDM3_RCLK: Used for clocking TDM3_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM3 Recovery Clock
TDM3_TCLK
TDM3_RCLK
TDM3_ACLK
O
8mA
TDM3_ACLK: Third interface recovered clock.
TDM3 Transmit/Receive Sync Pulse
TDM3_TX_SYNC: First interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM3 Transmit Multiframe Sync Pulse/Carrier Detect
TDM3_TX_MF_CD: Third interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM3_TX_SYNC
TDM3_TX_MF_CD
Ipd
IOpd
Ipd
TDM3 Receive Multiframe Sync Pulse
TDM3_RX_SYNC: Third interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM3 Transmit Signaling/Clear to Send
TDM3_TSIG_CTS: Third interface transmit signaling, or Clear to Send in case of
serial interface.
TDM3_RX_SYNC
TDM3_TSIG_CTS
O
8mA
TDM3 Receive Signaling/Request To Send
TDM3_RSIG_RTS
TDM4_TX
Ipu
TDM3_RSIG_RTS: Third interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
TDM4 Transmit
O
8mA
TDM4_TX: Fourth Interface serial transmit line.
TDM4 Receive
TDM4_RX
Ipu
Ipu
Ipu
TDM4_RX: Fourth interface serial receive line. This pin is active in external mode
only.
TDM4Transmit Clock
TDM4_TCLK: Used for clocking TDM4_TX and TDM4_RX lines in one-clock
mode, or TDM4_TX in two-clock mode. This pin is active in external mode only.
TDM4 Receive Clock
TDM4_RCLK: Used for clocking TDM4_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM4_TCLK
TDM4_RCLK
37 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
O
8mA
TDM4 Recovery Clock
TDM4_ACLK: Fourth interface recovered clock.
TDM4_ACLK
TDM4 Transmit/Receive Sync Pulse
TDM4_TX_SYNC: Fourth interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM4 Transmit Multiframe Sync Pulse/Carrier Detect
TDM4_TX_MF_CD: Fourth interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM4_TX_SYNC
TDM4_TX_MF_CD
Ipd
IOpd
Ipd
TDM4 Receive Multiframe Sync Pulse
TDM4_RX_SYNC: Fourth interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM4 Transmit Signaling/Clear to Send
TDM4_TSIG_CTS_D2A4: Fourth interface transmit signaling, or Clear to Send in
case of serial interface.
TDM4_RX_SYNC
TDM4_TSIG_CTS
O
8mA
TDM4 Receive Signaling/Request To Send
TDM4_RSIG_RTS
TDM5_TX
Ipu
TDM4_RSIG_RTS: Fourth interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
TDM5 Transmit
O
8mA
TDM5_TX: Fifth Interface serial transmit line.
TDM5 Receive
TDM5_RX
Ipu
Ipu
Ipu
TDM5_RX: Fifth interface serial receive line. This pin is active in external mode
only.
TDM5Transmit Clock
TDM5_TCLK: Used for clocking TDM5_TX and TDM5_RX lines in one-clock
mode, or TDM5_TX in two-clock mode. This pin is active in external mode only.
TDM5 Receive Clock
TDM5_RCLK: Used for clocking TDM5_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM5 Recovery Clock
TDM5_TCLK
TDM5_RCLK
TDM5_ACLK
O
8mA
TDM5_ACLK: Fifth interface recovered clock.
TDM5 Transmit/Receive Sync Pulse
TDM5_TX_SYNC: Fifth interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM5 Transmit Multiframe Sync Pulse/Carrier Detect
TDM5_TX_MF_CD: Fifth interface transmit multiframe sync pulse input for
framed interface (PCM), or Carrier Detect output in case of serial interface. This
pin is active in external mode only.
TDM5_TX_SYNC
Ipd
TDM5_TX_MF_CD
TDM5_RX_SYNC
IOpd
Ipd
TDM5 Receive Multiframe Sync Pulse
TDM5_RX_SYNC: First interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM5 Transmit Signaling/Clear to Send
TDM5_TSIG_CTS: Fifth interface transmit signaling, or Clear to Send in case of
serial interface.
TDM5 Receive Signaling/Request To Send
TDM5_RSIG_RTS: Fifth interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
O
8mA
TDM5_TSIG_CTS
TDM5_RSIG_RTS
Ipu
38 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
O
8mA
TDM6 Transmit
TDM6_TX: Sixth Interface serial transmit line.
TDM6_TX
TDM6 Receive
TDM6_RX
Ipu
Ipu
Ipu
TDM6_RX: Sixth interface serial receive line. This pin is active in external mode
only.
TDM6Transmit Clock
TDM6_TCLK: Used for clocking TDM6_TX and TDM6_RX lines in one-clock
mode, or TDM6_TX in two-clock mode. This pin is active in external mode only.
TDM6 Receive Clock
TDM6_RCLK: Used for clocking TDM6_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM6 Recovery Clock
TDM6_TCLK
TDM6_RCLK
TDM6_ACLK
O
8mA
TDM6_ACLK: Sixth interface recovered clock.
TDM6 Transmit/Receive Sync Pulse
TDM6_TX_SYNC: Sixth interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM6 Transmit Multiframe Sync Pulse/Carrier Detect
TDM6_TX_MF_CD: Sixth interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM6_TX_SYNC
TDM6_TX_MF_CD
Ipd
IOpd
Ipd
TDM6 Receive Multiframe Sync Pulse
TDM6_RX_SYNC: Sixth interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM6 Transmit Signaling/Clear to Send
TDM6_TSIG_CTS: Sixth interface transmit signaling, or Clear to Send in case of
serial interface.
TDM6_RX_SYNC
TDM6_TSIG_CTS
O
8mA
TDM6 Receive Signaling/Request To Send
TDM6_RSIG_RTS
TDM7_TX
Ipu
TDM6_RSIG_RTS: Sixth interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
TDM7 Transmit
O
8mA
TDM7_TX: Seventh Interface serial transmit line.
TDM7 Receive
TDM7_RX
Ipu
Ipu
Ipu
TDM7_RX: Seventh interface serial receive line. This pin is active in external
mode only.
TDM7Transmit Clock
TDM7_TCLK: Used for clocking TDM7_TX and TDM7_RX lines in one-clock
mode, or TDM7_TX in two-clock mode. This pin is active in external mode only.
TDM7 Receive Clock
TDM7_RCLK: Used for clocking TDM7_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM7 Recovery Clock
TDM7_TCLK
TDM7_RCLK
TDM7_ACLK
O
8mA
TDM7_ACLK: Seventh interface recovered clock.
TDM7 Transmit/Receive Sync Pulse
TDM7_TX_SYNC: Seventh interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every
N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM7 Transmit Multiframe Sync Pulse/Carrier Detect
TDM7_TX_MF_CD: Fifth interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM7_TX_SYNC
TDM7_TX_MF_CD
Ipd
IOpd
39 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TDM7 Receive Multiframe Sync Pulse
TDM7_RX_SYNC: Seventh interface receive multiframe sync pulse or frame
sync pulse input. When used as frame sync pulse the pulse frequency can be
once every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM7 Transmit Signaling/Clear to Send
TDM7_TSIG_CTS: Seventh interface transmit signaling, or Clear to Send in case
of serial interface.
TDM7_RX_SYNC
Ipd
O
8mA
TDM7_TSIG_CTS
TDM7 Receive Signaling/Request To Send
TDM7_RSIG_RTS
TDM8_TX
Ipu
TDM7_RSIG_RTS: Seventh interface serial Rx signaling input or Request To
Send input in case of serial interface. This pin is active in external mode only.
TDM8 Transmit
O
8mA
TDM8_TX: Eighth interface serial transmit line.
TDM8 Receive
TDM8_RX
Ipu
Ipu
Ipu
TDM8_RX: Eighth interface serial receive line. This pin is active in external mode
only.
TDM8 Transmit Clock
TDM8_TCLK: Used for clocking TDM8_TX and TDM8_RX lines in one-clock
mode, or TDM8_TX in two-clock mode. This pin is active in external mode only.
TDM8 Receive Clock
TDM8_RCLK: Used for clocking TDM8_RX line in two-clock mode. Not used in
one-clock mode. This pin is active in external mode only.
TDM8 Recovery Clock
TDM8_TCLK
TDM8_RCLK
TDM8_ACLK
O
8mA
TDM8_ACLK: Eighth interface recovered clock.
TDM8 Transmit/Receive Sync Pulse
TDM8_TX_SYNC: Eighth interface transmit frame sync pulse. Used as both
transmit and receive frame sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125μs, i.e., every 2ms. This pin is active in external mode only.
TDM8 Transmit Multiframe Sync Pulse/Carrier Detect
TDM8_TX_MF_CD: Eighth interface transmit multiframe sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface. This
pin is active in external mode only.
TDM8_TX_SYNC
Ipd
TDM8_TX_MF_CD
TDM8_RX_SYNC
IOpd
Ipd
TDM8 Receive Multiframe Sync Pulse
TDM8_RX_SYNC: First interface receive multiframe sync pulse or frame sync
pulse input. When used as frame sync pulse the pulse frequency can be once
every N x 125μs, i.e., every 2ms. This pin is active in external mode only.
TDM8 Transmit Signaling/Clear to Send
TDM8_TSIG_CTS: Eighth interface transmit signaling, or Clear to Send in case
of serial interface. This pin is active in external mode only.
TDM8 Receive Signaling/Request To Send
O
8mA
TDM8_TSIG_CTS
TDM8_RSIG_RTS
Ipu
TDM8_RSIG_RTS: Eighth interface serial Rx signaling input or Request To Send
input in case of serial interface. This pin is active in external mode only.
MAC(10/100) PINS
Clock Media Independent Interface Receive
CLK_MII_RX: MII receive clock or SSMII receive clock.
Media Independent Interface Receive Data 0
MII_RXD[0]: MII receive data ‘0’ or SSMII receive data.
Media Independent Interface Receive Data 1
MII_RXD[1]: MII receive data ‘1’ or receive data SSMII sync.
Media Independent Interface Receive Data 2
MII_RXD[2]: MII receive data ‘2’ or RMII receive data ‘0.’
Media Independent Interface Receive Data 3
MII_RXD[3]: MII receive data ‘3’ or RMII receive data ‘1.’
CLK_MII_RX
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
I
I
I
I
I
40 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
Media Independent Interface Receive Data Valid
MII_RX_DV: MII receive data valid, or RMII carrier sense/data valid.
Media Independent Interface Receive Error
MII_RX_ERR: MII receive error, or RMII receive error.
Media Independent Interface Collision
MII_COL: MII collision detection.
Media Independent Interface carrier sense.
MII_CRS: MII carrier sense.
MII_RX_DV
I
MII_RX_ERR
MII_COL
I
I
I
MII_CRS
Clock Media Independent Interface Transmit
CLK_MII_TX: MII transmit clock or RMII ref clock or SSMII ref clock.
Clock Source Synchronous Serial Media Independent Interface Transmit
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
MII_TX_EN
MII_TX_ERR
MDIO
I
O
12mA CLK_SSMII_TX: SSMII transmit clock (125MHz).
O
8mA
O
8mA
O
8mA
O
8mA
O
8mA
O
Media Independent Interface Transmit Data 0
MII_TXD[0]: MII transmit data ‘0’, or SSMII transmit data.
Media Independent Interface Transmit Data 1
MII_TXD[1]: MII transmit data ‘0’, or SSMII transmit sync.
Media Independent Interface Transmit Data 2
MII_TXD[2]: MII transmit data ‘2’ or RMII transmit data ‘0.’
Media Independent Interface Transmit Data 3
MII_TXD[3]: MII transmit data ‘3’, or RMII transmit data ‘1.’
Media Independent Interface Transmit Enable
MII_TX_EN: MII transmit enable or RMII transmit enable.
Media Independent Interface Transmit Error
MII_TX_ERR: MII transmit error.
8mA
IOpu
8mA
O
Management Data Input/Output
MDIO: Management data, synchronized to MDC.
Management Data Clock
MDC: Management data clock.
MDC
8mA
FRAMER AND LIU PORT PINS
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
Transmit Bipolar Tip for Channels 1–8
TTIPn: These pins are differential line driver tip outputs. The differential outputs
of TTIPn and TRINGn can provide internal matched impedance for E1 75Ω, E1
120Ω, T1 100Ω, or J1 110Ω.
Oa
TTIP6
TTIP7
Note: All these pins can be tri-stated when the TXENABLE pin is low.
TTIP8
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
TRING8
Transmit Bipolar Ring for Channels 1–8
TRINGn: These pins are differential line driver ring outputs. The differential
outputs of TTIPn and TRINGn can provide internal matched impedance for E1
75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.
Oa
Note: All these pins can be tri-stated when the TXENABLE pin is low.
Transmit Enable for all Channels 1–8
TXENABLE: If this pin is pulled low all the transmitter outputs (TTIP and TRING)
are high impedance. In addition, the register settings for tri-state control of
TTIP/TRING are ignored if TXENABLE is low. If TXENABLE is high, the particular
driver can be tri-stated if the TXEN bit is set in the LMCR register.
TXENABLE
I
41 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
Receive Bipolar Tip for Channels 1–8
RTIPn: Receive analog input for differential receiver. Data and clock are
recovered and output at RPOS/RNEG and RCLK pins, respectively. The
differential inputs of RTIPn and RRINGn can provide internal matched impedance
for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.
Ia
RTIP6
RTIP7
RTIP8
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
RRING8
Receive Bipolar Ring for Channels 1–8
RRINGn: Receive analog input for differential receiver. Data and clock are
recovered and output at RPOS/RNEG and RCLK pins, respectively. The
differential inputs of RTIPn and RRINGn can provide internal matched impedance
for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.
Ia
Receive Termination Selection
RXTSEL: The input selects internal termination when high and external
termination when low for the all the receivers when the RHPM bit is set in the
LTRCR register.
RXTSEL
I
Receive Framer Clock
RCLKFn: When the LIUs are disabled (GCR2.LIUDn bits), RCLKFn can be
1.544MHz (T1) or 2.048MHz (E1) input clock that is used to clock data through
the receive-side framer. RSER data is output on the rising edge of RCLKFn.
RCLKFn is used to output RSER when the elastic store is not enabled. When the
elastic store is enabled, the RSER is clocked by RSYSCLK.
RCLKF1/RCLK1
RCLKF2/RCLK2
RCLKF3/RCLK3
RCLKF4/RCLK4
RCLKF5/RCLK5
RCLKF6/RCLK6
RCLKF7/RCLK7
RCLKF8/RCLK8
IO
8mA
Receive Clock Out
RCLKn: When the LIU is used RCLKn is the recovered output clock from the
line. This clock is recovered from the signal at RTIP and RRING. The output is
1.544MHz for T1 and 2.048MHz for E1. This clock is used to clock data through
the receive-side framer. RSER data is output on the rising edge of RCLKn.
RCLKn is used to output RSER when the elastic store is not enabled. When the
elastic store is enabled, the RSER is clocked by RSYSCLK.
TCLKF1
TCLKF2
TCLKF3
TCLKF4
TCLKF5
TCLKF6
TCLKF7
TCLKF8
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TCLKO5
TCLKO6
TCLKO7
TCLKO8
Transmit Clock Input for the Formatter
TCLKFn: A 1.544MHz or a 2.048MHz primary clock. Used to clock data through
the transmit-side formatter. This pin is active in external mode.
I
Transmit Clock Output
O
8mA
TCLKOn: This signal is used to register the TDATFn output and is typically
synchronous with the TCLKFn input. However, in framer and payload loopback
applications this signal becomes synchronous with RCLKFn.
42 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
RSER1
RSER2
RSER3
Receive Serial Data Output
RSERn: Received NRZ serial data. Updated on rising edges of RCLKFn when
the receive-side elastic store is disabled. Updated on the rising edges of
RSYSCLKn when the receive-side elastic store is enabled. This output is low
when in internal mode.
RSER4
RSER5
RSER6
RSER7
O
8mA
RSER8
TDATF1
TDATF2
TDATF3
TDATF4
TDATF5
TDATF6
TDATF7
TDATF8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RSYSCLK5
RSYSCLK6
RSYSCLK7
RSYSCLK8
Transmit Data Formatter Output
O
8mA
TDATFn: Can be programmed to source NRZ data via a configuration register.
This pin is low when the internal LIU is enabled. This is active when the internal
LIUn is disabled (GCR2.LIUD bit).
Receive Sync
RSYNCn: If the receive-side elastic store is enabled, then this signal is used to
input a frame or multiframe boundary pulse. If set to output frame boundaries
then RSYNC can be programmed to output double-wide pulses on signaling
frames in T1 mode. In E1 Mode RSYNC out can be used to indicate CAS and
CRC4 multiframe.
IO
8mA
Receive System Clock
RSYSCLKn: 1.544MHz, or 2.048MHz receive backplane clock. Only used when
the receive side elastic store function is enabled. Should be tied low in
applications that do not use the receive side elastic store. This pin is active in
external mode only.
I
Frame Synchronization
RFSYNCn: RFSYNC is an extracted 8kHz pulse, one RCLKF or RCLK wide that
identifies frame boundaries.
RF/RMSYNC1
RF/RMSYNC2
RF/RMSYNC3
RF/RMSYNC4
RF/RMSYNC5
RF/RMSYNC6
RF/RMSYNC7
RF/RMSYNC8
Receive Multiframe Synchronization
O
8mA
RMSYNCn: RMSYNC is an extracted pulse, one RCLKF or RCLK wide (elastic
store disabled) or one RSYSCLK wide (elastic store enabled), which identifies
multiframe boundaries. When the receive elastic store is enabled, the RMSYNC
signal indicates the multiframe sync on the system (backplane) side of the elastic
store. In E1 mode, will indicate either the CRC4 or CAS multiframe as determined
by a configuration register.
RLOF/RLOS1
RLOF/RLOS2
RLOF/RLOS3
RLOF/RLOS4
RLOF/RLOS5
RLOF/RLOS6
RLOF/RLOS7
RLOF/RLOS8
Receive Loss of Frame
RLOFn: This pin can toggle high when the synchronizer is searching for the
frame and multiframe.
O
8mA
Receive Loss of Signal
RLOSn: This pin can toggle high when the framer detects a loss of signal
condition.
43 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
TSER1
TSER2
TSER3
Transmit Serial Data
TSER4
TSER5
TSER6
TSERn: Sampled on the falling edge of TCLKF when the transmit side elastic
store is disabled. Sampled on the falling edge of TSYSCLK when the transmit
side elastic store is enabled. This pin is active in external mode only.
I
TSER7
TSER8
RDATF1
RDATF2
RDATF3
RDATF4
RDATF5
RDATF6
RDATF7
RDATF8
Receive Data Framer input
RDATFn: RDATFn can be used for unipolar (NRZ) data if enabled. This is active
when the internal LIUn is disabled (GCR2.LIUD bit).
I
Transmit Synchronization In/Out
TSYNCn: A pulse at this pin establishes either frame or multiframe boundaries
for the transmit side. This signal can additionally be programmed to output either
a frame or multiframe pulse. If this pin is set to output pulses at frame
boundaries, it can additionally be set to output doublewide pulses at signaling
frames in T1 mode. The operation of this signal is synchronous with TCLKF. Only
used when elastic store is disabled.
TSYNC/TSSYNC1
TSYNC/TSSYNC2
TSYNC/TSSYNC3
TSYNC/TSSYNC4
TSYNC/TSSYNC5
TSYNC/TSSYNC6
TSYNC/TSSYNC7
TSYNC/TSSYNC8
IO
8mA
Transmit System Synchronization In
TSSYNCn: Only used when the transmit-side elastic store is enabled. A pulse at
this pin will establish either frame or multiframe boundaries for the transmit side.
The operation of this signal is synchronous with TSYSCLK.
TSYSCLK/ECLK1
TSYSCLK/ECLK2
TSYSCLK/ECLK3
TSYSCLK/ECLK4
TSYSCLK/ECLK5
TSYSCLK/ECLK6
TSYSCLK/ECLK7
TSYSCLK/ECLK8
Transmit System Clock
TSYSCLKn: 1.544MHz or 2.048MHz clock. Only used when the transmit-side
elastic store function is enabled. This pin is active in external mode.
I
External Clock
ECLK: This pin is an external clock input for the receive and transmit. The pins is
configured by register FMRTOPISM.
CLOCK PINS
System Clock Select
CLK_SYS_S: This pin selects the input CLK_SYS frequency. The pin should be
tied high when a 25MHz CLK_SYS is used. The pin should be tied low or left
unconnected when a 50MHz or 75MHz CLK_SYS is used.
System Clock
CLK_SYS: Clock input used to drive the TDM-over-Packet internal circuitry.
Requires a 25MHz or 50MHz or 75MHz(+50ppm or better) clock on this pin. The
25MHz CLK_SYS is used to generate a 50MHz or 75MHz internal system clock
for the TDM-over-Packet and SD_CLK. The 50MHz or 75MHz CLK_SYS is used
for the SD_CLK output, and the internal system clock for the TDM-over-Packet
block.
CLK_SYS_S
CLK_SYS
Ipd
I
44 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
Clock High Synthesis
CLK_HIGH: 19.44MHz or 38.88MHz or 77.76MHz clock input is used for E1/T1
clock recovery machines of the TDM-over-Packet and the internal MCLK for the
LIU and Framer. The LIU and FRAMER use this clock as the internal MCLK
when programmed in default mode. A configuration register sets if the clock input
is going to be 10.00MHz or 19.44MHz or 38.88MHz or 77.76MHz. It is
recommend that this signal be tied to DVSS when none of the recovered clock
outputs (TDM1_ACLK–TDM8_ACLK) are used or when the chip is in single-port
high-speed mode.
CLK_HIGH
I
Accuracy is described in the Clock Recovery section (Section 7.7.4).
Master Clock
MCLK: This is an independent free-running clock whose input can be 2.048MHz
±50ppm or 1.544MHz ±32ppm. An external MCLK is used when not using the
TDM-over-Packet engine CLK_HIGH. The user must program this pin to be used
as the external MCLK source. When using this MCLK pin set MCLKE bit and set
MCLKS bit for correct operation as described in the GCR1 register.
Common Clock
MCLK
I
CLK_CMN: Common clock has to be a multiple of 8kHz and in the range of
1MHz to 25MHz. The frequency input should not be too close to an integer
multiple of the service clock frequency. Based on these criteria, the following
frequencies are suggested:
For systems with access to a common SONET/SDH network, a frequency of
19.44MHz (2430 x 8kHz).
CLK_CMN
I
For systems with access to a common ATM network, 9.72MHz (1215 x 8kHz) or
19.44MHz (2430 x 8kHz).
For systems using GPS, 8.184MHz (1023 x 8kHz).
For systems connected by a single hop of 100Mbps Ethernet where it is possible
to lock the physical layer clock, 25MHz (3125 x 8kHz).
When common clock is not used tie to ground or VDD(3.3V).
MICROPROCESSOR PINS
Host Data Bus
IO
H_D[31:1]
H_D[31:1]: Host data bus MSB is HD[31] when the host data bus width is 32 bits
and HD_D[15] when the host data bus width is 16 bits.
Host Data Bus
8mA
H_D[0]: In CPU mode (H_CPU_SPI_N = 1), this pin is used as H_D[0], which is
the LSB of the CPU data bus.
H_D[0]/
IO
SPI_MISO
8mA
SPI MISO
SPI_MISO[0]: In SPI mode (H_CPU_SPI = 0), this pin is used as SPI_MISO
output. If the SPI interface is not selected(SPI_SEL_N), this output is tri-state.
Host Address Bus
H_AD[24:1]
H_CS_N
I
I
H_AD[24:1]: Host address bus, MSB is H_AD[24]. When the host data bus is 32
bits, H_AD[1] should be tied to VSS.
Host Chip Select
H_CS_N: Host chip select active low.
Host Read/Write
H_R_W_N: In CPU mode (H_CPU_SPI_N = 1), this input is host read/write.
H_R_W_N/
SPI_CP
I
SPI Clock Phase
SPU_CP: In SPI mode (H_CPU_SPI_N = 0), this input is the SPI clock phase.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
H_D[7:0] Write Enable, Active Low
H_WR_BE0_N: In CPU mode (H_CPU_SPI_N = 1) this input is H_D[7:0] write
enable, active low.
H_WR_BE0_N/
SPI_CLK
I
SPI Clock
SPI_CLK: In SPI mode (H_CPU_SPI_N = 0), this input is SPI clock.
H_D[15:8] Write Enable, Active Low
H_WR_BE1_N: In CPU mode (H_CPU_SPI_N = 1), this input is H_D[15:8] write
enable, active low.
H_WR_BE1_N/
SPI_MOSI
I
I
I
SPI_MOSI
SPI_MOSI: In SPI mode (H_CPU_SPI_N = 0), this input is SPI_MOSI.
H_D[23:16] Write Enable, Active Low
H_WR_BE2_N: In CPU mode (H_CPU_SPI_N = 1), this input is H_D[23:16] write
enable, active low.
H_WR_BE2_N/
SPI_SEL_N
SPI Select
SPI_SEL_N: In SPI mode (H_CPU_SPI_N = 0), this input is SPI_SEL_N.
H_D[31:24] Write Enable, Active Low
H_WR_BE3_N: In CPU mode (H_CPU_SPI_N = 1), H_D[31:24] write enable,
active low.
H_WR_BE3_N/
SPI_CI
SPI Clock Invert
SPI_CI: In SPI mode (H_CPU_SPI_N = 0), this input is clock invert for SPI mode.
Host Ready
Opu
8mA
H_READY_N
H_INT[1:0]
H_READY_N: Host ready, active low. This pin requires the use of an external
pullup resistor. The signal is actively driven high ‘1’ before it becomes tri-state.
Host Interrupt
O
8mA
H_INT[1:0]: Host Interrupts are active low. H_INT[0] is used for the TDM-over-
Packet and H_INT[1] is used for the LIU, FRAMER and BERT. H_INT[0] can also
be ORed with H_INT[1]. See register bit GCR1.IPOR.
Data 32/16-Bit Select
DAT_32_16_N
H_CPU_SPI_N
Ipu
Ipu
DAT_32_16_N: Selects the host data bus width to be ‘16’ when low ‘0’ and ‘32’
when high ‘1’. This pin is ignored in SPI mode.
SPI Mode
H_CPU_SPI_N: ‘0’ – SPI mode, CPU bus is disabled, ‘1’ – Regular CPU bus
MISCELLANEOUS PINS
System Reset
RST_SYS_N: System reset, active low.
JTAG Test Mode Select
JTMS: This pin is sampled on the rising edge of JTCLK and is used to place the
test access port into the various defined IEEE 1149.1 states. This pin has a 10kΩ
pullup resistor.
RST_SYS_N
JTMS
Ipu
Ipu
JTAG Test Clock
JTCLK
JTDI
I
JTCLK: This signal is used to shift data into JTDI on the rising edge and out of
JTDO on the falling edge.
JTAG Test Data In
JTDI: Test instructions and data are clocked into this pin on the rising edge of
JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Test Data Out
JTDO: Test instructions and data are clocked out of this pin on the falling edge of
JTCLK. If not used, this pin should be left unconnected.
Ipu
Oz
8mA
JTDO
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
JTAG Test Reset
JTRST: JTRST is used to asynchronously reset the test access port controller.
After power-up, JTRST must be toggled from low to high. This action sets the
device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal
device operation. JTRST is pulled HIGH internally via a 10kΩ resistor operation.
If boundary scan is not used, this pin should be held low.
Resistor Reference
JTRST
Ipu
RESREF: Requires a 10kΩ precision resistor (1% or better) to ground. This is
used to calibrate the termination resistors internal to the part and the transmit
impedance.
RESREF
I
TEST PINS
Scan Enable
SCEN
STMD
Ipd
Ipd
SCEN: Used during factory test. This pin should be a “No Connect.”
Scan Test Mode
STMD: Used during factory test. This pin should be a “No Connect.”
High-Impedance Test Enable (Active Low)
HIZ_N: This signal is used to enable testing. When this signal is low while JTRST
is low, all the digital output and bidirectional pins are placed in the high-
impedance state. For normal operation this signal is high. This is an
asynchronous input.
HIZ_N
I
MBIST_EN
MBIST_DONE
MBIST_FAIL
I
Used during factory test. Tie to DVSS.
O
O
Used during factory test. This pin should be a “No Connect.”
Used during factory test. This pin should be a “No Connect.”
Test Clock
TEST_CLK
TST_CLD
TST_TA
TST_TB
TST_TC
TST_RA
TST_RB
TST_RC
O
I
TEST_CLK: Used during factory test. This pin should be a “No Connect.”
Test CLAD
TST_CLD: Used during factory test. Tie to DVSS.
Test Transmit Probe A
TST_TA: Used during factory test. This pin should be a “No Connect.”
Test Transmit Probe B
TST_TB: Used during factory test. This pin should be a “No Connect.”
Test Transmit Probe C
TST_TC: Used during factory test. This pin should be a “No Connect.”
Test Receiver Probe A
TST_RA: Used during factory test. This pin should be a “No Connect.”
Test Receiver Probe A
TST_RA: Used during factory test. This pin should be a “No Connect.”
Test Receiver Probe A
TST_RA: Used during factory test. This pin should be a “No Connect.”
O
O
O
O
O
O
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
NAME
TYPE
FUNCTION
POWER PINS
DVSS
—
—
—
—
—
Digital Ground for Framers and TDM-over-Packet (31 pins)
1.8V Core Supply Voltage for Framers and TDM-over-Packet (17 pins)
3.3V Supply Voltage for IO (16 pins)
DVDDC
DVDDIO
DVSSLIU
DVDDLIU
Digital Ground for LIUs (2 pins)
3.3V Digital Supply for LIUs (2 pins)
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
ATVDD7
ATVDD8
ATVSS1
ATVSS2
ATVSS3
ATVSS4
ATVSS5
ATVSS6
ATVSS7
ATVSS8
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
ACVDD2
—
—
-
3.3V Power Supply for the Transmitter. All ATVDD pins need to be 3.3V.
Analog Ground for Transmitters
3.3V Analog Receive Power Supply
—
Analog Receive Ground
—
—
—
—
1.8V Analog CLAD Power Supply 2 Used for CLK_HIGH Adaption
1.8V Analog CLAD Power Supply 1
ACVDD1
ACVSS2
ACVSS1
Analog CLAD GND2 Used for CLK_HIGH Adaption
Analog CLAD GND1
Note: Pins with names ending in an asterisk (*) or “_N” are active low.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
11. JTAG Information
For the latest JTAG model search under www.maxim-ic.com/tools/bsdl/.
11.1 JTAG Description
The DS34T108 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP and IDCODE. See Figure 11-1 for a JTAG block diagram. The
DS34T108 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test Access
Port and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on
these pins can be found in Section 10.2. Details on the Boundary Scan Architecture and the Test Access Port can
be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 11-1. JTAG Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
MUX
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
SELECT
OUTPUT ENABLE
Vdd
Vdd
Vdd
10K
10K
10K
JTDI
JTMS
JTCLK
JTRST
JTDO
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
11.2 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See
Figure 11-2 for details on each of the states described below. The TAP controller is a finite state machine that
responds to the logic level at JTMS on the rising edge of JTCLK.
Figure 11-2. JTAG TAP Controller State Machine
Test-Logic-Reset
1
0
1
1
Select
Select
1
Run-Test/Idle
DR-Scan
IR-Scan
0
0
0
1
1
Capture-DR
0
Capture-IR
0
Shift-DR
1
Shift-IR
1
0
1
0
1
Exit1- DR
0
Exit1-IR
0
Pause-DR
1
Pause-IR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1 0
1
0
Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The Instruction
Register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register
and Test Register remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or
it to the Exit1-DR state if JTMS is high.
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the
shift register. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high,
the controller enters the Select-DR-Scan state.
Select-IR-Scan. All Test registers retain their previous state. The Instruction register remains unchanged during
this state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a
scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the controller back into
the Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the shift register in the Instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register as well as all test
registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-
IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state while moving data one
stage through the Instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the Instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high put the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the Instruction shift register is latched into the parallel output on the falling
edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller
enters the Select-DR-Scan state.
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11.3 JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output, and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to
the Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS34T108 and their respective operational binary codes
are shown in Table 11-1.
Table 11-1. JTAG Instruction Codes
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
BYPASS
Boundary Scan
Bypass
Boundary Scan
Bypass
010
111
000
011
100
001
EXTEST
CLAMP
HIGHZ
IDCODE
Bypass
Device Identification
Table 11-2. JTAG ID Code
ID CODE (hex)
Device ID[27:12]
0093
DEVICE
Rev[31:28]
Manu[11:0]
143
DS34T108
DS34T104
DS34T102
DS34T101
DS34S108
DS34S104
DS34S102
DS34S101
0
0
0
0
0
0
0
0
0092
0091
0090
009B
009A
0099
0098
143
143
143
143
143
143
143
11.3.1 SAMPLE/PRELOAD
SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS34T108 to
shift data into the boundary scan register via JTDI using the Shift-DR state.
11.3.2 EXTEST
EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all
digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR
samples all digital inputs into the boundary scan register.
11.3.3 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
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11.3.4 IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test register is
selected. The device identification code is loaded into the Identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
device ID code always has a one in the LSB position. The device ID codes are listed in Table 11-2.
11.3.5 HIGHZ
All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI and
JTDO.
11.3.6 CLAMP
All digital outputs pins output data from the boundary scan parallel output while connecting the bypass register
between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
11.4 JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included in the device design. This test register is the identification register and is
used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
11.4.1 Bypass Register
The bypass register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, providing a short path between JTDI and JTDO.
11.4.2 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
11.4.3 Boundary Scan Register
The boundary scan register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells, and is 32 bits in length. The BSDL file found at www.maxim-ic.com/tools/bsdl shows the entire
cell bit locations and definitions.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
12. DC Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input, Bidirectional or Open Drain
Output Lead with Respect to DVSS………………………………………………………………………..-0.5V to +5.5V
Supply Voltage Range (VDDIO, DVDDLIU) with Respect to DVSS and DVSSLIU……………………...-0.5V to +3.6V
Supply Voltage Range (DVDDC) with Respect to DVSS…………………………………………………...-0.5V to +2.0V
Ambient Operating Temperature Range……………………………………………………………………..-40°C to +85°C
Junction Operating Temperature Range……………………………………………………………………-40°C to +125°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Soldering Temperature………………………………………………………….See IPC/JEDEC J-STD-020 specification.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect reliability. Ambient
Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection cooled JEDEC test
enclosure.
Note: The typical values listed are not production tested.
Table 12-1. Recommended DC Operating Conditions
(Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Logic 1
VIH
VIL
2.4
-0.3
3.465
+0.8
V
V
Output Logic 0
Supply ±5%
Supply ±5%
DVDDIO,
DVDDLIU,
ARVDDn,
ATVDDn
DVDDC
3.135
1.71
3.300
1.8
3.465
1.89
V
V
Table 12-2. DC Electrical Characteristics
(Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
DS34T108
DS34T104
DS34T102
DS34T101
MIN
TYP
400
200
120
75
MAX
550
300
175
115
UNITS
3.3V Supply Current
(DVDDIO, DVDDLIU = 3.465V;
ARVDDn, ATVDDn = 3.465V)
(Note 1)
IDDIO
mA
1.8V Supply Current
(DVDDC = 1.89V)
Lead Capacitance
Input Leakage
IDDC
(Note 1)
300
7
350
mA
CIO
IIL
IILP
pF
μA
μA
-10
-100
+10
-10
Input Leakage
Output Leakage (when High
Impedance)
ILO
-10
2.4
+10
μA
Output Voltage (IOH = -4.0mA)
Output Voltage (IOL = +4.0mA)
Output Voltage (IOH = -8.0mA)
Output Voltage (IOL = -8.0mA)
Output Voltage (IOL = +12.0mA)
Output Voltage (IOH = -12.0mA)
Input Voltage Logic 0
Input Voltage Logic 1
VOH
VOL
VOH
VOL
VOL
VOH
VIL
4mA output
4mA output
8mA output
8mA output
12mA output
12mA output
V
V
V
V
V
V
V
V
0.4
2.4
0.4
0.4
2.4
2.0
0.8
VIH
Note 1:
All outputs loaded with rated capacitance; all inputs between DVDDIO and DVSS; inputs with pull-ups connected to DVDDIO.
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13. AC Timing Characteristics
Refer to the full data sheet for this information.
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_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
14. Pin Assignments
14.1 Board Design for the DS34T108 Family of Products
All devices in the DS34T108 family require the same footprint on the board. It is recommended that users design
their board in such a way that it supports the stuffing of higher port-count devices into a lower port-count socket. If
lower port-count designs are to be potentially stuffed with higher port-count devices, consideration must be taken
during board design to bias the unused inputs, input/outputs, and outputs appropriately. Generally, unused inputs
are tied directly to the ground plane, unused outputs are not connected, and unused input/outputs are tied to
ground through a 10kΩ resistor. Unused inputs with internal pullups or pulldowns are not connected. Table 14-1
designates how each ball on the package should be connected to implement a common board design. Shading
indicates balls for the unused inputs, input/outputs, and outputs of higher port-count devices.
When a user does stuff a socket with a higher port-count device, he/she needs a slightly modified BSDL file,
available from the factory upon request.
The user may decide to not implement a common board design. In that event, the balls for the unused inputs,
input/outputs, and outputs need not be connected, and the stuffing of higher port-count devices into a lower port-
count socket is not recommended.
Table 14-1. Common Board Design Connections
BALL
M2
DS34T108 SOCKET
ACVDD1
ACVDD2
ACVSS1
ACVSS2
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
DS34T104 SOCKET
ACVDD1
ACVDD2
ACVSS1
ACVSS2
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
DS34T102 SOCKET
ACVDD1
ACVDD2
ACVSS1
ACVSS2
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
DS34T101 SOCKET
ACVDD1
ACVDD2
ACVSS1
ACVSS2
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
K2
M1
K1
B14
B10
B2
F2
U2
AA2
AA11
AA13
A14
A10
B1
F1
U1
AA1
AB11
AB13
B16
B8
D1
H2
R2
W1
56 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
AA9
AA15
A16
A8
DS34T108 SOCKET
ATVDD7
ATVDD8
ATVSS1
DS34T104 SOCKET
ATVDD7
ATVDD8
ATVSS1
DS34T102 SOCKET
ATVDD7
ATVDD8
ATVSS1
DS34T101 SOCKET
ATVDD7
ATVDD8
ATVSS1
ATVSS2
ATVSS2
ATVSS2
ATVSS2
D2
ATVSS3
ATVSS3
ATVSS3
ATVSS3
H1
ATVSS4
ATVSS4
ATVSS4
ATVSS4
R1
ATVSS5
ATVSS5
ATVSS5
ATVSS5
W2
AB9
AB15
P1
ATVSS6
ATVSS6
ATVSS6
ATVSS6
ATVSS7
ATVSS7
ATVSS7
ATVSS7
ATVSS8
ATVSS8
ATVSS8
ATVSS8
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
CLK_CMN
CLK_HIGH
CLK_MII_RX
CLK_MII_TX
CLK_SSMII_TX
CLK_SYS/SCCLK
CLK_SYS_S
DAT_32_16_N
DVDDC
L1
V16
AA18
Y19
J1
J2
L21
L2
T5
DVDDC
DVDDC
DVDDC
DVDDC
V5
DVDDC
DVDDC
DVDDC
DVDDC
Y20
Y10
T18
G18
V18
V20
A12
E18
E20
C20
B11
G5
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
DVDDC
E5
DVDDC
DVDDC
DVDDC
DVDDC
C4
DVDDC
DVDDC
DVDDC
DVDDC
M9
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDIO
N9
P10
P13
N14
P12
M14
L14
P11
K14
J12
J13
57 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
J11
J10
L9
DS34T108 SOCKET
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDLIU
DVDDLIU
DVSS
DS34T104 SOCKET
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDLIU
DVDDLIU
DVSS
DS34T102 SOCKET
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDLIU
DVDDLIU
DVSS
DS34T101 SOCKET
DVDDIO
DVDDIO
DVDDIO
DVDDIO
DVDDLIU
DVDDLIU
DVSS
K9
C3
V3
M10
L13
H15
U17
L11
M11
K12
K11
K10
M12
N11
D4
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
H8
DVSS
DVSS
DVSS
DVSS
K13
M13
B12
N2
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
F6
DVSS
DVSS
DVSS
DVSS
L10
U6
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
W4
DVSS
DVSS
DVSS
DVSS
R8
DVSS
DVSS
DVSS
DVSS
N12
F17
L12
N10
R15
W19
N13
Y12
D19
Y3
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSSLIU
DVSSLIU
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
DVSSLIU
DVSSLIU
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
DVSSLIU
DVSSLIU
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
DVSSLIU
DVSSLIU
H_AD[1]
H_AD[10]
H_AD[11]
H_AD[12]
H_AD[13]
H_AD[14]
H_AD[15]
H_AD[16]
E3
L18
N22
L15
P21
N16
N20
P22
N19
58 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
R21
M19
N21
M21
M17
P20
R22
N17
T21
K16
M22
T20
M18
M16
M20
L16
DS34T108 SOCKET
H_AD[17]
H_AD[18]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
DS34T104 SOCKET
H_AD[17]
H_AD[18]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
DS34T102 SOCKET
H_AD[17]
H_AD[18]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
DS34T101 SOCKET
H_AD[17]
H_AD[18]
H_AD[19]
H_AD[2]
H_AD[20]
H_AD[21]
H_AD[22]
H_AD[23]
H_AD[24]
H_AD[3]
H_AD[4]
H_AD[5]
H_AD[6]
H_AD[7]
H_AD[8]
H_AD[9]
H_CPU_SPI_N
H_CS_N
H_D[0]/SPI_MISO
H_D[1]
K19
L17
T22
U21
V22
P18
W22
Y21
P19
Y22
AA21
AA22
AB21
U20
N18
R19
AB22
P17
V21
R17
V19
T19
W21
U16
R18
R20
W20
U19
T17
P16
U18
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[10]
H_D[11]
H_D[12]
H_D[13]
H_D[14]
H_D[15]
H_D[16]
H_D[17]
H_D[18]
H_D[19]
H_D[2]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[20]
H_D[21]
H_D[22]
H_D[23]
H_D[24]
H_D[25]
H_D[26]
H_D[27]
H_D[28]
H_D[29]
H_D[3]
H_D[30]
H_D[31]
H_D[4]
H_D[30]
H_D[31]
H_D[4]
H_D[30]
H_D[31]
H_D[4]
H_D[30]
H_D[31]
H_D[4]
H_D[5]
H_D[5]
H_D[5]
H_D[5]
H_D[6]
H_D[6]
H_D[6]
H_D[6]
59 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
R16
U22
T16
J17
L22
K17
K18
L19
J16
J18
DS34T108 SOCKET
H_D[7]
DS34T104 SOCKET
H_D[7]
DS34T102 SOCKET
H_D[7]
DS34T101 SOCKET
H_D[7]
H_D[8]
H_D[8]
H_D[8]
H_D[8]
H_D[9]
H_D[9]
H_D[9]
H_D[9]
H_INT[0]
H_INT[0]
H_INT[0]
H_INT[0]
H_INT[1]
H_INT[1]
H_INT[1]
H_INT[1]
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_R_W_N/SPI_CP
H_READY_N
H_WR_BE0_N/SPI_CLK
H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI
H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N
L20
T3
H_WR_BE3_N/SPI_CI
HiZ_N
H_WR_BE3_N/SPI_CI
HiZ_N
H_WR_BE3_N/SPI_CI
HiZ_N
H_WR_BE3_N/SPI_CI
HiZ_N
L3
JTCLK
JTCLK
JTCLK
JTCLK
M3
JTDI
JTDI
JTDI
JTDI
N3
JTDO
JTDO
JTDO
JTDO
K3
JTMS
JTMS
JTMS
JTMS
P3
JTRST_N
JTRST_N
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MCLK
JTRST_N
MBIST_DONE
MBIST_EN
MBIST_FAIL
MCLK
M15
P15
N15
N1
MBIST_DONE
MBIST_EN
MBIST_FAIL
MCLK
MBIST_DONE
MBIST_EN
MBIST_FAIL
MCLK
AB17
AA20
AA17
Y18
Y17
V17
AA16
W16
AB16
Y16
W17
AB20
AB18
W18
AA19
AB19
C10
L4
MDC
MDC
MDC
MDC
MDIO
MDIO
MDIO
MDIO
MII_COL
MII_COL
MII_COL
MII_COL
MII_CRS
MII_CRS
MII_CRS
MII_CRS
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
N.C.
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
N.C.
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
N.C.
MII_RX_DV
MII_RX_ERR
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
MII_TX_EN
MII_TX_ERR
MII_TXD[0]
MII_TXD[1]
MII_TXD[2]
MII_TXD[3]
N.C.
RCLKF1/RCLK1
RCLKF2/RCLK2
RCLKF3/RCLK3
RCLKF4/RCLK4
RCLKF5/RCLK5
RCLKF6/RCLK6
RCLKF7/RCLK7
RCLKF8/RCLK8
RCLKF1/RCLK1
RCLKF2/RCLK2
RCLKF3/RCLK3
RCLKF4/RCLK4
10K to GND
10K to GND
10K to GND
10K to GND
RCLKF1/RCLK1
RCLKF2/RCLK2
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
RCLKF1/RCLK1
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
C9
K5
D7
P6
Y6
P5
AB3
60 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
A6
DS34T108 SOCKET
RDATF1
DS34T104 SOCKET
RDATF1
RDATF2
RDATF3
RDATF4
GND
DS34T102 SOCKET
RDATF1
RDATF2
GND
DS34T101 SOCKET
RDATF1
GND
L7
RDATF2
C5
RDATF3
GND
F4
RDATF4
GND
GND
P4
RDATF5
GND
GND
Y4
RDATF6
GND
GND
GND
AA5
AA3
A11
K8
RDATF7
GND
GND
GND
RDATF8
GND
GND
GND
RESREF
RESREF
RF/RMSYNC1
RF/RMSYNC2
RF/RMSYNC3
RF/RMSYNC4
N.C.
RESREF
RF/RMSYNC1
RF/RMSYNC2
N.C.
RESREF
RF/RMSYNC1
N.C.
RF/RMSYNC1
RF/RMSYNC2
RF/RMSYNC3
RF/RMSYNC4
RF/RMSYNC5
RF/RMSYNC6
RF/RMSYNC7
RF/RMSYNC8
RLOF/RLOS1
RLOF/RLOS2
RLOF/RLOS3
RLOF/RLOS4
RLOF/RLOS5
RLOF/RLOS6
RLOF/RLOS7
RLOF/RLOS8
RRING1
E7
G4
E4
N.C.
N.C.
N.C.
M6
W8
T4
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AB5
M8
A4
N.C.
N.C.
N.C.
RLOF/RLOS1
RLOF/RLOS2
RLOF/RLOS3
RLOF/RLOS4
N.C.
RLOF/RLOS1
RLOF/RLOS2
N.C.
RLOF/RLOS1
N.C.
N.C.
H4
N.C.
N.C.
D5
N.C.
N.C.
U4
N.C.
N.C.
N.C.
U3
N.C.
N.C.
N.C.
N7
N.C.
N.C.
N.C.
V7
B13
B9
RRING1
RRING2
RRING3
RRING4
N.C.
RRING1
RRING2
N.C.
RRING1
N.C.
RRING2
N.C.
A2
RRING3
N.C.
N.C.
E2
RRING4
N.C.
N.C.
V2
RRING5
N.C.
N.C.
N.C.
AB2
AA10
AA12
J5
RRING6
N.C.
N.C.
N.C.
RRING7
N.C.
N.C.
N.C.
RRING8
RSER1
RSER1
RSER2
RSER3
RSER4
N.C.
RSER1
RSER2
N.C.
RSER1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D6
RSER2
H7
RSER3
N.C.
D3
RSER4
N.C.
N6
RSER5
N.C.
N.C.
W6
T8
RSER6
N.C.
N.C.
RSER7
N.C.
N.C.
AB4
P2
RSER8
RST_SYS_N
RSYNC1
RST_SYS_N
RSYNC1
RST_SYS_N
RSYNC1
RST_SYS_N
RSYNC1
A5
L6
RSYNC2
RSYNC2
RSYNC2
10K to GND
10K to GND
A3
RSYNC3
RSYNC3
10K to GND
61 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
H6
DS34T108 SOCKET
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RSYSCLK5
RSYSCLK6
RSYSCLK7
RSYSCLK8
RTIP1
DS34T104 SOCKET
RSYNC4
10K to GND
10K to GND
10K to GND
10K to GND
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
GND
DS34T102 SOCKET
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
RSYSCLK1
RSYSCLK2
GND
DS34T101 SOCKET
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
RSYSCLK1
GND
W3
R4
AA6
M5
C6
K7
F8
GND
H5
GND
GND
W5
GND
GND
U5
GND
GND
GND
Y8
GND
GND
GND
N8
GND
GND
GND
A13
A9
RTIP1
RTIP1
RTIP1
RTIP2
RTIP2
RTIP2
N.C.
N.C.
N.C.
A1
RTIP3
RTIP3
N.C.
N.C.
E1
RTIP4
RTIP4
N.C.
N.C.
N.C.
V1
RTIP5
N.C.
N.C.
N.C.
AB1
AB10
AB12
R3
RTIP6
N.C.
N.C.
N.C.
RTIP7
N.C.
N.C.
N.C.
RTIP8
RXTSEL
SCEN
RXTSEL
SCEN
RXTSEL
SCEN
RXTSEL
SCEN
J15
A17
F18
B19
D17
F16
B18
E17
A19
H17
F19
F20
D18
G17
C19
E16
H16
B17
C18
F21
B22
H20
C21
H18
SD_A[0]
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[13]
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[13]
SD_A[0]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[13]
SD_A[1]
SD_A[10]
SD_A[11]
SD_A[2]
SD_A[3]
SD_A[4]
SD_A[5]
SD_A[6]
SD_A[7]
SD_A[8]
SD_A[9]
SD_BA[0]
SD_BA[1]
SD_CAS_N
SD_CLK
SD_CS_N
SD_D[0]
SD_D[1]
SD_D[10]
SD_D[11]
SD_D[12]
SD_D[13]
62 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
C22
D21
G20
D22
J20
G21
G19
J21
E22
J19
H21
F22
K21
G22
K20
H22
G16
A21
K22
J22
C16
A22
A18
B21
E21
H19
A20
E19
B20
D20
D16
C17
K15
B6
DS34T108 SOCKET
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
DS34T104 SOCKET
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
DS34T102 SOCKET
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
DS34T101 SOCKET
SD_D[14]
SD_D[15]
SD_D[16]
SD_D[17]
SD_D[18]
SD_D[19]
SD_D[2]
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
SD_D[20]
SD_D[21]
SD_D[22]
SD_D[23]
SD_D[24]
SD_D[25]
SD_D[26]
SD_D[27]
SD_D[28]
SD_D[29]
SD_D[3]
SD_D[30]
SD_D[31]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_D[8]
SD_D[9]
SD_DQM[0]
SD_DQM[1]
SD_DQM[2]
SD_DQM[3]
SD_RAS_N
SD_WE_N
STMD
TCLKF1
TCLKF1
TCLKF1
TCLKF2
GND
TCLKF1
GND
K4
TCLKF2
TCLKF2
D8
TCLKF3
TCLKF3
GND
J6
TCLKF4
TCLKF4
GND
GND
T6
TCLKF5
GND
GND
GND
T7
TCLKF6
GND
GND
GND
U8
TCLKF7
GND
GND
GND
M4
TCLKF8
GND
GND
GND
L8
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TCLKO5
TCLKO1
TCLKO2
TCLKO3
TCLKO4
N.C.
TCLKO1
TCLKO2
N.C.
TCLKO1
N.C.
B5
N.C.
J7
N.C.
N.C.
E6
N.C.
N.C.
N4
63 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
U7
DS34T108 SOCKET
TCLKO6
DS34T104 SOCKET
DS34T102 SOCKET
DS34T101 SOCKET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
P7
TCLKO7
AA7
C7
TCLKO8
TDATF1
TDATF1
TDATF2
TDATF3
TDATF4
N.C.
TDATF1
TDATF2
N.C.
TDATF1
N.C.
J8
TDATF2
N.C.
B4
TDATF3
N.C.
N.C.
K6
TDATF4
N.C.
N.C.
R6
TDATF5
N.C.
N.C.
N.C.
N5
TDATF6
N.C.
N.C.
N.C.
Y7
TDATF7
N.C.
N.C.
N.C.
P8
TDATF8
E10
D12
C11
D10
D11
F12
E11
C12
F13
E13
E9
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_ACLK
TDM1_RCLK
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM2_ACLK
TDM2_RCLK
TDM2_RSIG_RTS
TDM2_RX
TDM2_RX_SYNC
TDM2_TCLK
TDM2_TSIG_CTS
TDM2_TX
TDM2_TX_MF_CD
TDM2_TX_SYNC
N.C.
TDM1_ACLK
TDM1_RCLK
TDM1_RSIG_RTS
TDM1_RX
TDM1_RSIG_RTS
TDM1_RX
TDM1_RX_SYNC
TDM1_TCLK
TDM1_TSIG_CTS
TDM1_TX
TDM1_RX_SYNC
TDM1_TCLK
TDM1_RX_SYNC
TDM1_TCLK
TDM1_TSIG_CTS
TDM1_TX
TDM1_TSIG_CTS
TDM1_TX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM2_ACLK
TDM2_RCLK
TDM2_RSIG_RTS
TDM2_RX
TDM1_TX_MF_CD
TDM1_TX_SYNC
TDM2_ACLK
TDM1_TX_MF_CD
TDM1_TX_SYNC
N.C.
N.C.
E12
C14
D13
C13
G10
F11
G11
F10
E14
G14
C15
G13
D15
D14
G9
TDM2_RCLK
N.C.
TDM2_RSIG_RTS
TDM2_RX
N.C.
N.C.
TDM2_RX_SYNC
TDM2_TCLK
TDM2_TSIG_CTS
TDM2_TX
TDM2_RX_SYNC
TDM2_TCLK
N.C.
N.C.
TDM2_TSIG_CTS
TDM2_TX
N.C.
N.C.
TDM2_TX_MF_CD
TDM2_TX_SYNC
TDM3_ACLK
TDM3_RCLK
TDM3_RSIG_RTS
TDM3_RX
TDM2_TX_MF_CD
TDM2_TX_SYNC
TDM3_ACLK
N.C.
N.C.
N.C.
N.C.
TDM3_RCLK
N.C.
N.C.
TDM3_RSIG_RTS
TDM3_RX
N.C.
N.C.
N.C.
N.C.
TDM3_RX_SYNC
TDM3_TCLK
TDM3_TSIG_CTS
TDM3_TX
TDM3_RX_SYNC
TDM3_TCLK
N.C.
N.C.
N.C.
N.C.
G12
E15
F9
TDM3_TSIG_CTS
TDM3_TX
N.C.
N.C.
N.C.
N.C.
TDM3_TX_MF_CD
TDM3_TX_SYNC
TDM4_ACLK
TDM4_RCLK
TDM4_RSIG_RTS
TDM4_RX
TDM3_TX_MF_CD
TDM3_TX_SYNC
TDM4_ACLK
N.C.
N.C.
F14
H12
J14
F15
H9
N.C.
N.C.
N.C.
N.C.
TDM4_RCLK
N.C.
N.C.
TDM4_RSIG_RTS
TDM4_RX
N.C.
N.C.
64 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
H14
H11
G15
J9
DS34T108 SOCKET
TDM4_RX_SYNC
TDM4_TCLK
DS34T104 SOCKET
DS34T102 SOCKET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS34T101 SOCKET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TDM4_RX_SYNC
TDM4_TCLK
TDM4_TSIG_CTS
TDM4_TX
TDM4_TSIG_CTS
TDM4_TX
TDM4_TX_MF_CD
TDM4_TX_SYNC
N.C.
H13
H10
V11
V9
TDM4_TX_MF_CD
TDM4_TX_SYNC
TDM5_ACLK
N.C.
TDM5_RCLK
N.C.
T9
TDM5_RSIG_RTS
TDM5_RX
N.C.
R11
U14
T13
P14
R12
R10
R14
W14
T12
R9
N.C.
TDM5_RX_SYNC
TDM5_TCLK
N.C.
N.C.
TDM5_TSIG_CTS
TDM5_TX
N.C.
N.C.
TDM5_TX_MF_CD
TDM5_TX_SYNC
TDM6_ACLK
N.C.
N.C.
N.C.
TDM6_RCLK
N.C.
TDM6_RSIG_RTS
TDM6_RX
N.C.
V12
T15
V15
V13
W15
U15
T10
V14
U13
T14
U12
R13
Y11
W9
N.C.
TDM6_RX_SYNC
TDM6_TCLK
N.C.
N.C.
TDM6_TSIG_CTS
TDM6_TX
N.C.
N.C.
TDM6_TX_MF_CD
TDM6_TX_SYNC
TDM7_ACLK
N.C.
N.C.
N.C.
TDM7_RCLK
N.C.
TDM7_RSIG_RTS
TDM7_RX
N.C.
N.C.
TDM7_RX_SYNC
TDM7_TCLK
N.C.
N.C.
TDM7_TSIG_CTS
TDM7_TX
N.C.
W12
Y15
U11
Y13
U9
N.C.
TDM7_TX_MF_CD
TDM7_TX_SYNC
TDM8_ACLK
N.C.
N.C.
N.C.
TDM8_RCLK
N.C.
Y9
TDM8_RSIG_RTS
TDM8_RX
N.C.
V10
T11
Y14
W11
W10
W13
N.C.
TDM8_RX_SYNC
TDM8_TCLK
N.C.
N.C.
TDM8_TSIG_CTS
TDM8_TX
N.C.
N.C.
TDM8_TX_MF_CD
65 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
BALL
U10
J3
DS34T108 SOCKET
TDM8_TX_SYNC
TEST_CLK
TRING1
DS34T104 SOCKET
DS34T102 SOCKET
DS34T101 SOCKET
N.C.
N.C.
N.C.
TEST_CLK
TRING1
TRING2
TRING3
TRING4
N.C.
TEST_CLK
TRING1
TRING2
N.C.
TEST_CLK
TRING1
N.C.
B15
B7
TRING2
N.C.
C2
TRING3
N.C.
N.C.
G2
T2
TRING4
N.C.
N.C.
TRING5
N.C.
N.C.
N.C.
Y2
TRING6
N.C.
N.C.
N.C.
AA8
AA14
D9
TRING7
N.C.
N.C.
N.C.
TRING8
TSER1
TSER1
TSER2
TSER1
TSER2
TSER1
GND
J4
TSER2
B3
TSER3
TSER3
GND
GND
F3
TSER4
TSER4
GND
GND
V6
TSER5
GND
GND
GND
R7
TSER6
GND
GND
GND
V8
TSER7
GND
GND
GND
P9
TSER8
GND
GND
GND
G3
L5
TST_CLD
TST_CLD
TSYNC/TSSYNC1
TSYNC/TSSYNC2
TSYNC/TSSYNC3
TSYNC/TSSYNC4
10K to GND
10K to GND
10K to GND
10K to GND
TSYSCLK1/ECLK1
TSYSCLK2/ECLK2
TSYSCLK3/ECLK3
TSYSCLK4/ECLK4
GND
TST_CLD
TSYNC/TSSYNC1
TSYNC/TSSYNC2
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
TSYSCLK1/ECLK1
TSYSCLK2/ECLK2
GND
TST_CLD
TSYNC/TSSYNC1
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
10K to GND
TSYSCLK1/ECLK1
GND
TSYNC/TSSYNC1
TSYNC/TSSYNC2
TSYNC/TSSYNC3
TSYNC/TSSYNC4
TSYNC/TSSYNC5
TSYNC/TSSYNC6
TSYNC/TSSYNC7
TSYNC/TSSYNC8
TSYSCLK1/ECLK1
TSYSCLK2/ECLK2
TSYSCLK3/ECLK3
TSYSCLK4/ECLK4
TSYSCLK5/ECLK5
TSYSCLK6/ECLK6
TSYSCLK7/ECLK7
TSYSCLK8/ECLK8
TTIP1
E8
G7
F5
M7
Y5
R5
AB6
C8
G8
F7
GND
G6
V4
GND
GND
GND
GND
AA4
W7
AB7
A15
A7
GND
GND
GND
GND
GND
GND
GND
GND
GND
TTIP1
TTIP1
TTIP1
N.C.
TTIP2
TTIP2
TTIP2
N.C.
N.C.
C1
TTIP3
TTIP3
N.C.
N.C.
G1
T1
TTIP4
TTIP4
N.C.
N.C.
N.C.
TTIP5
N.C.
N.C.
N.C.
Y1
TTIP6
N.C.
N.C.
N.C.
AB8
AB14
H3
TTIP7
N.C.
N.C.
N.C.
TTIP8
TXENABLE
TXENABLE
TXENABLE
TXENABLE
66 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
14.2 DS34T108 Pin Assignment
Figure 14-1. DS34T108 Pin Assignment (HSBGA Package)
1
2
3
4
5
6
7
8
9
10
11
RTIP3
RRING3
RSYNC3
RLOF/RLOS2
RSYNC1
RDATF1
TTIP2
ATVSS2
RTIP2
ARVSS2
RESREF
A
B
ARVSS3
TTIP3
ARVDD3
TRING3
TSER3
DVDDLIU
RSER4
TDATF3
DVDDC
TCLKO2
RDATF3
TCLKF1
RSYSCLK1
RSER2
TRING2
TDATF1
ATVDD2
TSYSCLK1/ECLK1
TCLKF3
RRING2
RCLKF2/RCLK2
TSER1
ARVDD2
NC
DVDDC
TDM 1_RSIG_RTS
TDM 1_RX_SYNC
TDM 1_TSIG_CTS
TDM 2_TSIG_CTS
TDM 2_TX
C
ATVDD3
RTIP4
ATVSS3
RRING4
ARVDD4
TRING4
DVSS
RLOF/RLOS4
DVDDC
RCLKF4/RCLK4
RF/RM SYNC2
TSYSCLK3/ECLK3
TSYNC/TSSYNC3
RSER3
TDM 1_RX
TDM 1_ACLK
D
DVSSLIU
TSER4
RF/RM SYNC4
RDATF4
TCLKO4
TSYNC/TSSYNC2
RSYSCLK3
TSYSCLK2/ECLK2
DVSS
TDM2_ACLK
E
ARVSS4
TTIP4
TSYNC/TSSYNC4
DVDDC
DVSS
TDM 3_TX_M F_CD TDM 2_TX_M F_CD
F
TST_CLD
TXENABLE
TEST_CLK
JTM S
RF/RM SYNC3
RLOF/RLOS3
TSER2
TSYSCLK4/ECLK4
RSYNC4
TDM 3_TCLK
TDM 4_RX
TDM 2_TCLK
TDM 4_TX_SYNC
DVDDIO
G
H
ATVSS4
CLK_SYS/SCCLK
ACVSS2
CLK_HIGH
ACVSS1
M CLK
ATVDD4
CLK_SYS_S
ACVDD2
DVDDC
RSYSCLK4
RSER1
TDM 4_TCLK
DVDDIO
TCLKF4
TCLKO3
TDATF2
TDM 4_TX
J
TCLKF2
RCLKF3/RCLK3
TSYNC/TSSYNC1
RSYNC8
TDATF4
RSYSCLK2
RDATF2
RF/RM SYNC1
TCLKO1
DVDDIO
DVSS
DVSS
K
JTCLK
RCLKF1/RCLK1
TCLKF8
RSYNC2
DVDDIO
DVSS
DVSS
L
ACVDD1
DVSS
JTDI
RF/RM SYNC5
RSER5
TSYNC/TSSYNC5
RLOF/RLOS7
TCLKO7
RLOF/RLOS1
RSYSCLK8
TDATF8
DVDDIO
DVSS
DVSS
M
N
JTDO
TCLKO5
TDATF6
DVDDIO
DVSS
DVSS
CLK_CM N
ATVSS5
TTIP5
RST_SYS_N
ATVDD5
TRING5
JTRST_N
RXTSEL
HiZ_N
RDATF5
RCLKF7/RCLK7
TSYNC/TSSYNC7
DVDDC
RCLKF5/RCLK5
TDATF5
TSER8
DVDDIO
DVDDIO
P
RSYNC6
TSER6
DVSS
TDM 6_RSIG_RTS
TDM 5_RSIG_RTS
TDM8_RCLK
TDM 5_RCLK
TDM 7_TSIG_CTS
TDM 8_RSIG_RTS
ATVDD7
TDM 5_TX_M F_CD
TDM 6_TX_SYNC
TDM 8_TX_SYNC
TDM 8_RX
TDM 8_TX
DVDDC
TDM 5_RX
R
RF/RM SYNC7
RLOF/RLOS5
TSYSCLK5/ECLK5
DVSS
TCLKF5
TCLKF6
RSER7
TDM 8_RX_SYNC
TDM 7_TX_SYNC
TDM 5_ACLK
TDM 8_TSIG_CTS
TDM 7_TCLK
ARVDD7
T
ARVSS5
RTIP5
ARVDD5
RRING5
ATVSS6
TRING6
RLOF/RLOS6
DVDDLIU
RSYNC5
DVSSLIU
RDATF8
RCLKF8/RCLK8
RSYSCLK6
DVDDC
DVSS
TCLKO6
TCLKF7
U
TSER5
RLOF/RLOS8
TSYSCLK7/ECLK7
TDATF7
TSER7
V
ATVDD6
TTIP6
RSYSCLK5
TSYNC/TSSYNC6
RDATF7
RSER6
RF/RM SYNC6
RSYSCLK7
TRING7
W
Y
RDATF6
RCLKF6/RCLK6
RSYNC7
ARVSS6
RTIP6
ARVDD6
RRING6
TSYSCLK6/ECLK6
RSER8
TCLKO8
RRING7
AA
AB
RF/RM SYNC8
TSYNC/TSSYNC8
TSYSCLK8/ECLK8
TTIP7
ATVSS7
RTIP7
ARVSS7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DVDDC
RTIP1
ARVSS1
TTIP1
ATVSS1
SD_A[0]
SD_D[6]
SD_A[5]
SD_DQM[0]
SD_D[3]
SD_D[5]
A
B
C
D
E
DVSS
RRING1
ARVDD1
TDM2_RSIG_RTS
TDM3_RX_SYNC
TDM2_TX_SYNC
TDM3_TX_SYNC
TDM3_ACLK
TDM4_RX_SYNC
TDM4_RCLK
DVDDIO
TRING1
TDM3_RCLK
TDM 3_RX
ATVDD1
SD_D[4]
SD_CS_N
SD_WE_N
SD_A[11]
SD_A[4]
DVSS
SD_A[3]
SD_D[0]
SD_A[9]
DVDDC
SD_A[1]
DVDDC
SD_D[13]
SD_A[10]
SD_BA[1]
DVSS
SD_DQM[2]
DVDDC
SD_D[7]
SD_D[12]
SD_D[15]
SD_D[8]
SD_D[1]
SD_D[10]
SD_D[14]
SD_D[17]
SD_D[21]
SD_D[24]
SD_D[26]
SD_D[28]
SD_D[31]
SD_D[30]
H_ IN T [ 1]
TDM1_TX
TDM 1_RCLK
TDM2_RCLK
TDM 1_TCLK
TDM 3_TSIG_CTS
TDM4_ACLK
DVDDIO
TDM2_RX_SYNC
TDM2_RX
SD_RAS_N
SD_CAS_N
SD_A[2]
SD_DQM[3]
DVDDC
TDM1_TX_SYNC
TDM 1_TX_MF_CD
TDM3_RSIG_RTS
TDM 4_TX_M F_CD
DVDDIO
TDM 3_TX
SD_DQM[1]
SD_A[7]
TDM4_RSIG_RTS
TDM4_TSIG_CTS
DVSS
SD_A[8]
F
SD_D[29]
SD_CLK
SD_BA[0]
SD_A[6]
SD_D[2]
SD_D[16]
SD_D[11]
SD_D[18]
SD_D[27]
SD_D[19]
SD_D[23]
SD_D[20]
SD_D[25]
D A T _ 3 2 _ 16 _ N
H_AD[2]
H_AD[19]
H_AD[12]
H_AD[17]
H_AD[24]
H_D[1]
G
H
J
SD_D[9]
H_WR_B E1_N/ SPI_
MOSI
H_WR_BE2_N/SPI_S
EL_N
SCEN
STMD
H_INT[ 0]
H_R_W_N/SPI_CP
H_CS_N
SD_D[22]
H_CPU_SPI_N
DVSS
DVSS
H_AD[3]
H_AD[9]
H_READY_N
H_AD[1]
K
L
H_WR_BE0_N/SPI_ H_WR_BE3_N/SPI_
DVSS
DVSS
DVDDIO
H_AD[11]
CLK
CI
DVSS
DVSS
DVDDIO
MBIST_DONE
MBIST_FAIL
M BIST_EN
DVSS
H_AD[7]
H_AD[20]
H_AD[23]
H_D[22]
H_AD[6]
H_D[2]
H_AD[18]
H_AD[8]
H_AD[4]
M
N
P
DVSS
DVSS
DVDDIO
H_AD[13]
H_D[5]
H_AD[16]
H_D[14]
H_AD[14]
H_AD[21]
H_D[3]
H_AD[10]
H_AD[15]
H_AD[22]
H_D[0]/SPI_MISO
H_D[8]
DVDDIO
DVDDIO
TDM5_TSIG_CTS
TDM5_TX_SYNC
TDM7_RSIG_RTS
TDM5_RX_SYNC
TDM7_ACLK
TDM6_ACLK
TDM8_TCLK
TRING8
H_D[11]
TDM5_TX
TDM6_RCLK
TDM7_RX
TDM6_RX
TDM7_TX
DVSS
TDM7_RX_SYNC
TDM 5_TCLK
TDM 7_RCLK
TDM6_TSIG_CTS
TDM 8_TX_M F_CD
TDM 8_ACLK
ARVDD8
H_D[7]
H_D[24]
H_D[29]
H_D[20]
R
T
TDM6_RX_SYNC
TDM6_TX_MF_CD
TDM6_TCLK
TDM 6_TX
H_D[9]
H_D[4]
DVDDC
H_D[26]
H_AD[5]
H_D[19]
H_D[28]
DVSS
H_D[6]
H_D[31]
U
V
CLK_MII_RX
MII_RXD[1]
M II_RXD[3]
M II_RXD[0]
M II_RXD[2]
MII_RX_ERR
MII_TX_EN
MII_RX_DV
M II_COL
DVDDC
H_D[25]
DVDDC
H_D[30]
DVDDC
MDIO
H_D[23]
H_D[10]
MII_TXD[1]
M II_CRS
CLK_MII_TX
MII_TXD[0]
DVSS
H_D[27]
H_D[12]
W
Y
TDM7_TX_MF_CD
ATVDD8
CLK_SSM II_TX
M II_TXD[2]
M II_TXD[3]
H_D[13]
H_D[15]
RRING8
H_D[16]
H_D[17]
AA
AB
RTIP8
ARVSS8
TTIP8
ATVSS8
MDC
M II_TX_ERR
H_D[18]
H_D[21]
12
13
14
15
16
17
18
19
20
21
22
67 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
14.3 DS34T104 Pin Assignment
Figure 14-2. DS34T104 Pin Assignment (TEBGA Package)
1
2
3
4
5
6
7
8
9
10
11
RTIP3
RRING3
RSYNC3
RLOF/RLOS2
RSYNC1
RDATF1
TTIP2
ATVSS2
RTIP2
ARVSS2
RESREF
A
B
ARVSS3
TTIP3
ARVDD3
TRING3
ATVSS3
RRING4
ARVDD4
TRING4
ATVDD4
CLK_SYS_S
ACVDD2
DVDDC
ACVDD1
DVSS
TSER3
DVDDLIU
RSER4
DVSSLIU
TSER4
TST_CLD
TXENABLE
TEST_CLK
JTM S
TDATF3
DVDDC
DVSS
TCLKO2
RDATF3
RLOF/RLOS4
DVDDC
TSYNC/TSSYNC4
DVDDC
RSYSCLK4
RSER1
TCLKF1
RSYSCLK1
RSER2
TCLKO4
DVSS
TRING2
ATVDD2
RRING2
RCLKF2/RCLK2
TSER1
ARVDD2
NC
DVDDC
TDM1_RSIG_RTS
TDM 1_RX_SYNC
TDM1_TSIG_CTS
TDM 2_TSIG_CTS
TDM 2_TX
TDM 4_TCLK
DVDDIO
DVSS
TDATF1
TSYSCLK1/ECLK1
C
ATVDD3
RTIP4
RCLKF4/RCLK4
TCLKF3
TDM 1_RX
TDM 1_ACLK
D
RF/RMSYNC4
RDATF4
RF/RM SYNC3
RLOF/RLOS3
TSER2
TCLKF2
RCLKF1/RCLK1
NC
RF/RM SYNC2
TSYNC/TSSYNC2
TDM2_ACLK
E
ARVSS4
TTIP4
TSYSCLK3/ECLK3
RSYSCLK3
TDM 3_TX_M F_CD TDM 2_TX_M F_CD
F
TSYSCLK4/ECLK4
RSYNC4
TCLKF4
TDATF4
RSYNC2
TST_RB
TST_RA
NC
TSYNC/TSSYNC3
TSYSCLK2/ECLK2
TDM 3_TCLK
TDM 4_RX
TDM 4_TX
DVDDIO
DVDDIO
DVDDIO
DVDDIO
NC
TDM 2_TCLK
G
H
ATVSS4
CLK_SYS/SCCLK
ACVSS2
CLK_HIGH
ACVSS1
M CLK
RSER3
TCLKO3
RSYSCLK2
RDATF2
TST_TC
NC
DVSS
TDM 4_TX_SYNC
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVDDIO
NC
TDATF2
J
RCLKF3/RCLK3
TSYNC/TSSYNC1
NC
RF/RM SYNC1
K
JTCLK
TCLKO1
DVSS
L
JTDI
RLOF/RLOS1
DVSS
M
N
JTDO
NC
TST_TA
NC
NC
NC
DVSS
CLK_CM N
ATVSS5
NC
RST_SYS_N
ATVDD5
NC
JTRST_N
RXTSEL
HiZ_N
TST_TB
NC
NC
DVDDIO
NC
P
NC
TST_RC
NC
NC
DVSS
NC
NC
R
NC
DVDDC
NC
NC
NC
NC
NC
T
ARVSS5
NC
ARVDD5
NC
NC
NC
DVSS
NC
NC
NC
NC
NC
U
DVDDLIU
NC
NC
DVDDC
NC
NC
NC
NC
NC
NC
NC
V
ATVDD6
NC
ATVSS6
NC
DVSS
NC
NC
NC
NC
NC
NC
W
Y
DVSSLIU
NC
NC
NC
NC
NC
NC
NC
DVDDC
NC
NC
ARVSS6
NC
ARVDD6
NC
NC
NC
NC
NC
NC
ATVDD7
ATVSS7
ARVDD7
ARVSS7
AA
AB
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DVDDC
RTIP1
ARVSS1
ARVDD1
TDM 2_RSIG_RTS
TDM 3_RX_SYNC
TDM 2_TX_SYNC
TDM 3_TX_SYNC
TDM 3_ACLK
TDM 4_RX_SYNC
TDM 4_RCLK
DVDDIO
DVDDIO
DVDDIO
DVDDIO
NC
TTIP1
ATVSS1
SD_A[0]
SD_D[6]
SD_A[5]
SD_DQM [0]
SD_D[3]
SD_D[5]
A
B
C
D
E
DVSS
RRING1
TRING1
TDM 3_RCLK
TDM3_RX
TDM3_TX
TDM 4_RSIG_RTS
TDM 4_TSIG_CTS
DVSS
ATVDD1
SD_D[4]
SD_CS_N
SD_WE_N
SD_A[11]
SD_A[3]
SD_D[0]
SD_A[9]
DVDDC
SD_A[1]
DVDDC
SD_D[13]
SD_A[10]
SD_BA[1]
DVSS
SD_DQM [2]
DVDDC
SD_D[7]
SD_D[12]
SD_D[15]
SD_D[8]
SD_D[1]
SD_D[10]
SD_D[14]
SD_D[17]
SD_D[21]
SD_D[24]
SD_D[26]
SD_D[28]
SD_D[31]
SD_D[30]
H_INT[1]
TDM 1_TX
TDM 1_RCLK
TDM2_RCLK
TDM 1_TCLK
TDM3_TSIG_CTS
TDM4_ACLK
DVDDIO
DVSS
TDM 2_RX_SYNC
TDM 2_RX
TDM 1_TX_SYNC
TDM 1_TX_M F_CD
TDM 3_RSIG_RTS
TDM 4_TX_MF_CD
DVDDIO
DVSS
SD_RAS_N
SD_CAS_N
SD_A[2]
SD_DQM [3]
DVDDC
SD_A[4]
SD_DQM [1]
SD_A[7]
DVSS
SD_A[8]
F
SD_D[29]
SD_CLK
SD_BA[0]
SD_A[6]
SD_D[2]
SD_D[16]
SD_D[11]
SD_D[18]
SD_D[27]
SD_D[19]
SD_D[23]
SD_D[20]
SD_D[25]
DAT_32_16_N
H_AD[2]
H_AD[19]
H_AD[12]
H_AD[17]
H_AD[24]
H_D[1]
G
H
J
SD_D[9]
H_WR_BE1_N/SPI_
M OSI
H_WR_BE2_N/SPI_S
EL_N
SCEN
H_ INT[ 0 ]
H_R_W_N/SPI_CP
H_CS_N
SD_D[22]
H_CPU_SPI_N
STM D
H_AD[3]
H_AD[9]
H_READY_N
H_AD[1]
K
L
H_WR_BE0_N/SPI_ H_WR_BE3_N/SPI_
DVSS
DVSS
H_AD[11]
M BIST_DONE
M BIST_FAIL
M BIST_EN
DVSS
CLK
CI
DVSS
DVSS
H_AD[7]
H_AD[20]
H_AD[23]
H_D[22]
H_AD[6]
H_D[2]
H_AD[18]
H_AD[8]
H_AD[4]
M
N
P
DVSS
DVSS
H_AD[13]
H_D[5]
H_AD[16]
H_D[14]
H_AD[14]
H_AD[21]
H_D[3]
H_AD[10]
H_AD[15]
H_AD[22]
H_D[0]/SPI_M ISO
H_D[8]
DVDDIO
NC
DVDDIO
NC
H_D[11]
NC
H_D[7]
H_D[24]
H_D[29]
H_D[20]
R
T
NC
NC
NC
NC
H_D[9]
H_D[4]
DVDDC
H_D[26]
H_AD[5]
H_D[19]
NC
NC
NC
NC
H_D[28]
DVSS
H_D[6]
H_D[31]
U
V
NC
NC
NC
NC
CLK_M II_RX
M II_RXD[1]
M II_RXD[3]
M II_RXD[0]
M II_RXD[2]
M II_RX_ERR
M II_TX_EN
M II_RX_DV
MII_COL
M DC
DVDDC
H_D[25]
DVDDC
H_D[30]
DVDDC
M DIO
H_D[23]
H_D[10]
NC
NC
NC
NC
M II_TXD[1]
M II_CRS
CLK_M II_TX
M II_TXD[0]
DVSS
H_D[27]
H_D[12]
W
Y
DVSS
NC
NC
NC
CLK_SSM II_TX
M II_TXD[2]
M II_TXD[3]
H_D[13]
H_D[15]
NC
ARVDD8
ARVSS8
NC
ATVDD8
ATVSS8
H_D[16]
H_D[17]
AA
AB
NC
NC
M II_TX_ERR
H_D[18]
H_D[21]
12
13
14
15
16
17
18
19
20
21
22
68 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
14.4 DS34T102 Pin Assignment
Figure 14-3. DS34T102 Pin Assignment (TEBGA Package)
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
RLOF/RLOS2
RSYNC1
RDATF1
TTIP2
ATVSS2
RTIP2
ARVSS2
RESREF
A
B
ARVSS3
NC
ARVDD3
NC
NC
DVDDLIU
NC
NC
DVDDC
DVSS
NC
TCLKO2
TCLKF1
RSYSCLK1
RSER2
NC
TRING2
ATVDD2
RRING2
RCLKF2/RCLK2
TSER1
TDM2_ACLK
NC
ARVDD2
DVDDC
TDM 1_RSIG_RTS
TDM 1_RX_SYNC
TDM 1_TSIG_CTS
TDM2_TSIG_CTS
TDM2_TX
NC
NC
TDATF1
TSYSCLK1/ECLK1
NC
TDM1_RX
TDM 1_ACLK
TDM 2_TX_M F_CD
TDM 2_TCLK
NC
C
ATVDD3
NC
ATVSS3
NC
NC
NC
NC
D
DVSSLIU
NC
DVDDC
RF/RMSYNC2
TSYNC/TSSYNC2
E
ARVSS4
NC
ARVDD4
NC
NC
NC
DVSS
NC
NC
NC
NC
F
TST_CLD
TXENABLE
TEST_CLK
JTM S
NC
DVDDC
TSYSCLK2/ECLK2
NC
G
H
ATVSS4
CLK_SYS/SCCLK
ACVSS2
CLK_HIGH
ACVSS1
MCLK
ATVDD4
CLK_SYS_S
ACVDD2
DVDDC
ACVDD1
DVSS
NC
NC
NC
NC
DVSS
NC
TSER2
TCLKF2
RCLKF1/RCLK1
NC
RSER1
NC
NC
TDATF2
NC
DVDDIO
DVSS
DVDDIO
DVSS
J
NC
NC
RSYSCLK2
RDATF2
NC
RF/RM SYNC1
DVDDIO
DVDDIO
DVDDIO
DVDDIO
NC
K
JTCLK
JTDI
TSYNC/TSSYNC1
RSYNC2
NC
TCLKO1
DVSS
DVSS
L
NC
NC
RLOF/RLOS1
DVSS
DVSS
M
N
JTDO
NC
NC
NC
NC
NC
DVSS
DVSS
CLK_CMN
ATVSS5
NC
RST_SYS_N
ATVDD5
NC
JTRST_N
RXTSEL
HiZ_N
NC
NC
NC
NC
DVDDIO
NC
DVDDIO
NC
P
NC
NC
NC
NC
DVSS
NC
NC
R
NC
DVDDC
NC
NC
NC
NC
NC
NC
T
ARVSS5
NC
ARVDD5
NC
NC
NC
DVSS
NC
NC
NC
NC
NC
NC
U
DVDDLIU
NC
NC
DVDDC
NC
NC
NC
NC
NC
NC
V
ATVDD6
NC
ATVSS6
NC
DVSS
NC
NC
NC
NC
NC
NC
NC
W
Y
DVSSLIU
NC
NC
NC
NC
NC
NC
DVDDC
NC
NC
ARVSS6
NC
ARVDD6
NC
NC
NC
NC
NC
NC
ATVDD7
ATVSS7
ARVDD7
ARVSS7
AA
AB
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DVDDC
DVSS
TDM 1_TX
TDM 1_RCLK
TDM 2_RCLK
TDM1_TCLK
NC
RTIP1
ARVSS1
TTIP1
ATVSS1
SD_A[0]
SD_D[6]
SD_A[5]
SD_DQM [0]
SD_D[3]
SD_D[5]
A
B
C
D
E
RRING1
ARVDD1
TRING1
NC
ATVDD1
SD_D[4]
SD_CS_N
SD_WE_N
SD_A[11]
SD_A[4]
SD_A[3]
SD_D[0]
SD_A[9]
DVDDC
SD_A[1]
DVDDC
SD_D[13]
SD_A[10]
SD_BA[1]
DVSS
SD_DQM [2]
DVDDC
SD_D[7]
SD_D[12]
SD_D[15]
SD_D[8]
SD_D[1]
SD_D[10]
SD_D[14]
SD_D[17]
SD_D[21]
SD_D[24]
SD_D[26]
SD_D[28]
SD_D[31]
SD_D[30]
H_INT[1]
TDM 2_RX_SYNC
TDM2_RSIG_RTS
TDM2_RX
NC
NC
SD_RAS_N
SD_CAS_N
SD_A[2]
SD_DQM [3]
DVDDC
TDM 1_TX_SYNC
TDM2_TX_SYNC
NC
SD_DQM [1]
SD_A[7]
TDM 1_TX_M F_CD
NC
NC
NC
DVSS
SD_A[8]
F
NC
NC
NC
SD_D[29]
SD_CLK
SD_BA[0]
SD_A[6]
SD_D[2]
SD_D[16]
SD_D[11]
SD_D[18]
SD_D[27]
SD_D[19]
SD_D[23]
SD_D[20]
SD_D[25]
DAT_32_16_N
H_AD[2]
H_A D[ 19]
H_AD[12]
H_AD[17]
H_AD[24]
H_D[1]
G
H
J
NC
NC
DVSS
SCEN
STMD
H_AD[11]
M BIST_DONE
M B IST_FA IL
M BIST_EN
DVSS
NC
SD_D[9]
H_WR_BE1_N/SPI_
M OSI
H_WR_BE2_N/SPI_S
EL_N
DVDDIO
DVSS
DVSS
DVSS
DV SS
DVDDIO
NC
DVDDIO
DVSS
DVSS
DVSS
DV SS
DVDDIO
NC
NC
H_INT[ 0]
H_R_W_N/SPI_CP
H_CS_N
SD_D[22]
H_CPU_SPI_N
DVDDIO
DVDDIO
DVDDIO
DV DDIO
NC
H_AD[3]
H_AD[9]
H_READY_N
H_AD[1]
K
L
H_WR_BE0_N/SPI_ H_WR_BE3_N/SPI_
CLK
CI
H_AD[7]
H_AD[20]
H_A D[ 23]
H_D[22]
H_AD[6]
H_D[ 2]
H_AD[18]
H_AD[8]
H_AD[4]
M
N
P
H_AD[ 13]
H_D[5]
H_AD[ 16]
H_D[14]
H_A D[ 14]
H_AD[21]
H_D[3]
H_AD[ 10]
H_AD[15]
H_AD[22]
H_D[0]/SPI_M ISO
H_D[8]
H_D[11]
NC
H_D[7]
H_D[24]
H_D[29]
H_D[20]
R
T
NC
NC
NC
H_D[9]
H_D[4]
DVDDC
H_D[26]
H_AD[5]
H_D[19]
NC
NC
NC
NC
H_D[28]
DVSS
H_D[6]
H_D[31]
U
V
NC
NC
NC
NC
CLK_M II_RX
M II_RXD[1]
M II_RXD[3]
M II_RXD[0]
M II_RXD[2]
M II_RX_ERR
M II_TX_EN
MII_RX_DV
M II_COL
M DC
DVDDC
H_D[25]
DVDDC
H_D[30]
DVDDC
M DIO
H_D[23]
H_D[10]
NC
NC
NC
NC
M II_TXD[1]
M II_CRS
CLK_M II_TX
M II_TXD[0]
DVSS
H_D[27]
H_D[12]
W
Y
DVSS
NC
NC
NC
NC
CLK_SSMII_TX
M II_TXD[2]
M II_TXD[3]
H_D[13]
H_D[15]
ARVDD8
ARVSS8
NC
ATVDD8
ATVSS8
H_D[16]
H_D[17]
AA
AB
NC
NC
M II_TX_ERR
H_D[18]
H_D[21]
12
13
14
15
16
17
18
19
20
21
22
69 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
14.5 DS34T101 Pin Assignment
Figure 14-4. DS34T101 Pin Assignment (TEBGA Package)
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
RSYNC1
RDATF1
NC
ATVSS2
NC
ARVSS2
RESREF
A
B
ARVSS3
NC
ARVDD3
NC
NC
DVDDLIU
NC
NC
NC
TCLKF1
RSYSCLK1
NC
NC
TDATF1
NC
ATVDD2
NC
NC
ARVDD2
NC
DVDDC
DVDDC
NC
TSYSCLK1/ECLK1
TDM 1_RSIG_RTS
C
ATVDD3
NC
ATVSS3
NC
DVSS
NC
NC
TSER1
NC
TDM1_RX
TDM 1_ACLK
NC
TDM 1_RX_SYNC
D
DVSSLIU
NC
NC
DVDDC
NC
NC
NC
TDM 1_TSIG_CTS
NC
E
ARVSS4
NC
ARVDD4
NC
NC
NC
DVSS
NC
NC
NC
NC
F
TST_CLD
TXENABLE
TEST_CLK
JTM S
NC
DVDDC
NC
NC
NC
NC
NC
G
H
ATVSS4
CLK_SYS/SCCLK
ACVSS2
CLK_HIGH
ACVSS1
MCLK
ATVDD4
CLK_SYS_S
ACVDD2
DVDDC
ACVDD1
DVSS
NC
NC
NC
NC
DVSS
NC
NC
NC
NC
RSER1
NC
NC
NC
NC
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVDDIO
NC
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVDDIO
NC
J
NC
NC
NC
NC
RF/RMSYNC1
DVDDIO
DVDDIO
DVDDIO
DVDDIO
NC
K
JTCLK
JTDI
RCLKF1/RCLK1
TSYNC/TSSYNC1
NC
NC
TCLKO1
L
NC
NC
NC
NC
NC
NC
RLOF/RLOS1
M
N
JTDO
NC
NC
NC
NC
CLK_CM N
ATVSS5
NC
RST_SYS_N
ATVDD5
NC
JTRST_N
RXTSEL
HiZ_N
NC
NC
NC
NC
P
NC
NC
NC
NC
DVSS
NC
NC
R
NC
DVDDC
NC
NC
NC
NC
NC
NC
T
ARVSS5
NC
ARVDD5
NC
NC
NC
DVSS
NC
NC
NC
NC
NC
NC
U
DVDDLIU
NC
NC
DVDDC
NC
NC
NC
NC
NC
NC
V
ATVDD6
NC
ATVSS6
NC
DVSS
NC
NC
NC
NC
NC
NC
NC
W
Y
DVSSLIU
NC
NC
NC
NC
NC
NC
DVDDC
NC
NC
ARVSS6
NC
ARVDD6
NC
NC
NC
NC
NC
NC
ATVDD7
ATVSS7
ARVDD7
ARVSS7
AA
AB
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DVDDC
DVSS
TDM 1_TX
TDM1_RCLK
NC
RTIP1
ARVSS1
ARVDD1
NC
TTIP1
TRING1
NC
ATVSS1
ATVDD1
SD_D[4]
SD_A[0]
SD_D[6]
SD_A[5]
SD_A[10]
SD_BA[1]
DVSS
SD_DQM [0]
SD_DQM [2]
DVDDC
SD_D[3]
SD_D[5]
SD_D[10]
SD_D[14]
SD_D[17]
SD_D[21]
SD_D[24]
SD_D[26]
SD_D[28]
SD_D[31]
SD_D[30]
H_INT[1]
A
B
C
D
E
RRING1
SD_CS_N
SD_WE_N
SD_A[11]
SD_A[4]
SD_A[3]
SD_D[0]
SD_A[9]
DVDDC
SD_A[1]
DVDDC
SD_D[13]
SD_D[7]
NC
SD_D[12]
SD_D[15]
SD_D[8]
SD_D[1]
NC
NC
NC
SD_RAS_N
SD_CAS_N
SD_A[2]
SD_DQM [3]
DVDDC
TDM 1_TX_SYNC
NC
NC
SD_DQM [1]
SD_A[7]
TDM 1_TCLK
NC
TDM 1_TX_MF_CD
NC
NC
DVSS
SD_A[8]
F
NC
NC
NC
NC
SD_D[29]
SD_CLK
SD_BA[0]
SD_A[6]
SD_D[2]
SD_D[16]
SD_D[11]
SD_D[19]
SD_D[23]
SD_D[20]
SD_D[25]
DAT_32_16_N
H_AD[2]
H_AD[19]
H_AD[12]
H_AD[17]
H_AD[24]
H_D[1]
G
H
J
NC
NC
DVSS
SCEN
STM D
H_AD[11]
M BIST_DONE
M BIST_FAIL
M BIST_EN
DVSS
NC
SD_D[9]
H_WR_BE1_N/SPI_
M OSI
H_WR_BE2_N/SPI_S
EL_N
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVDDIO
NC
DVDDIO
DVSS
DVSS
DVSS
DVSS
DVDDIO
NC
NC
H_INT[ 0]
H_R_W_N/SPI_CP
H_CS_N
SD_D[22]
H_CPU_SPI_N
SD_D[18]
SD_D[27]
DVDDIO
DVDDIO
DVDDIO
DVDDIO
NC
H_AD[3]
H_AD[9]
H_READY_N
H_AD[1]
K
L
H_WR_BE0_N/SPI_ H_WR_BE3_N/SPI_
CLK
CI
H_AD[7]
H_AD[20]
H_AD[23]
H_D[22]
H_AD[6]
H_D[2]
H_AD[18]
H_AD[8]
H_AD[4]
M
N
P
H_AD[13]
H_D[5]
H_AD[16]
H_D[14]
H_AD[14]
H_AD[21]
H_D[3]
H_AD[10]
H_AD[15]
H_AD[22]
H_D[0]/SPI_M ISO
H_D[8]
H_D[11]
NC
H_D[7]
H_D[24]
H_D[29]
H_D[20]
R
T
NC
NC
NC
H_D[9]
H_D[4]
DVDDC
H_D[26]
H_AD[5]
H_D[19]
NC
NC
NC
NC
H_D[28]
DVSS
H_D[6]
H_D[31]
U
V
NC
NC
NC
NC
CLK_M II_RX
M II_RXD[1]
M II_RXD[3]
M II_RXD[0]
M II_RXD[2]
MII_RX_ERR
M II_TX_EN
M II_RX_DV
M II_COL
M DC
DVDDC
H_D[25]
DVDDC
H_D[30]
DVDDC
M DIO
H_D[23]
H_D[10]
NC
NC
NC
NC
M II_TXD[1]
M II_CRS
CLK_MII_TX
M II_TXD[0]
DVSS
H_D[27]
H_D[12]
W
Y
DVSS
NC
NC
NC
NC
CLK_SSM II_TX
M II_TXD[2]
M II_TXD[3]
H_D[13]
H_D[15]
ARVDD8
ARVSS8
NC
ATVDD8
ATVSS8
H_D[16]
H_D[17]
AA
AB
NC
NC
M II_TX_ERR
H_D[18]
H_D[21]
12
13
14
15
16
17
18
19
20
21
22
70 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
15. Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a
link to the latest package outline information. The 484-ball HSBGA and the 484-ball TEBGA have the same footprint. The difference between
the packages is that the HSBGA has an internal heat spreader.)
15.1 484-Ball HSBGA (56-G6038-002)
71 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
15.2 484-Ball TEBGA (56-G6038-001)
72 of 74
_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
16. Thermal Information
VALUE
PARAMETER
HSBGA
TEBGA
Target Ambient Temperature Range
Die Junction Temperature Range
Theta-JC (Junction to Top of Case)
Theta-JB (Junction to Bottom Pins)
Theta-JA, Still Air (Note 1)
-40°C to +85°C
-40°C to +125°C
2.2°C/W
-40°C to +85°C
-40°C to +125°C
5.4°C/W
5.2°C/W
12.5°C/W
11.2°C/W
19.7°C/W
Note 1: Theta-JA values are estimates using JEDEC-standard PCB and enclosure dimensions.
73 of 74
______________________________________________________DS34T101/DS34T102/DS34T104/DS34T108
17. Document Revision History
REVISION
DESCRIPTION
New product release.
072707
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
74 of 74
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
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