DS3882ET [MAXIM]
Dual-Channel Automotive CCFL Controller; 双通道，汽车CCFL控制器
| 型号： | DS3882ET |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Channel Automotive CCFL Controller |
| 文件： | 总30页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 3/06
Dual-Channel Automotive CCFL Controller
General Description
Features
ꢀ Dual-Channel CCFL Controllers for Backlighting
LCD Panels and Instrument Clusters in
The DS3882 is a dual-channel cold-cathode fluorescent
lamp (CCFL) controller for automotive applications that
provides up to 300:1 dimming. It is ideal for driving
CCFLs used to backlight liquid crystal displays (LCDs)
in navigation and infotainment applications and for dri-
ving CCFLs used to backlight instrument clusters. The
DS3882 is also appropriate for use in marine and avia-
tion applications.
Automotive Navigation/Infotainment Applications
ꢀ Minimal External Components Required
2
ꢀ I C Interface
ꢀ Per-Channel Lamp-Fault Monitoring for Lamp-
Open, Lamp-Overcurrent, Failure to Strike, and
Overvoltage Conditions
The DS3882 features EMI suppression functionality and
provides a lamp current overdrive mode for rapid lamp
heating in cold weather conditions. The DS3882 sup-
ports configurations of 1 or 2 lamps with fully indepen-
dent lamp control and minimal external components.
Multiple DS3882 controllers can be cascaded to sup-
port applications requiring more than 2 lamps. Control
of the DS3882, after initial programming setup, can be
ꢀ Status Register Reports Fault Conditions
ꢀ Accurate (±±5% Independent On-Board Oscillators
for Lamp Frequency (40kHz to 100kHz% and DPWM
Burst-Dimming Frequency (22.±Hz to 440Hz%
ꢀ Lamp and DPWM Frequencies can be
Synchronized with External Sources to Reduce
Visual LCD Artifacts in Video Applications
ꢀ Optional Spread-Spectrum Lamp Clock Reduces
2
completely achieved through I C* software communi-
EMI
cation. Many DS3882 functions are also pin-controllable
if software control is not desired.
ꢀ Lamp Frequency can be Stepped Up or Down to
Move EMI Spurs Out of Band
Applications
ꢀ Lamp Current Overdrive Mode with Automatic
Turn-Off Quickly Warms Lamp in Cold
Temperatures
Automotive LCDs
Instrument Clusters
ꢀ Analog and Digital Brightness Control
Marine and Aviation LCDs
ꢀ 300:1 Dimming Range Possible Using the Digital
Pin Configuration
Brightness Control Option
ꢀ Programmable Soft-Start Minimizes Audible
TOP VIEW
Transformer Noise
FAULT
A0
1
2
3
4
5
6
7
8
9
28 OVD2
27 LCM2
26 GB2
ꢀ On-Board Nonvolatile (NV% Memory Allows Device
Customization
SDA
ꢀ 8-Byte NV User Memory for Storage of Serial
SCL
25 GA2
Numbers and Date Codes
LSYNC
LOSC
BRIGHT
PSYNC
POSC
24 V
CC
ꢀ Low-Power Standby Mode
DS3882
23 PDN
22 LCO
21 GND
20 STEP
19 N.C.
18 OVD1
17 LCM1
16 GB1
15 GA1
ꢀ 4.7±V to ±.2±V Single-Supply Operation
ꢀ Temperature Range: -40°C to +10±°C
ꢀ 28-Pin TSSOP Package
A1 10
GND_S 11
SVML 12
SVMH 13
Ordering Information
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
DS3882E+
28 TSSOP (173 mils)
28 TSSOP (173 mils)
V
14
CC
DS3882E+T&R
+Denotes lead-free package.
TSSOP
2
*Purchase of I C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
2
2
2
license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C
Standard Specification as defined by Philips.
Typical Operating Circuit appears at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Channel Automotive CCFL Controller
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and
Operating Temperature Range .........................-40°C to +105°C
EEPROM Programming Temperature Range .........0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 Specification
CC
SCL Relative to Ground.....................................-0.5V to +6.0V
Voltage Range on Leads Other than V , SDA, and
CC
SCL ......................-0.5V to (V
+ 0.5V), not to exceed +6.0V
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +105°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
4.75
5.25
V
CC
V
+ 0.3
CC
Input Logic 1
V
2.0
-0.3
-0.3
V
V
V
IH
Input Logic 0
V
IL
1.0
V
+
CC
SVML/H Voltage Range
V
SVM
0.3
V
V
V
+
+
+
CC
0.3
BRIGHT Voltage Range
LCM Voltage Range
OVD Voltage Range
V
-0.3
-0.3
-0.3
V
V
BRIGHT
CC
0.3
V
V
(Note 2)
(Note 2)
LCM
OVD
CC
0.3
V
Gate-Driver Output Charge
Loading
Q
20
nC
G
ELECTRICAL CHARACTERISTICS
(V
= +4.75V to +5.25V, T = -40°C to +105°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
G , G loaded with 600pF, 2 channels active
MIN
-1.0
-1.0
TYP
MAX
UNITS
mA
Supply Current
I
12
CC
A
B
Input Leakage (Digital Pins)
Power-Down Current
I
L
+1.0
2
µA
I
mA
PDN
Output Leakage (SDA, FAULT)
I
High impedance
+1.0
µA
LO
Low-Level Output Voltage
(LSYNC, PSYNC)
V
I
= 4mA
0.4
V
V
V
V
OL
OL
V
V
I
I
= 3mA
= 6mA
0.4
0.6
OL1
OL2
OL1
Low-Level Output Voltage
(SDA, FAULT)
OL2
Low-Level Output Voltage
(GA, GB)
V
I
= 4mA
0.4
OL3
OL3
High-Level Output Voltage
(LSYNC, PSYNC)
V
I = -1mA
OH
2.4
OH
2
_____________________________________________________________________
Dual-Channel Automotive CCFL Controller
ELECTRICAL CHARACTERISTICS (continued)
(V
= +4.75V to +5.25V, T = -40°C to +105°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High-Level Output Voltage
(GA, GB)
V
0.4
-
CC
V
I
= -1mA
V
OH1
OH1
UVLO Threshold: V
UVLO Threshold: V
UVLO Hysteresis
Rising
Falling
V
4.3
V
V
CC
CC
UVLOR
UVLOF
UVLOH
V
3.7
V
200
2.08
2.02
1.1
mV
V
SVML/H Threshold: Rising
SVML/H Threshold: Falling
LCM and OVD DC Bias Voltage
LCM and OVD Input Resistance
Lamp Off Threshold
V
2.03
1.95
2.15
2.07
SVMR
V
V
SVMF
V
V
DCB
DCB
R
50
kΩ
V
V
(Note 3)
0.22
2.2
0.9
0.9
0.25
2.5
0.28
2.8
1.1
1.1
LOT
Lamp Over Current
V
(Note 3)
V
LOC
Lamp Regulation Threshold
OVD Threshold
V
(Notes 3, 4)
(Note 3)
1.0
V
LRT
V
1.0
V
OVDT
Lamp Frequency Source
Frequency Range
f
40
-5
100
+5
kHz
ꢀ
LFS:OSC
Lamp Frequency Source
Frequency Tolerance
f
LOSC resistor 2ꢀ over temperature
LFS:TOL
Lamp Frequency Receiver
Frequency Range
f
40
100
60
kHz
ꢀ
LFR:OSC
Lamp Frequency Receiver
Duty Cycle
f
40
LFR:DUTY
DPWM Source (Resistor)
Frequency Range
f
22.5
-5
440.0
+5
Hz
ꢀ
DSR:OSC
DPWM Source (Resistor)
Frequency Tolerance
f
POSC resistor 2ꢀ over temperature
DSR:TOL
DSE:OSC
DFE:DUTY
DPWM Source (Ext. Clk)
Frequency Range
f
22.5
40
440.0
60
Hz
ꢀ
DPWM Source (Ext. Clk)
Duty Cycle
f
DPWM Receiver
Min Pulse Width
t
(Note 5)
25
µs
V
DR:MIN
BRIGHT Voltage: Minimum
Brightness
V
0.5
BMIN
BRIGHT Voltage: Maximum
Brightness
V
t
2.0
V
BMAX
Gate Driver Output Rise/Fall Time
GAn and GBn Duty Cycle
/ t
F
C = 600pF
L
100
44
ns
ꢀ
R
(Note 6)
_____________________________________________________________________
3
Dual-Channel Automotive CCFL Controller
2
I C AC ELECTRICAL CHARACTERISTICS (See Figure 9)
(V
= +4.75V to +5.25V, T = -40°C to +105°C, timing referenced to V
and V
.)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 7)
(Note 8)
0
400
kHz
SCL
Bus Free Time Between Stop and
Start Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) Start
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
0.9
HD:DAT
Data Setup Time
Start Setup Time
t
100
0.6
SU:DAT
t
SU:STA
20+
SDA and SCL Rise Time
t
(Note 9)
(Note 9)
300
300
ns
R
0.1C
B
20+
SDA and SCL Fall Time
Stop Setup Time
t
ns
µs
F
0.1C
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 9)
400
30
pF
ms
B
EEPROM Write Time
t
W
(Note 10)
20
NONVOLATILE MEMORY CHARACTERISTICS
(V
= +4.75V to 5.25V)
CC
PARAMETER
SYMBOL
CONDITIONS
+85°C (Note 11)
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
30,000
Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the I.C. are positive, out of the I.C. negative.
Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM or
OVD pin for up to 1 second.
Note 3: Voltage with respect to V
.
DCB
Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled.
Note 5: This is the minimum pulse width guaranteed to generate an output burst, which generates the DS3882’s minimum burst
duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC
input is greater than the DS3882’s minimum duty cycle, the output’s duty cycle tracks the PSYNC’s duty cycle. Leaving
PSYNC low (0ꢀ duty cycle) disables the GAn and GBn outputs in DPWM receiver mode.
Note 6: This is the maximum lamp frequency duty cycle that is generated at any of the GAn or GBn outputs with spread-spectrum
modulation disabled.
2
2
Note 7: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C stan-
dard-mode timing.
Note 8: After this period, the first clock pulse can be generated.
Note 9: C —total capacitance allowed on one bus line in picofarads.
B
Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs.
Note 11: Guaranteed by design.
4
_____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Typical Operating Characteristics
(V
= 5.0V, T = +25°C, unless otherwise noted.)
CC
A
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
INTERNAL FREQUENCY CHANGE
vs. TEMPERATURE
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
7.5
7.3
7.1
6.9
6.7
6.5
6.3
6.1
5.9
5.7
5.5
1.0
0.8
V
= 5.25V
CC
DPWM = 100%
V
= 4.75V
= 5.0V
CC
V
DPWM = 10%
CC
0.6
DPWM = 50%
DPWM FREQUENCY
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
SVML< 2V
LAMP FREQUENCY
f
= 64kHz
LF:OSC
f
= 64kHz
GATE Q = 3.5nC
C
GATE Q = 3.5nC
LF:OSC
DPWM = 100%
C
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
-40.0
32.5
105
-40.0
32.5
105
TEMPERATURE (°C)
TEMPERATURE (°C)
TYPICAL OPERATION AT 11V
TYPICAL OPERATION AT 13V
TYPICAL OPERATION AT 16V
10µs
10µs
5.0V
10µs
5.0V G
A
5.0V
G
A
G
A
10µs
5.0V
10µs
5.0V
10µs
5.0V
G
G
B
G
B
B
10µs
2.00V LCM
10µs
2.00V LCM
10µs
2.00V LCM
10µs
2.00V OVD
10µs
2.00V OVD
10µs
2.00V OVD
TYPICAL STARTUP WITH SVM
BURST DIMMING AT 150Hz AND 10%
BURST DIMMING AT 150Hz AND 50%
2ms
5.0V SVML
1ms
A
1ms
A
5.0V
G
5.0V
G
2ms
B
1ms
5.0V
1ms
5.0V
5.0V
G
G
G
B
B
1ms
2.00V LCM
2ms
2.00V LCM
1ms
2.00V LCM
2ms
2.00V OVD
1ms
2.00V OVD
1ms
2.00V OVD
_____________________________________________________________________
5
Dual-Channel Automotive CCFL Controller
Typical Operating Characteristics (continued)
(V
= 5.0V, T = +25°C, unless otherwise noted.)
A
CC
AUTO RETRY DISABLED
SOFT-START AT V = 16V
LAMP STRIKE—EXPANDED VIEW
INV
0.5s
5.0V
50µs
5.0V
1ms
5.0V
G
G
G
A
A
A
0.5s
5.0V
50µs
5.0V
1ms
5.0V
G
G
G
B
B
B
0.5s
2.00V LCM
50µs
2.00V LCM
1ms
2.00V LCM
0.5s
2.00 OVD
50µs
2.00V OVD
1ms
2.00V OVD
AUTORETRY DISABLED
STAGGERED BURST DIMMING START
0.1s
A
0.2ms
2.00V GA1
5.0V
G
0.1s
5.0V
0.2ms
2.00V GA2
G
B
LAMP OPENED
0.1s
2.00V LCM
0.1s
2.00V OVD
6
_____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Pin Description
PINS BY
CHANNEL (n)
FUNCTION
NAME
CH 1 CH 2
MOSFET A Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel
is unused.
GAn
GBn
15
16
17
18
25
26
27
28
MOSFET B Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel
is unused.
Lamp Current Monitor Input. Lamp current is monitored by a resistor placed in series with the low-voltage
side of the lamp. Leave open if channel is unused.
LCMn
OVDn
Overvoltage Detection. Lamp voltage is monitored by a capacitor divider placed on the high-voltage side
of the transformer. Leave open if channel is unused.
NAME
FAULT
A0
PIN
1
FUNCTION
Active-Low Fault Output. This open-drain pin requires external pullup resistor to realize high logic levels.
2
2
Address Select Input. Determines I C slave address.
2
Serial-Data Input/Output. I C bidirectional data pin, which requires a pullup resistor to realize high logic
levels.
SDA
SCL
3
4
2
Serial Clock Input. I C clock input.
Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency
when the DS3882 is configured as a lamp frequency receiver. If the DS3882 is configured as a lamp
frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for
use by other lamp frequency receiver DS3882s.
LSYNC
5
Lamp Oscillator Resistor Adjust. A resistor to ground on this pin sets the frequency of the internal lamp
oscillator.
LOSC
6
7
BRIGHT
Analog Brightness Control Input. Used to control the DPWM dimming feature. Ground if unused.
DPWM Input/Output. This pin is the input for an externally generated DPWM signal when the
DS3882 is configured as a DPWM receiver. If the DS3882 is configured as a DPWM source (i.e., the
DPWM signal is generated internally), the DPWM signal is output on this pin for use by other DPWM
receiver DS3882s.
PSYNC
8
_____________________________________________________________________
7
Dual-Channel Automotive CCFL Controller
Pin Description (continued)
NAME
PIN
FUNCTION
DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM
oscillator. This lead can optionally accept a 22.5Hz to 440Hz clock that will become the source timing of
the internal DPWM signal.
POSC
9
2
A1
10
11
Address Select Input. Determines I C slave address.
2
GND_S
SVML
SVMH
I C Interface Ground Connection. GND_S must be at the same potential as GND.
12
Low-Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions.
High-Supply Voltage Monitor Input. Used to monitor the inverter voltage for overvoltage conditions.
Power-Supply Connections. Both pins must be connected.
13
V
14, 24
19
CC
N.C.
STEP
GND
No Connection. Do not connect any signal to this pin.
Lamp Frequency Step Input. This active-high digital input moves the lamp oscillator frequency up or
down by 1ꢀ, 2ꢀ, 3ꢀ, or 4ꢀ as configured in the EMIC register. This pin is logically ORed with
the STEPE bit in the EMIC register.
20
21
Ground Connection
Lamp Current Overdrive Enable Input. A high digital level at this input enables the lamp current
overdrive circuit. The amount of overdrive current is configured by the LCOC register. When this input is
low, the lamp current is set to its nominal level. This pin is logically ORed with the LCOE bit in the LCOC
register.
LCO
PDN
22
23
Lamp On/Off Control Input. A low digital level at this input turns the lamp on. A high digital level turns the
lamps off, clears the fault logic, and places the device into the power-down mode. The high-to-low
transition on this input issues a controller reset, which clears the fault logic and reinitiates a lamp strike.
This pin is logically ORed with the PDNE bit in the CR2 register.
8
_____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Functional Diagrams
V
CC
[4.75V TO 5.25V]
PDN
UVLO
VREF
EEPROM
LCO
SDA
SCL
SVML
SUPPLY VOLTAGE
MONITOR—LOW
SYSTEM
CONTROL REGISTERS
2.0V
2.0V
ENABLE/
POR
8 BYTE USER MEMORY
STATUS REGISTERS
2
2
I C
I C DEVICE
SVMH
SUPPLY VOLTAGE
MONITOR—HIGH
A0/A1
GND_S
INTERFACE
CONFIGURATION AND
CONTROL PORT
FAULT
CHANNEL FAULT
CHANNEL ENABLE
FAULT
HANDLING
LCMn
LAMP CURRENT
MONITOR
LSYNC
STEP
[40kHz ~ 100kHz]
LAMP FREQUENCY
INPUT/OUTPUT
x512
[20.48MHz ~ 51.20MHz]
PLL
OVDn
OVERVOLTAGE
DETECTION
LFSS BIT
AT CR1.2
TWO
STEP LAMP FREQUENCY
UP OR DOWN
INDEPENDENT
CCFL
CONTROLLERS
LOSC
40kHz TO 100kHz
OSCILLATOR ( 5%)
EXTERNAL RESISTOR
LAMP FREQUENCY SET
DS3882
DPSS BIT
AT CR1.3
MUX
RGSO BIT
AT CR1.4
GAn
MOSFET
PSYNC
DPWM SIGNAL
INPUT/OUTPUT
GATE
GBn
DRIVERS
MUX
DPSS BIT
AT CR1.3
BRIGHT
POSC
ANALOG BRIGHTNESS
CONTROL
DPWM
SIGNAL
EXTERNAL RESISTOR
DPWM FREQUENCY
SET/DPWM CLOCK INPUT
MUX
POSCS BIT
AT CR1.1
RAMP
GENERATOR
22.5Hz TO
440Hz
OSCILLATOR
( 5%)
GND
22.5Hz TO 440Hz
Figure 1. Functional Diagram
_____________________________________________________________________
9
Dual-Channel Automotive CCFL Controller
Functional Diagrams (continued)
LAMP OUT
300mV
2.5V
LCMn
LAMP CURRENT
MONITOR
CHANNEL ENABLE
CHANNEL FAULT
LAMP OVERCURRENT
LOCE BIT IN CR1.0
DIGITAL
CCFL
CONTROLLER
LAMP STRIKE AND REGULATION
V
(1.0V NOMINAL)
OVDn
LRT
OVERVOLTAGE
64 LAMP CYCLE
INTEGRATOR
DIMMING PWM SIGNAL
OVERVOLTAGE DETECTOR
512 X LAMP FREQUENCY
[20.48MHz ~ 51.20MHz]
1.0V
LAMP MAXIMUM VOLTAGE REGULATION
GAn
GBn
MOSFET
GATE
DRIVERS
LAMP FREQUENCY
[40kHz ~ 80kHz]
GATE
DRIVERS
Figure 2. Per Channel Logic Diagram
mine the duty cycle for the MOSFET gates. Each CCFL
receives independent current monitoring and control,
which maximizes the lamp’s brightness and lifetime.
Detailed Description
The DS3882 uses a push-pull drive scheme to convert
a DC voltage (8V to 16V) to the high-voltage (300V
RMS
Block diagrams of the DS3882 are shown in Figures 1
and 2. More operating details of the DS3882 are dis-
cussed on the following pages of this data sheet.
to 1000V
) AC waveform that is required to power
RMS
the CCFLs. The push-pull drive scheme uses a minimal
number of external components, which reduces assem-
bly cost and makes the printed circuit board design
easy to implement. The push-pull drive scheme also
provides an efficient DC-to-AC conversion and pro-
duces near-sinusoidal waveforms.
Memory Registers and
2
I C-Compatible Serial Interface
2
The DS3882 uses an I C-compatible serial interface for
communication with the on-board EEPROM and SRAM
configuration/status registers as well as user memory.
The configuration registers, which are a mixture of
shadowed EEPROM and SRAM, allow the user to cus-
tomize many DS3882 parameters such as the soft-start
ramp rate, the lamp and dimming frequency sources,
brightness of the lamps, fault-monitoring options, chan-
nel enabling/disabling, EMI control, and lamp current
overdrive control. The eight bytes of NV user memory
can be used to store manufacturing data such as date
codes, serial numbers, or product identification num-
bers. The device is shipped from the factory with the
configuration registers programmed to a set of default
configuration parameters. To inquire about custom pro-
gramming, contact the factory.
Each DS3882 channel drives two logic-level n-channel
MOSFETs that are connected between the ends of a
step-up transformer and ground (see the Typical
Operating Circuit). The transformer has a center tap on
the primary side that is connected to a DC voltage sup-
ply. The DS3882 alternately turns on the two MOSFETs
to create the high-voltage AC waveform on the sec-
ondary side. By varying the duration of the MOSFET
turn-on times, the CCFL current is able to be accurately
controlled.
A resistor in series with the CCFL’s ground connection
enables current monitoring. The voltage across this
resistor is fed to the lamp current monitor (LCM) input
and compared to an internal reference voltage to deter-
10
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
(40kHz to 100kHz) as shown in Figure 6. This part of
the cycle is called the “burst” period because of the
lamp frequency burst that occurs during this time.
During the low period of the DPWM cycle, the controller
disables the MOSFET gate drivers so the lamps are not
driven. This causes the current to stop flowing in the
lamps, but the time is short enough to keep the lamps
from de-ionizing.
Shadowed EEPROM
The DS3882 incorporates SRAM-shadowed EEPROM
memory locations for all memory that needs to be
retained during power cycling. At power-up, SEEB (bit 7
of the BLC register) is low which causes the shadowed
locations to act as ordinary EEPROM. Setting SEEB
high disables the EEPROM write function and causes
the shadowed locations to function as ordinary SRAM
cells. This allows an infinite number of write cycles with-
out causing EEPROM damage and also eliminates the
The DS3882 can generate its own DPWM signal inter-
nally (set DPSS = 0 in CR1), which can then be
sourced to other DS3882s if required, or the DPWM sig-
nal can be supplied from an external source (set DPSS
= 1 in CR1). To generate the DPWM signal internally,
the DS3882 requires a clock (referred to as the dim-
ming clock) to set the DPWM frequency. The user can
supply the dimming clock by setting POSCS = 1 in CR1
and applying an external 22.5Hz to 440Hz signal at the
POSC pin, or the dimming clock can be generated by
the DS3882’s internal oscillator (set POSCS = 0 in
CR1), in which case the frequency is set by an external
resistor at the POSC pin. These two dimming clock
options are shown in Figure 3. Regardless of whether
the dimming clock is generated internally or sourced
externally, the POSC0 and POSC1 bits in CR2 must be
set to match the desired dimming clock frequency.
EEPROM write time, t from the write cycle. Because
W
memory changes made when SEEB is set high are not
written to EEPROM, these changes are not retained
through power cycles, and the power-up EEPROM values
are the last values written with SEEB low.
Channel Phasing
The lamp-frequency MOSFET gate turn-on times are
out of phase between the two channels during the burst
period. This reduces the inrush current that would
result from all lamps switching simultaneously, and
hence eases the design requirements for the DC sup-
ply. It is important to note that it is the lamp-frequency
signals that are phased, not the DPWM (burst) signals.
Lamp Dimming Control
The DS3882 provides two independent methods of
lamp dimming that can be combined to achieve a dim-
ming ratio of 300:1 or greater. The first method is
“burst” dimming, which uses a digital pulse-width-mod-
ulated (DPWM) signal (22.5Hz to 440Hz) to control the
lamp brightness. The second is “analog” dimming,
which is accomplished by adjusting the lamp current.
Burst dimming provides 128 linearly spaced brightness
steps. Analog dimming provides smaller substeps that
allow incremental brightness changes between burst
dimming steps. This ability is especially useful for low-
brightness dimming changes, where using burst dim-
ming alone would cause visible brightness step
changes. Analog dimming also allows the brightness to
be reduced below the minimum burst dimming level,
which provides for the maximum dimming range.
The internally generated DPWM signal can be provided
at the PSYNC I/O pin (set RGSO = 0 in CR1) for sourc-
ing to other DS3882s, if any, in the circuit. This allows
all DS3882s in the system to be synchronized to the
same DPWM signal. A DS3882 that is generating the
DPWM signal for other DS3882s in the system is
referred to as the DPWM source. When bringing in an
externally generated DPWM signal, either from another
DS3882 acting as a DPWM source or from some other
user-provided source, it is input into the PSYNC I/O pin
of the DS3882, and the receiving DS3882 is referred to
a DPWM receiver. In this mode, the BRIGHT and POSC
inputs are disabled and should be grounded (see
Figure 5).
When the DPWM signal is generated internally, its duty
cycle (and, thus, the lamp brightness) is controlled
either by a user-supplied analog voltage at the BRIGHT
Burst dimming can be controlled using a user-supplied
2
analog voltage on the BRIGHT pin or through the I C
2
input or through the I C interface by varying the 7-bit
interface. Analog dimming can only be controlled
PWM code in the BPWM register. When using the
BRIGHT pin to control burst dimming, a voltage of less
than 0.5V causes the DS3882 to operate with the mini-
mum burst duty cycle, providing the lowest brightness
setting, while any voltage greater than 2.0V causes a
100ꢀ burst duty cycle (i.e., lamps always being dri-
ven), which provides the maximum brightness. For
voltages between 0.5V and 2V, the duty cycle varies
linearly between the minimum and 100ꢀ. Writing a
2
through the I C interface. Therefore, for applications that
require the complete dimming range and resolution capa-
2
bility of the DS3882, I C dimming control must be used.
Burst Dimming
Burst dimming increases/decreases the brightness by
adjusting (i.e., modulating) the duty cycle of the DPWM
signal. During the high period of the DPWM cycle, the
lamps are driven at the selected lamp frequency
____________________________________________________________________ 11
Dual-Channel Automotive CCFL Controller
non-zero PWM code to the BPWM register disables the
an external resistor at the LOSC. In this case, the
2
BRIGHT pin and enables I C burst dimming control.
DS3882 can act as a lamp frequency source because
the lamp clock is output at the LSYNC I/O pin for
synchronizing any other DS3882s configured as lamp
frequency receivers. While DS3882 is sourcing lamp
frequency to other DS3882’s and spread-spectrum
modulation or frequency step features are enabled, the
LSYNC output is not affected by either EMI suppression
features. The DS3882 acts as a lamp frequency receiv-
er when the lamp clock is supplied externally. In this
case, a 40kHz to 100kHz clock must be supplied at the
LSYNC I/O. The external clock can originate from the
LSYNC I/O of a DS3882 configured as a lamp frequency
source or from some other source.
Setting the 7-bit PWM code to 0000001b causes the
DS3882 to operate with the minimum burst duty cycle,
while a setting of 1111111b causes a 100ꢀ burst duty
cycle. For settings between these two codes, the duty
cycle varies linearly between the minimum and 100ꢀ.
Analog Dimming
Analog dimming changes the brightness by increasing
or decreasing the lamp current. The DS3882 accom-
plishes this by making small shifts to the lamp regula-
tion voltage, V
(see Figure 2). Analog dimming is
LRT
only possible by software communication with the lower
five bits (LC4–LC0) in the BLC register. This function is
not pin controllable. The default power-on state of the
LC bits is 00000b, which corresponds to 100ꢀ of the
nominal current level. Therefore on power-up, analog
dimming does not interfere with burst dimming func-
tionality if it is not desired. Setting the LC bits to 11111b
reduces the lamp current to 35ꢀ of its nominal level. For
LC values between 11111b and 00000b, the lamp cur-
rent varies linearly between 35ꢀ and 100ꢀ of nominal.
DPWM RECEIVER
BRIGHT
DPWM
SIGNAL
PSYNC
Lamp Frequency Configuration
The DS3882 can generate its own lamp frequency
clock internally (set LFSS = 0 in CR1), which can then
be sourced to other DS3882s if required, or the lamp
clock can be supplied from an external source (set
LFSS = 1 in CR1). When the lamp clock is internally
generated, the frequency (40kHz to 100kHz) is set by
22.5Hz TO 440Hz
POSC
Figure 4. DPWM Receiver Configuration
RESISTOR-SET DIMMING CLOCK
EXTERNAL DIMMING CLOCK
2.0V
2.0V
ANALOG DIMMING
CONTROL VOLTAGE
ANALOG DIMMING
CONTROL VOLTAGE
BRIGHT
BRIGHT
0.5V
0.5V
DPWM
PSYNC
SIGNAL
DPWM
PSYNC
SIGNAL
22.5Hz TO 440Hz
22.5Hz TO 440Hz
POSC
POSC
EXTERNAL
DPWM CLOCK
EXTERNAL RESISTOR
SETS DPWM RATE
22.5Hz to 440Hz
Figure 3. DPWM Source Configuration Options
12
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
ANALOG
ANALOG
BRIGHTNESS
BRIGHTNESS
2.0V
2.0V
BRIGHT
PSYNC
BRIGHT
PSYNC
0.5V
0.5V
DS3882
DS3882
LAMP CLOCK
(40kHz TO 100kHz)
RESISTOR-SET
DIMMING
FREQUENCY
LSYNC
POSC
LSYNC
POSC
LOSC
LAMP FREQUENCY RECEIVER
DPWM SOURCE
LAMP FREQUENCY SOURCE
DPWM SOURCE
RESISTOR-SET
DIMMING FREQUENCY
N.C. LOSC
RESISTOR-SET
LAMP FREQUENCY
BRIGHT
PSYNC
BRIGHT
PSYNC
DS3882
DS3882
LSYNC
POSC
LSYNC
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
N.C.
N.C. POSC
N.C. LOSC
N.C. LOSC
ANALOG
BRIGHTNESS
0.5V
ANALOG
BRIGHTNESS
0.5V
2.0V
2.0V
BRIGHT
BRIGHT
PSYNC
PSYNC
LSYNC
POSC
DS3882
DS3882
LAMP CLOCK
(40kHz TO 100kHz)
LSYNC
POSC
LOSC
LAMP FREQUENCY RECEIVER
DPWM SOURCE
DIMMING CLOCK
(22.5Hz TO 440Hz)
LAMP FREQUENCY SOURCE
DPWM SOURCE
DIMMING CLOCK
(22.5Hz TO 440Hz)
LOSC
N.C.
RESISTOR-SET
LAMP FREQUENCY
BRIGHT
PSYNC
BRIGHT
PSYNC
LSYNC
DS3882
DS3882
LSYNC
POSC
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
N.C.
N.C.
POSC
N.C.
LOSC
N.C. LOSC
DPWM SIGNAL
BRIGHT
PSYNC
BRIGHT
DPWM SIGNAL
(22.5Hz TO 440Hz)
(22.5Hz TO 440Hz)
PSYNC
LSYNC
POSC
DS3882
DS3882
LSYNC
POSC
LAMP CLOCK
(40kHz TO 100kHz)
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
LAMP FREQUENCY SOURCE
DPWM RECEIVER
N.C.
N.C.
N.C. LOSC
RESISTOR-SET
LOSC
LAMP FREQUENCY
BRIGHT
BRIGHT
PSYNC
PSYNC
DS3882
DS3882
LSYNC
POSC
LSYNC
POSC
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
N.C.
N.C.
N.C.
N.C. LOSC
LOSC
Figure 5. Frequency Configuration Options for Designs Using Multiple DS3882s
____________________________________________________________________ 13
Dual-Channel Automotive CCFL Controller
gate-driver duty cycle (see Figure 6). This minimizes
Configuring Systems
with Multiple DS3882s
the possibility of audible transformer noise that could
result from current surges in the transformer primary.
The soft-start length is fixed at 16 lamp cycles, but the
soft-start ramp profile is programmable through the four
soft-start profile registers (SSP1/2/3/4) and can be
adjusted to match the application. There are seven dif-
ferent driver duty cycles to select from to customize the
soft-start ramp (see Tables 5a and 5b). The available
duty cycles range from 0ꢀ to 19ꢀ in ~3ꢀ increments.
In addition, the MOSFET duty cycle from the last lamp
cycle of the previous burst can be used as part of the
soft-start ramp by using the most recent value duty cycle
code. Each programmed MOSFET gate duty cycle
repeats twice to make up the 16 soft-start lamp cycles.
The source and receiver options for the lamp frequency
clock and DPWM signal allow multiple DS3882s to be
synchronized in systems requiring more than two
lamps. The lamp and dimming clocks can either be
generated on board the DS3882 using external resis-
tors to set the frequency, or they can be sourced by the
host system to synchronize the DS3882 to other system
resources. Figure 5 shows various multiple DS3882
configurations that allow both lamp and/or DPWM syn-
chronization for all DS3882s in the system.
DPWM Soft-Start
At the beginning of each lamp burst, the DS3882 pro-
vides a soft-start that slowly increases the MOSFET
DPWM SIGNAL
22.5Hz TO 440Hz
LAMP CURRENT
SOFT-START
SOFT-START (EXPANDED)
LAMP CYCLE
GAn/GBn
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MOSFET GATE DRIVERS
SSP2. 4-7
SSP4. 0-3
SSP4. 4-7
SOFT-START PROFILE REGISTER
SSP1. 4-7
SSP2. 0-3
SSP3. 4-7
SSP1. 0-3
SSP3. 0-3
PROGRAMMABLE SOFT-START PROFILE WITH INCREASING MOSFET PULSE WIDTHS OVER
A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT.
LAMP CURRENT
Figure 6. Digital PWM Dimming and Soft-Start
14
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
reaching the strike voltage and could potentially cause
numerous other problems. Operating with the trans-
former voltage at too high of a level can be damaging
to the inverter components. Proper use of the SVMs
can prevent these problems. If desired, the high and/or
low SVMs can be disabled by connecting the SVMH
Setting the Lamp and Dimming
Clock (DPWM) Frequencies
Using External Resistors
Both the lamp and dimming clock frequencies can be
set using external resistors. The resistance required for
either frequency can be determined using the following
formula:
pin to GND and the SVML pin to V
.
CC
K
R
1
+ R
R
1
2
R
=
V
TRIP
= 2.0
OSC
f
OSC
The V
monitor is used as a 5V supply undervoltage
CC
where K = 1600kΩ • kHz for lamp frequency calculations.
When calculating the resistor value for the dimming clock
frequency, K will be one of four values as determined by
the desired frequency and the POSCR0 and POSCR1 bit
settings as shown in the Control Register 2 (CR2) Table 7
in the Detailed Register Descriptions section.
lockout (UVLO) that prevents operation when the
DS3882 does not have adequate voltage for its analog
circuitry to operate or to drive the external MOSFETs.
The V
monitor features hysteresis to prevent V
CC
CC
noise from causing spurious operation when V
is
CC
near the trip point. This monitor cannot be disabled by
any means.
Example: Selecting the resistor values to configure a
DS3882 to have a 50kHz lamp frequency and a 160Hz
dimming clock frequency: For this configuration,
POSCR0 and POSCR1 must be programmed to 1 and
0, respectively, to select 90Hz to 220Hz as the dimming
clock frequency range. This sets K for the dimming
Fault Monitoring
The DS3882 provides extensive fault monitoring for
each channel. It can detect open-lamp, lamp overcur-
rent, failure to strike, and overvoltage conditions. The
DS3882 can be configured to disable all channels if
one or more channels enter a fault state or it can be
configured to disable only the channel where the fault
occurred. Once a fault state has been entered, the
FAULT output is asserted and the channel(s) remains
disabled until it is reset by a user or host control event.
See Step 4, Fault Handling for more detail. The DS3882
can also be configured to automatically attempt to clear
a detected fault (except lamp overcurrent) by re-striking
the lamp. Configuration bits for the fault monitoring
options are located in CR1 and CR2. The DS3882 also
has real-time status indicators bits located in the SR1
and SR2 register (SRAM) that assert whenever a corre-
sponding fault occurs.
clock resistor (R
) calculation to 4kΩ • kHz. For the
POSC
lamp frequency resistor (R
) calculation, K =
LOSC
1600kΩ • kHz, which sets the lamp frequency K value
regardless of the frequency. The formula above can
now be used to calculate the resistor values for R
LOSC
and R
as follows:
POSC
1600kΩ • kHz
R
=
= 32.0kΩ
LOSC
R
50kHz
4kΩ • kHz
0.160kHz
=
= 25.0kΩ
POSC
Supply Monitoring
The DS3882 has supply voltage monitors (SVMs) for
both the inverter’s transformer DC supply (V ) and its
INV
own V
supply to ensure that both voltage levels are
CC
V
V
INV
INV
adequate for proper operation. The transformer supply
is monitored for overvoltage conditions at the SVMH pin
and undervoltage conditions at the SVML pin. External
resistor-dividers at each SVM input feed into two com-
parators (see Figure 7), both having 2V thresholds.
Using the equation below to determine the resistor val-
R
R
2
2
DS3882
SVML
2.0V
SVMH
2.0V
V
V
TRIP
TRIP
R
R
1
1
ues, the SVMH and SVML trip points (V
) can be
TRIP
customized to shut off the inverter when the trans-
former’s supply voltage rises above or drops below
specified values. Operating with the transformer’s sup-
ply at too low of a level can prevent the inverter from
Figure 7. Setting the SVM Threshold Voltage
____________________________________________________________________ 15
Dual-Channel Automotive CCFL Controller
Figure 8 shows a flowchart of how the DS3882 controls
and monitors each lamp. The steps are as follows:
LSC1 bits in CR2. If lamp current ever drops below the
lamp out reference point for the period as defined by
the LST0 and LST1 control bits in the SSP1 register,
then the lamp is considered extinguished. In this case,
the MOSFET gate drivers are disabled and the device
moves to the fault handling stage.
1) Supply Check—The lamps do not turn on unless the
DS3882 supply voltage is above 4.3V and the volt-
age at the supply voltage monitors, SVML and SVMH,
are respectively above 2.0V and below 2.0V.
4) Fault Handling—During fault handling, the DS3882
performs an optional (user-selectable) automatic
retry to attempt to clear all faults except a lamp over-
current. The automatic retry makes 14 additional
attempts to rectify the fault before declaring the
channel in a fault state and permanently disabling
the channel. Between each of the 14 attempts, the
controller waits 1024 lamp cycles. In the case of a
lamp overcurrent, the DS3882 instantaneously
declares the channel to be in a fault state and per-
manently disables the channel. The DS3882 can be
configured to disable all channels if one or more
channels enter a fault state or it can be configured to
disable only the channel where the fault occurred.
Once a fault state is entered, the channel remains in
that state until one of the following occurs:
2) Strike Lamp—When both the DS3882 and the DC
inverter supplies are at acceptable levels, the
DS3882 attempts to strike each enabled lamp. The
DS3882 slowly ramps up the MOSFET gate duty
cycle until the lamp strikes. The controller detects
that the lamp has struck by detecting current flow in
the lamp, detected by the LCMn pin. If during the
strike ramp, the maximum allowable voltage is
reached on the OVDn pin, the controller stops
increasing the MOSFET gate duty cycle to keep from
overstressing the system. The DS3882 goes into a
fault handling state (step 4) if the lamp has not struck
after the timeout period as defined by the LST0 and
LST1 control bits in the SSP1 register. If an overvolt-
age event is detected during the strike attempt, the
DS3882 disables the MOSFET gate drivers and go
into the fault handling state.
• V
drops below the UVLO threshold.
CC
3) Run Lamp—Once the lamp is struck, the DS3882
adjusts the MOSFET gate duty cycle to optimize the
lamp current. The gate duty cycle is always con-
strained to keep the system from exceeding the
maximum allowable lamp voltage. The lamp current
sampling rate is user-selectable using the LSC0 and
• The SVML or SVMH thresholds are crossed.
• The PDN pin goes high.
• The PDNE software bit is written to a logic 1.
• The channel is disabled by the CH1D or CH2D
control bit.
16
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
DEVICE AND
INVERTER SUPPLIES
AT PROPER LEVELS?
FAULT STATE
[ACTIVATE FAULT OUTPUT]
YES
SET FAULT_L
AND FAULT_RT
STATUS BITS
RESET FAULT COUNTER
AND FAULT OUTPUT
YES
NO
NO
FAULT WAIT
[1024 LAMP CYCLES]
YES
AUTORETRY ENABLED?
[ARD BIT AT CR1.5]
FAULT COUNTER = 15?
CLEAR
FAULT_RT
STATUS BIT
INCREMENT FAULT
COUNTER / SET
FAULT_RT STATUS BIT
STRIKE LAMP
[RAMP AND REGULATE TO
OVD THRESHOLD]
LAMP STRIKE TIMEOUT
[SEE REGISTER SSP1]
SET STO_L
STATUS BIT
SET OV_L
STATUS BIT
OVERVOLTAGE
[64 LAMP CYCLES]
IF LAMP REGULATION
THRESHOLD IS MET
RUN LAMP
LAMP OVERCURRENT
[INSTANTANEOUS IF
ENABLED BY THE
[REGULATE LAMP
CURRENT BOUNDED BY
LAMP VOLTAGE]
LAMP OUT TIMEOUT
[SEE REGISTER SSP1]
SET LOUT_L
STATUS BIT
LOCE BIT AT CR1.0]
MOSFET GATE DRIVERS ENABLED
SET LOC_L
STATUS BIT
Figure 8. Fault-Handling Flowchart
____________________________________________________________________ 17
Dual-Channel Automotive CCFL Controller
EMI Suppression Functionality
The DS3882 contains two electromagnetic interference
suppression features: spread-spectrum modulation and
lamp oscillator frequency stepping. The first is the abili-
ty to spread the spectrum of the lamp frequency. By
setting either SS0 and/or SS1 in EMIC register, the con-
troller can be configured to dither the lamp frequency
by 1.5ꢀ, 3ꢀ, or 6ꢀ. By setting a non-zero value in
SS0/1, spread-spectrum modulation is enabled and
oscillator frequency stepping is disabled. In spread-
spectrum modulation mode the dither modulation rate
is also selectable by setting FS0/1/2, and has either a
triangular (SSM = 0) or a pseudorandom profile (SSM =
1). Users have the flexibility to choosing the best modu-
lation rate (through FS0/1/2) for the application.
Lamp Current Overdrive Functionality
Another feature the DS3882 offers is the ability to over-
drive the lamps to allow them to heat up quickly in cold
environments. After setting the LCO0/1/2 bits in the
LCOC register and enabling the LCOE bit or LCO pin,
the DS3882 overdrives the nominal current settings in
12.5ꢀ steps from 112.5ꢀ up to 200ꢀ. The DS3882
accomplishes this by automatically shifting the lamp
regulation threshold, V
, upward to allow more cur-
LRT
rent to flow in the lamps (Figure 2). This multilevel
adjustment makes it possible to slowly decrease the
2
current overdrive (through I C) after the lamps have
warmed up, so the end user does not see any change
in brightness when the overdrive is no longer needed.
The DS3882 also features an optional timer capable of
automatically turning off the current overdrive. This
timer is adjustable from approximately 1.5 minutes to
21 minutes (if a 50kHz lamp frequency is used).
The second EMI suppression scheme is the ability to
move the lamp frequency up or down by 1ꢀ, 2ꢀ, 3ꢀ,
or 4ꢀ. In this scheme, the actual radiated EMI is not
reduced but it is moved out of a sensitive frequency
region. STEPE bit and/or STEP pin is used to enable
lamp frequency stepping (SS0/1 must be 0). Once
enabled, the FS0/1/2 value controls the lamp oscillator
frequency shift. For example, if the lamp frequency cre-
ates EMI disturbing an audio radio station, it can be
moved up or down slightly to slide the spurious interfer-
er out of band.
Detailed Register Descriptions
The DS3882’s register map is shown in Table 1.
Detailed register and bit descriptions follow in the sub-
sequent tables.
Table 1. Register Map
BYTE
BYTE FACTORY
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDRESS NAME DEFAULT
E0h
E1h
E2h
E3h
SR1
SR2
00h
00h
00h
1Fh
SVMH_RT SVML_RT LOC_L1 LOUT_L1 OV_L1 STO_L1 FAULT_L1
FAULT_RT1
FAULT_RT2
PWM0
RSVD
RSVD
SEEB
RSVD
PWM6
CH2D
LOC_L1 LOUT_L2 OV_L2 STO_L2 FAULT_L2
BPWM
BLC
PWM5
CH1D
PWM4
LC4
PWM3
LC3
PWM2
LC2
PWM1
LC1
LC0
MDC code for soft-start lamp
cycles 3, 4
F0h
SSP1
21h
LST1
LST0
MDC code for soft-start lamp cycles 1, 2
F1h
F2h
SSP2
SSP3
SSP4
CR1
43h
65h
77h
00h
08h
00h
00h
00h
MDC code for soft-start lamp cycles 7, 8
MDC code for soft-start lamp cycles 11, 12
MDC code for soft-start lamp cycles 15, 16
MDC code for soft-start lamp cycles 5, 6
MDC code for soft-start lamp cycles 9, 10
MDC code for soft-start lamp cycles 13, 14
F3h
F4h
DPD
PDNE
FS2
FRS
RSVD
FS1
ARD
RSVD
FS0
RGSO
LSR1
STEPE
TO0
DPSS
LFSS
POSCS
LOCE
UMWP
SS0
F5h
CR2
LSR0 POSCR1 POSCR0
F6h
EMIC
LCOC
USER
RSVD
LCOE
EE
SSM
LCO2
EE
SS1
LCO1
EE
F7h
TO3
EE
TO2
EE
TO1
EE
LCO0
EE
F8h–FFh
EE
Note 1: E0h–E3h are SRAM locations, and F0h–FFh are SRAM-shadowed EEPROM.
Note 2: Altering DS3882 configuration during active CCFL operation can cause serious adverse effects.
Note 3: The BPWM, BLC, and LCOC registers control both channels of the DS3882.
18
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Table 2. Status Register 1 (SR1) [SRAM, E0h]
POWER-UP
DEFAULT
BIT R/W
NAME
FUNCTION
Fault Condition—Real Time. A real-time bit that indicates the current operating status of
channel 1.
0 = Normal condition
1 = Fault condition
0
R
0
FAULT_RT
Fault Condition—Latched. A latched bit that is set when the channel enters a fault
condition. This bit is cleared when read, regardless of the current state of fault.
1
2
3
4
5
6
7
R
R
R
R
R
R
R
0
0
0
0
0
0
0
FAULT_L
STO_L
Lamp Strike Timeout—Latched. A latched bit that is set when the lamp fails to strike.
This bit is cleared when read.
Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present for
at least 64 lamp cycles. This bit is cleared when read.
OV_L
Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is
cleared when read.
LOUT_L
LOC_L
Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is
detected. This bit is cleared when read.
Supply Voltage Monitor Low—Real Time. A real-time bit that reports the comparator
output of the SVML pin.
SVML_RT
SVMH_RT
Supply Voltage Monitor High—Real Time. A real-time bit that reports the comparator
output of the SVMH pin.
Note 1: Writing to this register has no effect on it.
Note 2: See Figure 8 for more details on how the status bits are set.
Note 3: SR1 is cleared when any of the following occurs:
• V
drops below the UVLO threshold
• the SVML or SVMH thresholds are crossed
CC
• the PDN hardware pin goes high
• the PDNE software bit is written to a logic 1
• the channel is disabled by the CH1D control bit
____________________________________________________________________ 19
Dual-Channel Automotive CCFL Controller
Table 3. Status Register 2 (SR2) [SRAM, E1h]
POWER-UP
DEFAULT
BIT
R/W
NAME
FUNCTION
Fault Condition—Real Time. A real-time bit that indicates the current operating status
of channel 2.
0 = Normal condition
1 = Fault condition
0
R
0
FAULT_RT
Fault Condition—Latched. A latched bit that is set when the channel enters a fault
condition. This bit is cleared when read regardless of the current state of fault.
1
2
3
4
5
R
R
R
R
R
0
0
0
0
0
FAULT_L
STO_L
OV_L
Lamp Strike Time Out—Latched. A latched bit that is set when the lamp fails to strike.
This bit is cleared when read.
Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present
for at least 64 lamp cycles. This bit is cleared when read.
Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is
cleared when read.
LOUT_L
LOC_L
Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is
detected. This bit is cleared when read.
6
7
R
R
0
0
RSVD
RSVD
Reserved. Could be either 0 or 1 when read.
Reserved. Could be either 0 or 1 when read.
Note 1: Writing to this register has no effect on it.
Note 2: See Figure 8 for more details on how the status bits are set.
Note 3: SR2 is cleared when any of the following occurs:
• V
drops below the UVLO threshold
• the SVML or SVMH thresholds are crossed
CC
• the PDN hardware pin goes high
• the PDNE software bit is written to a logic 1
• the channel is disabled by the CH2D control bit
Table 4. Brightness Lamp Current Register (BLC) [SRAM, E3h]
FACTORY
DEFAULT
BIT
R/W
NAME
FUNCTION
0
1
2
3
4
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
LC0
LC1
LC2
LC3
LC4
These five control bits determine the target value for the lamp current. 11111b is
35ꢀ of the nominal level and 00000b is 100ꢀ of the nominal level. These control
bits are used for fine adjustment of the lamp brightness.
Channel 1 Disable
5
6
7
R/W
R/W
R/W
0
0
0
CH1D
CH2D
SEEB
0 = Channel 1 enabled
1 = Channel 1 disabled
Channel 2 Disable. Useful for dimming in two lamp applications.
0 = Channel 2 enabled
1 = Channel 2 disabled
SRAM-Shadowed EEPROM Write Control
0 = Enables writes to EEPROM
1 = Disables writes to EEPROM
20
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Table 5a. Soft-Start Protocol Registers (SSPx) [Shadowed-EEPROM, F0h, F1h, F2h, F3h]
MSB
7
LSB
FACTORY
DEFAULT
SSP#
ADDR
6
5
4
3
2
1
0
SSP1
F0h
F1h
F2h
F3h
21h
43h
65h
77h
LST1
RSVD
RSVD
RSVD
Lamp Cycles 3 and 4
Lamp Cycles 7 and 8
Lamp Cycles 11 and 12
Lamp Cycles 15 and 16
LST0
RSVD
RSVD
RSVD
Lamp Cycles 1 and 2
Lamp Cycles 5 and 6
Lamp Cycles 9 and 10
Lamp Cycles 13 and 14
SSP2
SSP3
SSP4
Table 5b. MOSFET Duty Cycle (MDC)Codes for Soft-Start Settings
BIT R/W
NAME
FUNCTION
0
R/W
MDC0
MDC0/1/2: These bits determine a MOSFET duty cycle that will repeat twice in the
16 lamp cycle soft-start.
1
2
R/W
R/W
MDC1
MDC2
MDC CODE
MOSFET DUTY CYCLE
Fixed at 0ꢀ
MDC CODE
MOSFET DUTY CYCLE
Fixed at 13ꢀ
0h
1h
2h
3h
4h
5h
6h
7h
Fixed at 3ꢀ
Fixed at 16ꢀ
Fixed at 6ꢀ
Fixed at 19ꢀ
3
R/W LST0 / RSVD
Fixed at 9ꢀ
Most Recent Value
LST0/1: These bits select strike and lamp-out timeout. LST0 and LST1
control fault behavior for all lamps.
4
5
6
7
R/W
R/W
R/W
MDC0
MDC1
MDC2
STRIKE AND LAMP-OUT TIMEOUT
(LAMP FREQUENCY CYCLES)
EXAMPLE TIMEOUT IF
LAMP FREQUENCY IS 50kHz
LST1
LST0
0
0
1
1
0
1
0
1
32,768
65,536
98,304
131,072
0.66 Seconds
1.31 Seconds
1.97 Seconds
2.62 Seconds
R/W LST1 / RSVD
____________________________________________________________________ 21
Dual-Channel Automotive CCFL Controller
Table 6. Control Register 1 (CR1) [Shadowed-EEPROM, F4h]
FACTORY
DEFAULT
BIT
R/W
NAME
FUNCTION
Lamp Overcurrent Enable
0 = Lamp overcurrent detection disabled.
1 = Lamp overcurrent detection enabled.
0
R/W
0
LOCE
POSC Select. See POSCR0 and POSCR1 control bits in Control Register 2 to select
the oscillator range.
1
R/W
0
POSCS
0 = POSC input is connected with a resistor to ground to set the frequency of the
internal PWM oscillator.
1 = POSC input is a 22.5Hz to 440Hz clock.
Lamp Frequency Source Select
0 = Lamp frequency generated internally and sourced from the LSYNC output.
1 = Lamp frequency generated externally and supplied to the LSYNC input.
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
LFSS
DPSS
RGSO
ARD
DPWM Signal Source Select
0 = DPWM signal generated internally and sourced from the PSYNC output.
1 = DPWM signal generated externally and supplied to the PSYNC input.
Ramp Generator Source Option
0 = Source DPWM at the PSYNC output.
1 = Source internal ramp generator at the PSYNC output.
Autoretry Disable
0 = Autoretry function enabled.
1 = Autoretry function disabled.
Fault Response Select
0 = Disable only the malfunctioning channel.
1 = Disable both channels upon fault detection on any channel.
FRS
DPWM Disable
0 = DPWM function enabled.
1 = DPWM function disabled.
DPD
22
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Table 7. Control Register 2 (CR2) [Shadowed-EEPROM, F5h]
BIT
R/W
DEFAULT
NAME
FUNCTION
User Memory Write Protect
0 = Write access blocked.
1 = Write access permitted.
0
R/W
0
UMWP
DPWM Oscillator Range Select. When using an external source for the dimming clock,
these bits must be set to match the external oscillator’s frequency. When using a
resistor to set the dimming frequency, these bits plus the external resistor control the
frequency.
1
2
R/W
R/W
0
0
POSCR0
POSCR1
DIMMING CLOCK (DPWM)
FREQUENCY RANGE (Hz)
POSCR1
POSCR0
k (kΩ • kHz)
0
0
1
1
0
1
0
1
22.5 to 55.0
1
2
4
8
45 to 110
90 to 220
180 to 440
Lamp Sample Rate Select. Determines the feedback sample rate of the LCM inputs.
EXAMPLE SAMPLE RATE
SELECTED LAMP SAMPLE
3
4
R/W
R/W
1
0
LSR0
LSR1
IF LAMP FREQUENCY IS
50kHz
LSR1
LSR0
RATE
0
0
1
1
0
1
0
1
4 Lamp Frequency Cycles
8 Lamp Frequency Cycles
16 Lamp Frequency Cycles
32 Lamp Frequency Cycles
12,500Hz
6,250Hz
3,125Hz
1,563Hz
5
6
—
—
0
0
RSVD
RSVD
Reserved. This bit should be set to zero.
Reserved. This bit should be set to zero.
Power-Down. Logically ORed with the PDN pin. Setting this bit high resets the controller,
clears the fault logic, and places the part in power-down mode. 0 = Normal. All circuitry is
off, except I C interface.
7
R/W
0
PDNE
2
____________________________________________________________________ 23
Dual-Channel Automotive CCFL Controller
Table 8. EMI Control Register (EMIC) [Shadowed-EEPROM, F6h]
FACTORY
DEFAULT
BIT
R/W
NAME
FUNCTION
LAMP OSCILLATOR SPREAD-SPECTRUM MODULATION SELECT
0
R/W
0
SS0
SS1
0
SS0
0
SELECTED LAMP FREQUENCY SPREAD
Spread-Spectrum Disabled
0
1
1.5ꢀ
3.0ꢀ
6.0ꢀ
1
R/W
0
SS1
1
0
1
1
Lamp Oscillator Spread-Spectrum Modulation Select
0 = Triangular modulation.
1 = Pseudorandom modulation.
2
3
4
R/W
0
0
SSM
RSVD
Reserved. This bit should be set to zero.
Lamp Frequency Step Enable. Logically ORed with the Step Invoked.
STEPE 0 = Lamp operates at nominal frequency.
1 = Frequency step invoked.
R/W
LAMP OSCILLATOR FREQUENCY STEP SELECT
SELECTED LAMP
FREQUENCY STEP
(SS0 = 0 AND SS1= 0)
SPREAD-SPECTRUM
MODULATION RATE
(SS0 AND/OR SS1 = 1)
5
R/W
0
FS0
FS2
FS1
FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Step Up 1ꢀ
Step Up 2ꢀ
Lamp Frequency x4
Lamp Frequency x2
Lamp Frequency x1
Lamp Frequency x1/2
Lamp Frequency x1/4
Lamp Frequency x1/8
Lamp Frequency x1/16
Lamp Frequency x1/32
Step Up 3ꢀ
6
7
R/W
R/W
0
0
FS1
FS2
Step Up 4ꢀ
Step Down 1ꢀ
Step Down 2ꢀ
Step Down 3ꢀ
Step Down 4ꢀ
24
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Table 9. Lamp Current Overdrive Control Register (LCOC) [Shadowed-EEPROM, F7h]
FACTORY
DEFAULT
BIT
R/W
NAME
FUNCTION
LAMP CURRENT OVERDRIVE SELECT
LCO2 LCO1 LCO0
SELECTED LAMP CURRENT OVERDRIVE
0
R/W
0
LCO0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Nominal Current + 12.50ꢀ
Nominal Current + 25.00ꢀ
Nominal Current + 37.50ꢀ
Nominal Current + 50.00ꢀ
Nominal Current + 62.50ꢀ
Nominal Current + 75.00ꢀ
Nominal Current + 87.50ꢀ
Nominal Current + 100.00ꢀ
1
2
R/W
R/W
0
0
LCO1
LCO2
Lamp Current Overdrive Enable. Logically ORed with the LCO pin.
0 = Lamp operated with nominal current setting.
1 = Lamp overdrive invoked.
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
LCOE
TO0
TO1
TO2
TO3
AUTOMATIC LAMP CURRENT OVERDRIVE TIMEOUT SELECT
SELECTED TIMEOUT
IN LAMP FREQUENCY
CYCLES
EXAMPLE TIMEOUT IF
LAMP FREQUENCY IS
50kHz
TO3
TO2
TO1
TO0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
1 x 222
2 x 222
3 x 222
4 x 222
5 x 222
6 x 222
7 x 222
8 x 222
9 x 222
10 x 222
11 x 222
12 x 222
13 x 222
14 x 222
15 x 222
—
1.4 min
2.8 min
4.2 min
5.6 min
7.0 min
8.4 min
9.8 min
11.2 min
12.6 min
14.0 min
15.4 min
16.8 min
18.2 min
19.6 min
21.0 min
____________________________________________________________________ 25
Dual-Channel Automotive CCFL Controller
2
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 9). Data is
shifted into the device during the rising edge of the SCL.
I C Definitions
The following terminology is commonly used to
2
describe I C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 9) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The
device receiving data (the master during a read or the
slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 9) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition. See the timing diagram for applica-
ble timing.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit-write definition and the
acknowledgement is read using the bit-read definition.
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 9. I C Timing Diagram
26
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Byte Read: A byte read is an 8-bit information transfer
Acknowledge Polling: Any time EEPROM is written,
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minate communication so the slave will return control of
SDA to the master.
the DS3882 requires the EEPROM write time (t ) after
W
the stop condition to write the contents to EEPROM.
During the EEPROM write time, the DS3882 will not
acknowledge its slave address because it is busy. It is
possible to take advantage of that phenomenon by
repeatedly addressing the DS3882, which allows the
next byte of data to be written as soon as the DS3882 is
ready to receive the data. The alternative to acknowl-
edge polling is to wait for a maximum period of t to
W
elapse before attempting to write again to the DS3882.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte
(Figure 10) contains the slave address in the most sig-
nificant seven bits and the R/W bit in the least signifi-
EEPROM Write Cycles: The number of times the
DS3882’s EEPROM can be written before it fails is
specified in the Nonvolatile Memory Characteristics
table. This specification is shown at the worst-case
write temperature. The DS3882 is typically capable of
handling many additional write cycles when the writes
are performed at room temperature.
cant bit. The DS3882’s slave address is 10100A A 0
1
0
(binary), where A0 and A1 are the values of the
address pins (A0 and A1). The address pin allows the
device to respond to one of four possible slave
addresses. By writing the correct slave address with
R/W = 0, the master indicates it will write data to the
slave. If R/W = 1, the master will read data from the
slave. If an incorrect slave address is written, the
DS3882 will assume the master is communicating with
Reading a Data Byte from a Slave: To read a single
byte from the slave the master generates a start condi-
tion, writes the slave address byte with R/W = 0, writes
the memory address, generates a repeated start condi-
tion, writes the slave address with R/W = 1, reads the
data byte with a NACK to indicate the end of the trans-
fer, and generates a stop condition. See Figure 11 for
more detail.
2
another I C device and ignore the communications until
the next start condition is sent.
2
Memory Address: During an I C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
7-BIT SLAVE ADDRESS
0
1
0
0
A
1
R/W
1
A
0
2
I C Communication
Writing a Data Byte to a Slave: The master must gen-
erate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations. See Figure 11 for more detail.
MOST
SIGNIFICANT BIT
A
1,
A PIN VALUE
0
DETERMINES
READ OR WRITE
Figure 10. DS3882’s Slave Address Byte
____________________________________________________________________ 27
Dual-Channel Automotive CCFL Controller
NOTES
COMMUNICATIONS KEY
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
A
S
P
START
STOP
ACK
NOT
ACK
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
N
REPEATED
START
8-BITS ADDRESS OR DATA
X
X
X
X X X X X
SR
WRITE A SINGLE BYTE
S
A
A
1
0
1
0
0
A
A
A
A
0
0
A
MEMORY ADDRESS
MEMORY ADDRESS
DATA
1
P
A
1
0
READ A SINGLE BYTE
1
0
0
0
A
1
A
1
0
S
1
0
1
0
0
A
DATA
N
A
SR
P
1
0
2
Figure 11. I C Communications Examples
ratio should be selected so the MOSFET drivers run at
28ꢀ to 35ꢀ duty cycle during steady state operation.
The transformer must be able to withstand the high
open-circuit voltage that is used to strike the lamp.
Additionally, its primary/secondary resistance and induc-
tance characteristics must be considered because they
contribute significantly to determining the efficiency and
transient response of the system. Table 10 shows a
transformer specification that has been used for a 12V
inverter supply, 438mm x 2.2mm lamp design.
Applications Information
Addressing Multiple DS3882s
2
On a Common I C Bus
Each DS3882 responds to one of four possible slave
addresses based on the state of the address input pins
(A0 and A1). For information about device addressing,
2
see the I C Communications section.
Setting the RMS Lamp Current
Resistor R7 and R8 in the Typical Operating Circuit set
the lamp current. R7 and R8 = 140Ω corresponds to a
The n-channel MOSFET must have a threshold voltage
that is low enough to work with logic-level signals, a low
on-resistance to maximize efficiency and limit the n-
channel MOSFET’s power dissipation, and a break-
down voltage high enough to handle the transient. The
breakdown voltage should be a minimum of 3x the invert-
er voltage supply. Additionally, the total gate charge must
5mA
lamp current as long as the current waveform
RMS
is approximately sinusoidal. The formula to determine
the resistor value for a given sinusoidal lamp current is:
1
R
=
7 / 8
I
x
2
LAMP(RMS)
be less than Q , which is specified in the Recommended
G
DC Operating Conditions table. These specifications are
easily met by many of the dual n-channel MOSFETs now
available in 8-pin SO packages.
Component Selection
External component selection has a large impact on the
overall system performance and cost. The two most
important external components are the transformers
and n-channel MOSFETs.
Table 11 lists suggested values for the external resistors
and capacitors used in the Typical Operating Circuit.
The transformer should be able to operate in the 40kHz
to 80kHz frequency range of the DS3882, and the turns
28
____________________________________________________________________
Dual-Channel Automotive CCFL Controller
Table 10. Transformer Specifications (as Used in the Typical Operating Circuit)
PARAMETER
Turns Ratio (Secondary/Primary)
Frequency
CONDITIONS
(Notes 1, 2, 3)
MIN
TYP
MAX
UNITS
40
40
80
6
kHz
W
Output Power
Output Current
5
8
mA
mΩ
Ω
Primary DCR
Center tap to one end
200
500
12
Secondary DCR
Primary Leakage
µH
mH
µH
mH
Secondary Leakage
Primary Inductance
Secondary Inductance
185
70
500
100ms minimum
Continuous
2000
1000
Secondary Output Voltage
V
RMS
Note 1: Primary should be Bifilar wound with center tap connection.
Note 2: Turns ratio is defined as secondary winding divided by the sum of both primary windings.
Note 3: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12V supply. Refer to Application Note 3375 for more
information.
Table 11. Resistor and Capacitor Selection Guide
TOLERANCE TEMPERATURE
(%) AT +25°C COEFFICIENT
DESIGNATOR
QTY
VALUE
NOTES
R5, R6
R3, R4
1
1
10kΩ
1
1
—
—
—
12.5kΩ to
105kΩ
See the Setting the SVM Threshold Voltage section.
20kΩ to
40kΩ
2ꢀ or less total tolerance. See the Lamp Frequency
Configuration section to determine value.
R9
1
1
1
1
≤153ppm/°C
≤153ppm/°C
18kΩ to
45kΩ
2ꢀ or less total tolerance. See the Lamp Frequency
Configuration section to determine value.
R10
R1
R2
1
4.7kΩ
4.7kΩ
4.7kΩ
140Ω
5
5
5
1
Any grade
Any grade
Any grade
—
—
1
1
—
R11
—
R7, R8
1/Chan
See the Setting the RMS Lamp Current section.
Capacitor value will also affect LCM bias voltage during
power-up. A larger capacitor may cause a longer time
C6, C8
C2
1/Chan
1/Chan
1/Chan
100nF
10pF
27nF
10
5
X7R
1000ppm/°C
X7R
for V
to reach its normal operating level.
DCB
2kV to 4kV breakdown voltage required.
Capacitor value will also affect LCM bias voltage during
power-up. A larger capacitor may cause a longer time
C3
5
for V
to reach its normal operating level.
DCB
C1
C7
1/Chan
33µF
20
10
Any grade
X7R
—
2/DS3882
0.1µF
Place close to V
and GND on DS3882.
CC
____________________________________________________________________ 29
Dual-Channel Automotive CCFL Controller
Typical Operating Circuit
DEVICE
SUPPLY VOLTAGE
(5V 5%)
INVERTER SUPPLY
VOLTAGE (V
)
INV
(8V TO 16V)
V
V
CC
CC
R1
R2
C1
C7
R3
R5
R4
R6
V
CC
SDA
SCL
A0
2
I C
SVMH
SVML
CONFIGURATION
AND CONTROL PORT
A1
V
CC
GND_S
R11
CCFL LAMP
R7
GA1
GB1
C2
C3
DS3882
FAULT
TRANSFORMER
LAMP CURRENT
DUAL POWER
MOSFET
LCO
OVERDRIVE ENABLE
OVERVOLTAGE DETECTION
OVD1
LCM1
HARDWARE
CONTROL
PDN
LAMP ON/OFF
LAMP BRIGHTNESS
LAMP CURRENT MONITOR
BRIGHT
STEP
STEP LAMP
FREQUENCY
C8
CCFL LAMP
R8
DPWM SIGNAL
INPUT/OUTPUT
GA2
PSYNC
LSYNC
C4
C5
LAMP FREQUENCY
INPUT/OUTPUT
GB2
TRANSFORMER
LOSC
POSC
DUAL POWER
MOSFET
OVERVOLTAGE DETECTION
OVD2
LAMP CURRENT MONITOR
R9
R10
LCM2
GND
C6
Power-Supply Decoupling
Chip Information
To achieve best results, it is highly recommended that
a decoupling capacitor is used on the I.C. power-sup-
ply pin. Typical values of decoupling capacitors are
0.01µF or 0.1µF. Use a high-quality, ceramic, surface-
mount capacitor, and mount it as close as possible to
TRANSISTOR COUNT: 38,000
SUBSTRATE CONNECTED TO GROUND
Package Information
the V
and GND pins of the I.C. to minimize lead
CC
For the latest package outline information, go to
inductance.
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney
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