DS3901 [MAXIM]
Triple, 8-Bit NV Variable Resistor with Dual Settings and User EEPROM;
| 型号： | DS3901 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Triple, 8-Bit NV Variable Resistor with Dual Settings and User EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总20页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 4/06
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
General Description
Features
The DS3901 is a triple, 8-bit nonvolatile (NV) variable
resistor. Each of the resistors has two setting registers,
which are selectable by software or by pin configura-
tion. The selected register determines the value of the
variable resistor. Additionally, all three resistors have a
high-impedance setting. Resistor R0 has the additional
flexibility of allowing an external shunt resistor to pro-
vide increased dynamic range. Internal address set-
tings allow the DS3901 slave address to be
programmed to one of 128 possible addresses. The
DS3901 also features an optional password-protection
scheme that allows the protection of sensitive data.
♦ Three 256-Position Linear Digital Resistors
♦ Full-Scale Resistances 50kΩ, 30kΩ, 20kΩ
♦ Dual NV Settings for Each Resistor
♦ Low Temperature-Coefficient Resistors
2
♦ I C Serial Interface
♦ Wide Operating Voltage (2.4V to 5.5V)
♦ Two-Level Password Write Protection
♦ 232 Bytes of User EEPROM
♦ Programmable Slave Address
♦ -40°C to +95°C Operating Temperature Range
Ordering Information
Applications
Optical Transceivers
RESISTOR
PIN-
Optical Transponders
VALUES FOR
PART
TEMP RANGE
PACKAGE
Instrumentation and Industrial Controls
RF Power Amps
R0, R1, AND R2
DS3901E+ -40°C to +95°C 50kΩ, 30kΩ, 20kΩ 14 TSSOP
+Denotes lead-free package.
Audio Power-Amp Biasing
Replacement for Mechanical Variable Resistors
and DIP Switches
Pin Configuration
TOP VIEW
SCL
SDA
1
2
3
4
5
6
7
14 V
CC
13 N.C.
12 H2
11 L2
10 H1
ADD_SEL
BK_SEL
DIS
DS3901
N.C.
9
8
H0
L0
GND
TSSOP
Typical Operating Circuit appears at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
ABSOLUTE MAXIMUM RATINGS
Voltage on V
SDA, SCL Relative to GND .........-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature ....................................Refer to IPC/JEDEC
J-STD-020 Specification
CC,
Voltage on ADD_SEL, BK_SEL, DIS Relative
to GND.................-0.5V to (V + 0.5V), not to exceed +6.0V
CC
Voltage on H0, H1, H2, L2, L0 Relative to GND........-0.5V to +6.0V
Maximum Resistor Current....................................................3mA
Maximum Switch Current......................................................3mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +95°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
(Note 1)
2.4
5.5
V
CC
Input Logic 0
(SDA, SCL, ADD_SEL)
0.3 x
V
CC
V
-0.3
V
IL
Input Logic 1
(SDA, SCL, ADD_SEL)
0.7 x
V
+
CC
0.3
V
(Note 1)
(Note 1)
(Note 1)
V
V
V
IH
V
CC
Input Logic 0 (BK_SEL, DIS)
V
-0.3
+0.8
IL
V
+
CC
Input Logic 1 (BK_SEL, DIS)
V
2.0
IH
0.3
H0, H1,
L0, H2, L2
Voltage on Resistor Inputs
-0.3
+5.5
3
V
Switch Current
(L0_SW, Hi-Z0, Hi-Z1, Hi-Z2)
I
(Note 2)
mA
SW
ELECTRICAL CHARACTERISTICS
(V
= +2.4V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
250
+1
UNITS
µA
Standby Current
Input Leakage
I
(Note 3)
STBY
I
L
-1
0
µA
V
V
3mA sink current
6mA sink current
0.4
0.6
45
OL1
OL2
Low-Level Output Voltage (SDA)
V
0
Pulldown Resistance (BK_SEL)
Pullup Resistance (DIS)
BK_SEL Pulse Width
R
20
20
20
30
30
kΩ
kΩ
µs
BK
R
45
DIS
2
_____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
ANALOG RESISTOR CHARACTERISTICS
(V
= +2.4V to +5.5V, T = -40°C to +95°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
= +25°C
MIN
TYP
MAX
+20
500
250
UNITS
Resistor Tolerance
T
-20
%
A
R0, R2
R1
242
149
50
Position 00h Resistance
Ω
R0
Position FFh Resistance
kΩ
R1
30
R2
20
Switch Resistance
Absolute Linearity
R
At 3mA
(Note 4)
(Note 5)
150
Ω
LSB
L0_SW
-0.75
-0.75
+0.75
+0.75
Relative Linearity
LSB
Temperature Coefficient
Hi-Z Resistor Leakage
Position FFh (Notes 2, 6)
H0, H1, H2, L0, or L2 = V
50
ppm/°C
µA
I
-1
+1
RHIZ
CC
2
I C CHARACTERISTICS
(V
= +2.4V to +5.5V, T = -40°C to +95°C, unless otherwise noted. Timing referenced to V
and V
.)
CC
A
IL(MAX)
IH(MIN)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 7)
0
400
kHz
SCL
Bus Free Time between STOP and
START Condition
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated)
START Condition
t
HD:STA
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
0.9
HD:DAT
Data Setup Time
t
100
0.6
SU:DAT
Start Setup time
t
SU:STA
Rise Time of Both SDA and SCL
Signals
20 +
t
(Note 8)
(Note 8)
300
300
ns
ns
R
0.1C
B
Fall Time of Both SDA and SCL
Signals
20 +
t
F
0.1C
B
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
EEPROM Write Time
t
0.6
µs
pF
ms
pF
ms
SU:STO
C
(Note 8)
(Note 9)
400
10
B
t
W
Input Capacitance
C
5
I
Startup Time
t
0.3
2
ST
_____________________________________________________________________
3
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
NONVOLATILE MEMORY CHARACTERISTICS
(V
= +2.4V to +5.5V.)
CC
PARAMETER
SYMBOL
CONDITION
=+ 70 °C (Note 2)
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
T
A
50,000
Note 1: All voltages referenced to ground.
Note 2: Guaranteed by design.
Note 3: I
specified for the inactive state measured with SDA = SCL = V , ADD_SEL = GND, BK_SEL, DIS, H0, H1, H2, L2, L0
STBY
CC
floating.
Note 4: Absolute linearity is the deviation of a measured resistor-setting value from the expected value at each particular resistor
setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured
maximum setting.
Note 5: Relative linearity is the deviation of the step size change between two LSB settings from the expected step size. The expected
LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
Note 6: See the Typical Operating Characteristics.
2
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C standard mode.
Note 8: CB—total capacitance of one bus line in picofarads.
Note 9: EEPROM write begins after a STOP condition occurs.
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SCL FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
185
183
200
190
180
170
160
150
140
130
120
110
205
200
195
190
185
180
175
ADD_SEL = GND
SDA = SCL = V
ADD_SEL = GND
ADD_SEL = GND
,
SDA = SCL = V
,
SDA = SCL = V
,
CC
CC
CC
181
179
177
175
173
171
169
167
165
ALL OTHERS ARE FLOATING
ALL OTHERS ARE FLOATING
ALL OTHERS ARE FLOATING
-40
-13
14
41
68
95
2.400
3.175
3.950
4.725
5.500
0
50 100 150 200 250 300 350 400
SCL FREQUENCY (kHz)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE COEFFICIENT
vs. RESISTOR SETTING
CHANGE IN RESISTANCE
vs. TEMPERATURE
RESISTANCE vs. RESISTOR SETTING
1000
900
800
700
600
500
400
300
200
100
0
50
40
30
20
10
12
RESISTOR SETTING = 00h
R1
R0, -40°C TO +25°C
R1, -40°C TO +25°C
R2, -40°C TO +25°C
R0, +25°C TO +95°C
R1, +25°C TO +95°C
R2, +25°C TO +95°C
7
2
R0 R1 R2
R0
R2
-3
-8
-13
0
0
51
102
153
204
255
-40
-13
14
41
68
95
0
51
102
153
204
255
SETTING (DEC)
TEMPERATURE (°C)
SETTING (DEC)
4
_____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
CHANGE IN RESISTANCE
vs. TEMPERATURE
RESISTANCE vs. POWER-UP
SUPPLY VOLTAGE
RESISTANCE vs. SUPPLY VOLTAGE
1.400
0.10
0.08
0.06
0.04
0.02
0
> 1MΩ
RESISTOR SETTING = FFh
RESISTOR SETTING = FFh
RESISTOR SETTING = 7Fh
R2
R1
59
57
55
53
51
49
47
1.200
1.000
0800
R2
R0
0.600
0.400
0.200
0.000
-0.200
-0.400
-0.600
-0.02
-0.04
-0.06
-0.08
-0.10
R1
R0
R0
-40
-13
14
41
68
95
0
2.75
5.50
3.950
4.725
2.400
3.175
5.500
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
RESISTANCE vs. POWER-DOWN
SUPPLY VOLTAGE
R0 ABSOLUTE LINEARITY
vs. RESISTOR SETTING
R0 RELATIVE LINEARITY
vs. RESISTOR SETTING
> 1MΩ
RESISTOR SETTING = FFh
0.65
0.45
0.65
0.45
59
57
55
53
51
49
47
0.25
0.25
0.05
0.05
-0.15
-0.35
-0.55
-0.75
-0.15
-0.35
-0.55
-0.75
R0
0
2.75
5.50
0
51
102
153
204
255
0
51
102
153
204
255
SUPPLY VOLTAGE (V)
SETTING (DEC)
SETTING (DEC)
R1 ABSOLUTE LINEARITY
vs. RESISTOR SETTING
R1 RELATIVE LINEARITY
vs. RESISTOR SETTING
0.65
0.45
0.65
0.45
0.25
0.25
0.05
0.05
-0.15
-0.35
-0.55
-0.15
-0.35
-0.55
-0.75
-0.75
0
51
102
153
204
255
0
51
102
153
204
255
SETTING (DEC)
SETTING (DEC)
_____________________________________________________________________
5
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
R2 ABSOLUTE LINEARITY
vs. RESISTOR SETTING
R2 RELATIVE LINEARITY
vs. RESISTOR SETTING
0.65
0.45
0.65
0.45
0.25
0.25
0.05
0.05
-0.15
-0.35
-0.55
-0.75
-0.15
-0.35
-0.55
-0.75
0
51
102
153
204
255
0
51
102
153
204
255
SETTING (DEC)
SETTING (DEC)
Pin Description
PIN
NAME
SCL
FUNCTION
2
1
2
I C Clock Input
2
SDA
I C Data I/O Pin
2
3
ADD_SEL
BK_SEL
DIS
I C Slave Address Select Pin
4
Bank Select Pin. This pin has an internal pulldown resistor, R
.
BK
5
High-Impedance Disable Input. This pin has an internal pullup resistor, R
.
DIS
6, 13
7
N.C.
GND
L0
No Connection
Ground
8
Resistor 0 Low Terminal
Resistor 0 High Terminal
Resistor 1 High Terminal
Resistor 2 Low Terminal
Resistor 2 High Terminal
Voltage Supply
9
H0
10
11
12
14
H1
L2
H2
V
CC
6
_____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Block Diagram
DATA BUS
ADDRESS
SDA
SCL
2
I C
INTERFACE
V
CC
ADD_SEL
DS3901
V
CC
CONTROL
GND
V
CC
MEMORY
84h
88-8Bh
8Fh
CONFIGURATION
PASSWORD ENTRY (SRAM)
STATUS (SRAM)
R
DIS
DIS
R
BK
Hi-Z0
CONTROL
Hi-Z2
CONTROL
90-93h
94-97h
PW1 PASSWORD SETTING
PW2 PASSWORD SETTING
Hi-Z1
CONTROL
BK_SEL
H0
Hi-Z0
MUX
CONTROL
R0
98h
99h
9Ah
RESISTOR 0 BANK 0
RESISTOR 1 BANK 0
RESISTOR 2 BANK 0
50kΩ FS
256 POSITIONS
L0
BANK 0
MUX
L0_SW
Hi-Z1
H1
RESISTOR 0 BANK 1
RESISTOR 1 BANK 1
RESISTOR 2 BANK 1
9Ch
9Dh
9Eh
R1
30kΩ FS
256 POSITIONS
BANK 1
Hi-Z2
2
9Fh
I C SLAVE ADDRESS
H2
L2
PW1 EEPROM
PW2 EEPROM
R2
20kΩ FS
256 POSITIONS
_____________________________________________________________________
7
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
high-impedance state (see the Memory Map section for
Detailed Description
details). The state of the DIS pin overrides the state of
the high-impedance control bits (see the Memory Map
section for details).
The DS3901 contains three configurable variable resis-
tors. The Block Diagram illustrates the features of the
DS3901. The following sections discuss these features
in detail.
Slave Address Byte
2
The ADD_SEL pin is used to select the I C address of
Dual Bank Resistor Settings
The setting for each resistor can be loaded from one of
two possible registers. These registers are referred to
as “banks” with each resistor having a “Bank 0” and
“Bank 1” value. The bank to be loaded as the resistor
value is selected by the OR’ing of the BK_SEL pin logic
state and the BSC control bit (bit 3, register 84h). See
the Memory Map section for details. If the result of the
OR’ing is a 0, then all three resistors will use the values
stored in their Bank 0 locations. If the result is a 1, then
all three resistors will use the values stored in their
Bank 1 locations.
the DS3901. When the ADD_SEL pin is connected low,
2
the I C address of the DS3901 is A2h. When the
ADD_SEL pin is connected high, the value stored in the
Slave Address register (9Fh) is used. The default value
for the Slave Address register is shown in the Memory
Map section. The Slave Address register can be pro-
grammed to one of 128 possible addresses since the
LSB of the Slave Address register is reserved as the
2
read/write bit for the I C command structure.
Password Protection
The memory of the DS3901 is write-protected with a
two-level password scheme. All memory locations can
be read without a password, with the exception of the
Password Entry registers and Password Setting regis-
ters. Once the appropriate password is entered in the
Password Entry bytes (88 to 8Bh), the DS3901 will allow
write access to the memory areas designated for that
password. The setting for the PW1 password is written
in the PW1 Password Setting register (bytes 90 to 93h).
The setting for the PW2 password is written in the PW2
Password Setting register (bytes 94 to 97h). See the
Memory Map section for more details. Entering the PW2
password allows access to areas protected by the PW1
password.
Shunt Resistor Switch
Resistor 0 has the option to have an external fixed resis-
tor connected to the L0 pin. This provides a means to
select between a standard full-scale resistor value and
an extended full-scale value. By default, the L0_SW bit
(bit 4 of the Configuration Register, 84h) is set to a value
of 0. When the L0_SW bit is 0, the internal connection
from the low side of Resistor 0 to ground is opened, and
the low terminal of Resistor 0 is only connected to the
L0 pin. This allows for an external resistor to be
attached to the L0 pin for an extended full-scale value.
By writing the switch control bit L0_SW to a 1, the low
terminal of Resistor 0 is internally connected to ground.
When shipped from the factory, both password settings
are all zeroes. Likewise, every time the device is pow-
ered up the Password Entry register (SRAM) defaults to
all zeroes. If write protection is not desired, leave the
password setting at the factory default and ignore the
Password Entry register. Write protection goes into
effect once either or both default password settings
have been changed to unique values.
High-Impedance Function
There are two ways to place the resistors in a high-
impedance (Hi-Z) state. One way is to set the DIS pin to
a 1. This is done by either floating the pin (there is an
internal pullup resistor, R
) or by connecting DIS
DIS
directly to V . When the DIS pin is held high or left
CC
floating, all three resistors are held in a high-impedance
state. The second method is to use bits 0 to 2 of the
Configuration Register (84h), to set each resistor to a
8
_____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
how the memory map is organized. Register details are
discussed in the Register Descriptions section.
Memory Map
The memory consists of 256 bytes and is write-protected
with a two-level password scheme. Table 1 below shows
Table 1. Memory Map
ACCESS
BINARY
FACTORY
LSB DEFAULT
DESCRIPTION
ADDR
TYPE
MSB
NO PW PW1
PW2
R/W
R/W
R/W
R/W
W
Lower Memory
Memory
00–7Fh
80–83h
84h
PW2 EEPROM
PW1 EEPROM
00h
00h
R
R
R
EEPROM
EEPROM
EEPROM
EEPROM
SRAM
R/W
R/W
R/W
W
Configuration
Memory
L0_SW BSC HiZ2 HiZ1 HiZ0
00h
00h
00h
00h
R
85–87h
88–8Bh
8C–8Eh
8Fh
PW1 EEPROM
MSB–LSB
SRAM
R
Password Entry
Memory
W
R/W
R
R/W
R
R/W
R
SRAM
Status
0
0
0
BSS
0
0
0
DISS 000x000xb
SRAM
Password Setting
PW1
90–93h
94–97h
MSB–LSB
MSB–LSB
00h
—
—
—
—
W
W
EEPROM
EEPROM
Password Setting
PW2
00h
Resistor 0 Bank 0
Resistor 1 Bank 0
Resistor 2 Bank 0
Memory
98h
99h
—
7Fh
7Fh
7Fh
00h
7Fh
7Fh
7Fh
A0h
00h
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
—
9Ah
—
9Bh
PW2 EEPROM
Resistor 0 Bank 1
Resistor 1 Bank 1
Resistor 2 Bank 1
Slave Address
Memory
9Ch
—
—
—
9Dh
9Eh
2
9Fh
I C SLAVE ADDRESS
PW2 EEPROM
A0h–FFh
Register Descriptions
MEMORY REGISTERS 00h–7Fh: PW2 EEPROM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
00h–7Fh
EEPROM
_____________________________________________________________________
9
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTERS 80h–83h: PW1 EEPROM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read and Write
Read and Write
Nonvolatile (EEPROM)
80h–83h
EEPROM
MEMORY REGISTER 84h: CONFIGURATION REGISTER
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read and Write
Read and Write
Nonvolatile (EEPROM)
L0_SW
BSC
HiZ2
HiZ1
HiZ0
b0
84h
b7
These bits are set to 0.
bits 7–5
L0_SW: Selectable switch (see the Block Diagram) that allows for an external shunt resistor to be connected to the
L0 pin.
0 = Switch L0_SW is open (default).
bit 4
1 = Switch L0_SW is closed.
BSC: A control bit that, when OR’d with the state of the BK_SEL pin, selects which bank of registers will be used to
determine the setting of Resistors 0, 1, and 2.
0 = BK_SEL pin determines which bank settings are used.
1 = Bank 1 settings are used.
HiZ2: A control bit used to select a high-impedance state for Resistor 2.
If the DIS pin is high, all resistors are high impedance regardless of Hi-Z control pin state. If the DIS pin is low, then
the following is true:
bit 3
bit 2
0 = Resistor 2 is not in a high-impedance state (default).
1 = Resistor 2 is placed in a high-impedance state.
HiZ1: A control bit used to select a high-impedance state for Resistor 1.
If the DIS pin is high, all resistors are high impedance regardless of Hi-Z control pin state. If the DIS pin is low, then
the following is true:
0 = Resistor 1 is not in a high-impedance state (default).
1 = Resistor 1 is placed in a high-impedance state.
HiZ0: A control bit used to select a high-impedance state for Resistor 0.
If the DIS pin is high, all resistors are high impedance regardless of Hi-Z control pin state. If the DIS pin is low, then
the following is true:
bit 1
bit 0
0 = Resistor 0 is not in a high-impedance state. (Default)
1 = Resistor 0 is placed in a high-impedance state.
10
____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTERS 85h–87h: PW1 EEPROM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read and Write
Read and Write
Nonvolatile (EEPROM)
85h–87h
EEPROM
MEMORY REGISTERS 88h-8Bh: PASSWORD ENTRY
Factory Default:
00000000h
Write only
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Write only
Write only
Volatile (SRAM)
31
30
2
22
2
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
88h
89h
8Ah
8Bh
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
23
15
7
14
2
2
2
6
1
0
2
2
2
2
2
2
2
2
b7
b0
There are two passwords for the DS3901, the PW1
password and the PW2 password. The memory map
register descriptions indicate the type of access granted
for each level of password used. See the Password
Protection section for details on password access.
MEMORY REGISTERS 8Ch–8Eh: SRAM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read and Write
Read and Write
Read and Write
Volatile (SRAM)
8Ch-8Eh
SRAM
____________________________________________________________________ 11
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTER 8Fh: STATUS
Factory Default:
000x000xb
Read only
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Volatile (SRAM)
8Fh
0
0
0
BSS
0
0
0
DISS
b0
b7
bits 7–5
bit 4
These bits are 0.
BSS: A status bit that indicates the state of the BK_SEL pin.
0 = BK_SEL pin is low.
1 = BK_SEL pin is high.
bits 3–1
bit 0
These bits are 0.
DISS: A status bit that indicates the state of the DIS pin.
0 = DIS pin is low. Hi-Z control bits can be used to select high-impedance state for each resistor.
1 = DIS pin is high. All resistors are in a high-impedance state.
MEMORY REGISTERS 90h–93h: PW1 PASSWORD SETTING
Factory Default:
00000000h
None
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
None
Write only
Nonvolatile (EEPROM)
31
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
2
16
2
90h
91h
92h
93h
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
23
15
7
17
9
2
8
2
2
1
0
2
2
2
2
2
2
2
2
b7
b0
These four bytes contain the password used to access
memory that is protected by the PW1 password.
12
____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTERS 94h–97h: PW2 PASSWORD SETTING
Factory Default:
00000000h
None
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
None
Write only
Nonvolatile (EEPROM)
31
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
94h
95h
96h
97h
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
23
15
7
2
2
1
0
2
2
2
2
2
2
2
2
7
b
b0
These four bytes contain the password used to access
memory that is protected by the PW2 password.
MEMORY REGISTER 98h: RESISTOR 0, BANK 0
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
98h
b7
b0
This register contains the Bank 0 values for Resistor 0.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 0 Bank 0 or
Resistor 0 Bank 1 is used for the Resistor 0 setting. See
the Configuration Register in Register 84h for logic
details.
____________________________________________________________________ 13
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTER 99h: RESISTOR 1, BANK 0
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
99h
2
2
2
2
2
2
2
2
b7
b0
This register contains the Bank 0 values for Resistor 1.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 1 Bank 0 or
Resistor 1 Bank 1 is used for the Resistor 1 setting. See
the Configuration Register in Register 84h for logic
details.
MEMORY REGISTER 9Ah: RESISTOR 2, BANK 0
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
9Ah
2
2
2
2
2
2
2
2
b7
b0
This register contains the Bank 0 values for Resistor 2.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 2 Bank 0 or
Resistor 2 Bank 1 is used for the Resistor 2 setting. See
the Configuration Register in Register 84h for logic
details.
MEMORY REGISTER 9Bh: PW2 EEPROM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
9Bh
EEPROM
14
____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTER 9Ch: RESISTOR 0, BANK 1
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
9Ch
2
2
2
2
2
2
2
2
b7
b0
This register contains the Bank 1 values for Resistor 0.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 0 Bank 0 or
Resistor 0 Bank 1 is used for the Resistor 0 setting. See
the Configuration Register in Register 84h for logic
details.
MEMORY REGISTER 9Dh: RESISTOR 1, BANK 1
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
9Dh
2
2
2
2
2
2
2
2
b7
b0
This register contains the Bank 1 values for Resistor 1.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 1 Bank 0 or
Resistor 1 Bank 1 is used for the Resistor 1 setting. See
the Configuration Register in Register 84h for logic
details.
MEMORY REGISTER 9Eh: RESISTOR 2, BANK 1
Factory Default:
7Fh
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
9Eh
2
2
2
2
2
2
2
2
b7
b0
This register contains the Bank 1 values for Resistor 2.
The OR’d result of the state of the BSC bit (bit 3, 84h)
and the BK_SEL pin determines if Resistor 2 Bank 0 or
Resistor 2 Bank 1 is used for the Resistor 2 setting. See
the Configuration Register in Register 84h for logic
details.
____________________________________________________________________ 15
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
MEMORY REGISTER 9Fh: SLAVE ADDRESS REGISTER
Factory Default:
A0h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
7
6
5
4
3
2
1
0
9Fh
2
2
2
2
2
2
2
2
b7
b0
2
The I C slave address of the DS3901 depends on the
state of the ADD_SEL pin. If this pin is low, then the
slave address is fixed at A2h. If the ADD_SEL pin is
high, then the slave address is determined by the value
stored in EEPROM at address 9Fh. Factory default
value for the slave address is A0h. The seven most sig-
nificant bits are used (the LSB is not used because it is
in the bit position of the R/W bit) to allow the slave
address to be programmed to one of 128 possible
addresses.
MEMORY REGISTERS A0h–FFh: PW2 EEPROM
Factory Default:
00h
Access Without Password:
Access With PW1 Password:
Access With PW2 Password:
Memory Type:
Read only
Read only
Read and Write
Nonvolatile (EEPROM)
A0h–FFh
EEPROM
16
____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
2
specific memory address to begin a data transfer. A
I C Serial Interface Description
repeated START condition is issued identically to a nor-
mal START condition. See the timing diagram for
applicable timing.
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers.
2
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 1). Data is
shifted into the device during the rising edge of the SCL.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 1) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
Acknowledgement (ACK and NACK): An Acknowl-
edgement (ACK) or Not Acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 1) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it immediately initiates a new data
transfer following the current one. Repeated STARTS
are commonly used during read operations to identify a
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
R
t
F
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 1. I C Timing Diagram
____________________________________________________________________ 17
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (MSB first)
plus a 1-bit acknowledgement from the slave to the
master. The 8 bits transmitted by the master are done
according to the bit write definition and the acknowl-
edgement is read using the bit read definition.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOP condition.
The DS3901 is capable of writing up to 8 bytes (1 page
or row) with a single write transaction. This is internally
controlled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information that
are transferred (MSB first) from the slave to the master are
read by the master using the bit read definition above, and
the master transmits an ACK using the bit write definition
to receive additional data bytes. The master must NACK
the last byte read to terminate communication so the slave
will return control of SDA to the master.
Attempts to write to additional pages of memory without
sending a STOP condition between pages result in the
address counter wrapping around to the beginning of
the present row. To prevent address wrapping from
occurring, the master must send a STOP condition at
the end of the page, and then wait for the bus free or
EEPROM write time to elapse. Then the master may
generate a new START condition and write the slave
address byte (R/W = 0) and the first memory address of
the next memory row before continuing to write data.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave addressing byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The ADD_SEL pin and Slave Address register (9Fh)
2
determine the I C slave address for the DS3901. If
Acknowledge Polling: Any time an EEPROM page is
ADD_SEL is low, then the slave address is fixed at A2h.
If ADD_SEL is high, then the slave address in the Slave
Address Register (9Fh) is used.
written, the DS3901 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the page to EEPROM. During the EEPROM write time,
the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS3901, which allows the next page to be written as
soon as the DS3901 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
The LSB of the Slave Address Byte is the R/W bit. If the
R/W bit is 0, then the master indicates it will write data
to the slave. If R/W = 1, then the master will read data
from the slave. If an incorrect slave address is written,
the DS3901 will assume the master is communicating
2
with another I C device and ignore the communication
mum period of t to elapse before attempting to write
W
again to the device.
until the next START condition is sent.
2
Memory Address: During an I C write operation, the
EEPROM Write Cycles: When EEPROM writes occur,
the DS3901 will write the whole EEPROM memory page
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified during
the transaction are still subject to a write cycle. This can
result in a whole page being worn out over time by
writing a single byte repeatedly. The DS3901’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at the
worst-case temperature.
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
2
I C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgement during all byte write operations.
18
____________________________________________________________________
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Reading a Single Byte from a Slave: Unlike the write
done with or without modifying the address counter’s
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave, the mas-
ter generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
location before the read cycle.
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
mount the capacitors as close as possible to the V
GND pins to minimize lead inductance.
and
CC
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this, the master
generates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condition,
writes the slave address byte (R/W = 1), reads data
with ACK or NACK as applicable, and generates a
STOP condition.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS3901 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be uti-
lized for SCL. Pullup resistor values should be chosen
to ensure that the rise and fall times listed in the AC
Electrical Characteristics are within specification.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte, it NACKs to indicate the end of the
transfer and generates a stop condition. This can be
Chip Topology
TRANSISTOR COUNT: 52,353
SUBSTRATE CONNECTED TO GROUND
____________________________________________________________________ 19
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
Typical Operating Circuit
V
CC
H0
L0
MODSET
DS3901
V
CC
0.1µF
4.7kΩ
4.7kΩ
MAX3738
LASER DRIVER
(OPTIONAL SHUNT
RESISTOR)
SDA
SCL
DIS
SIGNALS
FROM HOST
H1
APCSET
ADD_SEL
BK_SEL
H2
L2
TH
GND
V
CC
2.5kΩ
0.1µF
MAX3747A
LIMITING AMP
0.1µF
50kΩ
VREF
50kΩ
0.1µF
IN+
IN-
DIFFERENTIAL
DATA IN
0.1µF
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
相关型号：
DS3901E+
Digital Potentiometer, 3 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO14, 0.173 INCH, ROHS COMPLIANT, TSSOP-14
MAXIM
DS3901E+T&R
Digital Potentiometer, 3 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO14, 0.173 INCH, ROHS COMPLIANT, TSSOP-14
MAXIM
DS3902U-515+
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO8, LEAD FREE, MICRO, SOP-8
MAXIM
DS3902U-515+T&R
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO8, LEAD FREE, MICRO, SOP-8
MAXIM
DS3902U-515/T&R
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO8, USOP-8
MAXIM
DS3902U-530+
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO8, LEAD FREE, MICRO, SOP-8
MAXIM
DS3902U-530+T&R
Digital Potentiometer, 2 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO8, SOP-8
MAXIM
©2020 ICPDF网 联系我们和版权申明