DS4077L-ADN [MAXIM]
50MHz to 122.88MHz VCXO;
| 型号： | DS4077L-ADN |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 50MHz to 122.88MHz VCXO 石英晶振 压控振荡器 |
| 文件： | 总5页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 3; 9/06
50MHz to 122.88MHz VCXO
DS407
General Description
Features
The DS4077 is an integrated voltage-controlled crystal
oscillator (VCXO) module designed to provide reference
clock generation in base stations, telecom/datacom, and
wireless applications. The DS4077 is developed using a
fundamental quartz crystal plus a unique integrated cir-
cuit design. The internal fundamental quartz crystal
determines the frequency of operation. Custom frequen-
cies are available. Contact the factory for availability.
♦ 50MHz to 122.88MHz Frequency
♦ 3.135V to 3.465V Operation
♦ Low Jitter: < 0.8ps RMS
♦
69ppm Absolute Pull Range (APR)
♦ Output Options:
The DS4077 is designed for use with applications requir-
ing low phase noise and jitter. Jitter performance of bet-
ter than 0.8ps RMS is achieved over the 12kHz to 20MHz
range. Phase noise performance of better than
-125dBc/Hz at 1kHz is achieved with this design.
LVCMOS Output Buffer
LVDS Complementary Output Buffer
♦ Minimum 110ppm Tuning Range (+25°C)
♦ 14mm x 9mm x 3.06mm Plastic LGA Package
Applications
Clock-Data Recovery in Telecom/Datacom
Applications
Data Retiming
Reference Clock Generation in Base Stations
and Wireless Applications
Ordering Information
FREQUENCY
PART
TEMP RANGE
OUTPUT TYPE
PIN-PACKAGE
TOP MARK
(f ) (MHz)
NOM
LVCMOS
LVDS
54
DS4077L-DCN
DS4077L-DDN
DS4077L-CCN
DS4077L-CDN
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
9 LGA
9 LGA
9 LGA
9 LGA
DS4077L-DCN
DS4077L-DDN
DS4077L-CCN
DS4077L-CDN
54
LVCMOS
LVDS
61.44
61.44
Ordering Information continued at end of data sheet.
Block Diagram
Pin Configuration
V
DD
TOP VIEW
N.C.
8
N.C.
7
N.C.
9
X1
LVCMOS
OUTPUT
VC
1
2
3
6
5
4
V
DD
CRYSTAL
OSC
N.C.
N.C. (LVDSO-)
DS4077
X2
V
LVCMOS (LVDSO+)
SS
VARACTOR
VC
CONTROL
DS4077
LGA
( ) LVDS OPTION
TRANSFER-MOLDED PLASTIC PACKAGE
LVCMOS OPTION SHOWN HERE.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
50MHz to 122.88MHz VCXO
ABSOLUTE MAXIMUM RATINGS
VC, V , LVCMOS, LVDSO+, LVDSO- Output ........-0.3V, +3.6V
DD
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature
Operating Temperature Range
(noncondensing) ..............................................-40°C to +85°C
Junction Temperature......................................................+150°C
Thermal Resistance
(reflow, 2 passes max)....See IPC/JEDEC STD-020 Specification
Junction to Ambient .................................................91.06°C/W
Junction to Case ......................................................44.51°C/W
DS407
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.135V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V
= 3.3V, unless otherwise
DD
A
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.465
30
UNITS
V
V
Operating Supply Range
Supply Current
V
3.135
3.3
20
25
V
DD
DD
DD
f
f
≤ 106.25MHz
OUT
OUT
I
Output open
mA
DD
> 106.25MHz
35
VC = 1.6V, V
(Note 2)
= 3.3V, T = +25°C
f
f
NOM
+8ppm
DD
A
NOM
Frequency
f
f
MHz
OUT
NOM
–8ppm
Frequency vs. V
Sensitivity
V
ppm
V = 3.3V 5ꢀ
DD
-3.5
+11.5
ppm
ppm/pF
ppm
V
DD
DD
Frequency vs. Load Sensitivity
Frequency vs. Temperature
VC Voltage Range
LOADpmm 10pF to 20pF (Note 3)
TEMPppm From +25°C
-1
-20
0.3
41
+20
2.8
VC
1.60
RANGE
Frequency Tuning Sensitivity
Tuning Voltage Bandwidth
Absolute Pull Range
VC
164
ppm/V
kHz
SEN
VC
(Note 3)
10
BW
f
VC = 0.3V to 2.8V (Note 2)
-69
-500
-5
+69
+500
+5
ppm
nA
TUNE
VC Input Leakage
I
VC = 0V to V
Total aging
LCV
DD
Aging, First Year
AGEppm
ppm
ppm
Aging, Years 0–10
t
-10
+10
AGE
LVDS OUTPUT
Output High Voltage
V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
1.475
V
V
OHLVDSO
Output Low Voltage
V
0.925
250
OLLVDSO
ODLVDSO
Differential Output Voltage
Output Common-Mode Variation
Offset Output Voltage
Differential Output Impedeance
Output Current
V
400
150
1.275
140
40
mV
mV
V
V
LVDSOCOM
V
1.125
80
OFFLVDSO
R
Ω
OLVDSO
I
Short ground
mA
mA
ps
ps
VSSLVDSO
Output Current
I
Short together (Note 3)
20ꢀ to 80ꢀ (Note 3)
80ꢀ to 20ꢀ (Note 3)
12
LVDSO
Output Rise Time (Differential)
Output Fall Time (Differential)
t
150
150
RLVDSO
t
FLVDSO
2
_____________________________________________________________________
50MHz to 122.88MHz VCXO
DS407
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.135V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, V
= 3.3V, unless otherwise
DD
A
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS OUTPUT
Output Logic 0
V
Output Current -450µA
0
0.4
V
V
OL
V
-
DD
0.8V
Output Logic 1
Output Rise Time
Output Fall Time
V
Output Current +450µA
V
OH
DD
2
Load condition: 10pF to ground; 10ꢀ to
t
ns
ns
R
90ꢀ V
(Note 3)
DD
Load condition: 10pF to ground; 90ꢀ to
10ꢀ V (Note 3)
t
2
F
DD
Duty Cycle
D
Load condition: 10pF, V / 2 (Note 3)
40
60
-8
ꢀ
CYC
H
DD
Harmonics
V
= 3.3V, T = +25°C (Note 3)
-18
dBc/Hz
DD
A
SSB PHASE NOISE AND JITTER, V
10Hz Offset
= 3.3, T = +25°C (Note 3)
A
DD
-70
-100
-125
-145
-150
0.8
100Hz Offset
1kHz Offset
LVCMOS
dBc/Hz
10kHz Offset
100kHz Offset
Jitter (12kHz to 20MHz)
ps
RMS
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: 10pF, LVCMOS.
Note 3: Guaranteed by design and not production tested.
Note 4: 100Ω differential load.
Pin Description
PIN
NAME
FUNCTION
LVDS
LVCMOS
1
1
VC
VCXO Control Voltage
No Connection
Ground
2, 7, 8, 9
2, 5, 7, 8, 9
N.C.
3
—
6
3
4
V
SS
LVCMOS
LVCMOS Output
DC Power
6
V
DD
4, 5
—
LVDSO+/LVDSO-
LVDS Positive and Negative Outputs
_____________________________________________________________________
3
50MHz to 122.88MHz VCXO
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
LVCMOS OUTPUT FREQUENCY
vs. LOAD CAPACITANCE vs. VC
150
FREQUENCY vs. TEMPERATURE
10
f
= 77.76MHz
OUT
f
= 77.76MHz
OUT
125
100
75
0
8
6
VC = 1.55V
C = 0pF
L
4
50
2
C = 20pF
L
25
0
0
-2
-4
-6
-8
-10
-25
-50
-75
-100
-125
-20
0
0.3
0.8
1.3
1.8
2.3
2.8
-40
20
40
60
80
VC (V)
TEMPERATURE (°C)
OUTPUT FREQUENCY
vs. SUPPLY VOLTAGE vs. VC
20
15
10
5
f
= 77.76MHz
OUT
T
= +25°C
A
VC = 0.3V
0
-5
VC = 1.6V
-10
-15
-20
VC = 2.8V
3.410 3.465
3.135 3.190 3.245
3.355
3.300
(V)
V
DD
4
_____________________________________________________________________
50MHz to 122.88MHz VCXO
DS407
Ordering Information (continued)
FREQUENCY
PART
TEMP RANGE
OUTPUT TYPE
PIN-PACKAGE
TOP MARK
(f ) (MHz)
NOM
LVCMOS
LVDS
74.17582
74.17582
74.25
DS4077L-ECN
DS4077L-EDN
DS4077L-FCN
DS4077L-FDN
DS4077L-ACN
DS4077L-ADN
DS4077L-0CN
DS4077L-0DN
DS4077L-GCN
DS4077L-GDN
DS4077L-BDN
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
9 LGA
DS4077L-ECN
DS4077L-EDN
DS4077L-FCN
DS4077L-FDN
DS4077L-ACN
DS4077L-ADN
DS4077L-0CN
DS4077L-0DN
DS4077L-GCN
DS4077L-GDN
DS4077L-BDN
LVCMOS
LVDS
74.25
LVCMOS
LVDS
76.8
76.8
LVCMOS
LVDS
77.76
77.76
LVCMOS
LVDS
106.25
106.25
122.88
LVDS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0265
9 LGA
L949A-1
Revision History
Rev 0; 8/05:
Initial release.
Rev 1; 12/05:
Rev 2; 6/06:
Added LVDS option.
Changed device description/frequency range; changed jitter typical value from 1 to 0.8psRMS;
added new parts numbers to Ordering Information table; changed jitter range upper limits from
80MHz to 20MHz.
Rev 3; 9/06:
Changed V ppm units from ppm/PF to ppm; added separate I
DD
parameter for parts with f
DD OUT
greater than 106.25MHz.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 5
© 2006 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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