DS4302 [MAXIM]
2-Wire, 5-Bit DAC with Three Digital Outputs; 2线， 5位DAC，提供三路数字输出
| 型号： | DS4302 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Wire, 5-Bit DAC with Three Digital Outputs |
| 文件： | 总8页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 6/04
2-Wire, 5-Bit DAC with Three Digital Outputs
General Description
Features
The DS4302 is a 5-bit digital-to-analog converter (DAC)
with three programmable digital outputs. The DS4302
communicates through a 2-wire, SMBus™-compatible,
serial interface. The tiny 8-pin µSOP package is ideal
for use in space-constrained applications.
♦ SO Package is a Drop-In Replacement for the
MPS1251 and MPS1252
♦ Single 5-Bit DAC (32 Steps)
♦ 0V to 2V and 0V to 1.9V Versions
♦ Three Programmable Digital Outputs
♦ SMBus-Compatible Serial Interface
♦ 4.5V to 5.5V Supply Voltage Range
♦ 8-Pin SO and 8-Pin µSOP Packages
♦ Industrial Temperature Range: -40°C to +85°C
Applications
Ordering Information
CCFL Backlight Brightness Control
V
TOP
BRAND
PIN-
PACKAGE
OUT
PART
RANGE
Power-Supply Calibration
DS4302Z-020
DS4302Z-019*
DS4302U-020
DS4302U-019*
0V to 2.0V
0V to 1.9V
0V to 2.0V
0V to 1.9V
4302B
4302A
4302B
4302A
8 SO
8 SO
8 µSOP
8 µSOP
Add “/T&R” for tape-and-reel orders.
*Contact factory for availability.
Pin Description
Pin Configuration
PIN
NAME
FUNCTION
TOP VIEW
1
SCL
Serial Clock Input. 2-wire clock input.
Serial Data Input/Output. Bidirectional,
2-wire data pin.
2
SDA
SCL
SDA
1
2
3
4
8
7
6
5
V
CC
P0
P1
P2
3
4
5
6
7
8
V
DAC Output Voltage
Ground
OUT
DS4302
GND
P2
V
OUT
GND
Programmable Digital Output
Power-Supply Input
P1
P0
SO/µSOP
V
CC
SMBus is a trademark of Intel Corp.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2-Wire, 5-Bit DAC with Three Digital Outputs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL Pins
CC
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature.....See IPC/JEDEC J-STD-020A Specification
Relative to Ground.............................................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
4.5
TYP
MAX
UNITS
V
(Note 1)
5.5
V
V
V
CC
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
V
2.0
V
+ 0.3
0.8
IH
CC
V
GND - 0.3
IL
DC ELECTRICAL CHARACTERISTICS
(V
= +4.5V to 5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
300
+1.0
0.4
UNITS
µA
Standby Current
Input Leakage
I
(Notes 2, 3)
(Note 4)
200
STBY
I
-1.0
0.0
0.0
µA
L
3mA sink current
6mA sink current
SDA Low-Level Output Voltage
V
V
V
V
V
OL1
OL2
0.6
P0, P1, P2 Low-Level Output
Voltage
(Note 1)
4mA sink
+0.4V
P0, P1, P2 High-Level Output
Voltage
(Note 1)
4mA source
V
V
- 0.4V
CC
OH
V
V
V
V
Maximum Level (-020)
Minimum Level (-020)
Maximum Level (-019)
Minimum Level (-019)
V
V
V
V
= 5.0V, Data = 00000XXX (Note 3)
= 5.0V, Data = 11111XXX
1.925
0.0
2.0
0.05
1.9
0.05
1.7
10
2.075
0.1
V
V
OUT
OUT
OUT
OUT
CC
CC
CC
CC
= 5.0V, Data = 00000XXX (Note 3)
= 5.0V, Data = 11111XXX
1.825
0.0
1.975
0.1
V
V
Power-On Reset
Settling Time
V
µs
steps
D/A Output Levels
32
X = Don’t care.
2
_____________________________________________________________________
2-Wire, 5-Bit DAC with Three Digital Outputs
AC ELECTRICAL CHARACTERISTICS (Figure 3)
(V
= +4.5V to 5.5V, T = -40°C to +85°C, timing referenced to V
and V
.)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
µs
BUF
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
µs
µs
µs
ns
µs
ns
ns
µs
LOW
t
HIGH
t
0
0.9
HD:DAT
Data Setup Time
t
100
SU:DAT
Start Setup Time
t
0.6
SU:STA
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Setup Time
t
R
(Note 5)
(Note 5)
20 + 0.1C
20 + 0.1C
0.6
300
300
B
B
t
F
t
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 5)
400
pF
B
Note 1: All voltages referenced to ground.
Note 2: I specified for the inactive state measured with SDA = SCL = V
and with V , P0, P1, and P2 floating.
OUT
STBY
CC
Note 3: No load on V
.
OUT
Note 4: The DS4302 will not obstruct the SDA and SCL lines if V
is switched off as long as the voltages applied to these inputs
CC
does not violate their min and max input-voltage levels.
Note 5: C —total capacitance of one bus line in picofarads.
B
_____________________________________________________________________
3
2-Wire, 5-Bit DAC with Three Digital Outputs
Typical Operating Characteristics
(V
= +5.0V, T = +25°C.)
A
CC
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTGE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SCL FREQUENCY
300
300
250
200
150
100
50
300
250
200
150
100
50
OUTPUTS UNLOADED
OUTPUTS UNLOADED
SDA = SCL = V
OUTPUTS UNLOADED
SDA = SCL = V = 5.0V
CC
250
200
150
100
50
SDA = V
CC
CC
0
0
0
40
TEMPERATURE (°C)
60
80
4.50
4.75
5.00
5.25
5.50
-40
-20
0
20
0
100
200
300
400
SUPPLY VOLTAGE (V)
SCL FREQUENCY (kHz)
V
OUT
PERCENT CHANGE FROM +25°C
V
OUT
vs. DAC SETTING
V
OUT
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
2.10
2.05
2.00
1.95
1.90
1.0
0.5
0
V
= SDA = SCL
CC
V
= SDA = SCL
CC
DS4302-020 VERSION
2.0
1.5
1.0
-0.5
-1.0
0.5
0
40
60
80
0
5
10
DAC SETTING (dec)
15
20
25
30
4.50
4.75
SUPPLY VOLTAGE (V)
5.00
5.25
5.50
-40 -20
0
20
TEMPERATURE (°C)
4
_____________________________________________________________________
2-Wire, 5-Bit DAC with Three Digital Outputs
Functional Diagram
DATA BYTE REGISTER
DAC VALUE
SDA
SCL
2-WIRE
INTERFACE
OUTPUT CELL
LSB
MSB
P2 P1 P0
V
CC
P0
V
OUT
5-BIT
DAC
V
CC
OUTPUT CELL
OUTPUT CELL
V
CC
BUFFER
P1
P2
GND
BANDGAP
REFERENCE
DS4302
_____________________________________________________________________
5
2-Wire, 5-Bit DAC with Three Digital Outputs
5-bit DAC to adjust the voltage on VOUT and set the
level of the three output pins: P0, P1, and P2. The read
operation is used to recall the programmed settings.
DATA BYTE
DAC VALUE
MSB
P2 P1 P0
2-Wire Definitions
The following terminology is commonly used to
describe 2-wire data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START, and STOP conditions.
Figure 1. Data Byte Configuration
Detailed Description
The DS4302 contains a 5-bit DAC and three programma-
ble digital outputs. The DAC setting and the pro-
grammed output levels are contained in a 1-byte data
word that defaults to 00h on power-up (see Figure 1 for
data byte configuration). The upper 5 MSbits of the byte
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it initiates a
low-power mode for slave devices.
set the DAC and control the voltage produced on V
.
OUT
A setting of 1111 1XXX sets the minimum output voltage
from the DAC while a setting of 0000 0XXX sets the maxi-
mum output voltage from the DAC. The three LSbits of
the data byte control the three output pins, P0, P1, and
P2. Setting any of these control bits to a 0 pulls the corre-
sponding outputs low and setting the bits to a 1 pulls the
outputs high.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
The DS4302 communicates through a 2-wire (SMBus-
compatible) digital interface and has a 2-wire address of
58h. Write and read operations are used to access the
DAC and output settings. Each operation begins with a
2-wire START condition, consists of three bytes, and
ends with a 2-wire STOP condition (see Figure 2). Using
the write operation, the 2-wire master can program the
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 3). Data is
shifted into the device during the rising edge of the SCL.
COMMUNICATIONS KEY
NOTES:
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
S
P
START
STOP
A
ACK
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
X
X
X
X
X
X
X
X
8-BITS ADDRESS OR DATA
WRITE A SINGLE BYTE
58h
AAh
0
S
0
1
0
1
1
0
0
0
A
1
0
1
1
0
1
0
A
A
DATA BYTE
DATA BYTE
A
P
P
READ A SINGLE BYTE
59h
00h
0
S
0
1
0
1
1
0
0
1
A
0
0
0
0
0
0
0
A
Figure 2. 2-Wire Communication Examples
6
_____________________________________________________________________
2-Wire, 5-Bit DAC with Three Digital Outputs
SDA
SCL
t
BUF
t
t
HD:STA
SP
t
LOW
t
F
t
R
t
SU:STA
tHIGH
t
HD:STA
t
SU:DAT
t
SU:STO
REPEATED
START
t
HD:DAT
STOP
START
NOTE: TIMING IS REFERENCE TO V
IL(MAX)
AND V .
IH(MIN)
Figure 3. 2-Wire Timing Diagram
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
7-BIT SLAVE ADDRESS
0
1
0
1
1
0
0
R/W
MOST
DETERMINES
READ OR WRITE
SIGNIFICANT
BIT
Figure 4. Slave Address and the R/W Bit
Acknowledgement (ACK): An Acknowledgement
(ACK) is always the 9th bit transmitted during a byte
transfer. The device receiving data (the master during a
read or the slave during a write operation) performs an
ACK by transmitting a zero during the 9th bit. For tim-
ing, see Figure 3. An ACK is the acknowledgement that
the device is properly receiving data.
Slave Address and the R/W Bit: Each slave on the
2-wire bus responds to a slave addressing byte sent
immediately following a START condition. The slave
address byte contains the slave address and the R/W
bit. The slave address (see Figure 4) is the most signifi-
cant 7 bits and the R/W bit is the least significant bit.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
The DS4302’s slave address is 0101100X (binary),
where X is the R/W bit. If the R/W bit is zero
(01011000), the master will write data to the slave. If the
R/W is a one (01011001), the master will read data from
the slave.
Memory Address: During a 2-wire write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is the second byte transmitted
during a write or read operation following the slave
address byte (R/W=0). For a write operation, the mem-
ory address is 10101010 (AAh) and for a read opera-
tion, the memory address is 00000000 (00h).
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK from the
master to the slave. The 8 bits of information that are
transferred (most significant bit first) from the slave to
the master are read by the master using the bit read
definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must ACK the last byte read to termi-
nated communication so the slave returns control of
SDA to the master.
_____________________________________________________________________
7
2-Wire, 5-Bit DAC with Three Digital Outputs
2-Wire Communication
Chip Information
Writing to a Slave: The master must generate a START
condition, write the slave address (R/W = 0), write the
memory address, write the byte of data, and generate a
STOP condition. Remember the master must read the
slave’s acknowledgement during all byte-write opera-
tions. See Figure 2 for the write command example.
TRANSISTOR COUNT: 2428
SUBSTRATE CONNECTED TO GROUND
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address with R/W = 1, receives an ACK from the slave,
reads a memory address of 00h from the slave, sends
an ACK to the slave, reads the data byte, then sends
an ACK to indicate the end of the transfer, and gener-
ates a STOP condition. See Figure 2 for the read com-
mand example.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS4302,
decouple the power supply with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as pos-
sible to the V
and GND pins of the DS4302 to mini-
CC
mize lead inductance.
SDA and SCL Pullup Resistors
Pullup resistor values for SDA and SCL should be cho-
sen to ensure that the rise and fall times listed in the AC
electrical characteristics are within specification.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
DALLAS is a registered trademark of Dallas Semiconductor Corporation.
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