DS4420 [MAXIM]
I2C Programmable-Gain Amplifier for Audio Applications; I2C可编程增益放大器，用于音频应用
| 型号： | DS4420 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I2C Programmable-Gain Amplifier for Audio Applications |
| 文件： | 总10页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 9/06
2
I C Programmable-Gain Amplifier
for Audio Applications
DS420
General Description
Features
The DS4420 is a fully differential, programmable-gain
amplifier for audio applications. It features a -35dB to
ꢀ Differential Inputs and Outputs
ꢀ -35dB to +25dB Adjustable Gain
ꢀ Low Output Noise
2
+25dB gain range controlled by an I C interface and it
is optimized to drive loads as low as 50Ω. The gain is
adjustable in 3dB increments across the entire range.
ꢀ Low-Distortion Driving into a 50Ω Load
2
Three address inputs, used to select the I C slave
address, enable up to eight devices on a common bus.
2
ꢀ 3dB Gain Steps Programmed through I C Interface
ꢀ 5V Single Supply
The product operates from a single 5V supply over a
-20°C to +70°C temperature range. It is offered in a
3mm x 3mm TDFN package.
ꢀ 20kHz Bandwidth for All Gain Settings
ꢀ Small 3mm x 3mm x 0.8mm TDFN Package
ꢀ Up to Eight DS4420s can be Placed on the Same
Applications
Telephone Headsets
Audio Volume Control
Microphone Gain Control
2
I C Bus
Ordering Information
Pin Configuration
PART
TEMP RANGE
PIN-PACKAGE
TOP VIEW
DS4420+
-20°C to +70°C
14 TDFN-EP*
14 AV
A2
A1
1
2
3
4
5
6
7
CC
13 OUT+
12 OUT-
+Denotes lead-free package.
*EP = Exposed paddle.
A0
SCL
SDA
11
AGND
DS4420
10 N.C.
V
9
8
IN-
IN+
CC
GND
TDFN
(3mm x 3mm x 0.8mm)
Typical Operating Circuit
V
CC
AV
CC
GND
AGND
SDA
SCL
A2
MICROPR0CESSOR-
CONTROLLED GAIN
2
I C INTERFACE
A1
A0
OUT+
IN+
IN-
-35dB
TO +25dB
GAIN
AUDIO
AMPLIFIER
AUDIO
SOURCE
OUT-
DS4420
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2
I C Programmable-Gain Amplifier
for Audio Applications
ABSOLUTE MAXIMUM RATINGS
Voltage on V , SDA, and SCL
Voltage on AV Relative to V ..........................-0.3V to +0.3V
CC CC
CC
Relative to GND.................................................-0.5V to +6.0V
Voltage on A0, A1, and A2
Voltage on AGND Relative to GND .......................-0.3V to +0.3V
Output Current ..................................................................150mA
Operating Temperature Range ...........................-20°C to +70°C
Storage Temperature .....................See J-STD-020 Specification
Relative to GND......................................-0.5V to (V
+ 0.5V;
CC
not to exceed 6.0V)
Voltage on IN+, IN-, OUT-, and OUT+
Relative to AGND .................................-0.5V to (AV
+ 0.5V;
CC
DS420
not to exceed 6.0V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -20°C to +70°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Supply Voltage
Analog Supply Voltage
Analog Ground
V
(Note 1)
+4.5
+5.5
V
V
V
CC
AV
V
CC
CC
AGND
(See Figure 5)
GND
V
+ 0.3
CC
Input Logic 1 (SCL, SDA, A0, A1, A2)
Input Logic 0 (SCL, SDA, A0, A1, A2)
V
2.0
V
V
IH
V
-0.3
+0.8
IL
ELECTRICAL CHARACTERISTICS
(V = +4.5V to +5.5V, T = -20°C to +70°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 5.5V, R = ∞, V = 0V differential
CC
L
IN
Supply Current
I
1.7
3
mA
CC
(Note 9)
Standby Current
I
V
V
= 5.5V (Notes 2, 9)
= 5.5V
140
1
µA
µA
µA
STBY
CC
CC
Input Leakage (SDA, SCL, A2, A1, A0)
Output Leakage (SDA)
I
IL
I
L
1
V
V
= 0.4V
= 0.6V
3
6
OL
OL
Output-Current Low (SDA)
I
mA
OL
Input Voltage Range
Max Peak-to-Peak Input Level
Input Resistance
V
Differential
-19
49
+1
3.2
60
dBV
V
IN
V
Differential
INP-P
R
Differential, active mode (Note 3)
29
kΩ
IN
0.45 x
0.55 x
Input Common-Mode Voltage
V
V
IN:CM
V
V
CC
CC
Output Voltage
V
R = 50Ω differential
6
dBV
V
O
L
Output Peak-to-Peak Signal Swing
V
Differential
5.6
OP-P
0.45 x
0.5 x
0.55 x
V
CC
Output Common-Mode Voltage
V
V
O:CM
V
V
CC
CC
Output Offset Voltage
V
A = +25dB
-20
95
64
+20
mV
mA
O:OS
V
V
V
= GND
OUT
OUT
Amplifier Output Current
(Sourcing)
I
OS1
= V
- 0.75V
CC
2
_____________________________________________________________________
2
I C Programmable-Gain Amplifier
for Audio Applications
DS420
ELECTRICAL CHARACTERISTICS (continued)
(V = +4.5V to +5.5V, T = -20°C to +70°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
89
TYP
MAX
UNITS
V
V
= V
CC
OUT
OUT
Amplifier Output Current
(Sinking)
I
mA
OS2
= 0.75V
64
Resistive Load Range
Capacitive Load
R
C
Differential
50
50k
100
20k
+1
Ω
L
Cap to GND (Note 4)
pF
Hz
dB
L
Closed-Loop Bandwidth
Passband Flatness
All gain settings (Note 5)
20Hz to 20kHz (Notes 2, 5)
A = -35dB, 300Hz to 3.4kHz
A = +25dB, 300Hz to 3.4kHz
20
-1
-123
-88
Output Noise (Note 5)
N
dBV
O
R = 50Ω, V ≤ +6dBV,
f = 1kHz, A = 16dB
L
O
0.03
0.01
1.0
Total Harmonic Distortion (Note 5)
THD
A
%
R = 1kΩ, V ≤ +6dBV,
L
O
f = 1kHz, A = 16dB
Gain Range
-35
2.0
+25
4.0
dB
dB
dB
dB
µs
Gain Step Size
A
3.0
S
Gain Accuracy
A
(Note 10)
(Note 5)
(Note 6)
-2.5
+2.5
-90
10
ERR1
MUTE
Mute and Standby Mode Gain
Standby Mode Exit Time
A
t
PU
2
I C AC ELECTRICAL CHARACTERISTICS (See Figure 3)
(V
= +4.5V to +5.5V, T = -20°C to +70°C, timing referenced to V
and V
, unless otherwise noted.)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 7)
0
400
kHz
SCL
Bus Free Time Between STOP and
START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
0.9
HD:DAT
Data Setup Time
Start Setup Time
t
100
0.6
SU:DAT
t
SU:STA
20 +
SDA and SCL Rise Time
SDA and SCL Fall Time
t
(Note 8)
(Note 8)
300
300
ns
ns
R
0.1C
B
20 +
t
F
0.1C
B
STOP Setup Time
t
0.6
µs
SU:STO
SDA and SCL Capacitive Loading
C
(Note 8)
400
pF
B
_____________________________________________________________________
3
2
I C Programmable-Gain Amplifier
for Audio Applications
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Standby supply current specified with SDA = SCL = V , the output disconnected, and A0, A1, and A2 driven to within
CC
100mV of V
or GND.
CC
Note 3: Input resistance during mute and power-down is approximately one-half of the active-mode resistance.
Note 4: Each output is capable of driving a 100nF capacitive load to ground using an external 10Ω series resistor. However, output
capacitance should be minimal for optimal distortion performance.
Note 5: Guaranteed by design.
Note 6: This is the time it takes for the output to become active after exiting standby mode.
Note 7: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C standard-
DS420
2
2
mode timing.
Note 8:
C = total capacitance of one bus line in picofarads.
B
Note 9: The current specified is the sum of V and AV
supply currents.
CC
CC
Note 10: Gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is ≤ 2.5kΩ.
Typical Operating Characteristics
(T = +25°C, V = AV = 5.0V, unless otherwise noted.)
CC
A
CC
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(STANDBY MODE ENABLED)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SETTING AT -11dB)
SUPPLY CURRENT vs. GAIN SETTING
84
82
80
78
76
74
72
70
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.7
1.6
1.5
1.4
V
= AV = SDA = SCL
V
= AV = SDA = SCL
CC CC
CC
CC
+25°C
NO LOAD
IN+ AND IN- SHORTED
TOGETHER
NO LOAD
IN+ AND IN- SHORTED
TOGETHER
+70°C
-20°C
+25°C
-20°C
+70°C
IN+ AND IN- SHORTED
TOGETHER
NO LOAD
0
5
10
15
20
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
GAIN SETTING
4
_____________________________________________________________________
2
I C Programmable-Gain Amplifier
for Audio Applications
DS420
Typical Operating Characteristics (continued)
(T = +25°C, V = AV = 5.0V, unless otherwise noted.)
CC
A
CC
POWER-SUPPLY REJECTION RATIO
vs. GAIN SETTING
COMMON-MODE FREQUENCY RESPONSE
SWEEP AT -11dB
GAIN vs. FREQUENCY RESPONSE
30
20
0
-10
-20
-30
120
100
80
60
40
20
0
50Ω LOAD
NO LOAD
+25dB SETTING
1kHz
50Ω LOAD
10
0
-2dB SETTING
-40
-50
-10
-20
20kHz
50Ω LOAD
-60
-70
-80
-30
-40
-35dB SETTING
10,000
1000
100,000
1,000,000
0
5
10
15
20
1000
10,000
100,000
FREQUENCY (Hz)
GAIN SETTING
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
GAIN vs. SETTING
CCITT NOISE vs. GAIN SETTING
0.018
30
20
0
-20
IN+ AND IN- SHORTED TOGETHER
ACROSS -20°C TO +70°C
WITH 50Ω LOAD, 1kΩ LOAD,
AND NO LOAD
NO LOAD
WITH 50Ω LOAD
AND 1kΩ LOAD
0.016
0.014
1V
INPUT
RMS
-11dB SETTING
10
-40
0.012
0.010
0
-60
0.008
0.006
0.004
-10
-20
-30
-40
-80
-100
-120
-140
0.002
0.000
10
100
1000
10,000
100,000
0
5
10
15
20
0
5
10
15
20
GAIN SETTING
GAIN SETTING
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
TOTAL HARMONIC DISTORTION vs. V
OUT
DS4420 toc11
0.09
10
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0.000
WITH 50Ω LOAD
AND 1kΩ LOAD
50Ω LOAD
5
0
1kHz 2V
INPUT
0.08
0.07
RMS
VOUT
1V
INPUT
RMS
+10dB SETTING
-5
0.06
0.05
-10
-15
-20
-25
-30
-35
-40
0.04
0.03
0.02
THD+N
0.01
0.00
10
100
1000
10,000
100,000
2
4
6
8
10 12 14 16 18 20
FREQUENCY (Hz)
GAIN SETTING
_____________________________________________________________________
5
2
I C Programmable-Gain Amplifier
for Audio Applications
Pin Description
PIN
1
NAME
A2
FUNCTION
2
Address Select Inputs—Determine I C Slave Address. Device address is 1010A A A .
2
A1
2
1 0
3
A0
DS420
2
2
4
SCL
SDA
I C Serial Clock—Input for I C Clock
2
2
5
I C Serial Data—Input/Output for I C Data
Digital Power-Supply Terminal
Ground
6
V
CC
7
GND
IN+
8
Differential Audio Input Signal
9
IN-
10
11
12
13
14
EP
N.C.
No Connection
AGND
OUT-
OUT+
Analog Ground (Must be Connected to GND)
Differential Audio Output Signal
AV
Analog Power Supply (Must be Connected to V
)
CC
CC
EP
Exposed Paddle. Connect to GND and AGND.
Detailed Description
Block Diagram
The key features of the DS4420 are illustrated in the
Block Diagram.
V
AV
CC
A0 A1 A2
CC
Controlling the DS4420
2
SDA
The DS4420 is controlled through the I C serial inter-
DS4420
2
I C INTERFACE
face. Gain, mute, and standby settings all reside in one
control register located at memory address F8h (see
Figure 1). Writes to other memory addresses are invalid.
3dB
GAIN
STEPS
SCL
Programmable Gain
The gain is adjustable from -35dB to +25dB in 3dB
increments. The gain is determined by the five LSBs of
the control register as shown in Figure 1. Gain settings
greater than 14h are invalid.
IN+
IN-
OUT+
-35dB
TO +25dB
GAIN
OUT-
Mute Mode
The DS4420 is placed in mute mode by setting the mute
bit located in the control register (see Figure 1). When in
this mode, the output of the amplifier is muted and is
independent of the gain setting. The input-to-output
attenuation is specified in the Electrical Characteristics
GND
AGND
low-current (I
) consumption state. Unlike mute
STBY
mode, however, standby mode is intended for use when
no input signal is present. While in standby mode, the
DS4420 maintains input and output common-mode bias
voltages. The device produces no audible clicks or
pops when entering or exiting the standby state. The
time required for the output to become active when
table as A
.
MUTE
Standby Mode
Standby mode is entered by setting the standby control
bit (see Figure 1). Setting the standby control bit mutes
the output of the amplifier and places the DS4420 into a
exiting standby mode is specified as t
.
PU
6
_____________________________________________________________________
2
I C Programmable-Gain Amplifier
for Audio Applications
DS420
Control Register (F8h)
Power-Up Default:
1000 0000 b
F8h
Standby
bit 7
x
Mute
Gain Setting[4:0]
bit 2
bit 4
bit 3
bit 1
bit 0
Standby: Places the DS4420 in standby mode.
bit 7
bit 6
0 = Normal operation.
1 = Places the DS4420 in standby mode. (Power-up default.)
Don’t care.
Mute: Mutes the amplifier output, regardless of the current gain setting.
0 = Normal operation. (Power-up default.)
bit 5
1 = Mutes the amplifier output.
bit 4:0
Gain Setting: Five-bit gain setting. The power-up default is setting 00h.
GAIN
SETTING
(hex)
GAIN
SETTING
(hex)
GAIN
(dB)
GAIN
(dB)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
-35
-32
-29
-26
-23
-20
-17
-14
-11
-8
0Bh
0Ch
-2
+1
0Dh
+4
0Eh
+7
0Fh
+10
+13
+16
+19
+22
+25
Illegal
10h
11h
12h
13h
14h
-5
15h to 1Fh
Figure 1. Control Register Description
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 2). The DS4420’s
slave address is determined by the state of the A0, A1,
and A2 address pins. These pins allow up to eight
MSB
LSB
R/W
1
0
1
0
A1
A0
A2
SLAVE
ADDRESS*
READ/WRITE
BIT
2
DS4420s to reside on the same I C bus. Address pins
connected to GND result in a ‘0’ in the corresponding
bit position in the slave address. Conversely, address
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
pins connected to V
result in a ‘1’ in the correspond-
CC
ing bit positions. For example, the DS4420’s slave
address byte is A0h when A0, A1, and A2 pins are
Figure 2. DS4420 Slave Address Byte
2
grounded. I C communication is described in detail in
2
the I C Serial Interface Description section.
_____________________________________________________________________
7
2
I C Programmable-Gain Amplifier
for Audio Applications
SDA
t
BUF
t
SP
t
HD:STA
DS420
t
LOW
t
R
t
F
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 3. I C Timing Diagram
2
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into
the device during the rising edge of the SCL.
I C Serial Interface Description
2
I C Definitions
The following terminology is commonly used to
2
describe I C data transfers. See the timing diagram
2
(Figure 3) and the I C AC Electrical Characteristics
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock
pulses including when it is reading bits from the slave.
table for additional information.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave dur-
ing a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one (done by releasing SDA) during the 9th
bit. Timing (Figure 3) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
8
_____________________________________________________________________
2
I C Programmable-Gain Amplifier
for Audio Applications
DS420
Byte Read: A byte read is an 8-bit information transfer
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minate communication so the slave will return control of
SDA to the master.
2
I C Communication
Writing a Single Byte to a Slave: The master must gen-
erate a start condition, write the slave address byte (R/W
= 0), write the memory address, write the byte of data,
and generate a stop condition. The master must read the
slave’s acknowledgement during all byte write operations.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read oper-
ation occurs at the present value of the memory
address counter. A dummy write cycle can be used to
force the address pointer to a desired location. To do
this, the master generates a start condition, writes the
slave address byte (R/W =0), writes the memory
address where it desires to read, generates a repeated
start condition, writes the slave address byte (R/W = 1),
reads the data byte with a NACK to indicate the end of
the transfer, and generates a stop condition.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS4420’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure
2. Address pins connected to GND result in a ‘0’ in the
corresponding bit position in the slave address.
Conversely, address pins connected to V
‘1’ in the corresponding bit positions.
result in a
CC
When the R/W bit is 0 (such as in A0h), the master is indi-
cating it will write data to the slave. If R/W is set to a 1,
(A1h in this case), the master is indicating it wants to read
from the slave.
2
See Figure 4 for I C communication examples.
Applications Information
Power-Supply Decoupling
The DS4420 has separate supply voltages for its ana-
log and digital circuitry. For best noise and distortion
performance, place a 0.1µF or 0.01µF capacitor from
If an incorrect (nonmatching) slave address is written,
the DS4420 will assume the master is communicating
with another I C device and ignore the communication
2
until the next start condition is sent.
V
to GND and from AV
to AGND. These capaci-
CC
CC
2
Memory Address: During an I C write operation to the
DS4420, the master must transmit a memory address to
identify the memory location where the slave is to store
tors should be placed as close as possible to the sup-
ply and ground pins of the device.
COMMUNICATIONS KEY
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
A
S
P
START
STOP
ACK
NOTE 1: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
NOT
ACK
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
N
NOTE 2: THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
REPEATED
START
8-BITS ADDRESS OR DATA
X
X
X
X
X
X
X
X
Sr
WRITE THE GAIN SETTING
F8h
A
A
REGISTER SETTING
A
S
1
0
1
0
A
A
A
A
A
0
0
A
1
1
1
1
1
1
1
1
0
0
0
0
0
0
P
A
2
1
1
0
0
READ THE GAIN SETTING
F8h
A
1
0
1
0
A
1
1
A
N
S
REGISTER SETTING
Sr
P
1
0
1
0
A
A
1
1
0
2
2
2
Figure 4. I C Communication Examples
_____________________________________________________________________
9
2
I C Programmable-Gain Amplifier
for Audio Applications
Exposed Paddle
Internal Ground Connections
The DS4420 exposed paddle is not electrically isolated.
It must be soldered to ground for proper operation.
The DS4420’s ground pins, GND and AGND, must be
connected together externally. Internally, they are con-
nected as shown in Figure 5.
Input-Coupling Capacitors
The DS4420 is designed to be operated with an AC-
coupled input signal. The input resistance, R , is suffi-
IN
13Ωꢀ
TYPICAL
ciently large to allow the use of small and inexpensive
external capacitors. The input resistance combined
with the AC-coupling capacitor will create a highpass
DS420
filter. The -3dB cutoff frequency of the highpass, f , is
C
given by:
1
2π ×C × R
f
=
GND
AGND
C
IN
IN
Figure 5. Internal Ground Connections
where C is the external coupling capacitor and R is
IN
IN
the internal input resistance.
At the cutoff frequency, the input signal will be attenuat-
ed 3dB, with less attenuation as the signal’s frequency
increases beyond the cutoff frequency. To guarantee
passband flatness, the cutoff frequency of the filter
should be designed using the specified minimum input
resistance, and placed well below the desired flat band
of the circuit. The typical input resistance should only
be used to estimate typical performance.
Chip Topology
TRANSISTOR COUNT: 5347
SUBSTRATE CONNECTED TO: Ground
Package Information
For the latest package outline information, go to www.maxim-
ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Springer
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