DS4432 [MAXIM]
Dual-Channel, I2C, 7-Bit Sink/Source Current DAC; 双通道， I2C ， 7位可吸入/源出电流DAC
| 型号： | DS4432 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Channel, I2C, 7-Bit Sink/Source Current DAC |
| 文件： | 总9页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 12/08
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
DS432
General Description
Features
2
The DS4432 contains two I C programmable current
DACs that are each capable of sinking and sourcing
current up to 200µA. Each DAC output has 127 sink
and 127 source settings that are programmed using the
♦ Two Current DACs
♦ Full-Scale Current 50µA to 200µA
♦ Full-Scale Range for Each DAC Determined by
2
I C interface. The current DAC outputs power up in a
External Resistors
high-impedance state.
♦ 127 Settings Each for Sink and Source Modes
2
♦ I C-Compatible Serial Interface
Applications
♦ Low Cost
Power-Supply Adjustment
Power-Supply Margining
♦ Small Package (8-Pin µSOP)
♦ -40°C to +85°C Temperature Range
♦ 2.7V to 5.5V Operating Range
Adjustable Current Sink or Source
Ordering Information
Pin Configuration
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 μSOP
TOP VIEW
DS4432U+
DS4432U+T&R
8 μSOP
+
SDA
SCL
FS1
1
2
3
4
8
7
6
5
V
CC
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
OUT1
OUT0
FS0
DS4432
GND
μSOP
Typical Operating Circuit
V
CC
V
OUT0
V
OUT1
OUT
OUT
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
DC-DC
CONVERTER
DC-DC
CONVERTER
R
0A
R
1A
FB
FB
OUT0
OUT1
DS4432
R
0B
R
1B
GND
FS0
FS1
R
FS0
R
FS1
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature ...............................Refer to the IPC/JEDEC
J-STD-020 Specification.
CC
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on FS0, FS1, OUT0, OUT1
Relative to Ground..................................-0.5V to (V
+ 0.5V)
CC
(Not to exceed 6.0V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS432
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
V
CC
(Note 1)
(Note 2)
5.5
V
V
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
Full-Scale Resistor Values
V
0.7 x V
-0.3
V
+ 0.3
IH
CC
CC
V
0.3 x V
V
IL
CC
R , R
FS0 FS1
40
160
kꢀ
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= 5.5V (Note 3)
MIN
TYP
0.997
TYP
MAX
150
1
UNITS
μA
Supply Current
I
V
V
CC
CC
Input Leakage (SDA, SCL)
Output Leakage (SDA)
I
= 5.5V
μA
IL
CC
I
L
1
μA
V
V
= 0.4V
= 0.6V
3
6
OL
OL
Output Current Low (SDA)
I
mA
OL
RFS Voltage
V
RFS
V
I/O Capacitance
C
I/O
10
pF
OUTPUT CURRENT SOURCE CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Output Voltage for Sinking Current
V
(Note 4)
(Note 4)
0.5
3.5
V
OUT:SINK
Output Voltage for Sourcing
Current
V
CC
-
V
0
V
OUT:SOURCE
0.75
200
-50
Full-Scale Sink Output Current
Full-Scale Source Output Current
I
(Notes 1, 4)
(Notes 1, 4)
50
μA
μA
OUT:SINK
I
-200
OUT:SOURCE
Output Current Full-Scale
Accuracy
+25°C, V = 3.3V; using 0.1% R
CC FS
I
5
%
OUT:FS
OUT:TC
resistor, V
= V
= 1.2V (Note 2)
OUT1
OUT0
Output Current Temperature
Coefficient
I
(Note 5)
130
ppm/°C
2
_______________________________________________________________________________________
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
DS432
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
measured at 1.2V
OUT
MIN
TYP
0.41
0.41
0.08
0.14
MAX
UNITS
DC source, V
Output Current Variation Due to
Power-Supply Change
%/V
DC sink, V
measured at 1.2V
OUT
DC source, V = 3.3V
Output Current Variation Due to
Output-Voltage Change
CC
%/V
μA
DC sink, V = 3.3V
CC
Output Leakage Current at Zero
Current Setting
I
-1
+1
ZERO
Output Current Differential
Linearity
DNL
INL
(Notes 6, 7)
(Notes 7, 8)
-0.5
-1
+0.5
+1
LSB
LSB
Output Current Integral Linearity
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 9)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
μs
μs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
μs
μs
μs
ns
μs
ns
ns
μs
LOW
t
HIGH
t
t
t
0
0.9
HD:DAT
SU:DAT
SU:STA
Data Setup Time
100
START Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Setup Time
0.6
t
(Note 10)
(Note 10)
20 + 0.1C
20 + 0.1C
0.6
300
300
R
B
t
F
B
t
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 10)
400
pF
B
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Input resistors (R ) must be between the specified values to ensure the device meets its accuracy and linearity specifications.
FS
Note 3: Supply current specified with all outputs set to zero current setting. SDA and SCL are connected to V . Excludes current
CC
through R resistors (I
). Total current including I
is I + (2 x I
).
RFS
FS
RFS
RFS
CC
Note 4: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Guaranteed by design.
Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
2
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard-mode timing.
Note 10: C —total capacitance of one bus line in pF.
B
_______________________________________________________________________________________
3
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
Pin Description
NAME
SDA
PIN
1
FUNCTION
2
2
I C Serial Data. Input/output for I C data.
2
2
SCL
2
I C Serial Clock. Input for I C clock.
FS1
3
Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current
for each output. FS0 controls OUT0; FS1 controls OUT1.
DS432
FS0
5
GND
OUT0
OUT1
4
Ground
6
Current Outputs. Sinks or sources the current determined by the register settings and the
resistance connected to FS0 and FS1.
7
V
CC
8
Power Supply
Typical Operating Characteristics
(Applies to OUT0 and OUT1. V
otherwise noted.)
= 2.7V to 5.0V, SDA = SCL = V , T = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
CC A
CC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
VOLTCO (SOURCE)
150
125
100
75
150
125
100
75
-150
-175
-200
-225
-250
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 OR FS1.
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 OR FS1.
40kΩ LOAD ON FS0 AND FS1.
V
= 5.5V
CC
V
= 2.7V
CC
V
CC
= 3.3V
50
50
25
25
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
20
40
60
80
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
V
(V)
OUT
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
VOLTCO (SINK)
300
250
200
150
100
50
650
550
450
350
250
150
50
250
225
200
175
150
RANGE FOR THE 50μA TO 200μA CURRENT
SOURCE RANGE.
RANGE FOR THE 50μA TO 200μA CURRENT
SINK RANGE.
40kΩ LOAD ON FS0 AND FS1.
+25°C TO -40°C
+25°C TO +85°C
+25°C TO -40°C
+25°C TO +85°C
-50
0
-150
-250
-50
0
25
50
75
100
125
0
25
50
75
100
125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(V)
SETTING (DEC)
SETTING (DEC)
V
OUT
4
_______________________________________________________________________________________
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
DS432
Typical Operating Characteristics (continued)
(Applies to OUT0 and OUT1. V
otherwise noted.)
= 2.7V to 5.0V, SDA = SCL = V , T = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
CC A
CC
INTEGRAL LINEARITY
DIFFERENTIAL LINEARITY
1.0
1.0
0.8
RANGE FOR THE 50μA TO 200μA CURRENT
SOURCE AND SINK RANGE.
RANGE FOR THE 50μA TO 200μA CURRENT
SOURCE AND SINK RANGE.
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
100
125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
Block Diagram
SDA SCL
V
CC
2
I C-COMPATIBLE
SERIAL INTERFACE
DS4432
V
CC
F8h
F9h
SOURCE OR
SINK MODE
127 POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC0
CURRENT
DAC1
GND
FS1
R
FS0
OUT0
OUT1
R
FS0
FS1
_______________________________________________________________________________________
5
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
Memory Organization
Detailed Description
To control the DS4432’s current sources, write to the
memory addresses listed in Table 1.
2
The DS4432 contains two I C adjustable current DACs
that are each capable of sinking and sourcing current.
Each output (OUT0 and OUT1) has 127 sink and 127
2
Table 1. Memory Addresses
source settings that can be controlled by the I C inter-
face. The full-scale ranges and corresponding step
sizes of the outputs are determined by external resis-
tors, connected to pins FS0 and FS1.
MEMORY ADDRESS
CURRENT SOURCE
(HEX)
DS432
F8h
F9h
OUT0
OUT1
The formula to determine R (connected to the FSx
FS
pins) to attain the desired full-scale current range is:
Equation 1:
The format of each output control register is:
V
16 × I
RFS
R
=
× 127
FS
FS
MSB
LSB
S
D
6
D
5
D
4
D
3
D
2
D
1
D
0
where I is the desired full-scale current value, V
is
FS
RFS
the R voltage (see the DC Electrical Characteristics
FS
table), and R is the external resistor value.
FS
where:
To calculate the output current value (I
corresponding DAC value (see Table 1 for corresponding
memory addresses), use equation 2.
) based on the
OUT
POWER-ON
DEFAULT
BIT NAME
FUNCTION
Determines if DAC sources or
sinks current. For sink
S = 0; for source S = 1.
Equation 2:
Sign
Bit
S
0b
DAC Value(dec)
I
=
× I
FS
OUT
127
7-Bit Data Controlling DAC
Output. Setting 0000000b
outputs zero current regardless
of the state of the sign bit.
On power-up the DS4432 outputs zero current. This is
done to prevent the device from sinking or sourcing an
incorrect amount of current before the system host con-
troller has had a chance to modify the DS4432’s setting.
D
Data
0000000b
X
Example: R
= 80kΩ and register 0xF8h is written to
As a source for biasing instrumentation or other circuits,
the DS4432 provides a simple and inexpensive current
FS0
a value of 0xAAh. Calculate the output current.
2
DAC with an I C interface for control. The adjustable
I
FS
= (0.997V/80kΩ) x (127/16) = 98.921µA
full-scale range allows the application to get the most
out of its 7-bit sink or source resolution.
The MSB of the output register is 1, so the output is sourc-
ing the value corresponding to position 2Ah (42 decimal).
The magnitude of the output current is equal to:
When used in adjustable power-supply applications
(see the Typical Operating Circuit), the DS4432 does
not affect the initial power-up voltage of the supply
because it defaults to providing zero output current on
power-up. As the device sources or sinks current into
the feedback-voltage node, it changes the amount of
output voltage required by the regulator to reach its
steady-state operating point. Using the external resistor,
98.921µA x (42/127) = 32.714µA
2
I C Serial Interface Description
2
I C Slave Address
The DS4432’s slave address is 90h.
2
I C Definitions
R
, to set the output current range, the DS4432 pro-
FS
The following terminology is commonly used to describe
vides some flexibility for adjusting the impedances of
the feedback network or the range over which the power
supply can be controlled or margined.
2
I C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
6
_______________________________________________________________________________________
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
DS432
Slave Devices: Slave devices send and receive
data at the master’s request.
Data is shifted into the device during the rising edge
of the SCL.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 1) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is reading
bits from the slave.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a one during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 2). An
ACK is the acknowledgement that the device is
properly receiving data. A NACK is used to termi-
nate a read sequence or as an indication that the
device is not receiving data.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 1 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
applicable timing.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit-write definition,
and the acknowledgement is read using the bit-read
definition.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup and hold time requirements (Figure 1).
SDA
t
BUF
t
t
F
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 1. I C Timing Diagram
_______________________________________________________________________________________
7
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
2
TYPICAL I C WRITE TRANSACTION
MSB
1
LSB
R/W
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
0
0
1
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER/MEMORY ADDRESS
SLAVE
ADDRESS
DATA
DS432
2
EXAMPLE I C TRANSACTIONS
90h
F9h
A) SINGLE BYTE WRITE
-WRITE RESISTOR
F9h TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1
START
STOP
90h
F8h
91h
DATA
B) SINGLE BYTE READ
-READ RESISTOR F8h
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
1 0 0 1 0 0 0 1
START
1 0 0 1 0 0 0 0
STOP
1 1 1 1 1 0 0 0
2
Figure 2. I C Communication Examples
2
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
I C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately fol-
lowing a START condition. The slave address byte
contains the slave address in the most significant 7
bits, and the R/W bit in the least significant bit. The
DS4432’s slave address is 90h.
Applications Information
Example Calculation
for an Adjustable Power Supply
When the R/W bit is 0 (such as in 90h), the master is
indicating it will write data to the slave. If R/W = 1
(91h in this case), the master is indicating it wants to
read from the slave. If an incorrect slave address is
written, the DS4432 assumes the master is commu-
In this example, the typical operating circuit is used to
create Figure 3, a 2.0V voltage supply with 20ꢀ mar-
gin. The adjustable power supply has a DC-DC convert-
er output voltage, V
, of 2.0V and a DC-DC converter
OUT
FB
0B
feedback voltage, V , of 0.8V. To determine the rela-
2
nicating with another I C device and ignores the
tionship of R and R , start with the equation:
0A
communication until the next START condition is
sent.
R
0B
V
=
× V
OUT
FB
R
+ R
0B
2
0A
Memory Address: During an I C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
Substituting V = 0.8V and V
= 2.0V, the relation-
FB
OUT
ship between R and R is determined to be:
0A
0B
R
0A
= 1.5 x R
0B
8
_______________________________________________________________________________________
2
Dual-Channel, I C, 7-Bit Sink/Source
Current DAC
DS432
I
is chosen to be 100µA (midrange source/sink
To create a 20ꢀ margin in the supply voltage, the value
OUT0
current for the DS4432). Summing the currents into the
feedback node, we have the following:
of V
is set to 2.4V. With these values in place, R
OUT 0B
is calculated to be 2.67kΩ, and R is calculated to be
0A
4kΩ. The current DAC in this configuration allows the
output voltage to be moved linearly from 1.6V to 2.4V
using 127 settings. This corresponds to a resolution of
6.3mV/step.
I
= I
− I
OUT0
R0B R0A
where
and
V
V
CC
Decoupling
FB
I
=
R0B
To achieve the best results when using the DS4432,
decouple the power supply with a 0.01µF or 0.1µF
capacitor. Use a high-quality ceramic surface-mount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance,
and ceramic capacitors tend to have adequate high-
frequency response for decoupling applications.
R
0B
V
− V
FB
OUT
I
=
R0A
R
0A
V
CC
V
OUT
= 2.0V*
OUT
FB
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
DC-DC
CONVERTER
I
I
R
= 4kΩ
R0A
0A
DS4432
OUT0
V
FB
= 0.8V*
R0B
R
0B
= 2.67kΩ
GND
FS0
I
OUT0
R
FS0
= 80kΩ
*V
OUT
AND V VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH V
AND V OF THE DS4432.
OUT RFS
FB
Figure 3. Example Application Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0036
8 µSOP
U8+1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
DS4432U+T&R
D/A Converter, 1 Func, Serial Input Loading, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
MAXIM
©2020 ICPDF网 联系我们和版权申明