DS4625P+150/200 [MAXIM]

3.3V Dual-Output LVPECL Clock Oscillator; 3.3V双输出LVPECL时钟振荡器
DS4625P+150/200
型号: DS4625P+150/200
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

3.3V Dual-Output LVPECL Clock Oscillator
3.3V双输出LVPECL时钟振荡器

振荡器 时钟
文件: 总6页 (文件大小:130K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
19-4558; Rev 0; 4/09  
3.3V Dual-Output LVPECL Clock Oscillator  
DS4625  
General Description  
Features  
The DS4625 is a dual-output, low-jitter clock oscillator  
capable of producing frequency output pair combina-  
tions ranging from 100MHz to 625MHz. The device  
combines an AT-cut crystal, an oscillator, and a low-  
noise phase-locked loop (PLL) in a 5.0mm x 3.2mm  
surface-mount LCCC package. Standard frequency  
options are listed in the Ordering Information/Selector  
Guide table. For custom frequency options, contact the  
factory at: Custom.Oscillators@maxim-ic.com.  
Standard Clock Output Frequencies: 100MHz,  
125MHz, 150MHz, 156.25MHz, and 200MHz  
Phase Jitter < 0.7ps RMS (typical) from 12kHz to  
20MHz  
LVPECL Output  
+3.3V 10ꢀ Operatinꢁ Voltaꢁe  
-40°C to +70°C Temperature Ranꢁe  
Excellent Power-Supply Noise Rejection  
5.0mm x 3.2mm Ceramic LCCC Packaꢁe  
Output Enable/Disable  
The DS4625 provides dual, low-voltage, positive emit-  
ter-coupled logic (LVPECL) clock output drivers. The  
output drivers can be enabled and disabled through  
the OE pin, which is an active-high CMOS input that  
has an internal pullup resistor. When high, both output  
pairs are enabled.  
The device operates from a single +3.3V 10ꢀ supply.  
The operating temperature range is -40°C to +70°C.  
Applications  
XGMII Clock Oscillator  
InfiniBand™  
SAS/SATA  
®
PCIe  
1GbE/10GbE  
Ordering Information/Selector Guide  
FREQUENCY (OP1:ON1)  
FREQUENCY (OP2:ON2)  
TOP  
MARK  
PART  
TEMP RANGE  
PIN-PACKAGE  
(MHz) (f )*  
C
(MHz) (f )*  
C
DS4625P+100/150  
DS4625P+125/125  
DS4625P+125/156  
DS4625P+150/150  
DS4625P+150/200  
-40°C to +70°C  
-40°C to +70°C  
-40°C to +70°C  
-40°C to +70°C  
-40°C to +70°C  
100.000  
125.000  
125.000  
150.000  
150.000  
150.000  
125.000  
156.250  
150.000  
200.000  
10 LCCC  
10 LCCC  
10 LCCC  
10 LCCC  
10 LCCC  
6AC  
6BB  
6BD  
6CC  
6CE  
+Denotes a lead(Pb)-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both  
lead-based and lead-free soldering processes.  
*Standard frequency options. Contact the factory at Custom.Oscillators@maxim-ic.com for custom frequencies.  
Pin Confiꢁuration and Typical Application Circuit appear at end of data sheet.  
InfiniBand is a trademark and service mark of the InfiniBand Trade Association.  
PCIe is a registered trademark of PCI-SIG Corp.  
________________________________________________________________ Maxim Inteꢁrated Products  
1
For pricinꢁ, delivery, and orderinꢁ information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
3.3V Dual-Output LVPECL Clock Oscillator  
ABSOLUTE MAXIMUM RATINGS  
(All voltages referenced to ground unless otherwise noted.)  
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.0V  
Operating Temperature Range ...........................-40°C to +70°C  
Junction Temperature......................................................+150°C  
θ
...................................................................+90°C/W (Note 1)  
JA  
Storage Temperature Range...............................-55°C to +85°C  
Soldering Temperature (3 passes max of reflow)......Refer to the  
IPC/JEDEC J-STD-020 Specification.  
Note 1: Package thermal resistances were obtained using a two-layer board. For detailed information on package thermal consider-  
ations, refer to www.maxim-ic.com/thermal-tutorial.  
DS4625  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
2.97  
0.7 x  
TYP  
MAX  
UNITS  
Operating Voltage Range  
V
3.3  
3.63  
V
CC  
Input-Voltage High (OE)  
Input-Voltage Low (OE)  
V
V
V
V
IH  
CC  
V
CC  
0.3 x  
V
0
IL  
V
CC  
ELECTRICAL CHARACTERISTICS  
(V = +2.97V to +3.63V, T = -40°C to +70°C, typical values are at V = +3.3V and T = +25°C, unless otherwise noted.) (Notes 2, 3)  
CC  
A
CC  
A
PARAMETER  
SYMBOL  
CONDITIONS  
LVPECL, output unloaded  
LVPECL, output loaded  
MIN  
TYP  
65  
MAX  
90  
UNITS  
mA  
I
CC_PU  
Operating Current  
I
120  
80  
140  
115  
mA  
CC_PL  
I
V
= V  
mA  
CC_OEZ  
OE  
IL  
f
f
OUT1  
OUT2  
Output Frequency  
Startup Time  
V
= V  
f
MHz  
ms  
OE  
IH  
C
t
(Note 4)  
1.0  
START  
Temperature, aging, load, supply, and  
initial tolerance (Note 5)  
Frequency Stability  
f  
f
-50  
-35  
+50  
+35  
ppm  
TOTAL/ C  
Frequency Stability Over  
Temperature with Initial  
Tolerance  
f  
/f  
V
CC  
= +3.3V  
ppm  
TEMP C  
Initial Tolerance  
f  
/f  
V
V
= +3.3V, T = +25°C  
20  
1
ppm  
INITIAL C  
CC  
A
Frequency Change Due to V  
f  
= +3.3V 10%, T = +25°C  
-3  
+3  
ppm/V  
CC  
VCC  
CC  
A
Frequency Change Due to Load  
Variation  
f  
/f  
10% variation in termination resistance  
ppm  
LOAD C  
Aging (15 Years)  
f  
/f  
-7  
+7  
ppm  
AGING C  
OE Pullup Resistance  
R
T
A
= +25°C  
70  
100  
130  
k  
PU  
2
_______________________________________________________________________________________  
3.3V Dual-Output LVPECL Clock Oscillator  
DS4625  
ELECTRICAL CHARACTERISTICS (continued)  
(V = +2.97V to +3.63V, T = -40°C to +70°C, typical values are at V = +3.3V and T = +25°C, unless otherwise noted.) (Notes 2, 3)  
CC  
A
CC  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Output connected to 50at PECL_BIAS at  
- 2.0V  
V
-
V
0.88  
-
CC  
CC  
Output High Voltage  
Output Low Voltage  
V
V
OH  
V
CC  
1.085  
Output connected to 50at PECL_BIAS at  
- 2.0V  
V
CC  
-
V
CC  
-
V
V
V
OL  
V
CC  
1.825  
1.62  
Output connected to 50at PECL_BIAS at  
- 2.0V  
Differential Output Voltage  
|V  
|
0.595  
0.710  
OD  
V
CC  
Output Rise Time  
Output Fall Time  
Duty Cycle  
t
20% to 80%  
80% to 20%  
200  
200  
ps  
ps  
%
R
t
F
D
45  
55  
CYCLE  
Propagation Delay from OE  
Going Low to Output High  
Impedance  
t
t
(See Figure 2)  
100  
ns  
PAZ  
Propagation Delay from OE  
Going High to Output Active  
(See Figure 2)  
100  
ns  
ps  
ps  
PZA  
Integrated phase RMS, 12kHz to 20MHz,  
Jitter  
J
0.7  
0.1  
RMS  
V
CC  
= +3.3V, T = +25°C  
A
Accumulated Deterministic  
Jitter Due to Reference Spurs  
125.00MHz output, V = +3.3V,  
CC  
T
A
= +25°C  
10kHz  
100kHz  
200kHz  
1MHz  
12.9  
26.3  
20.1  
6.4  
ps  
ps  
ps  
ps  
Accumulated Deterministic  
Jitter Due to Power-Supply Noise  
(P-P) (Note 6)  
Note 2: Limits at -40°C are guaranteed by design and are not production tested.  
Note 3: AC parameters are guaranteed by design and not production tested.  
Note 4: Startup time is from V  
= V  
until PLL locks to the crystal oscillator output.  
CC  
CCMIN  
Note 5: Frequency stability is calculated as: Δf  
= Δf  
+ Δf  
x (3.3 x 10ꢀ) + Δf  
+ Δf  
.
TOTAL  
TEMP  
VCC  
LOAD  
AGING  
Note 6: Supply-induced jitter is the deterministic jitter as measured on a LeCroy SDA11000 measured with a 50mV  
sine wave  
P-P  
forced on V  
.
CC  
SINGLE-SIDEBAND PHASE NOISE  
SSB PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, +3.3V)  
UNITS  
OFFSET  
100Hz  
1kHz  
f
C
= 100MHz  
-71  
f
C
= 125MHz  
-85  
f
C
= 150MHz  
-84  
f
C
= 156.25MHz  
-79  
f
C
= 200MHz  
-85  
-116  
-117  
-116  
-115  
-113  
10kHz  
100kHz  
1MHz  
-119  
-118  
-116  
-117  
-113  
dBc/Hz  
-126  
-125  
-122  
-123  
-120  
-143  
-142  
-141  
-140  
-139  
10MHz  
20MHz  
-151  
-149  
-149  
-148  
-149  
-151  
-150  
-149  
-149  
-150  
_______________________________________________________________________________________  
3
3.3V Dual-Output LVPECL Clock Oscillator  
Typical Operating Characteristics  
(T = +25°C, unless otherwise noted.)  
A
f DEVIATION vs. V  
I
vs. V  
CC  
f DEVIATION vs. TEMPERATURE  
C
C
CC  
CC  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
140  
130  
120  
110  
100  
90  
50  
40  
DS4625  
I
CC_PU  
30  
20  
10  
ONE OUTPUT LOADED  
0
-10  
-20  
-30  
-40  
-50  
80  
I
CC_PL  
70  
60  
50  
3.0  
3.1  
3.2  
3.3  
V
3.4  
3.5  
3.6  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
-40  
-20  
0
20  
40  
60  
(V)  
V
(V)  
TEMPERATURE (°C)  
CC  
CC  
Pin Description  
PIN  
NAME  
FUNCTION  
1
2, 3  
4
OE  
Active-High Output Enable. Has an internal pullup resistor (R ).  
PU  
GND  
OP1  
ON1  
Ground  
Positive Output 1 for LVPECL  
Negative Output 1 for LVPECL  
Supply Voltage Input  
5
6
V
CC  
A1, A2  
A3  
A4  
N.C.  
OP2  
ON2  
No Internal Connection. Must be connected to ground.  
Positive Output 2 for LVPECL  
Negative Output 2 for LVPECL  
Exposed Pad. The exposed pad must be used for thermal relief. This pad must be connected to  
ground.  
EP  
4
_______________________________________________________________________________________  
3.3V Dual-Output LVPECL Clock Oscillator  
DS4625  
V
CC  
V
CC  
R
PU  
OE  
X1  
X2  
X0  
PLL  
OP1  
LC-VCO  
DIV M  
DIV N  
LVPECL  
PFD  
LPF  
ON1  
OP2  
ON2  
DIV P  
DS4625  
LVPECL  
GND  
Figure 1. Block Diagram  
0.7 x V  
CC  
OE  
0.3 x V  
CC  
t
PZA  
t
PAZ  
OP_  
ON_  
PECL_BIAS  
PECL_BIAS  
PECL_BIAS  
PECL_BIAS  
Figure 2. LVPECL Output Timing Diagram When OE is Enabled and Disabled  
_______________________________________________________________________________________  
5
3.3V Dual-Output LVPECL Clock Oscillator  
Pin Configuration  
Detailed Description  
The DS4625 is a dual-output, low-jitter clock oscillator  
that produces frequency output pair combinations as  
shown in the Ordering Information/Selector Guide table.  
The phase relationship between the outputs is not guar-  
anteed. The device combines an AT-cut, fundamental-  
mode crystal, an oscillator, and a low-noise PLL in a  
5.0mm x 3.2mm surface-mount LCCC package.  
TOP VIEW  
N.C.  
A1  
N.C.  
A2  
+
DS4625  
OE  
GND  
GND  
1
6
5
4
V
CC  
The DS4625 provides dual LVPECL clock output dri-  
vers. The output drivers can be enabled and disabled  
through the OE pin. The OE pin is an active-high CMOS  
input that has an internal pullup resistor. When OE is  
high, both output pairs are enabled.  
2
3
ON1  
OP1  
DS4625  
*EP  
A3  
Chip Information  
A4  
PROCESS: Bipolar SiGe  
OP2  
ON2  
Package Information  
For the latest package outline information and land patterns, go  
to www.maxim-ic.com/packaꢁes.  
(5.00mm × 3.20mm × 1.49mm)  
*EXPOSED PAD  
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.  
10 LCCC  
L1053+H2  
21-0389  
Typical Application Circuit  
V
OP1  
CC  
0.1μF  
0.01μF  
50Ω  
PECL_BIAS AT V - 2.0V  
CC  
DS4625  
50Ω  
ON1  
OP2  
OE  
50Ω  
50Ω  
PECL_BIAS AT V - 2.0V  
CC  
GND  
ON2  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2009 Maxim Integrated Products  
Maxim is a registered trademark of Maxim Integrated Products, Inc.  

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