DS4830A [MAXIM]
Optical Microcontroller;
| 型号： | DS4830A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Optical Microcontroller 微控制器 |
| 文件： | 总32页 (文件大小：1366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS4830A
Optical Microcontroller
General Description
Benefits and Features
● 16-Bit Low Power Microcontroller
The DS4830A is a low-power, 16-bit microcontroller with a
unique peripheral set supporting optical applications that
require high-resolution conversion of many analog sig-
nals and digital signal processing (DSP) of those signals,
high-speed data communication to an external host, and
ultra-low power dissipation. A wide variety of optical trans-
ceiver controller applications is supported without need of
external circuitry, thereby minimizing cost and PCB area.
● Slave Communication Interface: 400kHz without
2
Clock Stretching I C-Compatible 2-Wire or SPI
2
● Master Communication Interface: 400kHz I C-
Compatible 2-Wire, SPI, or Maxim 3-Wire Laser
Driver
● Pin-Compatible with DS4830
● 32KWords Flash Program Memory
● 2KWords Data RAM
Power dissipation and throughput are optimized through
the use of a programmable round-robin analog-to-digital
converter (ADC) and 10-bit fast comparator, which oper-
ate completely independently of the core and significantly
relieve core overhead. A dual multiply/accumulate (MAC)
is included to minimize interrupt service timing/design
complexity. Ten 16-bit PWM channels are included to pro-
vide an unprecedented level of precision in digital power-
control applications.
● 4KWords ROM Memory
● 32-Level Stack Memory
● 2.85V to 3.63V Operating Voltage Range
● 8 Independent 12-Bit Voltage DACs with 2.5V
Internal Reference or External Reference
● 10 x 16-Bit PWM Channels
• Supports 4-Channel TECC H-Bridge Control
• Boost/Buck DC-DC Control
The DS4830A provides a complete optical control, cali-
bration, and monitor solution compatible with SFF-8472.
Additional resources include a fast/accurate ADC, fast
comparators with an internal comparison digital-to-analog
converter (DAC), eight independent 12-bit DACs, an
accurate internal temperature sensor, two fast sample/
holds with various programmable options, and a multi-
protocol serial master/slave interface. An independent,
• 1MHz Switching Frequency
● 13-Bit ADC with 26-Input Mux
• 40ksps
• Individual Channel Averaging Option
● Two Independent Sample/Holds with Individual
Channel Averaging Option
• 1V Full Scale
2
400kHz-compliant, slave I C interface with four configu-
• 300ns Sample Time
rable slave addresses facilitates communication to a host,
in addition to password-protected in-system programming
of the on-chip flash.
● Fast Temperature Measurement with Averaging Option
• Internal Temperature Sensor, ±2°C
● 10-Bit Fast Comparator with 16 Input Mux
● 31 GPIO Pins
Extensive design-in and applications support are available,
including comprehensive user’s and programmer’s guides,
complete reference designs with documented code, and
in-depth application notes showing numerous code exam-
ples in both C and assembly language. Firmware develop-
ment is supported by third-party vendors.
● Internal 20MHz Oscillator
● Up to 133MHz External Clock for PWM and Timers
● Two 16-Bit Timers and One Programmable Watchdog Timer
● Maskable Interrupt Sources
● Fast Hardware CRC-8 for Packet Error Checking (PEC)
Applications
● PON Diplexers and Triplexers: GPON, 10GEPON,
2
● I C and JTAG Bootloader
● Four Software Interrupts
XPON OLT, ONU
● Supply Voltage Monitor (SVM) and Brownout Monitor
● JTAG Port with In-System Debug and Programming
● Optical Transceivers: XFP, SFP, SFP+, QSFP+,
CSFP, 40G, 100G
● Low Power Consumption (16mA) with All Analog
Active
Ordering Information appears at end of data sheet.
● 5mm x 5mm, 40-Pin TQFN Package
19-6870; Rev 1; 1/17
DS4830A
Optical Microcontroller
Absolute Maximum Ratings
V
to GND .......................................................-0.3V to +3.97V
Continuous Power Dissipation (T = +70°C)
DD
A
SCL, SDA, RST..................................................-0.3V to +3.63V
TQFN (derate 27.8mW/°C above + 70°C) .............2222.2mW
All Other Pins to GND except
Operating Temperature Range............................-40ºC to +85ºC
Storage Temperature Range.............................-55ºC to +125ºC
Lead Temperature (soldering, 10s) ............................. …+300°C
Soldering Temperature (reflow)................................... …+260°C
REG18 and REG274...........................-0.3V to (V
+ 0.5V)*
DD
Continous Sink Current...................... 20mA per pin, 50mA total
Continous Source Current.................. 20mA per pin, 50mA total
*Subject to not exceeding +3.97V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
40 TQFN
Package Code
T4055+2
21-0140
90-0016
Outline Number
Land Pattern Number
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Recommended Operating Conditions
(T = -40ºC to +85ºC, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.85
0.7 x
TYP
MAX
UNITS
V
DD
Operating Voltage
V
(Note 2)
3.63
V
DD
V
+
DD
0.3
Input Logic-High
Input Logic-Low
V
V
V
IH
V
DD
0.3 x
V
-0.3
IL
V
DD
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DS4830A
Optical Microcontroller
DC Electrical Characteristics
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
DD
A
DD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CPU mode, all analog disabled
(Notes 3, 4)
I
7.25
CPU
I
2.5
1.5
FASTCOMP
Supply Current
mA
I
Both sample/hold
SAMPLEHOLDS
I
2.5
ADC
I
Per channel (Note 5)
0.7
DACS
Brownout Voltage
V
Monitors V
Monitors V
(Note 2)
(Note 2)
(Note 2)
2.62
110
1.8
V
mV
V
BO
DD
DD
Brownout Hysteresis
V
BOH
1.8V Regulator Initial Voltage
2.74V Regulator Initial Voltage
V
1.71
2.68
1.89
2.80
REG18
V
(Note 2)
2.74
V
REG270
f
OSC-
PERIPHERAL
T
= +25°C (Note 6)
20
10
A
Clock Frequencies
MHz
f
T
T
= +25°C (Note 6)
= -40°C to +85°C
MOSC-CORE
A
A
Clock Error
f
5
%
ERR
External Clock Input
f
20
133
MHz
XCLK
Voltage Range: GP[15:0], SHEN,
DACPW[7:0], REFINA, REFINB
V
(Note 2)
-0.3
V
+ 0.3
0.4
V
V
V
RANGE
DD
Output Logic-Low: All Pins
V
I
I
= 4mA (Note 2)
= -4mA (Note 2)
OL1
OL
Output Logic-High: All Pins Except
GP2, GP3, SCL, SDA
V
V
- 0.5
DD
OH1
OH
Pullup Current: All Pins Except GP2,
GP3, SCL, SDA
I
V
= 0V
PIN
55
µA
PU1
GPIO Drive Strength, Extra Strong
Outputs: GP0, GP1, MCS, PWM8,
PWM9
R
9
8
22
22
HISt
Ω
R
LOSt
R
17
12
27
31
32
32
46
52
GPIO Drive Strength, Strong
Outputs: MSDI, DACPW3, DACPW6
HIA
Ω
Ω
R
LOA
R
GPIO Drive Strength, Excluding
Strong GPIO Outputs
HIB
R
LOB
DAC
DAC Resolution
DAC
12
Bits
%
R
DAC Internal Reference Accuracy
DAC
(Note 5)
-1.25
+1.25
2.5
REFACC
DAC Internal Reference Power-Up
Speed
t
99% settled
10
µs
V
DACPUP
Reference Input Full-Scale Range
(REFINA, REFINB)
REFFS
1
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DS4830A
Optical Microcontroller
DC Electrical Characteristics (continued)
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
DD
A
DD A
PARAMETER
SYMBOL
CONDITIONS
Per channel
MIN
TYP
MAX
UNITS
See the DC Electrical
DAC Operating Current
I
mA
DACS
Characteristics
DAC Integral Nonlinearity
DAC Differential Nonlinearity
DAC Offset
DACINL
(Note 5)
5
LSB
LSB
DACDNL
Not production tested (Notes 5, 7)
At code “0”
±1
V
0
18
3
mV
OFFSET-DAC
DAC Source Load Regulation
I
0 to full-scale output, V
= 3.3V
mV/mA
DAC-SOURCE
DD
0 to 0.5V output, limited by output
buffer impedance
R
500
10
Ω
mV/mA
µs
DAC-SINK
DAC Sink Capability and Sink Load
Regulation
I
0.5V to full-scale output
5
DAC-SINK
Output load capacitance between
33pF to 270pF, from 10% to 90%
DAC Settling Time
t
DAC
FAST COMPARATOR
Fast Comparator Resolution
FC
10
Bits
%
R
Fast Comparator Internal Reference
Accuracy
FC
±0.2
REFTC
See the DC Electrical
Fast Comparator Operating Current
Fast Comparator Full Scale
I
mA
V
FASTCOMP
Characteristics
V
T
= +25°C
A
2.42
±2
FS-COMP
INL
Fast Comparator Integral
Nonlinearity
Differential mode, 2.2nF capacitor
at input (Note 7)
LSB
Fast Comparator Differential
Nonlinearity
Differential mode, 2.2nF capacitor
at input (Note 8)
DNL
±0.5
±2
LSB
LSB
V
OFFSET-
COMP
Fast Comparator Offset
Fast Comparator Input Impedance
Fast Comparator Input Capacitance
Fast Comparator Sample Rate
ADC
R
C
15
4
MΩ
pF
IN-COMP
IN-COMP
f
625
ksps
COMP
ADC Resolution
ADC
V
≥ 1.2V (Note 9)
FS
13
Bits
%
R
ADC Internal Reference Accuracy
ADC
-0.85
+0.85
1.236
REFACC
10kΩ < REFOUT load,
= 2.2nF
Reference Output Accuracy
ADC Operating Current
REFOUT
1.214
1.225
V
C
MAX
See the DC Electrical
I
mA
ADC
Characteristics
ADC Full-Scale 1
ADC Full-Scale 2
ADC Full-Scale 3
V
V
V
Factory calibrated
Factory calibrated
Factory calibrated
1.2
0.6
2.4
V
V
V
FS-ADC1
FS-ADC2
FS-ADC3
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DS4830A
Optical Microcontroller
DC Electrical Characteristics (continued)
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
DD
A
DD A
PARAMETER
SYMBOL
CONDITIONS
Factory calibrated
13-bit, T = +25°C, V
MIN
TYP
MAX
UNITS
ADC Full-Scale 4
V
6.55
V
FS-ADC4
= 3.3V,
DD
A
ADC Integral Nonlinearity
ADCINL
±3
LSB
V
(Note 10)
FS-ADC3
ADC Differential Nonlinearity
ADC Sample-Sample Deviation
ADC Offset
ADCDNL
V
≥ 1.2V
±0.5
±2
LSB
LSB
LSB
MΩ
FS
ADC full scale set to V
FS-ADC3
V
13-bit, V ≥ 1.2V
-8
+1
15
+8
OFFSET-ADC
FS
ADC[15:0] Input Resistance
ADC Sample Rate
R
IN-ADC
f
(Note 11)
40
ksps
µs
SAMPLE
ADC Temperature Conversion Time
t
With default ADC clock
41
TEMP
Internal Temperature Measurement
Error
TINT
(Note 12)
±2
°C
ERR
SAMPLE/HOLD
Sample/Hold Input Range
Sample/Hold Capacitance
Sample Input Leakage
V
ADC-SHN[1:0] = GND
1
V
SHP
C
ADC-SHP[1:0] to ADC-SHN[1:0]
ADC-SHP[1:0] and ADC-SHN[1:0]
5
pF
µA
SH
SHLKG
I
1.2
ADC-SHP[1:0] and ADC-SHN[1:0]
connected to 50Ω voltage source
Sample Time
t
300
ns
s
Sample Conversion Complete
Sample Offset
t
(Note 13)
320
7
µs
h
V
Measured at 10mV
-10
-4
-1.6
mV
SH-OFF
VADC-SHP_ to VADC-SHN_ =
300mV,
ts = 300ns, driven with 50Ω voltage
source
Sample Error
ERR
+4
%
SH
ADC-SHP[1:0] or ADC-SHN[1:0]
to GND
Sample Discharge Strength
FLASH MEMORY
R
50
Ω
DIS
t
Mass erase
Page erase
(Notes 14, 15)
25
25
75
ME
Flash Erase Time (Note 14)
ms
t
PE
Flash Programming Time per Word
Flash Programming Temperature
t
µs
°C
PROG
T
-40
20,000
100
+85
FLASH
Write
Cycles
Flash Endurance
Data Retention
n
T
T
= +50°C (Note 7)
= +50°C (Note 7)
FLASH
A
A
t
Years
RET
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DS4830A
Optical Microcontroller
AC Electrical Characteristics
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C COMPATIBLE INTERFACE (See Figure 1)
SCL/MSCL Clock Frequency
f
Timeout not enabled
400
100
kHz
kHz
SCL
SCL Bootloader Clock
Frequency
f
SCL:BOOT
Bus Free Time Between a STOP
and START Condition
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated)
START Condition
t
t
(Note 16)
HD:STA
Low Period of SCL/MSCL Clock
High Period of SCL/MSCL Clock
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a (Repeated)
START Condition
0.6
µs
SU:STA
HD:DAT
Receive
Transmit
0
Data Hold Time (Note 17)
Data Setup Time
t
ns
ns
pF
300
100
t
SU:DAT
SCL/MSCL, SDA/MSDA
Capacitive Loading
C
(Note 18)
(Note 18)
(Note 18)
400
300
300
B
Rise Time of Both SDA and SCL
Signals
t
20 + 0.1C
ns
R
B
B
Fall Time of Both SDA and SCL
Signals
t
20 + 0.1C
0.6
ns
µs
ns
F
Setup Time for STOP Condition
t
SU:STO
Spike Pulse Width That Can Be
Suppressed by Input Filter
t
(Note 19)
50
SP
SCL/MSCL and SDA/MSDA
Input Capacitance
C
5
pF
BIN
SMBusTimeout
t
30
ms
SMBUS
JTAG INTERFACE (See Figure 2)
JTAG Logic Reference
TCK High Time
V
V
/2
DD
V
REF
t
0.5
0.5
µs
µs
µs
TH
TCK Low Time
t
TL
TCK Low to TDO Output
t
0.125
TLQ
TMS, TDI Input Setup to TCK
High
t
t
0.25
µs
µs
DVTH
TMS, TDI Input Hold after TCK
High
0.25
THDX
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DS4830A
Optical Microcontroller
AC Electrical Characteristics (continued)
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3-WIRE DIGITAL INTERFACE (See Figure 3)
MSCL Clock Frequency
MSCL Duty Cycle
f
1000
kHz
%
SCLOUT
t
50
3WDC
MSDIO Setup Time
MSDIO Hold Time
t
100
100
500
ns
ns
ns
DS
DH
t
MCS Pulse-Width Low
t
CSW
MCS Leading Time Before the
First MSCL Edge
t
500
ns
L
MCS Trailing Time After the Last
MSCL Edge
t
500
10
ns
T
MSDIO, MSCL Load
C
Total bus capacitance on one line
pF
B3W
SPI DIGITAL INTERFACE SPECIFICATION (See Figure 4 and Figure 5)
SPI Master Operating Frequency 1/t
(Note 14)
(Note 14)
5
MHz
MHz
ns
MSPICK
SPI Slave Operating Frequency
SPI I/O Rise/Fall Time
1/t
2.5
25
SSPICK
t
C = 15pF, pullup = 560Ω
L
SPI_RF
MSPICK Output Pulse-Width
High/Low
t
- t
/2
MSPICK
t
, t
ns
ns
MCH MCL
SPI_RF
MSPIDO Output Hold After
MSPICK Sample Edge
t
- t
/2
MSPICK
t
MOH
SPI_RF
MSPIDO Output Valid to MSPICK
Sample Edge (MSPIDO Setup)
t
- t
/2
MSPICK
t
ns
MOV
SPI_RF
MSPIDI Input Valid to MSPICK
Sample Edge (MSPIDI Setup)
t
2t
ns
ns
ns
ns
ns
ns
MIS
SPI_RF
0
MSPIDI Input to MSPICK Sample
Edge Rise/Fall Hold
t
MIH
MSPICK Inactive to MSPIDO
Inactive
t
/2
MSPICK
- t
t
MLH
SPI_RF
SSPICK Input Pulse-Width High/
Low
t
, t
t
/2
SCH SCL
SSPICK
SSPICS Active to First Shift Edge
t
t
t
SSE
SPI_RF
SPI_RF
SSPIDI Input to SSPICK Sample
Edge Rise/Fall Setup
t
SIS
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DS4830A
Optical Microcontroller
AC Electrical Characteristics (continued)
(V
= 2.85V to 3.63V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SSPIDI Input from SSPICK
Sample Edge Transition Hold
t
t
ns
SIH
SPI_RF
SSPIDO Output Valid After
SSPICK Shift Edge Transition
t
2t
ns
ns
ns
ns
SOV
SPI_RF
t
+
SSPICK
t
SSPICS Inactive
t
SSH
SPI_RF
SSPICK Inactive to SSPICS
Rising
t
t
SD
SPI_RF
SSPIDO Output Disabled After
SSPICS Edge Rise
2t
+
SSPICK
t
SLH
2t
SPI_RF
Note 1: Limits are 100% production test at T = +25°C. Limits over the operating temperature range and relevant supply voltage
A
range are guaranteed by design and characterization.
Note 2: All voltages referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 3: Maximum current assuming 100% CPU duty cycle.
Note 4: The value does not include current in GPIO, SCL, SDA, MSDIO, MSDI, MSCL, REFINA, and REFINB.
Note 5: Using 2.5V internal reference.
Note 6: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
Note 7: Guaranteed by design.
Note 8: Tested at worse-case positions.
Note 9: Default or slower ADC clock settings.
Note 10: Computed using end-point best fit and histogram method.
Note 11: ADC conversions are delayed up to 1.6µs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
Note 12: Temperature readings averaged 64 times.
Note 13: Time from valid sample to ADC data available (without any averaging).
Note 14: Minimum and maximum timings depend upon f
error.
MOSC-CORE
Note 15: Programming does not include overhead associated with the utility ROM interface.
Note 16: f must meet the minimum clock low time plus the rise/fall times.
SCL
Note 17: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V
of the SCL signal) to
IH:MIN
bridge the undefined region of the falling edge of SCL.
Note 18: C —total capacitance of one bus line in pF.
B
Note 19: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
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DS4830A
Timing Diagrams
SDA
Optical Microcontroller
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
ILMAX
IHMIN
2
Figure 1. I C Timing Diagram
t
TL
V
TCK
TMS/TDI
TDO
REF
t
TH
t
t
THDX
DVTH
t
TLQ
Figure 2. JTAG Timing Diagram
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DS4830A
Optical Microcontroller
Timing Diagrams (continued)
WRITE MODE
MCS
MSCL
t
t
T
L
t
CL
t
CH
0
1
2
3
4
5
6
7
8
9
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
t
DS
MSDIO
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
t
DH
READ MODE
MCS
MSCL
t
t
T
L
t
CL
t
CH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
DS
MSDIO
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
t
DH
Figure 3. 3-Wire Timing Diagram
SHIFT
SAMPLE
SHIFT
SAMPLE
MSPICS
(SAS = 0)
t
MSPICK
1/0
1/0
0/1
MSPICK
CKPOL/CKPHA
0/1
t
t
MCL
MCH
1/1
0/0
1/1
0/0
MSPICK
CKPOL/CKPHA
t
MOH
t
SPI_RF
t
t
MLH
MOV
MSPIDO
MSPIDI
MSB
MSB-1
LSB
t
t
MIH
MIS
MSB
MSB-1
LSB
Figure 4. SPI Master Communications Timing Diagram
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DS4830A
Optical Microcontroller
Timing Diagrams (continued)
SHIFT
SAMPLE
SHIFT
SAMPLE
t
SSH
SSPICS
(SAS = 1)
t
SSE
t
SD
t
SSPICK
1/0
0/1
1/0
SSPICK
CKPOL/CKPHA
0/1
t
t
SCL
SCH
1/1
0/0
1/1
0/0
SSPICK
CKPOL/CKPHA
t
t
SIH
SIS
SSPIDI
MSB
MSB-1
LSB
t
SPI_RF
t
t
SLH
SOV
SSPIDO
MSB
MSB-1
LSB
Figure 5. SPI Slave Communications Timing Diagram
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DS4830A
Optical Microcontroller
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
IDDDAC vs. VDD
IDD CPU vs. VDD
toc01
toc02
7.3
7.25
7.2
6.1
6.05
6
5.95
5.9
7.15
7.1
5.85
5.8
5.75
5.7
7.05
TA = +25oC
3.45
TA = +25oC
7
5.65
2.85
2.85
2.85
3
3
3
3.15
3.3
3.45
3.6
2.85
2.85
0
3
3.15
VDD (V)
3.3
3.6
VDD (V)
IDD ADC vs. VDD
IDD FASTCOMP vs. VDD
toc03
toc04
2.85
2.825
2.8
2.48
2.45
2.42
2.39
2.36
2.33
2.3
2.775
2.75
2.725
2.7
TA = +25oC
3.45
TA = +25oC
3.15
VDD (V)
3.3
3.6
3
3.15
VDD (V)
3.3
3.45
3.6
IDD FASTCOMP vs. VDD
ADC INL vs. INPUT VOLTAGE
toc04
toc06
0.5
0
2.48
2.45
2.42
2.39
2.36
2.33
2.3
-0.5
-1
-1.5
-2
-2.5
-3
TA = +25oC
TA = +25oC
3.15
VDD (V)
3.3
3.45
3.6
0.2
0.4
0.6
0.8
1
1.2
INPUT VOLTAGE (V)
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DS4830A
Optical Microcontroller
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DAC INL vs. DAC SETTING
DAC DNL vs. DAC SETTING
toc07
toc08
0.4
0.3
0.2
0.1
0
4
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
No Load,
No Load, 3.3V,
TA = +25oC
VDD = 3.3V, TA = +25oC
0
1023
2046
3069
4092
0
1023
2046
3069
4092
DAC SETTING (COUNT)
DAC SETTING
FAST COMP DNL vs. FAST COMP
SETTING
FAST COMP INL vs. FAST COMP
SETTING
toc09
toc10
0.5
0.4
0.3
0.2
0.1
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
-0.4
-0.5
3.3V, TA = +25oC
-1.2
-1.4
3.3V,
A = +25oC
T
0
127 254 381 508 635 762 889 1016
FAST COMP SETTING
0
127 254 381 508 635 762 889 1016
FAST COMP SETTING
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DS4830A
Optical Microcontroller
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
20
31
32
33
GP13
REFINA
DACPW0
DACPW1
19 GP12
18 GP11
17 GP10
DACPW2 34
16
REG18
15 GP9
14
35
36
37
38
39
40
DACPW3
DACPW4
DACPW5
DACPW6
REFINB
DS4830A
GP8
13 GP7
12
EP
+
GP6
11 GP5
DACPW7
1
2
3
4
5
6
7
8
9
10
TQFN
(5mm x 5mm)
Pin Description
INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION)
PORT
PIN
NAME
STATE
High
Impedance
1
RST
Digital
None
RST
—
—
—
—
—
—
—
—
—
2
High
Impedance
I C Slave
SPI
2
SCL
Digital
Digital
Open Drain
Open Drain
—
Clock SCL SSPICK
2
High
Impedance
I C Slave
Data SDA
SPI
SSPIDI
3
SDA
—
Push-Pull,
Extra Strong
ADC-
D0P
PWM-
ALT0
4
GP0
ADC/Digital Input
55µA Pullup
2.74V
ADC-S0
P2.0
—
Only function is for bypass capacitors for
2.74V internal regulator
5
REG274
GP1
V
None
REG
Push-Pull,
Extra Strong
ADC-
D0N
PWM-
ALT1
6
ADC/Digital Input
55µA Pullup
ADC-S1
ADC-VDD
ADC-S2
ADC-S3
REFOUT P2.1
Voltage Supply, ADC
Input
7
V
None
None
None
V
—
—
—
—
—
—
—
—
DD
DD
High
Impedance
ADC-
SHP0
ADC-
D1P
8
GP2
GP3
SH Input, ADC Input
SH Input, ADC Input
High
Impedance
ADC-
SHN0
ADC-
D1N
9
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DS4830A
Optical Microcontroller
Pin Description (continued)
INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION)
PORT
P6.0
P6.1
P2.2
P2.3
P2.4
PIN
10
11
NAME
GP4
GP5
GP6
GP7
GP8
STATE
ADC-
D2P
ADC/Digital Input
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
55µA Pullup
55µA Pullup
55µA Pullup
55µA Pullup
55µA Pullup
JTAG TCK ADC-S4
—
—
ADC-
D2N
ADC/Digital Input
ADC/Digital Input
ADC/Digital Input
ADC/Digital Input
ADC/Digital Input
JTAG TDI
ADC-S6
ADC-S7
ADC-S8
ADC-S9
ADC-S5
ADC-
D3P
SPI
12
13
14
PWM2
PWM3
—
SSPIDO
ADC-
D3N
SPI
SSPICS
ADC-
D4P
—
—
ADC-
D4N
15
16
17
GP9
REG18
GP10
Push-Pull
None
55µA Pullup
1.8V
—
P2.5
—
V
Pin for 1.8V regulator bypass capacitor
REG
ADC-
S10
ADC-
D5P
ADC/Digital Input
ADC/Digital Input
Push-Pull
55µA Pullup
JTAG TMS
JTAG TDO
ADC-S12
ADC-S13
ADC-S14
—
—
—
—
—
P6.2
ADC-
S11
ADC-
D5N
18
19
20
21
GP11
GP12
GP13
GP14
Push-Pull
Push-Pull
Push-Pull
Push-Pull
55µA Pullup
55µA Pullup
55µA Pullup
55µA Pullup
P6.3
P0.0
P0.1
P0.2
SH Input, ADC/Digital
Input
ADC-
SHP1
ADC-
D6P
SH Input, ADC/Digital
Input
ADC-
SHN1
ADC-
D6N
ADC-
D7P
ADC/Digital Input
SHEN1
—
ADC-
D7N
22
23
24
GP15
SHEN
MSDIO
ADC/Digital Input
Digital
Push-Pull
Push-Pull
Push-Pull
55µA Pullup
55µA Pullup
55µA Pullup
ADC-S15
SHEN0
—
—
P0.3
P6.4
P1.0
—
—
2
3-Wire Data
MSDIO
I C
SPI
PWM-
ALT4
Digital
MSDA MSPIDO
Push-Pull,
Strong
SPI
—
PWM-
ALT5
25
26
MSDI
MSCL
MCS
Digital
Digital
55µA Pullup
55µA Pullup
55µA Pullup
—
P1.3
P1.1
MSPIDI
2
3-Wire Clock
MSCL
I C
SPI
PWM-
ALT6
Push-Pull
MSCL MSPICK
Push-Pull,
Extra Strong
3-Wire Chip
Select MCS
SPI
—
PWM-
ALT7
27
28
29
Digital
Voltage Supply
Digital
P1.2
—
MSPICS
V
None
V
ADC-VDD
—
—
—
—
DD
DD
Push-Pull,
Extra Strong
PWM9
PWM8
55µA Pullup
55µA Pullup
55µA Pullup
PWM9
—
—
P0.7
Push-Pull,
Extra Strong
30
31
Digital
PWM8
—
—
—
—
—
—
P0.6
P2.6
Reference,
ADC/Digital Input
ADC-
REFINA
REFINA
Push-Pull
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DS4830A
Optical Microcontroller
Pin Description (continued)
INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION)
PORT
PIN
NAME
STATE
DAC0, FS
= REFINA
or Internal
Reference
High
Impedance
32
DACPW0
Digital
Push-Pull
Push-Pull
Push-Pull
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
—
—
—
—
—
—
—
—
P0.4
DAC1, FS
= REFINA
or Internal
Reference
High
Impedance
33
34
35
36
37
DACPW1
DACPW2
DACPW3
DACPW4
DACPW5
Digital
Digital
Digital
Digital
Digital
Digital
P0.5
P6.5
P1.5
P1.6
P1.7
DAC2, FS
= REFINA
or Internal
Reference
High
Impedance
CLKIN
—
DAC3, FS
= REFINA
or Internal
Reference
Push-Pull,
Strong
High
Impedance
DAC4, FS
= REFINB
or Internal
Reference
I2C
MSDA-
ALT
High
Impedance
Push-Pull
Push-Pull
DAC5, FS
= REFINB
or Internal
Reference
I2C
MSCL-
ALT
High
Impedance
DAC6, FS
= REFINB
or Internal
Reference
Push-Pull,
Strong
High
Impedance
38
39
40
—
DACPW6
REFINB
DACPW7
EP
PWM6
—
—
—
—
—
—
—
—
—
P6.6
P1.4
P2.7
—
Reference, ADC/
Digital Input
ADC-
REFINB
Push-Pull
Push-Pull
—
55µA Pullup
DAC7, FS
= REFINB
or Internal
Reference
High
Impedance
Digital
PWM7
—
Exposed Pad
(Connect to GND)
GND
—
Note: Bypass V , REG274, and REG18 each with 1µF X5R and 10nF capacitors to ground. All input-only pins and open-drain out-
DD
puts are high impedance after V
exceeds V
and prior to code execution. Except for pins having DAC functions, pins configured
DD
BO
as GPIO have a weak internal pullup at power-up. See the Selectable Functions table for more information.
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DS4830A
Optical Microcontroller
Selectable Functions
FUNCTION NAME
ADC-D[7:0][P/N]
ADC-REFIN[A/B]
ADC-S[15:0]
DESCRIPTION
Differential Inputs to ADC. Also used for sample/hold inputs.
REFINA and REFINB Monitor Inputs to ADC
Single-Ended Inputs to ADC
ADC-SH[P/N][1:0]
ADC-VDD
Sample/Hold Inputs 1 and 0
V
Monitor Input to ADC
DD
DAC[7:0]
Voltage DAC Outputs
Maxim Proprietary 3-Wire Interface: MSCL (3-Wire Master Clock), MCS (Chip Select), MSDIO (3-
Wire Data). Used to control the Maxim family of high-speed laser drivers.
MSCL, MCS, MSDIO
2
2
2
MSCL, MSDA
I C Master Interface: MSCL (I C Master Clock), MSDA (I C Master Data)
2
2
2
MSCL-ALT, MSDA-ALT
I C Master Interface: MSCL-ALT (I C Master Clock), MSDA (I C Master Data)
MSPICK, MSPICS, MSPIDI, SPI Master Interface: MSPICK (SPI Master Clock), MSPICS (Chip Select), MSPIDI (Master Data
MSPIDO
P0.n, P1.n, P2.n, P6.n
PWM[9:0]
In), MSPIDO (Master Data Out)
General-Purpose Inputs/Outputs. Can also function as edge interrupts.
PWM Outputs
PWM-ALT[9:0]
RST
PWM Alternate Outputs
Used by JTAG and as Active-Low Reset for Device
2
2
2
I C Slave Interface: SCL (I C Slave Clock), SDA (I C Slave Data). These also function as a
password-protected programming interface.
SCL, SDA
SHEN[1:0]
Sample/Hold Trigger Inputs
SSPICK, SSPICS, SSPIDI,
SSPIDO
SPI Slave Interface: SSPICK (Clock), SSPICS (Chip Select), SSPIDI (Data In), SSPIDO (Data
Out). In SPI slave mode, the I C slave interface is disabled.
2
TCK, TDI, TDO, TMS
REFOUT
JTAG Interface Pins. Also includes RST.
ADC Internal Reference Output
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DS4830A
Optical Microcontroller
Block Diagram
DS4830A
31 x GPIO
COMMUNICATION
SPI SLAVE
SPI MASTER
2
GP
PORT0
x8
I C 400kHz SLAVE
3W
MASTER
10 x PWMs16-BIT
2
I C 400kHz MASTER
8 x DACs
12-BIT VOLTAGE
INTERNAL REF
16-BIT CPU AT 10MHz
8K x 8
ROM
64K x 8
FLASH
4K x 8
SRAM
32 x 16
LEVEL STACK
2 x HARDWARE 16-BIT
MULTIPLIER AND 48-BIT
ACCUMULATOR
GP
PORT1
x8
2
I C BOOTLOADER
POR
WATCHDOG
2 x 16-BIT
TIMERS
FAST COMPARATOR
DAC 10-BIT
AMUX
16-CHANNEL 625ksps SEQUENCER
HIGH/LOW THRESHOLD COMPARISON
PROGRAMMABLE INTERRUPTS
GP
PORT2
x8
1.225V
VREF
DAC 10-BIT
1.8V
REGULATOR
ADC
V
, DAC INTERNAL REF
DD
GP
PORT6
x7
x2
SAMPLE AND HOLD
2.74V
REGULATOR
PROGRAMMABLE
INTERRUPTS
C
S
ADC
40ksps
13-BIT
AMUX
24-CHANNEL
SEQUENCER
WITH AVERAGING
20MHz
OSCILLATOR
18 SINGLE-ENDED/
8 DIFFERENTIAL INPUTS
TEMPERATURE SENSOR
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DS4830A
Optical Microcontroller
arithmetic and logical operations to use any register along
with the accumulator. Special-function registers control
the peripherals and are subdivided into register modules.
Detailed Description
The following is an introduction to the primary features
of the DS4830A optical microcontroller. More detailed
descriptions of the device features can be found in the
DS4830A User’s Guide.
Memory Organization
The device incorporates several memory areas:
Core Architecture
● 32KWords of flash memory for application program
and constant data storage
The device employs a low-power, low-cost, high-perfor-
mance, 16-bit RISC microcontroller with on-chip flash
memory. It is structured on an advanced, 16 accumulator-
based, 16-bit RISC architecture. Fetch and execution
operations are completed in one cycle without pipelining,
since the instruction contains both the op code and data.
The highly efficient core is supported by 16 accumulators
and a 32-level hardware stack, enabling fast subroutine
calling and task switching. Data can be quickly and
efficiently manipulated with three internal data pointers.
Multiple data pointers allow more than one function to
access data memory without having to save and restore
data pointers each time. The data pointers can auto-
matically increment or decrement following an operation,
eliminating the need for software intervention.
● 2KWords of SRAM
● 4KWords of utility ROM contain a debugger and pro-
gram loader
● 32-level stack memory for storage of program return
addresses and application use
The memory is implemented with separate address
spaces for program memory, data memory and register
space which also allows ROM, application code, and
data memory into a single contiguous memory map. The
device allows data memory to be mapped into program
space, permitting code execution from data memory.
In addition program memory may be mapped into data
space, permitting code constants to be accessed as data
memory. Figure 6 shows the DS4830A’s memory map
when executing from program memory space. Refer to
the DS4830A User’s Guide for memory map information
when executing from data or ROM space.
Module Information
Top-level instruction decoding is extremely simple and
based on transfers to and from registers. The registers
are organized into functional modules, which are in turn
divided into the system register and peripheral register
groups.
The incorporation of flash memory allows field upgrade of
the firmware. Flash memory can be password protected
with a 16-word key, denying access to program memory
by unauthorized individuals.
Peripherals and other features are accessed through
peripheral registers. These registers reside in modules
0–5. The following provides information about the specific
module that each peripheral resides in:
Utility ROM
The utility ROM is a 4KWord block of internal ROM
memory that defaults to a starting address of 8000h. The
utility ROM consists of subroutines that can be called from
application software, which include the following:
Module 0: Timer 1, GPIO Ports 0, 1, and 2
2
Module 1: I C Master, GPIO Port 6, Supply Voltage Monitor
2
Module 2: I C Slave
● In-system programming (bootstrap loader) over JTAG
Module 3: Timer 2, MAC-Related Registers, Software
Interrupt and General-Purpose Registers
2
or I C-compatible interfaces
● Callable routines for in-application flash programming
Module 4: ADC, Sample/Hold, Internal Temperature,
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of application code, or to one of the special
routines mentioned. Routines within the utility ROM are
firmware-accessible and can be called as subroutines by
the application software. More information on the utility
ROM contents is contained in the DS4830A User’s Guide.
3-Wire Master, SPI Slave, DAC
Module 5: Quick Trips, SPI Master, PWM
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
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DS4830A
Optical Microcontroller
SYSTEM
REGISTERS
PROGRAM
MEMORY SPACE
DATA MEMORY
(BYTE MODE)
DATA MEMORY
(WORD MODE)
FFFFh
8FFFh
FFFFh
FFFFh
8FFFh
8h
9h
Bh
Ch
Dh
Eh
Fh
AP
A
PFX
IP
SP
DPC
DP
9FFFh
8000h
4K x 16
UTILITY ROM
8K x 8
UTILITY ROM
4K x 16
UTILITY ROM
00h
0Fh
8000h
7FFFh
8000h
PERIPHERAL
REGISTERS
0h
1h
2h
3h
4h
5h
M0
M1
M2
M3
M4
M5
32K x 16
USER PROGRAM
FLASH MEMORY
00h
1Fh
1Fh
00h
0FFFh
0000h
07FFh
32 x 16
STACK
4K x 8
SRAM DATA
2K x 16
SRAM DATA
0000h
001Fh
0010h
0000h
PASSWORD
Figure 6. Memory Map When Program Is Executing from Flash Memory
following a mass erase. Mass erase can be performed
without password match.
Password
Some applications require protection against unauthor-
ized viewing of program code memory. For these applica-
Detailed information regarding the password can be
found in the DS4830A User’s Guide.
tions, access to in-system programming, in-application
programming, or in-circuit debugging is prohibited until a
password has been supplied. The password is defined as
the 16 words of physical program memory at addresses
0010h–001Fh.
Stack Memory
A 16-bit, 32-level internal stack provides storage for pro-
gram return addresses. The stack is used automatically
by the processor when the CALL, RET, and RETI instruc-
tions are executed and interrupts serviced. The stack can
also be used explicitly to store and retrieve data by using
the PUSH, POP, and POPI instructions.
A single password lock (PWL) bit is implemented in
the device. When the PWL is set to 1 (power-on reset
default) and the contents of the memory at addresses
0010h–001Fh are any value other than all FFh or 00h, the
password is required to access the utility ROM, including
in-circuit debug and in-system programming routines that
allow reading or writing of internal memory. When PWL is
cleared to 0, these utilities are fully accessible without the
password. The password is automatically set to all ones
On reset, the stack pointer, SP, initializes to the top of the
stack (1Fh). The CALL, PUSH, and interrupt-vectoring
operations increment SP, then store a value at the location
pointed to by SP. The RET, RETI, POP, and POPI opera-
tions retrieve the value at SP and then decrement SP.
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DS4830A
Optical Microcontroller
allows on-the-fly software updates in mission-critical
applications that cannot afford downtime. Alternatively, it
allows the application to develop custom loader software
that can operate under the control of the application soft-
ware. The utility ROM contains firmware-accessible flash
programming functions that erase and program flash
memory. These functions are described in detail in the
DS4830A User’s Guide.
Programming
The microcontroller’s flash memory can be programmed
by one of two methods: in-system programming and in-
application programming. These provide great flexibility in
system design as well as reduce the life-cycle cost of the
embedded system. Programming can be password pro-
tected to prevent unauthorized access to code memory.
In-System Programming
An internal bootstrap loader allows the device to be pro-
grammed over the JTAG or I C compatible interfaces.
Register Set
2
Sets of registers control most device functions. These
registers provide a working space for memory opera-
tions as well as configuring and addressing periph-
eral registers on the device. Registers are divided
into two major types: system registers (special pur-
pose registers, or SPRs) and peripheral registers (spe-
cial function registers, or SFRs). The system registers
includes the ALU, accumulator registers, data point-
ers, interrupt vectors and control, and stack pointer.
The peripheral registers define additional functionality
and the functionality is broken up into discrete modules.
Both the system registers and the peripheral registers are
described in detail in the DS4830A User’s Guide.
As a result, system software can be upgraded in-system,
eliminating the need for a costly hardware retrofit when
software updates are required.
The programming source select (PSS) bits in the ICDF
register determine which interface is used for boot loading
2
operation. The device supports JTAG and I C as an inter-
face corresponding to 00 and 01 bits of PSS, respectively
as shown in Figure 7.
In-Application Programming
The in-application programming feature allows the micro-
controller to modify its own flash program memory. This
ANY DEVICE
RESET OCCURS
WAIT FOR 320 SYSTEM
RESET DEVICE.
BEGIN BOOT ROM CODE
EXECUTION AT 8000h.
2
CYCLES (32µs). RESET I C.
SET PWL BIT.
SET ROD BIT.
YES
IS JTAG_SPE BIT SET?
BOOTLOADER
NO
SET USING JTAG PROGRAMMER,
FOLLOWED BY RESET OF DEVICE.
WAITS FOR EXIT LOADER
COMMAND FROM HOST
ROM CODE ENABLES
2
SLAVE I C INTERFACE:
ADDRESS IS 36h.
SET BY WRITING F0h TO
2
I C SLAVE 34h.
YES
IS I2C_SPE BIT SET?
NO
SET PSS[1:0] = 01
JUMP TO USER CODE
(FLASH) AT 0000h.
Figure 7. In-System Programming
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DS4830A
Optical Microcontroller
On power-up, the device always enters brownout state
first and then follows the above sequence. The reset
issued by brownout is same as POR. Any action per-
formed after POR also happens on brownout reset. All
the registers that are cleared on POR are also cleared on
brownout reset.
System Timing
The device generates its 10MHz instruction clock (MOSC)
and 20MHz peripheral clock internally. On power-up,
oscillator’s output (which cannot be accessed externally)
is disabled until V
rises above V . Once this threshold
DD
BO
is reached, the output is enabled after approximately 1ms
(t ), clocking the device as shown in Figure 8.
SU:MOSC
External Reset
Asserting the RST pin low causes the device to enter the
reset state. Execution resumes at location 8000h after
RST is released.
System Reset
The device features several sources that can be used
to reset the DS4830A. The DAC and PWM outputs are
maintained during execution of all resets except POR.
Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution. The
watchdog timer is a hardware timer designed to be peri-
odically reset by the application software. If the software
operates correctly, the timer is reset before it reaches its
maximum count. However, if undesirable code execution
prevents a reset of the watchdog timer, the timer reaches
its maximum count and resets the processor.
Power-On Reset
An internal power-on reset (POR) circuit is used to enhance
system reliability. This circuit forces the device to perform a
POR whenever a rising voltage on V
When this happens the following events occur:
climbs above V
.
DD
BO
● All registers and circuits enter their reset state.
● The POR flag (WDCN.7) is set to indicate the source
of the reset.
The watchdog timer is controlled through 2 bits in the
WDCN register (WDCN[5:4] : WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
● Code execution begins at location 8000h when the
reset condition is released.
12
21
ranging from 2 to 2 system clock (MOSC) periods
(0.410ms to 0.210s). The watchdog interrupt occurs at
the end of this timeout period, which is 512 MOSC clock
periods, or approximately 50µs, before the reset. The
reset generated by the watchdog timer lasts for 4 system
clock cycles, which is 0.4µs. Software can determine if a
reset is caused by a watchdog timeout by checking the
watchdog timer reset flag (WTRF) in the WDCN register.
Execution resumes at location 8000h following a watch-
dog timer reset. The watchdog reset has the same effect
as the external reset as far as the reset values of all reg-
isters are concerned.
Brownout Detect/Reset
The device features a brownout detect/reset function.
Whenever the power monitor detects a brown-out condi-
tion (when V
< V ), it immediately issues a reset and
DD
BO
stays in that state as long as V
remains below V
.
BO
DD
Once V
voltage rises above V , the device waits
DD
BO
for t
before returning to normal operation, also
SU:MOSC
referred to as CPU state. If a brownout occurs during this
the device again goes back to the brownout
t
SU:MOSC,
state. Otherwise, it enters into CPU state. In CPU state,
the brownout detector is also enabled.
t
= ~1ms
SU:MOSC
CORE
CLOCK
V
BO
V
DD
Figure 8. System Timing
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DS4830A
Optical Microcontroller
within the firmware-interrupt routine to avoid repeated
interrupts from the same source. Application software
must ensure a delay between the write to the flag and the
RETI instruction to allow time for the interrupt hardware
to remove the internal interrupt condition. Asynchronous
interrupt flags require a one-instruction delay and syn-
chronous interrupt flags require a two-instruction delay.
Internal System Reset
The host can issue an I C command (BBh) to reset the
2
communicating device. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1). This
reset has the same effect as the external reset as far as
the reset values of all registers are concerned.
When an enabled interrupt is detected, execution jumps
to a user-programmable interrupt vector location. The IV
register defaults to 0000h on reset or power-up, so if it is
not changed to a different address, application firmware
must determine whether a jump to 0000h came from a
RST or interrupt source.
Software Reset
The device UROM provides option to soft reset through
the application program. The application program can
jump to UROM code, which generates the internal sys-
tem reset. This reset has the same effect as the internal
system reset.
Once control has been transferred to the ISR, the inter-
rupt identification register (IIR) can be used to determine
which module was the source of the interrupt. In addition
to IIR, MIIR registers are implemented to indicate which
particular function under a peripheral module has caused
the interrupt. The device contains six peripheral modules,
M0 to M5. An MIIR register is implemented in modules
M1, M4, and M5. The MIIRs are 16-bit read only registers
and all of them default to all zero on system reset. Once
the module that causes the interrupt is singled out, it
can then be interrogated for the specific interrupt source
and software can take appropriate action. Interrupts are
evaluated by application code allowing the definition of
a unique interrupt priority scheme for each application.
Interrupt sources are available from the watchdog timer,
the ADC (including sample/holds and internal tempera-
ture), fast comparators, the programmable timers, SVM,
Further information regarding various resets can be found
in the DS4830A User’s Guide.
Programmable Timer
The device features two general-purpose programmable
timers. Various timing loops can be implemented using
the timers. The timer can be used in two modes: free-
running mode and compare mode. The functionality of the
timers can be accessed through three SFRs for each of
the general purpose timers. GTCN is the general control
register, GTV is the timer value register and GTC is the
timer compare register.
The timer SFRs are accessed in Module 0 and 3. Detailed
information regarding the timer block can be found in the
DS4830A User’s Guide.
2
the I C-compatible master and slave interface, 3-wire,
master and slave SPI, software interrupts, as well as all
GPIO pins.
Hardware Multiplier
The hardware multiplier (a multiply-accumulate, or MAC
module) is a very powerful tool, especially for applications
that require heavy calculations. This multiplier is capable
of executing the multiply, multiply-negate, multiply-accu-
mulate, multiply-subtract operation for signed or unsigned
operands in a single machine cycle. The MAC module
uses 10 SFRs, mapped as register 0h–05h, 07h–09h and
0Eh in Module M3.
I/O Port
The device allows for most inputs and outputs to func-
tion as general purpose input and/or output pins. There
are four ports: P0, P1, P2, and P6. Note that there is no
port pin corresponding to P6.7. The 7th bit of port 6 is
nonfunctional in all SFRs. Each pin is multiplexed with at
least one special function, such as interrupts, ADC, DAC,
PWM, or JTAG pins etc.
System Interrupts
Multiple interrupt sources are available to respond to
internal and external events. The microcontroller archi-
tecture uses a single interrupt vector (IV) and single inter-
rupt-service routine (ISR) design. For maximum flexibility,
interrupts can be enabled globally, individually, or by mod-
ule. When an interrupt condition occurs, its individual flag
is set, even if the interrupt source is disabled at the local,
module, or global level. Interrupt flags must be cleared
The GPIO pins have Schmitt trigger receivers and full
CMOS output drivers, and can support alternate functions.
The ports can be accessed through SFRs (PO[0,1,2,6],
PI[0,1,2,6], PD[0,1,2,6], EIE[0,1,2,6], EIF[0,1,2,6], and
EIES[0,1,2,6]) in Modules 0 and 1 and each pin can be
individually configured. The pin is either high impedance
or a weak pullup when defined as an input, dependent on
the state of the corresponding bit in the output register.
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DS4830A
Optical Microcontroller
In addition, each pin can function as an external interrupt
with individual enable, flag and active edge selection,
when programmed as input.
sequence mode) or run a short burst of conversions
and enter a shut down mode to conserve power (single-
sequence mode).
The GPIO pins also having DAC function are by default
high impedance. The I/O port SFRs are accessed in
Module 0 and 1. Detailed information regarding the GPIO
block can be found in the DS4830A User’s Guide.
In voltage mode there are four full-scale values that
can be programmed. These values can be trimmed by
modifying the associated gain registers (ADCG1, ADCG2,
ADCG3, and ADCG4). By default these are set to 1.2V,
0.6V, 2.4V, and 6.55V full scale.
DAC Outputs
The ADC clock (ADCCLK) is derived from the system
clock with division ratio defined by the ADC control reg-
ister. The ADC sampling rate is approximately 40ksps for
the fastest ADC clock (Core Clk/8). The device provides
eight different ADC clock configurations to set differ-
ent ADC clock setting. Refer to the ADC section of the
DS4830A User’s Guide for different ADC clock settings.
In applications where extending the acquisition time is
desired, the sample can be acquired over a prolonged
period determined by the ADC control register.
The device provides eight 12-bit DAC outputs with mul-
tiple reference options. An internal 2.5V reference is pro-
vided. There are also two selectable external references.
REFINA pin can be selected as the full-scale reference
for DAC0 to DAC3. REFINB pin can be selected as the
full-scale reference for DAC4 to DAC7. The external
reference can be between 1.0V to 2.5V. The DAC out-
puts are voltage buffered. Each DAC can be individually
disabled and put into a low power power-down mode
using DACCFG.
Each ADC channel can have its own configuration, such
as differential mode select, data alignment select, acquisi-
tion extension enable and ADC gain select, etc. The ADC
also has 24 (0 to 23) 16-bit data buffers for conversion
result storage. The ADC data available interrupt flag
(ADDAI) can be configured to trigger an interrupt following
a predetermined number of samples. Once set, ADDAI
can be cleared by software or at the start of a conversion
process.
If a DAC output is used during the lifetime of the
DS4830A, the DAC must always be enabled to guarantee
meeting the INL and offset specifications. If a pin is used
for a DAC, it should be used only for the DAC function.
The pin’s function should not be switched between DAC
and PWM or switched between DAC and GPIO.
The DAC SFRs are accessed in Module 4. Detailed
information regarding the DAC block can be found in the
DS4830A User’s Guide.
The ADC controller provides options to average the ADC
results of individual channel. The device provides 1, 4, 8,
and 16 samples averaging configurations for each chan-
nel independently. The ADC’s internal reference can be
output at pin GP1.
Analog-to-Digital Converter, Sample/Hold
The analog-to-digital converter (ADC) controller is the
digital interface block between the CPU and the ADC. It
provides all the necessary controls to the ADC and the
CPU interface. The ADC uses a set of SFRs for configur-
ing the ADC in desired mode of operation.
ADCCFG
The device contains a 13-bit ADC with an input mux, as
shown in Figure 9. The mux selects the ADC input from
16 single-ended or eight differential inputs. Additionally,
the channels can be configured to convert internal
ADC-S[15:0]
ADC-D[7:0]
ADC-SHP[1:0]
ADC-SHN[1:0]
temperature, V , internal reference or REFINA/B. Two
DD
13-BIT ADC
ADGAIN
MUX
channels can be programmed to be sample/hold inputs.
The internal channel is used exclusively to measure the
die temperature. The SFR registers control the ADC.
ADC-REFIN[A/B]
ADC-VDD
PGA
ADC-VREF_2.5V
ADC-TINT
ADC
When used in voltage input mode, the voltage applied on
the corresponding channel (differential or single-ended)
is converted to a digital readout. The ADC can be set up
to continuously poll selected input channels (continuous-
ADCONV
(START CONVERSATION)
Figure 9. ADC Block Diagram
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Optical Microcontroller
capacitance on the input node and the sample capacitor
before sampling begins. The negative input pins are used
to reduce ground offsets and noise.
Sample/Hold
Pin combinations GP2-GP3 and GP12-GP13 can be used
for sample/hold conversions if enabled in the SHCN regis-
ter. These two can be independently enabled or disabled
by writing a 1 or 0 to their corresponding bit locations in
SHCN register. A data buffer location is reserved for each
channel. When a particular channel is enabled, a sample
of the input voltage is taken when a signal is issued on
the SHEN pin, converted and stored in the corresponding
data buffer.
The ADC controller provides options to average the sam-
ple/hold results of individual channel. The device provides
1, 2, 4, and 8 samples averaging configurations for each
channel independently.
The sample/hold inputs can be used for monitoring the
burst mode receive power signal in APD biasing and OLT
applications using current mirror, as shown Figure 10.
The two sample/hold channels can sample simultane-
ously on the same SHEN signal or different SHEN signals
depending on the SH_DUAL bit in the SHCN SFR.
Temperature Measurement
The device provides an internal temperature sensor for
die temperature monitoring which can be enabled inde-
pendently by setting the appropriate bit locations in the
TEMPCN register. Whenever a temperature conversion
is complete the INTDAI is set. This can be configured to
cause an interrupt, and can be cleared by software. The
temperature measurement resolution is 0.0625°C.
The sample/hold data available interrupt flag (SHnDAI)
can be configured to trigger an interrupt following sample
completion. Once set, SHnDAI can be cleared by software.
Each sample/hold circuit consists of a sampling capaci-
tor, charge injection nulling switches, and a buffer. Also
included is a discharge circuit used to discharge parasitic
3.3V
<76V
DS4830A PWM
APD BIAS
R
C
BSS123
APD FEEDBACK
TO ADC
R
D
MIRIN
DS1842
3.3V
V
CC
DS4830A
I
I
MIROUT/10
MIROUT/5
MIR1
MIR2
VINP
CLAMP
GND
CURRENT
LIMIT
S/H A
C
C
IN
C
C
S
R
IN
MIROUT
S
IN
I
BIAS
MCU
CORE
VINN
VINP
ADC
R
100Ω
R
1MΩ
AGC
A
APD VOLTAGE
MONITOR TO ADC
S/H B
C
C
IN
ROSA
C
C
S
R
15kΩ
B
4 x R
IN
S
IN
TIA
APD
VINN
SEN
GND
BURST MODE
RSSI TRIGGER
CONTROL LOGIC
Figure 10. Burst Mode RSSI Monitoring
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DS4830A
Optical Microcontroller
The ADC controller provides options to average the internal
temperature results. The device provides 1, 8, 16, and 32
samples averaging configurations for the internal temperature.
the corresponding PWM output and selects the PWM
polarity. The user can set the duty cycle and the frequen-
cy of each PWM output individually by configuring the cor-
responding DCYCn register and the PWMCFGn register.
The ADC related SFRs are accessed in Module 1 and
Module 4. For further detailed information regarding ADC can
be found in the ADC section of the DS4830A User’s Guide.
The device allows delta sigma dithering for each PWM
channel. The PWM outputs can be configured to be
output on an alternate location using the configuration
register. PWMDLY is a 16-bit register for providing start-
ing delay on different PWM channels, and can be used to
create multiphase PWM operation.
PWM Outputs
The device provides 10 independently configurable PWM
outputs. Each PWM output’s resolution can be config-
ured from 7-bit to 16-bit independently. The PWM outputs
are configured using three SFRs: PWMCN, PWMDATA,
and PWNSYNC. Using PWMCN and PWMDATA, indi-
vidual PWM channels can be programmed for unique Duty
Cycles (DCYCn), configurations (PWMCFGn) and delays
(PWMDLYn) where n represents the PWM channel number.
Different channels can be synchronized using the
PWMSYNC register. Doing so effectively brings the chan-
nels in phase by restarting the channels that are to be
synchronized. The PWM SFRs are accessed in Module 5.
Detailed information regarding the PWM block can be
found in the DS4830A User’s Guide.
The PWM clock can be obtained from the core clock,
peripheral clock or an external clock depending on
CLK_SEL bits programmed in individual PWMCFG
registers. The PWMCFGn register also enables/disables
Figure 11 shows how the PWM outputs can be used
to control a TEC. Refer to Application Note AN5424:
Thermoelectric Cooler Control Using the DS4830 Optical
Microcontroller for further detailed information.
DS1088EX
133MHz CLOCK
CLKIN
DS4830A
16-BIT PWM
PWM9
PWM8
16-BIT PWM
16-BIT PWM
V
CC
Q
BH
Q
AH
PWM1
P
P
V
V
A
B
R
L
SENSE
L
A
B
SIDE B
TEC
SIDE A
C
A
Q
BL
Q
AL
C
B
R
TH
N
N
PWM0
VREF
16-BIT PWM
ADC REFERENCE
VOLTAGE
MONITOR
R
THERMAL
FEEDBACK
ADC
CURRENT
MONITOR
Figure 11. TEC Application
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DS4830A
Optical Microcontroller
2
Details can be found in the I C master section of the
DS4830A User’s Guide.
Fast Comparator/Quick Trips
The device supports 10-bit quick trip comparison function-
ality. The quick trips may be used to continuously monitor
user defined channels in a round robin sequence. The
quick trip controller allows the user to control the list of
channels to monitor in the round-robin sequence.
2
I C-Compatible Slave Interface
The device also features an internal I C-compatible slave
interface for communication with a host. Furthermore,
the device can be in system programmed (bootloaded)
through the I C-compatible slave interface. The two inter-
2
2
The quick trip (analog) performs two comparisons on any
selected channel.
2
face signals used by the I C slave interface are SCL and
SDA. For the I C-compatible slave interface, the device
2
1) Comparison with a high threshold value.
2) Comparison with a low threshold value.
relies on an externally generated clock to drive SCL and
responds to data and commands only when requested by
Any comparison above the high threshold value or below
the low threshold value causes a bit to set in the cor-
responding register. This bit can be used to trigger an
interrupt. The threshold values are stored in 32 internal
register (16 for low threshold settings and 16 for high
threshold settings). The quick trip controller provides user
defined threshold values for the quick trips. Because the
quick trips and the ADC use the same input pins, the con-
troller ensures that no collision takes place.
2
2
the I C master device. The I C-compatible slave inter-
face is open-drain and requires external pull up resistors.
The device supports four slave addresses. Each slave
address has dedicated 8-byte transmit page and all slave
addresses share common 8-byte receive FIFO.
SMBus Timeout
2
Both the I C-compatible slave interfaces can work in
SMBus-compatible mode for communication with other
SMBus devices. To achieve this, a 30ms timer has been
implemented on the I C-compatible slave interface to
make the interface SMBus-compatible. The purpose of
this timer is to issue a timeout interrupt and thus the firm-
ware can reset the I C-compatible slave interface when
the SCL is held low for longer than 30ms. The timer only
starts when none of the following conditions is true:
The quick-trip-related SFRs are accessed in Module 5.
Refer to the quick trip section of the DS4830A User’s
Guide for more information.
2
2
2
I C-Compatible Interface Modules
2
The device provides two independent I C-compatible
interfaces, one is a master and another is a slave.
2
1) The I C-compatible slave interface is in the idle state
2
I C-Compatible Master Interface
and there is no communication on the bus.
2
The device features an internal I C-compatible master
2
2) The I C-compatible slave interface is not working in
interface for communication with a wide variety of external
SMBus-compatible mode.
2
2
I C devices. The I C-compatible master bus is a bidirec-
tional bus using two bus lines, the serial data line (MSDA)
3) The SCL logic level is high.
2
2
and the serial clock line (MSCL). For the I C-compatible
master, the device has ownership of the I C bus and
drives the clock and generates the START and STOP
signals. This allows the device to send data to a slave or
receive data from a slave.
4) The I C-compatible slave interface is disabled.
2
When a timeout occurs, the timeout bit is set and an
interrupt is generated, if enabled. The I C master related
SFRs are accessed in Module 1. The I C slave related
SFRs are accessed in Module 2. Details can be found in
2
2
2
The device has a configuration bit in the I2CCN_M regis-
the I C master and slave section of the DS4830A User’s
2
ter that allows the user to configure I C master MSDA and
Guide.
MSCL pins to two different set of pins.
PIN
I2CCN_M.I2CM_ALT = 0
I2CCN_M.I2CM_ALT = 1
MSDA
MSCL
P1.0
P1.1
P1.6
P1.7
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DS4830A
Optical Microcontroller
transfer. Writing a data character to the SPI data buffer
(SPIB), when in master mode, starts a data transfer. The
SPI master immediately shifts out the data serially on
MSPIDO, MSB first, while providing the serial clock on the
MSPICK output. New data is simultaneously gated in on
MSPIDI into the least significant bit (LSB) of the shift reg-
ister. At the end of a transfer, the received data is loaded
into the data buffer for reading, and the SPI transfer com-
plete flag (SPIC) is set. If SPIC is set, an interrupt request
is generated to the interrupt handler, if enabled.
Serial Peripheral Interface Module
The device supports master and slave SPI interfaces.
The SPI provides an independent serial communication
channel to communicate synchronously with peripheral
devices in a multiple master or multiple slave system. The
interface allows access to a four-wire, full-duplex serial
bus, and can be operated in either master mode or slave
mode. Collision detection is provided when two or more
masters attempt a data transfer at the same time. The
maximum data rate of the SPI is 1/4 the system reference
clock frequency for slave mode and 1/2 the system clock
frequency for master mode.
SPI Slave Interface
Slave mode is used when the SPI is controlled by another
peripheral device. The SPI is in slave mode when an inter-
nal bit (MSTM) is cleared to logic 0. In slave mode, the
SPI is dependent on the SPICK sourced from the master
to control the data transfer. The SPICK input frequency
should not be greater than the system clock frequency of
the slave device divided by 4. The SPI master transfers
data to a slave on the SSPIDI, MSB first, the selected
slave device simultaneously transfers the contents of its
shift register to the master on the SSPIDO, also MSB
first. Data received from the master replaces data in the
slave’s shift register at the completion of a transfer. Just
like in the master mode, received data is loaded into the
read buffer and the SPIC is set at the end of the transfer.
Setting the SPIC flag may cause an interrupt if enabled.
The SPI uses the following four interface signals:
●
Master In-Slave Out. This signal is an output from
a slave device, SSPIDO, and an input to the master
device, MSPIDI. It is used to serially transfer data
from the slave to the master. Data is transferred most
significant bit (MSB) first. The slave device places this
pin in an input state with a weak pullup when it is not
selected.
●
●
●
Master Out-Slave In. This signal is an output from
a master device, MSPIDO, and an input to the slave
devices, SSPIDI. It is used to serially transfer data from
the master to the slave. Data is transferred MSB first.
SPI Clock. This serial clock is an output from the mas-
ter device, MSPICK, and an input to the slave devices,
SSPICK. It is used to synchronize the transfer of data
between the master and the slave on the data bus.
The SPI master-related SFRs are accessed in Module 5.
The SPI slave-related SFRs are accessed in Module 4.
Details can be found in the SPI section of the DS4830A
User’s Guide.
Slave Select. The slave-select signal is an input to
enable the SPI module in slave mode, SSPICS, by a
master device. The SPI module supports configuration
of an active SSPICS state through the slave-active
select. Normally, this signal has no function in master
mode and its port pin can be used as a general-pur-
pose I/O. However, the SSEL can optionally be used
as mode fault detection in master mode.
3-Wire Interface Module
The device controls 3-wire slave devices like the MAX3798
and MAX3799 over a proprietary 3-wire interface. The
device acts as the 3-wire master, initiating communica-
tion with and generating the clock for the 3-wire slave. It
is a 3-pin interface consisting of MSDIO (a bidirectional
data line), an MSCL clock signal, and an MCS chip-select
output (active high).
SPI Master Interface
The master mode is used when the device’s SPI controls
the data transmission rates and data format. The SPI is
placed in master mode by setting the master mode bit
(MSTM). Only an SPI master device can initiate a data
The 3-wire master-related SFRs are accessed in Module 4.
Detailed information regarding the 3-wire interface block
can be found in the DS4830A User’s Guide.
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DS4830A
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In-Circuit Debug
Applications Information
Embedded debugging capability is available through the
JTAG-compatible test access port (TAP). Embedded
debug hardware and embedded ROM firmware provide
in-circuit debugging capability to the user application,
eliminating the need for an expensive in-circuit emulator.
Figure 12 shows a block diagram of the in-circuit debug-
ger. The in-circuit debug features include the following:
Power-Supply Decoupling
To achieve the best results when using the DS4830A,
decouple the V
power supply with a 0.1µF X5R
DD
capacitor. Use a high-quality, ceramic, surface-mount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance, and
ceramic capacitors tend to have adequate high-frequency
response for decoupling applications.
● Hardware debug engine
● Set of registers able to set breakpoints on register,
code, or data accesses (ICDA, ICDB, ICDC, ICDD,
ICDF, ICDT0, and ICDT1)
Decouple the REG274 and REG18 pins using 1µF X5R
and 10nF capacitors (one each/per output). Note: Do not
use either of these pins for external circuitry.
● Set of debug service routines stored in the utility ROM
Additional Documentation
The embedded hardware debug engine is an independent
hardware block in the microcontroller. The debug engine
can monitor internal activities and interact with selected
internal registers while the CPU is executing user code.
Collectively, the hardware and software features allow two
basic modes of in-circuit debugging:
Designers must have three documents to fully use
all the features of this device. This data sheet con-
tains pin descriptions, feature overviews, and elec-
trical specifications. Errata sheets contain devia-
tions from published specifications. User guides offer
detailed information about device features and opera-
tion. The following documents can be downloaded from
www.maximintegrated.com/DS4830A.
● Background mode allows the host to configure and set
up the in-circuit debugger while the CPU continues to
execute the application software at full speed. Debug
mode can be invoked from background mode.
● The DS4830A data sheet, which contains electrical/
timing specifications, package information, and pin
descriptions.
● Debug mode allows the debug engine to take control
of the CPU, providing read/write access to internal
registers and memory, and single-step trace operation.
● The DS4830A revision-specific errata sheet, if appli-
cable.
● The DS4830A User’s Guide, which contains detailed
information and programming guidelines for core fea-
tures and peripherals.
Development and Technical Support
DEBUG
SERVICE
ROUTINES
Maxim Integrated and third party suppliers provide a vari-
ety of highly versatile, affordably priced development tools
for this microcontroller, including the following:
DS4830A
(UTILITY ROM)
● Compilers (C and assembly)
● In-circuit debugger
CPU
DEBUG
ENGINE
● Integrated development environments (IDEs)
● Serial-to-JTAG converters for programming and
TMS
TCK
TDI
CONTROL
BREAKPOINT
ADDRESS
DATA
TAP
CONTROLLER
debugging
● USB-to-JTAG converters for programming and
TDO
debugging
A partial list of development tool vendors can be found at
www.maximintegrated.com/MAXQ_tools.
Figure 12. In-Circuit Debugger
Go to www.maximintegrated.com/support for addi-
tional technical support.
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DS4830A
Optical Microcontroller
Typical Application Circuit
V
(+3.3V)
R1
CC
VCCT
VSEL
25Ω
TOUTA
DS4830A
MODE_DEF2 (SDA)
MODE_DEF1 (SCL)
SLAVE
I C
MD
2
MAX3948
MAX3948
MAX3948
MAX3948
ALT
DFB
SCL
SDA
MSCL
MSDIO
MCS
ROSA
MASTER
2
I C
25Ω
TOUTC
VOUT
CSEL
13-BIT ADC
VCCT
VSEL
25Ω
TOUTA
MD
R2
BIAS
MONITOR
RSSI
MONITOR
DFB
SCL
SDA
25Ω
TOUTC
VOUT
CSEL
VCCT
VSEL
25Ω
TOUTA
MD
R3
DFB
SCL
SDA
25Ω
TOUTC
VOUT
CSEL
VCCT
VSEL
25Ω
TOUTA
MD
DFB
SCL
SDA
25Ω
TOUTC
VOUT
CSEL
Maxim Integrated
│ 30
www.maximintegrated.com
DS4830A
Optical Microcontroller
Ordering Information
PART
DS4830AT+
DS4830AT+T
TEMP RANGE
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
-40°C to +85°C
-40°C to +85°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Maxim Integrated
│ 31
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DS4830A
Optical Microcontroller
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
12/13
1/17
0
1
Initial release
Updated DAC Outputs section and Package Information table
—
2, 24
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 32
相关型号：
DS4830T+
RISC Microcontroller, 16-Bit, FLASH, MAXQ20 CPU, 10MHz, CMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-40
MAXIM
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