DS8102+ [MAXIM]
Dual Delta-Sigma Modulator and Encoder; 双Δ-Σ调制器和编码器
| 型号： | DS8102+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Delta-Sigma Modulator and Encoder |
| 文件： | 总9页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 2/09
Dual Delta-Sigma Modulator and Encoder
DS8102
General Description
Features
The DS8102 is a stand-alone, dual-channel, delta-
sigma modulator that converts measurements from two
differential analog input pairs into a Manchester-encod-
ed output bit stream that can be processed by a com-
panion microcontroller such as the MAXQ3108. One
channel operates at a fixed 1x gain, while the other
operates at a pin-selectable gain of 1x, 4x, 16x, or 32x.
The DS8102 includes an internal power-supply monitor,
on-board voltage reference, and low-power oscillator to
reduce the number of external components required for
data acquisition.
♦ Dual Delta-Sigma 2nd-Order Modulators
Channel 0: Pin-Selectable Gain of 1x, 4x, 16x,
or 32x
Channel 1: Fixed Gain of 1x
♦ Selectable Internal or External Voltage Reference
♦ Manchester-Encoded Bit Stream Output
Includes Synchronization Bits to Allow Clock
Recovery
Single-Pin Transmission Scheme Simplifies
Electrical Isolation Using Capacitive Coupling
The Manchester-encoded output from the DS8102
combines pulse-density-modulated measurement val-
ues from both differential input channels with a syn-
chronization bit stream and is transmitted over a single
pin. This transmission scheme is ideal for split voltage
domain applications where the DS8102 and other “hot”-
side components must be electrically isolated from
“cold” low-voltage components such as a companion
microcontroller. In this type of application, the DS8102
can be capacitively coupled to a companion microcon-
troller with only two connection points required
(MNOUT and DGND).
♦ Selectable Internal or External Clock Source
♦ Integrated Low-Power 8MHz Oscillator
♦ Operating Mode
Active Mode (8MHz, V
= 3.6V): 3.5mA
DD
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS8102+
-40°C to +85°C
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
The MAXQ3108 dual-core microcontroller, which
includes specialized Manchester bit-stream decoding
inputs and sinc3 filters, is specifically designed to act
as a companion microcontroller for up to three DS8102
devices. This configuration, which supports up to six
differential analog input channels, is well suited for
three-phase electricity-metering applications.
Pin Configuration
TOP VIEW
+
DGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Applications
APDREF
AGND
V
RST
Single-Phase Electricity Metering
Three-Phase Electricity Metering
Power-Line Conditioning
REF
DS8102
AN1-
AN1+
AN0-
AN0+
MNOUT
CLKIO
G1
Electrochemical and Optical Sensors
Industrial Control
G0
V
DD
CLKSEL
Data-Acquisition Systems and Data Loggers
TSSOP
Typical Operating Circuit appears at end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual Delta-Sigma Modulator and Encoder
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Voltage Range on V
Relative to DGND.............-0.3V to +4.0V
Relative to AGND.............-0.3V to +4.0V
Voltage Range on AN0+, AN0-, AN1+, and AN1-
DD
DD
Relative to AGND ...............................................-4.0V to +4.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Voltage Range on AGND Relative to DGND.........-0.3V to +0.3V
Voltage Range on Any Pin Relative to DGND
Except AN0+, AN0-, and AN1+, AN1-...............-0.3V to +4.0V
DS8102
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V, T = -40°C to +85°C, f
= 8MHz, V = internal, OSR = 128, unless otherwise noted.) (Note 1)
REF
A
CLK
TYP
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Supply Voltage
V
V
3.3
2.8
3.5
3.6
2.99
5.0
V
V
DD
RST
Power-Fail Reset Voltage
V
RST
Monitors V
DD
2.7
Active V Current
DD
I
Normal operation
RST = 0 or V < V
RST
mA
DD
Shutdown (Power-Down) V
Current
DD
I
2
nA
STOP
DD
Input Low Voltage
Input High Voltage
V
DGND
0.7 x V
0.3 x V
V
V
IL
DD
V
V
DD
IH
DD
Output Low Voltage
(CLKIO, MNOUT)
V
I
I
= 4mA
= -4mA
DGND
0.4
V
V
OL
OL
Output High Voltage
(CLKIO, MNOUT)
V
V
DD
- 0.4
OH
OH
Input/Output Pin Capacitance
Input Leakage Current (All Inputs)
CLOCK SOURCE
C
I
(Note 3)
15
pF
nA
IO
-100
+100
L
External Clock Input Frequency
External Clock Input Period
f
CLKSEL = 1
CLKSEL = 1
CLKSEL = 1
DC
125
40
8
MHz
ns
XCLK
t
XCLK-CLCL
External Clock Input Duty Cycle
t
60
%
XCLK-DUTY
Internal Oscillator Output
Frequency
f
CLKSEL = 0
CLKSEL = 0
7.5
8.0
8.5
MHz
%
ICLK
Internal Oscillator Output Duty
Cycle
t
47.8
49.1
49.7
ICLK-DUTY
ANALOG-TO-DIGITAL CONVERTER
AFE Warmup Delay
t
t
f
f
= 8MHz (Notes 1, 4)
= 8MHz (Notes 1, 5)
1.02
7.17
ms
ms
WU1
ICLK
ICLK
Reference Buffer Warmup Delay
WU2
OSR = 32
16
19
OSR = 64
Decimator Output (Note 6)
Bits
OSR = 128
OSR = 256
(Notes 1, 6)
Gain = 1 (Note 6)
22
24
Integral Nonlinearity
Offset Error
INL
±0.01
%FSR
mV
1.4
2
_______________________________________________________________________________________
Dual Delta-Sigma Modulator and Encoder
DS8102
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V, T = -40°C to +85°C, f
= 8MHz, V = internal, OSR = 128, unless otherwise noted.) (Note 1)
REF
A
CLK
TYP
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS
V
= 3.0V to 3.6V, AN0+ = AN0- = AGND,
DD
DC Power-Supply Rejection Ratio
Signal-to-Noise Ratio
PSRR
SINAD
THD
95
85
dB
dB
100mV ripple on V
DD
V
DD
= 3.6V, gain = 1, AN0 = 500mV
,
,
,
P-P
P-P
P-P
70
70
sinewave at 62.5Hz
V
DD
= 3.6V, gain = 32, AN0 = 20mV
85
sinewave at 62.5Hz
V = 3.6V, gain = 32, AN0 = 20mV
DD
sinewave at 62.5Hz
Total Harmonic Distortion
(to 21st Harmonic)
-95
-70
+1
dB
V
ANALOG-TO-DIGITAL CONVERTER INPUTS
Input Voltage Range
AN0+, AN0-, AN1+, and AN1- to AGND
-1
Gain = 1
1
4
Gain = 4
Input Sampling Capacitance
(Note 1)
C
pF
MHz
kꢀ
IN
Gain = 16
Gain = 32
Clock at 8MHz (Note 7)
Gain = 1
16
32
Input Sampling Rate
f
0.667
750
187
47
S
Gain = 4
Input Impedance to AGND for
8MHz (Note 8)
Gain = 16
Gain = 32
Gain = 1
23.4
1500
375
94
Gain = 4
Differential Input Impedance for
8MHz (Note 9)
kꢀ
Gain = 16
Gain = 32
46.9
7
Input Bandwidth (-3dB)
kHz
V
External Reference Input Voltage
V
REF
1.2
1.25
1.3
1
External Reference Input
Sampling Capacitance
2
pF
Reference Input Sampling Rate
INTERNAL REFERENCE
Reference Output Voltage
f
0.67
MHz
S
1.24
30
V
Reference Output Temperature
Coefficient
ppm/°C
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Typical values are not guaranteed. These values are measured at room temperature, V
Note 3: These numbers are guaranteed by design and are not tested.
= 3.3V.
DD
Note 4: Calculated as t
Note 5: Calculated as t
= 1/f
= 1/f
x 8192.
x 57,344.
WU1
WU2
ICLK
ICLK
Note 6: Parameter specifications are based upon the presence of an external cubic sinc filter (as implemented in the MAXQ3108)
for generating full ADC output codewords.
Note 7: f = f
/12. f
is the system clock frequency.
S
CLK
CLK
Note 8: This is a function of input sampling capacitance (C ) and sampling frequency, and can be approximated as 6/(f
x C ).
IN
IN
CLK
Note 9: Z (differential) = 2 x Z (single-ended).
IN
IN
_______________________________________________________________________________________
3
Dual Delta-Sigma Modulator and Encoder
Pin Description
PIN
1
NAME
DGND
AGND
FUNCTION
Digital Ground
Analog Ground
2
Reference Voltage Input/Output. When APDREF = 0, the buffered internal voltage reference is driven on
this pin as an output and can be used by other devices. When APDREF = 1, an external voltage
reference must be provided on this pin.
DS8102
3
V
REF
4
5
AN1-
AN1+
AN0-
AN0+
Negative Input for Differential Analog Input Channel 1
Positive Input for Differential Analog Input Channel 1
Negative Input for Differential Analog Input Channel 0
Positive Input for Differential Analog Input Channel 0
Digital and Analog Power Supply
6
7
8, 16
V
DD
Clock Select Input. When CLKSEL = 0, the DS8102 uses its internal 8MHz oscillator as a clock source.
When CLKSEL = 1, the DS8102 operates from an external clock source (which must be provided at
CLKIO).
9
CLKSEL
Gain Select Input 0. This pin, along with G1, is used to select the gain setting for differential analog
input channel 0.
10
11
G0
G1
Gain Select Input 1. This pin, along with G0, is used to select the gain setting for differential analog
input channel 0.
Clock Input/Output. When CLKSEL = 0 (internal clock selected), the internal 8MHz clock is output on
this pin and can be used by external devices. When CLKSEL = 1 (external clock selected), an external
clock must be provided on this pin.
12
13
14
CLKIO
MNOUT
RST
Manchester Encoder Output. This output pin provides a Manchester-encoded bit stream containing
output bits from both modulators interleaved with an alternating synchronization bit.
Reset. This input pin can be used to force the DS8102 into a shutdown (low-power) state by driving
RST = 0. If the external reset function is not used, this pin must be connected to V for proper
DD
operation. An RC circuit is not required on this pin for power-up, as this function is provided internally.
Analog Power-Down Reference. This input pin controls whether the internal voltage reference is
enabled. If APDREF = 0, the internal voltage reference is enabled and the voltage reference level is
15
APDREF
driven out on V
. If APDREF = 1, the internal voltage reference is disabled and an external voltage
REF
reference must be provided on V
.
REF
4
_______________________________________________________________________________________
Dual Delta-Sigma Modulator and Encoder
DS8102
Functional Diagram
APDREF
RST
INTERNAL
REFERENCE
REFERENCE
BUFFER
8MHz
OSCILLATOR
CLKSEL
CLKIO
V
REF
DS8102
AN1+
AN1-
1x
INTEGRATORS/
COMPARATOR
DELTA-SIGMA MODULATOR
MANCHESTER
ENCODER
MNOUT
1x, 4x,
16x, 32x
AN0+
AN0-
INTEGRATORS/
COMPARATOR
POWER
MONITOR
DELTA-SIGMA MODULATOR
G1
G0
AGND
DGND
V
DD
1) Drive the RST line on the DS8102 low to force the
DS8102 into shutdown mode.
Detailed Description
Operating Modes
The DS8102 has two operating modes: shutdown (or
power-down) mode and active mode.
2) Enter stop mode. Both the companion microcon-
troller and the DS8102 are now in their lowest cur-
rent consumption modes.
Shutdown Mode
In shutdown mode, the DS8102 is in an inactive state
and consumes a minimal amount of current. No analog-
to-digital conversion or encoding is performed, and the
internal 8MHz oscillator and internal voltage reference
are disabled.
3) Exit stop mode.
4) Drive the RST line on the DS8102 high to return the
DS8102 to active mode.
Note: The RST line on the DS8102 does not include
a pullup. This means that if the RST line is not dri-
ven by a companion microcontroller, RST must be
An integrated power-supply monitor holds the DS8102
connected to V
for proper operation. RST cannot
DD
in shutdown mode whenever V
≤ V
. Additionally,
DD
RST
be left unconnected.
the RST pin can be driven low by an external compan-
ion microcontroller (such as the MAXQ3108) to force the
DS8102 to remain in shutdown mode, regardless of the
While the DS8102 is in shutdown mode, the levels on
the configuration input pins (APDREF, CLKSEL, G1,
and G0) can be changed if they are being driven by a
supply level at V . This is useful in nonisolated config-
DD
urations (when a power supply is shared between the
DS8102 and the companion microcontroller) to reduce
the current consumption of the entire system. In this
scenario, the companion microcontroller would perform
this sequence of actions when entering stop mode:
companion microcontroller instead of hardwired to V
DD
or DGND. However, once the DS8102 enters active
mode, the levels on these pins must remain static for
proper operation.
_______________________________________________________________________________________
5
Dual Delta-Sigma Modulator and Encoder
Once the power supply is at an acceptable level
DD
Active Mode
(V
> V
) and the RST line is driven high, the
RST
In active mode, the AFE and delta-sigma modulators on
the DS8102 are enabled, and the DS8102 converts and
outputs samples over the Manchester-encoded output
(MNOUT) at a rate determined by either the internal
8MHz oscillator (if CLKSEL = 0) or the external clock
input at CLKIO (if CLKSEL = 1).
DS8102 exits shutdown mode. However, a warmup
sequence must then be completed before analog-to-
digital conversion and Manchester encoding begins.
The length of this sequence depends on the
internal/external voltage reference mode (controlled by
the APDREF pin).
DS8102
If RST is driven low or if V
drops below the V
RST
DD
If the external voltage reference is selected (APDREF = 1),
the following actions are performed:
level, the DS8102 enters shutdown mode immediately
and must go through the warmup sequence again
(once V
mode.
> V
and RST = 1) to return to active
RST
DD
1) Upon exit from shutdown mode (V
> V
and
RST
DD
RST = 1), the 8MHz oscillator is started.
2) The DS8102 delays for 16 cycles of the 8MHz oscil-
lator. This allows the 8MHz oscillator to warm up.
Configuration Inputs
The input pins G0, G1, APDREF, and CLKSEL are con-
figuration inputs for the DS8102 that determine its oper-
ating mode, including:
3) The analog front-end (AFE) is enabled.
4) The DS8102 delays for 8192 cycles of the 8MHz
oscillator. This allows the AFE to warm up.
• Clock selection—internal or external
• Voltage reference—internal or external
5) If CLKSEL = 1, the 8MHz oscillator is disabled at
this point and the DS8102 switches to the external
clock source provided at CLKIO.
• Gain setting for analog input channel 0—1x, 4x, 16x,
or 32x
6) Both modulator channels are enabled, and the
DS8102 begins performing conversions using the
external voltage reference.
These pins must be set to a valid level for proper oper-
ation; they cannot be left disconnected. If any of the
configuration inputs are driven by a companion micro-
controller (as opposed to being statically connected to
If the internal voltage reference is selected (APDREF = 0),
the followings actions are performed:
V
or DGND), the inputs can only be changed when
DD
the DS8102 is in shutdown mode.
1) Upon exit from shutdown mode (V
> V
and
RST
DD
RST = 1), the 8MHz oscillator is started.
Channel 0 Gain Selection
2) The DS8102 delays for 16 cycles of the 8MHz oscil-
lator. This allows the 8MHz oscillator to warm up.
Configuration input pins G0 and G1 are used to select
the gain setting for analog input channel 0. The avail-
able gain configurations are 1x, 4x, 16x, and 32x. The
effective input voltage range scales downward propor-
tionally with each increased gain selection. For exam-
ple, full-scale output at gain = 1x occurs when AN0+ is
2V higher than AN0-. However, with the gain setting at
4x, the output reaches full scale when AN0+ is only
500mV higher than AN0-.
3) The AFE is enabled.
4) The DS8102 delays for 8192 cycles of the 8MHz
oscillator. This allows the AFE to warm up.
5) The internal voltage reference is enabled.
6) The DS8102 delays for an additional 57,344 cycles
of the 8MHz oscillator. This allows the internal refer-
ence to warm up.
Table 1 lists the gain configuration settings available for
channel 0. The levels at G0 and G1 should be set when
the DS8102 is in shutdown mode.
7) If CLKSEL = 1, the 8MHz oscillator is disabled at
this point and the DS8102 switches to the external
clock source provided at CLKIO.
Table 1. Modulator 0 Gain Settings
8) Both modulator channels are enabled, and the
DS8102 begins performing conversions using the
internal voltage reference.
G1 PIN
G0 PIN
GAIN
1x
0
0
1
1
0
1
0
1
Even if the external clock has been selected by setting
CLKSEL = 1, the internal 8MHz oscillator is still used to
control the warmup sequence. Once the warmup
sequence has completed, the internal 8MHz oscillator
is disabled if CLKSEL = 1.
4x
16x
32x
6
_______________________________________________________________________________________
Dual Delta-Sigma Modulator and Encoder
DS8102
occurs halfway through the bit time slot.
Internal/External Voltage Reference
Selection
As shown in Figure 1, the Manchester-encoded bit-
stream output on MNOUT contains three interleaved bit
streams. These bit streams, in the order that they are
output, are as follows:
The configuration pin APDREF selects whether the
DS8102 uses its internal voltage reference or an exter-
nal voltage reference provided at V
when perform-
REF
ing conversions. If the internal voltage reference is
selected, the internal reference is buffered and driven
1) SYNC—Synchronization bit stream containing alter-
nating 0s and 1s.
out at V
desired.
, and can be used by external devices if
REF
2) CHAN0—Pulse-density-modulated output from ana-
log channel 0.
Table 2 summarizes the modes of operation for the
DS8102 based on the APDREF input. The level at
APDREF should be set when the DS8102 is in shut-
down mode.
3) CHAN1—Pulse-density-modulated output from ana-
log channel 1.
Both modulator outputs are always included in the bit
stream, even if only one of them is being used by the
application. This means that the maximum bit-rate out-
put for either modulator channel over MNOUT is
Internal/External Clock Selection
The configuration input pin CLKSEL selects whether the
DS8102 uses the internal 8MHz oscillator or an external
clock (provided at CLKIO) when performing conver-
sions. If the internal 8MHz oscillator is selected, the
internal clock is driven out at CLKIO and can be used
by external devices if desired.
f
/12 as shown in Figure 1.
CLK
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line is either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified.
Table 3 summarizes the modes of operation for the
DS8102 based on the CLKSEL input. The level at
CLKSEL should be set when the DS8102 is in shutdown
mode.
Manchester Encoder
Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal point.
Once the DS8102 enters active mode, it begins gener-
ating a Manchester-encoded bit stream on the MNOUT
pin. This bit stream is output at a rate equal to the
selected clock frequency divided by 4, so, for example,
if the internal 8MHz oscillator is selected as the DS8102
clock source, a new bit is output on MNOUT approxi-
mately every 500ns.
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is the ratio of
changes in the power supply (V) to changes in the con-
verter output (V). It is typically measured in decibels.
Bit values are encoded as either low-to-high transitions
(for bit values of 1) or high-to-low transitions (for bit val-
ues of 0). The transition from low-to-high or high-to-low
Table 2. Voltage Reference Selection and Operating Modes
RST PIN
APDREF PIN
DS8102 MODE
0
1
1
X
0
1
Shutdown.
Operation using internal voltage reference (V
output buffer enabled).
output buffer disabled).
REF
Operation using external voltage reference (V
REF
Table 3. Clock Source Selection
CLKSEL PIN
DS8102 CLOCK SOURCE
CLKIO PIN MODE
0
1
Internal 8MHz oscillator
Output: Drives out 8MHz clock.
Input: Accepts external clock.
External clock (provided at CLKIO)
_______________________________________________________________________________________
7
Dual Delta-Sigma Modulator and Encoder
1
2
1
2
1
2
1
2
3
4
5
6
7
8
9
10 11 12
3
4
5
6
7
8
9
10 11 12
3
4
5
6
7
8
9
10 11 12
3
4
5
6
7
8
9 10 11 12
1
0
CLKIO
DS8102
1
0
0
0
0
1
1
1
0
0
1
1
MNOUT
Figure 1. Manchester Encoder Output Example
Typical Operating Circuit
DC POWER
SUPPLY
1
2
3
4
5
6
7
8
DGND
AGND
V
16
15
14
13
12
11
10
9
DD
V
DD
APDREF
V
RST
MNOUT
CLKIO
G1
REF
MNIN+
MNIN-
DS8102
AN1-
AN1+
AN0-
AN0+
ISOLATION
CAPACITORS
G0
COMPANION
µC
V
CLKSEL
DD
DGND
VOLTAGE-
DIVIDER
LINE
SUPPLY
AC LINE
OUT
AC LINE
IN
CURRENT SHUNT
AC NEUTRAL
OUT
AC NEUTRAL
IN
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0066
16 TSSOP
U16+2
8
_______________________________________________________________________________________
Dual Delta-Sigma Modulator and Encoder
DS8102
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1/09
Initial release.
Changed the part number in the Ordering Information table.
In the Electrical Characteristics table, changed f
—
1
from 12MHz to 8MHz;
XCLK(MAX)
changed t
from 83ns to 125ns; changed the Offset Error parameter
XCLK-CLCL(MIN)
2, 3
7
from 1.4mV (min) to 1.4mV (max); added new conditions and note and changed
1.33MHz (typ) to 0.667MHz (typ) for the Input Sampling Rate parameter.
1
2/09
Corrected the reference from CLKSEL to APDREF in the Internal/External Voltage
Reference Selection section; corrected the reference from APDREF to CLKSEL in
the Internal/External Clock Selection section.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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