MAX1007 [MAXIM]
Mobile-Radio Analog Controller; 移动无线模拟控制器
| 型号： | MAX1007 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Mobile-Radio Analog Controller |
| 文件： | 总12页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1180; Rev 0; 6/98
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
________________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Multi-Input 8-Bit ADC
The MAX1007 is a multifunctional integrated circuit
d e s ig ne d for hig h-p e rforma nc e mob ile ra d ios . It
includes one 8-bit analog-to-digital converter (ADC),
and two 7-bit and two 6-bit digital-to-analog converters
(DACs) for functions including radio-frequency (RF)
power sensing and antenna-diversity selection.
♦ Two 7-Bit DACs with Buffered Outputs
♦ Two 6-Bit DACs: Buffered/Unbuffered
♦ Power-Sense Conditioning Circuitry
♦ RSSI Measurement
The ADC p rovid e s for p owe r s e ns e , re c e ive -s ig na l
strength intensity (RSSI) measurements and system
supervision. In the power-sense mode, the ADC con-
verts the power-sensing circuitry signal (representing
either the transmitted (Tx) or received (Rx) RF power)
into a digital code, ensuring optimum Tx power setting
and Rx signal analysis. An additional direct input to the
ADC provides for system-supervision measurements,
such as power-supply voltages, battery voltage, and
temperature.
♦ Antenna-Diversity Circuitry
♦ Internal Reference
♦ Serial-Logic Interface
♦ +2.85V to +3.6V Single-Supply Operation
♦ Two Shutdown Modes
Four DAC blocks typically control DC levels in radios.
As part of the Maxim PWT1900 chip set, the two 7-bit
DACs control the gain settings and the two 6-bit DACs
control the varactor diodes to tune a TCXO and bias a
GaAs amplifier. Each DAC register and output can be
updated independently, providing maximum flexibility.
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
24 SSOP
MAX1007CAG
MAX1007EAG
-40°C to +85°C
24 SSOP
Pin Configuration appears at end of data sheet.
For antenna diversity, a magnitude-comparison circuit
captures and compares two peak signals. A latched
logic-comparator output reveals which signal has the
largest magnitude. The MAX1007 also includes an on-
board voltage reference for the ADC and DACs.
Fu n c t io n a l Dia g ra m
PSDCTRL
PSDWDW
The MAX1007 offers a high level of signal integrity with
minima l powe r dissipa tion. Single -supply ope ra tion
ranges from +2.85V to +3.6V. To further save power, there
are two shutdown modes: standby and total shutdown.
Standby is a partial shutdown that keeps the bandgap
reference and the 2.4V reference generator active. Total
shutdown disables all circuit blocks except the serial
interface, reducing supply current to less than 1µA.
PREAMBLE-SWITCHED DIVERSITY
DUAL
D FLIP-FLOP
BANT
T/H
REF
RSSI
PKWDW
ADC CTRL
RPS
CH1
ADC
CH0
The MAX1007 is available in a 24-pin SSOP and is
specified for commercial and extended temperature
ranges.
POWER
SENSE
FPS1
FPS2
CS
PSOUT
SCLK
DIN
________________________Ap p lic a t io n s
POWER SENSE CIRCUITRY
7
DOUT
PWT1900
SDAC
SDAC
XDAC
SDG
Wireless Communications:
6
6
MAX1007
XDAC
GDAC
Cellular Radios
PCS Radios
PMR/SMR
WLL
VREF
GDAC
KDAC
7
KDAC
PSBIAS
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Mo b ile -Ra d io An a lo g Co n t ro lle r
ABSOLUTE MAXIMUM RATINGS
AV or DV to AGND or DGND...........................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
Digital Inputs to DGND.............................................-0.3V to +6V
Analog Inputs to AGND............................................-0.3V to +6V
REF to AGND............................................................-0.3V to +6V
AGND to DGND.................................................................± 0.3V
SSOP (derate 8.0mW/°C above +70°C) ......................640mW
Operating Temperature Ranges
MAX1007CAG.....................................................0°C to +70°C
MAX1007EAG ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
AV to DV ....................................................................± 0.3V
DD
DD
Maximum Current into Any Pin............................................50mA
MAX107
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV = DV = +2.85V to +3.6V, f
= 1.152MHz, T = T
to T , unless otherwise noted.)
MAX
DD
DD
SCLK
A
MIN
PARAMETER
CONDITIONS
MIN
2.85
TYP
MAX
UNITS
POWER-SUPPLY REQUIREMENTS
Supply Voltages AV , DV
SUPPLY CURRENTS [I(AV ) + I(DV )] (Note 1)
3.0
3.6
V
DD
DD
DD
DD
Transmit Mode 1:
All DACs, Ref, RefBuf Active
RxEN = 0, TxEN = 1; AV = DV = 3V;
DD DD
PKWDW = ADCCTRL = DGND
1.8
4.7
5.0
mA
mA
Transmit Mode 2:
All DACs, PGA, REF, Peak
Detector, PSBIAS, I
RefBuf Active
RxEN = 0, TxEN = 1; AV = DV = 3V;
DD DD
PKWDW and ADCCTRL as per state B on Figure 1
,
SOURCE
Transmit Mode 3:
All DACs, PGA, REF, Peak
RxEN = 0, TxEN = 1; AV = DV = 3V;
DD DD
PKWDW and ADCCTRL as per state C on Figure 1
12.2
32
mA
Detector, PSBIAS, I
RefBuf, ADC Active
,
SOURCE
Receive Mode 1:
KDAC, XDAC, Ref, RefBuf
Active
RxEN = 1, TxEN = 0; AV = DV = 3V;
PKWDW = ADCCTRL = DGND
DD
DD
1.24
2.95
3.5
mA
mA
Receive Mode 2:
KDAC, XDAC, Peak Detector,
RSSI Buffer, Ref, RefBuf Active
RxEN = 1, TxEN = 0; AV = DV = 3V; PKWDW and
ADCCTRL as per state B on Figure 1
DD
DD
Receive Mode 3:
KDAC, XDAC, ADC, Peak
Detector RSSI Buffer, Ref,
RefBuf Active
RxEN = 1, TxEN = 0; AV = DV = 3V; PKWDW and
DD DD
ADCCTRL as per state C on Figure 1
11.2
4.07
31
mA
mA
Receive Mode 4:
RxEN = 1, TxEN = 0; AV = DV = 3V; PKWDW and
DD
DD
KDAC, XDAC, ADC, RSSI
Buffer, Ref, RefBuf, PSD
Circuit Active
ADCCTRL as per state B on Figure 1. PSDWDW and PSD-
CNTRL as per state D on Figure 2
10.5
Standby:
XDAC, GDAC, Ref, RefBuf Active
RxEN = 1, TxEN = 1; AV = DV = 3V
1.24
1
3.5
10
mA
µA
DD
DD
RxEN = 0, TxEN = 0; AV = DV = 3V;
DD
DD
Total Shutdown
ADCCTRL = PSDCTRL = PKWDW = PSDWDW = DGND;
SCLK not active, either high or low
2
_______________________________________________________________________________________
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
ELECTRICAL CHARACTERISTICS (continued)
(AV = DV = +2.85V to +3.6V, f
= 1.152MHz, T = T
to T
, unless otherwise noted.)
DD
DD
SCLK
A
MIN
MAX
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
XDAC
Resolution
6
Bits
LSB
LSB
LSB
%FSR
V
Differential Nonlinearity
Integral Nonlinearity
Offset Error
2 < code ≤ FS
2 < code ≤ FS
±1
±1/2
±1
Gain Error
(Note 2)
±10
2.42
30
Full-Scale Output Swing
Output Resistance
GDAC
No resistive load
2.1
6
2.75
±1
kΩ
Resolution
Bits
LSB
LSB
LSB
%FSR
V/µs
V
Differential Nonlinearity
Integral Nonlinearity
Offset Error
2 < code ≤ FS
2 < code ≤ FS
±1
±1
C
= 30pF, R = 40kΩ
L
L
Gain Error
(Note 2)
±10
0.1
2.42
4
Output Slew Rate
Full-Scale Output Swing
Full-Scale Step Response Time
SDAC, KDAC
R
C
= 40kΩ
2.1
7
2.75
±1
L
L
= 30pF, R = 40kΩ, settling to 5% of final value
µs
L
Resolution
Bits
LSB
LSB
LSB
%FSR
V/µs
V
Differential Nonlinearity
Integral Nonlinearity
Offset Error
2 < code ≤ FS
2 < code ≤ FS
±1
±1
±10
0.1
2.42
4
Gain Error
(Note 2)
Output Slew Rate
Full-Scale Output Swing
Full-Scale Step Response Time
Power-Up Time from Standby
ADC
C
R
C
C
= 30pF, R = 40kΩ
L
L
L
L
L
= 40kΩ
2.1
2.75
= 30pF, R = 40kΩ, settling to 2% of final value
µs
L
= 30pF, R = 40kΩ, settling to within 2% of final value
4
µs
L
Resolution
8
0
Bits
V
Input Signal Range
Differential Nonlinearity
Integral Nonlinearity
Conversion Time
Offset Error
V
REF
V
= 1.028V (typ)
= 1.028V (typ)
±1
LSB
LSB
µs
REF
V
REF
±1
5.2
±2
±5
LSB
LSB
V
Gain Error
With respect to V
REF
Reference Voltage
ADC Power-Up Time from Standby
1.028
1.74
µs
_______________________________________________________________________________________
3
Mo b ile -Ra d io An a lo g Co n t ro lle r
ELECTRICAL CHARACTERISTICS (continued)
(AV = DV = +2.85V to +3.6V, f
= 1.152MHz, T = T
to T
, unless otherwise noted.)
DD
DD
SCLK
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RSSI CIRCUIT
Lowpass-Filter Time Constant
Minimum Peak Level Detected
Maximum Peak Level Detected
TRANSMIT POWER SENSE
Offset Voltage
10
20
µs
mV
V
100
300
V
REF
MAX107
RPS, FPS1, FPS2 to ADC input
Forward transmit
150
-0.53
-6
mV
V/V
Power-Sense Amp Gain (PGA)
Reflected transmit, class 1
Reflected transmit, classes 2, 3, 4
Figure 3b
-0.44
100
Current Source
50
180
1.1
µA
RPS, FPS1, FPS2 pulled to AGND when not
selected
Pull-Down Input Resistance
200
Ω
REFERENCE
Output Voltage
0.96
200
1.028
1.87
V
V
PS Bias Voltage Output
PS Bias Sink Current
Internal DAC Reference
SERIAL-LOGIC INTERFACE
R
R
in series with C , C = 1nF, 200Ω ≤ R ≤ 1kΩ
L
L S
S
µA
V
in series with C , C = 1nF, 200Ω ≤ R ≤ 1kΩ
2.42
S
L
L
S
Digital Inputs (CS, SCLK, DIN, PKWDW, ADCCTRL, PSDWDW, PSDCTRL)
Input Voltage High
Input Voltage Low
Input Current
V
0.7V
V
V
IH
DD
V
IL
0.3V
DD
I
IN
Excluding PSDCTRL, PSDWDW
PSDCTRL, PSDWDW
Digital inputs
±1
µA
kΩ
pF
Input Resistance
Inpt Capacitance
R
20
IN
IN
C
10
Digital Outputs (DOUT, BANT, SDG)
Output Voltage High
V
C
C
= 20pF, R = 100kΩ
V - 0.4
DD
V
V
L
L
L
OH
Output Voltage Low
V
OL
= 20pF, R = 100kΩ
0.4
L
TIMING SPECIFICATIONS (Figure 4)
DIN Valid to SCLK Setup
DIN to SCLK Hold
t
100
0
ns
ns
1
t
2
CS Low to SCLK High
t
t
20
ns
ns
3
100
CS Low to DOUT Valid
SCLK High to DOUT Valid
SCLK Pulse Width High
SCLK Pulse Width Low
4
t
5
t
6
t
7
150
100
ns
ns
ns
200
200
434
434
t
8
C
= 20pF
ns
CS High to DOUT Disable
L
ADC Data Output Delay After
End of ADC Conversion
(Figure 4b)
t
9
500
ns
4
_______________________________________________________________________________________
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
ELECTRICAL CHARACTERISTICS (continued)
(AV = DV = +2.85V to +3.6V, f
= 1.152MHz, T = T
to T
, unless otherwise noted.)
DD
DD
SCLK
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RF input on RSSI, RPS, FPS1, FPS2, or
PSBIAS, (Figure 4c)
ADCCTRL Low to RF input
t
t
200
ns
10
11
PSDWDW Low to BANT Valid
SCLK Duty Cycle
C
= 20pF (Figure 4c)
100
50
ns
%
L
Note 1: All digital inputs at DV or DGND.
DD
Note 2: All DACs use an internal reference voltage of 2.42V.
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. TEMPERATURE
(Tx MODE)
SUPPLY CURRENT vs. TEMPERATURE
(Rx MODE)
DIFFERENTIAL NONLINEARITY
0.5
1.55
1.50
1.45
1.40
1.35
1.30
1.25
2.40
2.30
2.20
2.10
2.00
1.90
1.80
0.4
0.3
V
DD
= 3.6V
V
= 3.6V
DD
0.2
0.1
V
DD
= 2.85V
V
DD
= 2.85V
0
-0.1
-0.2
-0.3
-0.4
-0.5
-40
25
TEMPERATURE (°C)
85
-40
25
TEMPERATURE (°C)
85
0
50
100
150
200
250
300
CODES
REFERENCE VOLTAGE
vs. TEMPERATURE
PS BIAS VOLTAGE vs. TEMPERATURE
1.86
1.84
1.025
V
DD
= 3.6V
V
= 3.6V
1.024
1.023
1.022
1.021
1.020
1.019
DD
V
DD
= 2.85V
1.82
1.80
1.78
V
= 2.85V
DD
1.76
-40
-5
25
55
85
-40
-5
25
55
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Mo b ile -Ra d io An a lo g Co n t ro lle r
P in De s c rip t io n
PIN
NAME
FUNCTION
Used to measure reverse-transmit power level. Only active in transmit mode when PKWDW = 1,
SDAC[F/R] = Reverse. When not selected, this pin is internally pulled to AGND through a 200Ω switch.
1
RPS
Used to measure forward power-sense class 2/3/4. Only active in transmit mode when GDAC[Power
Class] = Class 2/3/4, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally
pulled to AGND through a 200Ω switch.
2
3
FPS2
MAX107
Used to measure forward power-sense level 1. Only active in transmit mode when GDAC[Power Class] =
Class 1, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND
through a 200Ω switch.
FPS1
4
5
SDAC
Buffered output of 7-bit DAC. Controls gain stage in up/down converter.
Analog Supply Voltage
AV
DD
6
XDAC
AGND
REF
Unbuffered output of 6-bit DAC. Used to control VCXO frequency.
Analog Ground
7
8
1.028V Reference Voltage Output
9
KDAC
GDAC
SDG
Buffered output of 7-bit DAC. Controls gain stage in external modulator block.
Buffered output of 6-bit DAC. Controls negative gate bias voltage of external power amplifier.
Software-Programmable Logic Output. Can be used to shut down external bias generator.
10
11
Best-Antenna Digital Output. Result of preamble-switched diversity measurement (Figure 2). “0” indicates
more power was sensed from period A with respect to period B. “1” means vice versa. Period A is
sensed in the first 12 clock periods following the PSDWDW rising edge.
12
BANT
Preamble-Switched Diversity Measurement-Control Signal (Figure 2). This pin has a 20kΩ pull-down
resistor to digital ground.
13
14
PSDCTRL
PSDWDW
Preamble-Switched Diversity Measurement Window (Figure 2). This pin has a 20kΩ pull-down resistor to
digital ground.
15
16
17
18
19
20
21
22
23
ADCCTRL
PKWDW
DOUT
RSSI/Power-Sense Measurement-Control Input (Figure 1)
RSSI/Power-Sense Measurement-Window Digital Input (Figure 1)
Serial-Data Output. Enabled when CS is low.
DGND
Digital Ground
SCLK
Serial-Clock Input. Clock can be stopped and resumed at any time (40% to 60% duty cycle).
Digital Supply Voltage
DV
DD
DIN
Serial-Data Input
Chip Select Input. Enables serial interface when low.
Power-Sense Measurement Buffered-Bias Output Voltage. Active only during power sensing.
CS
PSBIAS
Received-Signal Strength Indicator Analog Input for power-sense and antenna diversity measurements.
Signal goes into peak-detector circuit and is sampled at the end of the measurement window by the 8-bit
ADC. Only active in receive mode when PKWDW = 1. Peak-detector circuit can be bypassed by using
CH1 as the ADC input.
24
RSSI
6
_______________________________________________________________________________________
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
STATE
A
1
B
C
CONTROL
SIGNALS
2
PKWDW
≥ 7 CLOCKS
CLOCKS
ADCCTRL
10 CLOCKS
8 CLOCKS
8 CLOCKS
INTERNAL SIGNALS
ACTIVE ADC
ADC CONVERSION
RESET
6 CLOCKS
1
1
SWITCH FOR PS
10 CLOCKS
Figure 1. RSSI/Power-Sense Control Signals
STATE
D
ANTENNA SELECT
(EXTERNALLY GENERATED)
FIRST ANTENNA
PERIOD A
SECOND ANTENNA
RSSI
PSDWDW
PSDCTRL
PERIOD B
9 CLOCKS
1
4
8 CLOCKS
4
INTERNAL RESET 1
INTERNAL RESET 2
COMPARE
NEW VALUE
OLD VALUE
BANT
Figure 2. Antenna-Diversity Control Signals
P o w e r S e n s e
_______________De t a ile d De s c rip t io n
The power-sense circuit consists of a multiplexer (mux),
a programmable gain amplifier (PGA), a peak detector,
a nd a b uffe r. The c irc uit a mp lifie s /a tte nua te s the
demodulated RF waveform, peak-holds the signal, and
buffers the outputs to the ADC for power-sense mea-
surement.
The MAX1007 comprises several blocks for measuring
and controlling radio-frequency (RF) signals. The mea-
surement blocks, including power sense, antenna or
preamble-switched diversity, and the analog-to-digital
converter (ADC), allow the comparison of various RF
inputs. The control blocks, including four digital-to-ana-
log converters (DACs), digital outputs BANT and SDG,
and the serial interface, aid frequency tuning and allow
the optimization of transceiver gain under microproces-
sor control.
The demodulation process with external circuitry for
one channel is shown in Figures 3a and 3b. This circuit
typ ic a lly re c ove rs the ne g a tive e nve lop e of the RF
waveform. The 1.87V PSBIAS voltage and the 100µA
current source are both generated by the MAX1007.
_______________________________________________________________________________________
7
Mo b ile -Ra d io An a lo g Co n t ro lle r
In Figure 3b, the mux selects the signal from one of
three input channels: RPS, FPS1, and FPS2. The PGA
then amplifies or attenuates the input signal according
to the signal power-class level and the transmission
mode (forward or reverse) (Table 1). Three gain set-
tings are provided in the PGA: -0.53, -0.44, and -6. The
voltage range at the internal node PSOUT is equal to
the ADC’s input range.
After the PGA, the signal is fed to a peak detector,
which tracks the input and holds the positive peak volt-
age until the ADC starts a conversion.
MAX107
Table 1. Data-Byte Definitions
A [2:0]
NAME
D [7:0]
DESCRIPTION
Write [7,6]:
[5:0]:
Reserved
0 0 0
XDAC
XDAC value [5:0]; LSB is bit 0, binary.
Write
Write
[7]:
F/R bit, defines forward or reverse power-sense measurement
0 = Reverse power-sense measurement; RPS pin
1 = Forward power-sense measurement; FPS1/FPS2 pin
SDAC value [6:0]; LSB is bit 0, binary.
0 0 1
0 1 0
SDAC
KDAC
[6:0]:
[7]:
ADC channel selection:
0 = Power sense or RSSI via peak-hold circuit connected to ADC (CH0)
1 = RSSI pin connected to ADC directly (CH1)
KDAC value [6:0]; LSB is bit 0, binary.
[6:0]:
Write [7,6]:
Power class: 00 = Class 1
01 = Class 2
0 1 1
GDAC
10 = Class 3
11 = Class 4
[6:0]:
GDAC value [5:0]; LSB is bit 0, binary.
1 0 0
1 0 1
1 1 0
1 1 1
Reserved
Reserved
Reserved
ADC
Read [7:0]:
ADC value [7:0]; LSB is bit 0, binary.
PSBIAS
1.87V
AV
DD
R5
300Ω
I
SOURCE
100µA
C3
C4
10pF
1nF
50Ω TRANSMIT LINE
OR 22nH INDUCTOR
RPS
FPS1
FPS2
AGND
R1
D1
R3
RPS
FPS1
FPS2
50Ω
1k
PSOUT
PGA
C1
10pF
+
–
R2
50Ω
RF INPUT
C2
10pF
AGND
Figure 3a. External Circuit for Envelope Detection
(one channel)
Figure 3b. Power-Sense Block
8
_______________________________________________________________________________________
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
RS S I
The RSSI input provides a filtered input and a direct
input to the ADC. The filtered signal path consists of a
unity-gain buffer, an RC lowpass filter, and a peak
detector to condition the signal for the ADC. The low-
pass filter’s time constant is 10µs (min). The mux at the
ADC’s input selects CH0 (filtered input) or CH1 (direct
RSSI input).
Re fe re n c e
The b a nd g a p volta g e re fe re nc e s up p orts s e ve ra l
blocks of the MAX1007. The nominal 1.21V output is
s c a le d a nd b uffe re d for the p owe r-s e ns e b ia s , the
PGA, the ADC, and the DACs. The PSBIAS output volt-
age is 1.87V nominal. The ADC reference is 1.028V. It
is buffered to isolate switching noise and to allow exter-
nal capacitor bypassing (0.014µF to 0.05µF) for AC sta-
bility. A buffered gain supplies all DACs with a nominal
2.42V reference voltage.
Co n t ro l Tim in g
The power-sense circuit is activated by the externally
g e ne ra te d PKWDW s ig na l (Fig ure 1) whe n the
MAX1007 is either in transmit or receive mode. When
the PKWDW signal goes high, the entire power-sense
circuit turns on. However, since the PGA is active only
in the transmit mode, it remains shut down during RSSI
power measurements to conserve power.
Dig it a l-t o -An a lo g Co n ve rt e rs
All four DAC outputs are reset to zero at power-up.
Preset DACs to output voltages other than zero in total
shutdown mode and update DACs by settling the LD
bit in the command byte.
XDAC
XDAC is a 6-bit voltage-output DAC intended to drive
varactor diodes to tune a voltage-controlled crystal
oscillator. The input is double-buffered for independent
updates. The inverted R-2R ladder output is unbuffered
since the load is strictly capacitive. The maximum out-
put voltage is 2.42V nominal, and the maximum output
re s is ta nc e is 30kΩ. The outp ut is re s e t to ze ro a t
power-up and is active instantly. When XDAC is dis-
abled, the DAC output is actively pulled to AGND.
An t e n n a Dive rs it y
The antenna or preamble-switched diversity (PSD) cir-
cuit compares the signal amplitude presented at RSSI
during two different time periods and latches the result
at BANT (Best Antenna). The circuit consists of a dual
track/hold (T/H) stage, a comparator, and an output
latch (D flip-flop).
The comparison begins with the signal from the first
antenna applied to the RSSI pin (Figure 2). PSDWDW
goes high, and the PSD circuit is turned on. A power-
on-reset signal initializes the D flip-flop so that it always
starts with BANT low. After 4 clocks to reset the peak
detector, PSDCTRL goes high to start the measure-
ment. The T/H stage acquires the signal for 8 clocks
while PSDCTRL is high, then holds the peak value while
the second antenna is switched externally to the RSSI
p in a nd the T/H is ze roe d . PSDCTRL g oe s low for
another 4 clocks, then goes high to enable the peak
detector again. The peak detector is active for another
8 clocks while the output is compared with the peak
value for the first antenna. When PSDWDW goes low at
the end of the comparison phase, the comparator’s out-
put is clocked into the D flip-flop. The D flip-flop’s out-
put, BANT, is low if the first antenna signal is greater
tha n the s e c ond , a nd hig h if the s e c ond s ig na l is
greater than the first. PSDCTRL goes low one clock
period after PSDWDW goes low to power down the
PSD circuitry.
GDAC
GDAC is a 6-bit voltage-output DAC intended to control
a n e xte rna l ne g a tive b ia s g e ne ra tor, s uc h a s the
MAX840, for a GaAs amplifier. The digital input is double-
buffered. The inverted R-2R ladder output is buffered
and can drive a 5kΩ load. The maximum output voltage
is 2.42V nominal. The DAC output is reset to zero at
power-up and is active in standby. A programmable
logic output (SDG) is provided to shut down the exter-
nal bias generator.
S DAC a n d KDAC
SDAC and KDAC are 7-bit voltage-output DACs intend-
ed to tune power levels of an up/downconverter or a
modulator. The digital inputs are double-buffered. The
inverted R-2R ladder outputs are buffered and can
drive 5kΩ loads. The maximum output voltage is 2.42V
nominal. The SDAC and KDAC DAC outputs are reset
to zero at power-up.
An a lo g -t o -Dig it a l Co n ve rt e r
The ADC is an 8-bit, half-flash ADC with a T/H and two
inputs (CH0, CH1). When selected, the acquisition time
is 1.74µs. The ADC input range is equal to the 1.028V
internal reference.
S e ria l-In t e rfa c e a n d Co n t ro l Lo g ic
The serial interface is a 4-wire implementation with CS,
SCLK, and DIN inputs and a DOUT output. The hard-
ware consists of a 7-bit command register, an 8-bit
data input register, an 8-bit data output register, a
counter, and control logic. Communication is framed in
16-bit words (8 command bits followed by 8 data bits)
_______________________________________________________________________________________
9
Mo b ile -Ra d io An a lo g Co n t ro lle r
LD is the software control to update the output regis-
READ
CS
ters. During a write operation, the addressed DAC’s
input buffer is updated. With LD reset to “0,” the DAC
register and DAC output remain unchanged. With LD
s e t to “1,” a ll DACs a nd p owe r-c la s s re g is te rs a re
simultaneously updated to the values in their input reg-
isters immediately after the last data bit (including DAC
values, power-class bits, F/R bit, RSSI and ADC input
selections, SDG, and power-down bits).
t
t
6
t
7
3
SCLK
DOUT
t
t
5
t
8
4
MAX107
After a 16-bit read cycle, pull CS high. The interface is
now ready for a new command sequence. During a
read operation, the ADC conversion result is output to
DOUT. With LD set to “1,” all other outputs and power-
class registers are also updated.
WRITE
SCLK
t
1
t
2
DIN
Write Command
The 8 data bits are latched in the data input register.
The command byte is decoded, and the data bits are
transferred to the appropriate registers.
Figure 4a. Read/Write Detailed Interface Timing
by the counter. Data is clocked into DIN or the falling
edge of SCLK, and is clocked out of DOUT on SCLK’s
rising edge. The serial interface is always active.
Read Command
After the command byte is decoded, the last 8 clocks
output data, MSB first, from the ADC output register to
DOUT (Figure 4b). After a 16-bit read cycle, pull CS
high. The interface is now ready for a new command
sequence.
The SCLK and DIN idle state is low (Figure 4). The first
“1” clocked in after CS goes low is the start bit, signify-
ing the beginning of a 16-bit data word. The command
and data input registers are cleared and the counter is
started. The next 7 bits are latched in the command
register.
To minimize the delay between the power-sense measure-
ment and the ADC output, program a ‘READ ADC’ com-
mand prior to making the power-sense measurement and
clock out the data as soon as the conversion is complete
(Figure 4b). This reduces the delay by 8 clock cycles.
Command Byte
The c omma nd b yte (Fig ure 4d ) c ons is ts of thre e
address bits (A2, A1, A0), two power-mode bits (RxEN,
TxEN), a shutdown control bit (SD), and a load data bit
(LD). Table 1 lists the address and data-byte defini-
tions.
To minimize the delay between the power-sense measure-
ment and the ADC output, program a “READ ADC” com-
mand prior to making the power-sense measurement and
clock out the data as soon as the conversion is complete
(Figure 4b). This reduces the delay by F clock cycles.
SD is the software control for the GaAs FET bias gener-
a tor s hutd own p in a nd GDAC. Re s e tting SD to “0”
causes SDG to go low and disables GDAC. The SDG
output is updated if LD is set high.
CS
SCLK
CLOCK COMMAND
BYTE INTO DIN
CLOCK CONVERSION
DATA ONTO DOUT
ACTIVE ADC
t
9
DOUT
ADC CONVERSION DATA
WRITE A
“READ ADC”
COMMAND
POWER-SENSE
MEASUREMENTS
CLOCK OUT
CONVERSION
RESULT
Figure 4b. Clock Command Conversion
10 ______________________________________________________________________________________
Mo b ile -Ra d io An a lo g Co n t ro lle r
MAX107
Table 2. Power Modes
ADCCTRL
RSSI
RxEN,
DESCRIPTION
TxEN
t
10
RPS
0 0
0 1
1 0
Total shutdown
FPS1
FPS2
PSBIAS
Transmit mode, all DACs enabled
Receive mode, SDAC and GDAC outputs disabled
PSDWDW
Standby: REF, GDAC, and XDAC enabled. Rest of
IC is shut down.
1 1
t
11
BANT
OLD DATA
VALID
Figure 4c. Power-Sense/Best-Antenna Detailed Interface
WRITE
CS
SCLK
START A2 A1 A0 RxEN TxEN SD LD D7 D6 D5 D4 D3 D2 D1 D0
COMMAND BYTE
DIN
READ
CS
SCLK
DIN
START A2 A1 A0 RxEN TxEN SD LD
COMMAND BYTE
DOUT
D7 D6 D5 D4 D3 D2 D1
D0
Figure 4d. Serial-Interface Timing
P o w e r-S u p p ly Byp a s s in g a n d
Gro u n d Ma n a g e m e n t
Optimum system performance is obtained with printed
circuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommend-
e d . The two g round p la ne s s hould b e c onne c te d
together at the low-impedance power-supply source.
Ap p lic a t io n s In fo rm a t io n
Precautions must be taken to minimize RF coupling
through the IC.
S h u t d o w n Mo d e s
At power-up, the device initializes in total shutdown
mode. The digital interface is always active. Table 2
describes the various power modes available.
Bypass AV
with a 0.1µF ceramic capacitor connect-
DD
ed between AV and AGND. Mount it with short leads
DD
Whe n the PGA is not on (in shutdown, sta ndb y, or
receive mode, or when PKWDW is low), the PS input
pins (RPS, FPS1, FPS2) are pulled down to ground. To
minimize RF coupling, the unselected channels are
also pulled down to ground when the circuit is active.
The current source and the 1.87V PSBIAS voltage gen-
erator are turned on only when the device is performing
the transmit power-sense measurement.
close to the device. Similarly bypass DV with a 0.1µF
DD
c e ra mic c a p a c itor c onne c te d b e twe e n DV
a nd
DD
DGND. Ferrite beads may also be used to further iso-
late the analog and digital power supplies.
______________________________________________________________________________________ 11
Mo b ile -Ra d io An a lo g Co n t ro lle r
P in Co n fig u ra t io n
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 6744
TOP VIEW
RPS
FPS2
FPS1
SDAC
1
2
3
4
5
6
7
8
9
24 RSSI
23 PSBIAS
22 CS
21 DIN
MAX107
MAX1007
AV
DD
20 DV
DD
XDAC
AGND
REF
19 SCLK
18 DGND
17 DOUT
KDAC
16 PKWDW
15 ADCCTRL
14 PSDWDW
13 PSDCTRL
GDAC 10
SDG 11
BANT 12
SSOP
________________________________________________________P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1011CEG+
ADC, Flash Method, 6-Bit, 1 Func, 1 Channel, Parallel, Word Access, PDSO24, 0.150 INCH, 0.025 INCH PITCH, QSOP-24
MAXIM
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