MAX101CFR [MAXIM]
500Msps, 8-Bit ADC with Track/Hold; 500 MSPS ， 8位ADC，采样/保持
| 型号： | MAX101CFR |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 500Msps, 8-Bit ADC with Track/Hold |
| 文件： | 总16页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0296; Rev 0; 8/94
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 500Msps Conversion Rate
The MAX101 ECL-compatible, 500Msps, 8-bit analog-
to-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequen-
cy). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time inter-
leaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101 contains a high-perfor-
mance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
♦ 7.0 Effective Bits Typical at 250MHz
♦ 1.2GHz Analog Input Bandwidth
♦ Less than ±1/2LSB INL
♦ 50Ω Differential or Single-Ended Inputs
♦ ±270mV Input Signal Range
♦ Ratiometric Reference Inputs
♦ Dual Latched Output Data Paths
The innovative design of the internal T/H assures an
exceptionally wide 1.2GHz input bandwidth and aper-
ture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
c omp a ra tor outp ut d e s ig n a nd d e c od ing c irc uitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
-15
♦ Low Error Rate, Less than 10
♦ 84-Pin Ceramic Flat Pack
Metastable States
________________________Ap p lic a t io n s
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
15
less than 1 error per 10 clock cycles. And, unlike
other ADCs that can have errors resulting in false full-
scale or zero-scale outputs, the MAX101 keeps the error
magnitude to less than 1LSB.
Radar/Signal Processing
High-Energy Physics
The analog input is designed for either differential or
single-ended use with a ±270mV range. Sense pins for
the reference input allow full-scale calibration of the
input range or facilitate ratiometric use.
Communications
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing convert-
er performance. Input clock phasing is also available
for interleaving several MAX101s for higher effective
sampling rates.
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
84 Ceramic Flat Pack
(with heatsink)
MAX101CFR* 0°C to +70°C
*Contact factory for 84-pin ceramic flat pack without heatsink.
_________________________________________________________Fu n c t io n a l Dia g ra m
VA
RT
VA
RTS
VA
RBS
VA
RB
L
A
T
C
H
E
S
MAX101
8
8
ADATA
AIN+
AIN-
FLASH CONVERTER
(8 -BIT)
B
U
F
TRACK
AND
HOLD
DCLK
DCLK
STROBE
STROBE
F
E
R
CLK
CLK
FLASH CONVERTER
(8 -BIT)
8
8
L
A
T
C
H
E
S
BDATA
TRK1
PH
ADJ
VB
RT
VB
RTS
TRK1
VB
RBS
VB
RB
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e lit e ra t u re .
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
DIV10 Input Voltage (V , V ).......................................V to 0V
IH IL EE
V
V
EE
...........................................................................0V to +7V
.............................................................................-7V to 0V
Output Current, (I max)
T <100°C .......................................................................14mA
J
CC
O
V
CC
- V .........................................................................+12V
EE
100°C < T <125°C.........................................................12mA
J
Analog Input Voltage .............................................................±2V
Reference Voltage (VA , VB )...........................-0.3V to +1.5V
Operating Temperature Range ...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+250°C
RT
RT
Reference Voltage (VA , VB )..........................-1.5V to +0.3V
RB
RB
MAX01
Clock Input Voltage (V , V ).....................................-2.3V to 0V
IH IL
Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage
may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.
Note 2: Typical thermal resistance, junction-to-case R
= 5°C/W and thermal resistance, junction to ambient (MAX101CFR)
θJC
R
θJA
=12°C/W, if 200 lineal ft/min airflow is provided. See Package Information.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.
EE
CC
L
RT
RT
RB
RB
A
T
MIN
to T
= 0°C to +70°C. Note 3)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Bits
T
= +25°C
±0.50
±0.75
±0.75
±0.85
A
Integral Nonlinearity (Note 4)
INL
AData, BData
LSB
T
A
= T to T
MIN MAX
T
A
= +25°C
AData, BData,
no missing codes
Differential Nonlinearity
DNL
LSB
T
A
= T to T
MIN MAX
DYNAMIC SPECIFICATIONS
f
= 10MHz
7.6
7.1
7.0
AIN
f
V
= 500MHz,
= 95% full scale
CLK
Effective Bits
ENOB
SNR
f
= 125MHz
= 250MHz
Bits
dB
IN
AIN
(Note 5)
f
6.7
AIN
f
V
= 125MHz, f
= 95% full scale (Note 6)
= 500MHz,
CLK
AIN
Signal-to-Noise Ratio
44.5
IN
Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
f
(Note 7)
500
Msps
GHz
ps
CLK
BW
1.2
270
2
3dB
t
Figure 4
Figure 4
AW
Aperture Jitter
t
ps
AJ
ANALOG INPUT
Full scale
230
-305
-17
1.8
315
-215
32
AIN+ to AIN-, Table 2,
Input Voltage Range
V
mV
IN
T
A
= T to T
MIN MAX
Zero scale
Input Offset Voltage
Least Significant Bit Size
Input Resistance
V
IO
AIN+, AIN-, T = T
to T
MAX
mV
mV
Ω
A
MIN
LSB
T
A
= T
to T
MAX
2.5
51
MIN
R
AIN+, AIN-, to GND
49
I
Input Resistance
Temperature Coefficient
0.008
Ω/°C
2
_______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
ELECTRICAL CHARACTERISTICS (continued)
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.
EE
CC
L
RT
RT
RB
RB
A
T
MIN
to T
= 0°C to +70°C. Note 3)
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Reference String Resistance
R
VA to VA
RT
100
175
Ω
REF
RB
Reference String Resistance
Temperature Coefficient
0.02
Ω/°C
LOGIC INPUTS
Digital Input Low Voltage
V
CLK, CLK
CLK, CLK
T
= T
= T
= T
= T
= T
to T
to T
to T
to T
to T
-1.50
V
V
IL
A
MIN
MIN
MIN
MIN
MIN
MAX
Digital Input High Voltage
Digital Input High Current
Input Bias Current
V
IH
T
A
-1.1
1.1
MAX
MAX
MAX
MAX
I
IH
DIV10 = 0V
PH = 0V
T
A
3.1
40
50
mA
µA
µA
I
B
T
A
ADJ
CLK, CLK = -0.8V
(no termination)
Clock Input Bias Current
I
T
A
CLK
LOGIC OUTPUTS (Note 8)
T
= +25°C
-1.95
-1.95
-1.3
-1.60
-1.50
-1.00
-0.9
A
AData, BData
DCLK, DCLK
T
A
= T
to T
MIN
MAX
MAX
Digital Output Low Voltage
V
OL
V
T
A
= +25°C
T
A
= T
to T
-1.4
MIN
T
= +25°C
-1.02
-1.10
-0.70
-0.60
A
AData, BData,
DCLK, DCLK
Digital Output High Voltage
V
V
OH
T
A
= T
to T
MIN
MAX
MAX
Digital Output Voltage
POWER REQUIREMENTS
Positive Supply Current
V
- V
DCLK, DCLK
T
A
= T
to T
275
445
mV
OH
OL
MIN
T
A
= +25°C
550
765
1065
1130
-525
I
V
CC
= 5.0V
mA
VCC
T
A
= T to T
MIN MAX
T
A
= +25°C
-935
-975
35
-750
Negative Supply Current
I
V
EE
= -5.2V
mA
dB
dB
VEE
CMRR
PSRR
T
A
= T
to T
MIN
MIN
MAX
MAX
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
V
INCM
= ±0.5V
T
A
= T
to T
V
(nom) = ±0.25V
(nom) = ±0.25V
40
CC
T
A
= T
to T
MIN
MAX
V
EE
40
_______________________________________________________________________________________
3
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
TIMING CHARACTERISTICS
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.)
EE
CC
L
RT
RT
RB
RB
A
PARAMETER
SYMBOL
CONDITIONS
MIN
0.9
TYP
MAX
2.5
UNITS
ns
Clock Pulse Width Low
Clock Pulse Width High
t
CLK, CLK
CLK, CLK
PWL
t
0.9
2.5
ns
PWH
CLK to DCLK
Propagation Delay
t
DIV10 = 0, Figures 1, 2
DIV10 = 0, Figures 1, 2
20% to 80%
1.2
0.7
2.3
1.3
3.4
1.8
ns
ns
ps
ps
PD1
PD2
MAX01
DCLK to A/BData
Propagation Delay
t
DCLK
DATA
DCLK
DATA
400
850
400
700
Rise Time
Fall Time
t
R
t
20% to 80%
F
Pipeline Delay
(Latency)
See Figures 2, 3
and Table 1
Clock
Cycles
t
Divide-by-1 mode
15
15
NPD
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for T = T
to T
as specified.
A
MIN
MAX
Note 4: Deviation from best-fit straight line. See Integral Nonlinearity section.
Note 5: See the Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications.
Note 6: SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Note 7: Clock pulse width minimum requirements t
Note 8: Outputs terminated through 100Ω to -2.0V.
and t
must be observed to achieve stated performance.
PWL
PWH
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.)
EE
CC
L
RT
RT
RB
RB
A
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.75
0.50
0.25
0.50
0.25
0
0
-0.25
-0.25
-0.50
-0.75
-0.50
-0.75
0
64
128
192
256
0
64
128
192
256
OUTPUT CODE
OUTPUT CODE
4
_______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.)
EE
CC
L
RT
RT
RB
RB
A
FFT PLOT
(f = 251.4462MHz)
FFT PLOT
(f = 10.4462MHz)
AIN
AIN
0
0
f
= 500MHz,
f
= 250MHz,
CLK
CLK
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
SER = -44.5dB,
NOISE FLOOR = -67.3dB,
SPURIOUS = -58.2dB
SER = -47.2dB,
NOISE FLOOR = -70.5dB,
SPURIOUS = -61.8dB
-70
-80
-70
-80
-90
-90
-100
-100
0
25
50
75
100
125
0
12.5
25
37.5
(MHz)
50
62.5
(MHz)
EFFECTIVE BITS vs. ANALOG INPUT
EFFECTIVE BITS vs. CLOCK
FREQUENCY (f
(f = 500MHz, V = 95% FS)
AIN IN
FREQUENCY (f
)
)
AIN
= 500MHz, V = 95% FS)
CLK
(f
CLK
IN
8
8
7
6
7
6
0
50
100
150
(MHz)
200
250
300
0
100
200
300
(MHz)
400
500
600
f
f
AIN
CLK
_______________________________________________________________________________________
5
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = -5.2V, V = +5V, R = 100Ω to -2V, VA , VB = 1.02V, VA , VB = -1.02V, T = +25°C, unless otherwise noted.)
EE
CC
L
RT
RT
RB
RB
A
DATA CLOCK (DCLK)
RISE TIME (526ps), DIV10 = OPEN
DATA CLOCK (DCLK) FALL TIME
(352ps), DIV10 = OPEN
-550mV
-550mV
MAX01
100mV/div
100mV/div
-1.55V
-1.55V
-4.18ns
-4.18ns
5.2ns
5.2ns
BDATA FALL TIME (714ps),
DIV10 = OPEN
BDATA RISE TIME (855ps),
DIV10 = OPEN
-825mV
-825mV
100mV/div
100mV/div
-1.825V
-1.825V
-4.98ns
5.02ns
-4.98ns
5.02ns
6
_______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1
PAD
Internal connection, leave open.
2, 62
3, 61
CLK
CLK
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50Ω transmission line. Either end
can be driven with the other end terminated with 50Ω to -2V. See Typical Operating Circuit.
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
GND
Power-Supply Ground
5, 59
6, 58
TRK1
TRK1
Phasing inputs (normally left open). See Applications Information section.
Positive Power Supply, +5V ±5% nominal
8, 21, 43,
56, 81
VCC
9
VB
“B” side negative reference voltage input (Note 9)
“B” side negative reference voltage sense (Note 9)
Internal connection, leave pin open.
RB
10
VB
RBS
11
TP4
TP3
VB
12
13
Internal connection, leave pin open.
“B” side positive reference voltage sense (Note 9)
“B” side positive reference voltage input (Note 9)
No Connect—no internal connection to these pins.
RTS
14
VB
RT
16, 48, 63
29
N.C.
SUB
Circuit Substrate contact. This pin must be connected to V
.
EE
31
33
DCLK
DCLK
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
32, 69, 80
35
VEE
Negative Power Supply, -5.2V ±5% nominal
DIV10
Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
36, 38, 39,
41, 42, 44,
45, 47
A7–A0
B7–B0
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100Ω transmission lines. Terminate with 100Ω to -2V
(120Ω for Tj > +100°C). See Figures 1–3.
28, 26, 25,
23, 22, 20,
19, 17
_______________________________________________________________________________________
7
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
_________________________________________________P in De s c rip t io n (c o n t in u e d )
PIN
50
NAME
VA
FUNCTION
“A” side positive reference voltage input (Note 9)
RT
51
VA
“A” side positive reference voltage sense (Note 9)
Internal connection, leave pin open.
RTS
MAX01
52
TP1
TP2
VA
53
Internal connection, leave pin open.
54
“A” side negative reference voltage sense (Note 9)
“A” side negative reference voltage input (Note 9)
Internal connection, leave pin open.
RBS
55
VA
RB
65
TP5
66
TP6
AIN+
AIN-
Internal connection, leave pin open.
72, 73
75, 76
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
83
PH
ADJ
Note 9: VA , VA , VB , and VB should be adjusted separately from a well bypassed reference circuit to ensure proper
RT
RB
RT
RB
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10: Good results are obtained by connecting the PH
input to ground. Improve performance by applying a voltage between
ADJ
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
CLK
CLK
t
t
PWL
PWH
DCLK
DCLK
t
PD1
ADATA
BDATA
t
t
PD2
PD2
Figure 1. Output Timing, Normal Mode, DIV10 = OPEN
8
_______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
N–1
N
N+2
+14
+15
+16
+17
N+1
CLK
0
1
7
8
DCLK
ADATA
BDATA
N-1
N+1
N+3
N-2
N
N+2
t
PD2
t
PD2
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING.
Figure 2. Output Timing, Clock to Data, Normal Mode DIV10 = OPEN
N
N+2
N+3
+15
+16
+17
N+1
CLK
DCLK
ADATA
BDATA
N
N+5
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INPUT CLOCK PHASING.
Figure 3. Output Timing, Test Mode (DIV10 = GND)
_______________________________________________________________________________________
9
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
______De fin it io n s o f S p e c ific a t io n s
S ig n a l-t o No is e Ra t io a n d Effe c t ive Bit s
CLK
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency to the
CLK
t
AW
RMS amplitude of all other analog-to-digital (A/D) out-
p ut s ig na ls . The the ore tic a l minimum A/D nois e is
caused by quantization error and is a direct result of
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N
is the number of effective bits of resolution. Therefore, a
perfect 8-bit ADC can do no better than 50dB. The FFT
plots in the Typical Operating Characteristics show the
output level in various spectral bands.
ANALOG
INPUT
MAX01
t
AD
t
AJ
SAMPLED
DATA (T/H)
Effective bits is calculated from a digital record taken
from the ADC under test. The quantization error of the
ideal converter equals the total error of the device. In
addition to ideal quantization error, other sources of
error include all DC and AC nonlinearities, clock and
aperture jitter, missing output codes, and noise. Noise
on references and supplies also degrades effective bits
performance.
TRACK
HOLD
APERTURE DELAY (t
TRACK
T/H
)
AD
APERTURE WIDTH (t
)
AW
APERTURE JITTER (t
)
AJ
The ADC’s input is a sine wave filtered with an anti-
aliasing filter to remove any harmonic content. The digi-
tal record taken from this signal is compared against a
ma the ma tic a lly g e ne ra te d s ine wa ve . DC offs e ts ,
phase, and amplitudes of the mathematical model are
adjusted until a best-fit sine wave is found. After sub-
tracting this sine wave from the digital record, the resid-
ual error remains. The rms value of the error is applied
in the following equation to yield the ADC’s effective
bits.
Figure 4. T/H Aperture Timing
typical converters can be incorrect, including false full-
or zero-scale output. The MAX101’s unique design
reduces the magnitude of this type of error to 1LSB,
and reduces the probability of the error occurring to
15
less than one in every 10 clock cycles. If the MAX101
were operated at 500MHz, 24 hours a day, this would
translate to less than one metastable state error every
46 days.
measured rms error
Effective bits = N - log
—————————-
2
ideal rms error
In t e g ra l No n lin e a rit y
Integral nonlinearity is the deviation of the transfer func-
tion from a reference line measured in fractions of 1LSB
us ing a “b e s t s tra ig ht line ” d e te rmine d b y a le a s t
square curve fit.
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the con-
verter’s maximum clock rate with the analog input near
the Nyquist rate (one-half the input clock rate).
Diffe re n t ia l No n lin e a rit y
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
Ap e rt u re Wid t h a n d J it t e r
Aperture width is the time the T/H circuit takes to dis-
connect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 4).
[V
MEAS
- (V
)] - LSB
MEAS - 1
DNL(LSB) = ——————————————-
LSB
Erro r Ra t e s
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
where V
code.
is the measured value of the previous
MEAS - 1
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
10 ______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
_______________De t a ile d De s c rip t io n
Table 1. Output Mode Control
DCLK*
(MHz)
Co n ve rt e r Op e ra t io n
The parallel or “flash” architecture used by the MAX101
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash, as
with all other ADC architectures, is the comparator, which
has a positive input, a negative input, and an output. If
the voltage at the positive input is higher than the nega-
tive input (connected to a reference), the output will be
high. If the positive input voltage is lower than the refer-
ence, the output will be low. A typical n-bit flash consists
DIV10
MODE
DESCRIPTION
Normal AData and BData valid on oppo-
Divide
by 2
OPEN
250
site DCLK edges (AData on rise,
BData on fall).
AData and BData valid on oppo-
site DCLK edges (AData on rise,
BData on fall). Data sampled at
input CLK rate but 4 out of every
5 samples discarded.
Test
Divide
by 10
GND
50
n
of 2 - 1 comparators with negative inputs evenly spaced
at 1LSB increments from the bottom to the top of the ref-
erence ladder. For n = 8, there are 255 comparators.
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In
all modes, the output clock DCLK will be a 50% duty cycle signal.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1 and all comparators
with negative inputs above the input voltage will have
outputs of 0. Decode logic is provided to convert this
information into a parallel n-bit digital word (the output)
corresponding to the number of LSBs (minus 1) that the
input voltage is above the bottom of the ladder.
Da t a Flo w
The MAX101’s internal T/H amplifier samples the analog
input voltage for the ADC to convert. The T/H is split into
two sections that operate on alternate negative clock
edges. The input clock, CLK, is conditioned by the T/H
and fed to the A/D section. The output clock, DCLK,
used for output data timing, will be divided by 2 or 10
from the input clock, CLK (Table 1). This would result in
an output data rate of 250Mbps on each output port in
normal mode and 50Mbps in test mode. The differential
inp uts , AIN+ a nd AIN-, a re tra c ke d c ontinuous ly
between data samples. When a negative strobe edge is
sensed, one-half of the T/H goes into the hold mode
(Figure 4). When the strobe is low, the just-acquired
sample is presented to the ADC’s input comparators.
Internal processing of the sampled data takes an addi-
tional 15 clock cycles before it is available at the out-
puts, AData and BData. See Figures 1–3 for timing.
The c omp a ra tors c onta in la tc h c irc uitry a nd a re
clocked. This allows the comparators to function as
described previously when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
The MAX101 uses a monolithic dual interleaved parallel
q ua ntize r c hip with two s e p a ra te 8-b it c onve rte rs .
These converters deliver results to the A and B output
latches on alternate negative edges of the input clock.
Tra c k /Ho ld
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will d e c re a s e . The MAX101 ha s a n inte rna l
track/hold (T/H) that increases attainable effective bits
performance and allows more accurate capture of ana-
log data at high conversion rates.
__________Ap p lic a t io n s In fo rm a t io n
An a lo g In p u t Ra n g e s
Although the normal operating range is ±270mV, the
MAX101 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
The internal T/H circuit provides two important circuit
functions for the MAX101:
To ob ta in full-s c a le d ig ita l outp ut with d iffe re ntia l
inp ut d rive , a nomina l + 270mV mus t b e a p p lie d
between AIN+ and AIN-. That is, AIN+ = +135mV and
AIN- = -135mV (with no DC offset). Mid-scale digital
output code occurs when there is no voltage difference
across the analog inputs. Zero-scale digital output
code, with differential -270mV drive, occurs when AIN+
= -135mV and AIN- = +135mV. Table 2 shows how the
output of the converter stays at all ones (full scale)
when over-ranged or all zeros (zero scale) when under-
ranged.
1) Its nominal voltage gain of 4 reduces the input dri-
ving s ig na l to ± 270mV d iffe re ntia l (a s s uming a
±1.02V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX101.
______________________________________________________________________________________ 11
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
Table 2. Input Voltage Range
AIN+
(mV)
AIN-
(mV)
OUTPUT
CODE
MSB to
LSB
INPUT
+135
0
-135
1 1 1 1 1 1 1 1 full scale
1 0 0 0 0 0 0 0 mid scale
0 0 0 0 0 0 0 0 zero scale
1 1 1 1 1 1 1 1 full scale
1 0 0 0 0 0 0 0 mid scale
0 0 0 0 0 0 0 0 zero scale
POSITIVE
REFERENCE
Differential
0
VA
RT
-135
+270
0
+135
MAX01
0
0
0
PARASITIC
RESISTANCE
Single
Ended
VA
RTS
-270
* An offset V , as specified in the DC electrical paramters, will be
IO
R
present at the input. Compensate for this offset by adjusting the
reference voltage. Offsets may be different between side A and
side B.
TO
COMPARATORS
For single-ended operation:
R
R
R
R
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are ter-
minated internally with 50Ω to analog ground.)
2) Drive the othe r inp ut with a ± 270mV + offs e t to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Re fe re n c e
The ADC’s reference resistor is a Kelvin-sensed, resis-
tor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 21mA due to the 100Ω
minimum resistor string impedance. A ±1.02V refer-
ence voltage is normally applied to inputs VA , VB
,
RT
RT
VA , and VB . This reference voltage can be adjust-
RB
RB
e d up to ± 1.2V to a c c ommod a te e xte nd e d inp ut
requirements (accuracy specifications are guaranteed
with ±1.02V references). The reference inputs VA
,
RTS
VA
, VB
, and VB
allow Kelvin sensing of the
RBS
RTS
RBS
VA
RBS
applied voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the buffer out-
put that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the buffer’s output
(s e e Typ ic a l Op e ra ting Circ uit). This re s is tor a nd
capacitor combination should be located within 0.5
inches of the MAX101 package. Any noise on these
p ins will d ire c tly a ffe c t the c od e unc e rta inty a nd
degrade the ADC’s effective bits performance.
PARASITIC
RESISTANCE
VA
RB
NEGATIVE
REFERENCE
Figure 5. Reference Ladder
12 ______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
CLK a n d DCLK
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing sig-
nals for the MAX101. CLK (pins 2, 62) and CLK (pins 3,
61) are fed to the internal circuitry through an internal
50Ω transmission line. One set of CLK, CLK inputs
should be driven and the other pair terminated by 50Ω
to -2V. Either set of inputs can be used as the driven
inputs (input lines are balanced) for easy circuit con-
La yo u t , Gro u n d in g , a n d P o w e r S u p p lie s
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEE and VCC
supply pins to GND with high-quality 0.1µF and 0.001µF
ceramic capacitors located as close to the package as
possible. Connect all ground pins to a ground plane to
optimize noise immunity and highest device accuracy.
P h a s e Ad ju s t
This control pin affects the point in time that one-half of
the converter samples the input signal relative to the
nection. A minimum pulse width (t ) is required for
PWL
CLK and CLK (Figures 1–3).
other half. PH
is normally connected to ground (0V),
ADJ
For best performance and consistent results, use a low-
phase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
c onve rte r’s e ffe c tive b its p e rforma nc e a nd c a us e s
inconsistent results. The clock supplied to the MAX101
is internally divided by two, reshaped, and buffered.
This divided clock becomes the internal signal used as
strobes for the converters.
but can be adjusted over a ±1.25V range that typically
provides a ±18ps adjustment between the “A” side T/H
bridge strobe and the “B” side T/H bridge strobe.
In p u t Clo c k P h a s in g (TRK1 , TRK1 )
At power-up, the clock edge from which AData and
BData are synchronized is undetermined. The convert-
e r c a n work from a s p e c ific inp ut c loc k e d g e , a s
described in the following paragraph.
DCLK and DCLK are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. (AData is valid after the ris-
ing edge of DCLK and BData is valid after the falling
edge.) They are fixed at one-half the rate of the input
clocks in normal mode (Table 1). The MAX101 is char-
acterized to work with 500MHz maximum input clock
frequencies. See Typical Operating Circuit.
TRK1 and TRK1 are differential inputs that are used in
addition to the normal input clock (CLK) to set data
phasing. A signal at one-half the input clock rate with
the proper setup and hold times (setup and hold typi-
cally 300ps) is applied to these inputs. Choose AData
by applying a logic “1” to TRK1 (“0” to TRK1) before
CLK’s negative transition. Choose BData by applying a
logic “0” at CLK’s negative edge (“1” to TRK1). In this
manner, several MAX101s can be interleaved to obtain
faster effective sampling rates. Voltages at the TRK1
input between ±50mV are interpreted as logic “1” and
voltages between -350mV and -500mV are interpreted
as logic “0”.
Ou t p u t Mo d e Co n t ro l (DIV1 0 )
When DIV10 is grounded, it enables the test mode,
where the input incoming clock is divided by ten. This
reduces the output data and clock rates by a factor of
5, allowing the output clock duty cycle to remain at
50%. The clock to output phasing remains the same
and four out of every five sampled input values are dis-
carded.
When left open, this input (DIV10) is pulled low by inter-
nal circuitry and the converter functions in its normal
mode.
______________________________________________________________________________________ 13
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
___________________________________________________Typ ic a l Op e ra t in g Circ u it
0.01µF
+5V
0.1µF
1
+VS
2
2.5V
1.5k
VOUT
GND
MAX01
0.001µF
3
MX580LH
MC100E151
0.01µF
8, 21, 43, 56, 81
1/ MAX412
2
D
>
Q
Q
500Ω
20Ω
33Ω
50
V
CC
VA
RT
1.2k
0.47µF
50Ω
CMPSH-3
51
0.01µF
0.01µF
8
VA
RTS
ADATA
D
>
Q
Q
50Ω
20k
54
VA
RBS
1.5k
20k
1/ MAX412
2
500Ω
20Ω
33Ω
55
VA
RB
0.47µF
CMPSH-3
1.2k
WATKINS-JOHNSON
SMRA 89-1 (2x)
10k
MAX101
72, 73
75, 76
33
31
DCLK
DCLK
AIN+
AIN-
1.5k
1/ MAX412
2
MC100E151
500Ω
20Ω
33Ω
14
VB
RT
D
>
Q
Q
1.2k
0.47µF
50Ω
CMPSH-3
13
0.01µF
0.01µF
VB
RTS
50Ω
20k
10
8
VB
RBS
D
>
Q
Q
BDATA
1.5k
20k
1/ MAX412
2
500Ω
20Ω
33Ω
9
VB
RB
0.47µF
CMPSH-3
1.2k
+1.25V
10k
62
83
PHASE
PH
ADJ
CLK
CLK
50Ω
2
-2V
-2V
-1.25V
61
MC100E116
50Ω
3
GND SUB
29
VEE
32, 69, 80
4, 7, 15, 18, 24, 27, 30, 34,
37, 40, 46, 49, 57, 60, 64, 67, 68,
70, 71, 74, 77, 78, 79, 82, 84
0.001µF
0.1µF
-5.2V
14 ______________________________________________________________________________________
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
MAX01
____________________________________________________________P in Co n fig u ra t io n
TOP VIEW
1
2
3
63
PAD
CLK
CLK
GND
N.C.
CLK
CLK
GND
62
61
4
60
59
58
57
56
55
54
53
5
6
7
TRK1
TRK1
GND
VCC
TRK1
TRK1
GND
VCC
8
9
VB
RB
VA
RB
10
VB
VA
RBS
RBS
TP4
TP3
MAX101
11
12
13
14
15
16
17
18
19
20
21
TP2
TP1
52
51
50
49
48
47
46
VB
RTS
VA
RTS
VB
VA
RT
RT
GND
N.C.
B0
GND
N.C.
A0
GND
B1
GND
A1
45
44
43
B2
A2
VCC
VCC
Ceramic Flat Pack
______________________________________________________________________________________ 15
5 0 0 Ms p s , 8 -Bit ADC w it h Tra c k /Ho ld
________________________________________________________P a c k a g e In fo rm a t io n
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
23
21
19
MAX01
17
15
0° Angle*
13
11
45° Angle*
9
7
0
100
200
300
400
500
VELOCITY (ft /min)
*DIRECTION OF AIRFLOW ACROSS HEATSINK
MILLIMETERS
INCHES
E1
E
DIM
MIN
MAX
MIN MAX
E2
A
17.272 18.288 0.680 0.720
S
e
A1 1.041 1.270 0.041 0.050
A2 3.048 3.302 0.120 0.130
0.060±.005(7x)
b
C
D
0.406 0.508 0.016 0.020
0.228 0.279 0.009 0.011
29.184 29.794 1.149 1.173
D1
D1 44.196 44.704 1.740 1.760
D2 25.298 25.502 0.996 1.004
D3 28.448 28.829 1.120 1.135
D
D2
D3
e
1.270 BSC
0.050 BSC
E
29.184 29.794 1.149 1.173
E1 44.196 44.704 1.740 1.760
E2 25.298 25.502 0.996 1.004
E3 28.194 28.702 1.110 1.130
0.075±.020(6x)
EQUAL SPACES
PIN #1
b
A2 A1
C
S
1.930 2.184 0.076 0.086
84-PIN CERAMIC FLAT
PACK WITH HEAT SINK
A
5°–6°
0.060±.005
E3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1022BETX+T
Analog Circuit, 1 Func, BICMOS, PQCC36, 6 X 6 MM, 0.80 MM HEIGHT, MO-220-WJJD, TQFN-36
MAXIM
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