MAX1028BCEP+ [MAXIM]
A/D Converter, 10-Bit, 1 Func, 12 Channel, Serial Access, BICMOS, PDSO20, ROHS COMPLIANT, QSOP-20;
| 型号： | MAX1028BCEP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | A/D Converter, 10-Bit, 1 Func, 12 Channel, Serial Access, BICMOS, PDSO20, ROHS COMPLIANT, QSOP-20 信息通信管理 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2853; Rev 4; 4/11
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
General Description
Features
The MAX1026/MAX1028/MAX1030 are serial 10-bit ana-
log-to-digital converters (ADCs) with an internal reference
and an internal temperature sensor. These devices fea-
ture on-chip FIFO, scan mode, internal clock mode, inter-
nal averaging, and AutoShutdown™. The maximum
sampling rate is 300ksps using an external clock. The
MAX1030 has 16 input channels, the MAX1028 has 12
input channels, and the MAX1026 has 8 input channels.
All input channels are configurable for single-ended or
differential inputs in unipolar or bipolar mode. All three
devices operate from a +5V supply and contain a 10MHz
SPI™/QSPI™/MICROWIRE™-compatible serial port.
o Internal Temperature Sensor ( 0.7°C Accuracy)
o 16-Entry First-In/First-Out (FIFO)
o Analog Multiplexer with True Differential
Track/Hold
16-, 12-, 8-Channel Single Ended
8-, 6-, 4-Channel True Differential
(Unipolar or Bipolar)
o Accuracy: 1 LSB INL, 1 LSB DNL, No Missing
Codes Over Temperature
o Scan Mode, Internal Averaging, and Internal Clock
o Low-Power Single +5V Operation
The MAX1030 is available in 28-pin 5mm x 5mm TQFN
with exposed pad and 24-pin QSOP packages. The
MAX1026/MAX1028 are only available in QSOP pack-
ages. All three devices are specified over the extended
-40°C to +85°C temperature range.
2.3mA at 300ksps
o Internal 4.096V Reference or External Differential
Reference
o 10MHz 3-Wire SPI/QSPI/MICROWIRE-Compatible
________________________Applications
Interface
o Space-Saving 28-Pin 5mm x 5mm TQFN Package
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Ordering Information
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
16 QSOP
MAX1026BCEE+T
MAX1026BEEE+T
MAX1028BCEP+T
MAX1028BEEP+T
16 QSOP
Instrumentation
20 QSOP
20 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Pin Configurations
+
TOP VIEW
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
20 EOC
19 DOUT
18 DIN
17 CS
+
AIN0
1
2
3
4
5
6
7
8
16 EOC
15 DOUT
14 DIN
13 CS
AIN1
AIN2
MAX1028
AIN3
MAX1026
16 SCLK
15
14
V
DD
AIN4
12 SCLK
AIN5
11
10 GND
REF+
V
GND
DD
13 REF+
REF-/AIN6
CNVST/AIN7
9
12 CNVST/AIN11
11 REF-/AIN10
AIN9 10
QSOP
Pin Configurations continued at end of data sheet.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
CS% SCLK% DIN% EOC% DOUT to GND.........-0.3V to (V
AIN0–AIN13% REF-/AIN_% CNVST/AIN_%
REF+ to GND.........................................-0.3V to (V
Maximum Current into Any Pin............................................50mA
+ 0.3V)
MAX10__C__.......................................................0°C to +70°C
MAX10__E__....................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering% 10s) .................................+300°C
Soldering Temperature (reꢁlow) .......................................+260°C
DD
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
28-Pin TQFN 5mm x 5mm
(derate 20.8mW/°C above +70°C)..........................1667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only% and ꢁunctional
operation oꢁ the device at these or any other conditions beyond those indicated in the operational sections oꢁ the speciꢁications is not implied. Exposure to
absolute maximum rating conditions ꢁor extended periods may aꢁꢁect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V 5ꢀ% ꢁ
= 300kHz% ꢁ
= 4.8MHz (50ꢀ duty cycle)% V
= 4.096V% T = T
to T
% unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
10
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Diꢁꢁerential Nonlinearity
Oꢁꢁset Error
1.0
1.0
2.0
2.0
DNL
No missing codes over temperature
(Note 2)
0.5
0.5
628/MAX130
Gain Error
Oꢁꢁset Error Temperature
Coeꢁꢁicient
ppm/°C
FSR
2
Gain Temperature Coeꢁꢁicient
0.8
0.1
ppm/°C
Channel-to-Channel Oꢁꢁset
Matching
LSB
DYNAMIC SPECIFICATIONS (30kHz sine wave input, 4.096V , 300ksps, f
= 4.8MHz)
P-P
SCLK
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
61
-88
89
76
1
dB
dBc
dBc
dBc
MHz
kHz
Up to the 5th harmonic
SFDR
IMD
ꢁ
= 29.9kHz% ꢁ
= 30.2kHz
IN2
IN1
-3dB point
S/(N + D) > 68dB
Full-Linear Bandwidth
100
2
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V 5ꢀ% ꢁ
= 300kHz% ꢁ
= 4.8MHz (50ꢀ duty cycle)% V
= 4.096V% T = T
to T
% unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
External reꢁerence
0.8
65
Power-Up Time
Acquisition Time
Conversion Time
t
μs
μs
μs
PU
Internal reꢁerence (Note 3)
t
0.6
ACQ
Internally clocked
3.5
t
CONV
Externally clocked (Note 4)
Externally clocked conversion
Data I/O
2.7
0.1
4.8
10
External Clock Frequency
ꢁ
MHz
SCLK
Aperture Delay
Aperture Jitter
ANALOG INPUT
30
ns
ps
<50
Unipolar
0
V
REF
Input Voltage Range
V
Bipolar (Note 5)
-V /2
REF
V
REF
/2
Input Leakage Current
Input Capacitance
V
= V
0.01
24
1
μA
pF
IN
DD
During acquisition time (Note 6)
INTERNAL TEMPERATURE SENSOR
Grade B% T = +25°C
0.7
1.2
0.1
1/8
0.3
A
Measurement Error (Note 7)
°C
Grade B% T = T
A
to T
3.0
MIN
MAX
Temperature Measurement Noise
Temperature Resolution
Power-Supply Rejection
INTERNAL REFERENCE
REF Output Voltage
°C
RMS
°C
°C/V
4.024
4.096
20
4.168
V
ppm/°C
k_
REF Temperature Coeꢁꢁicient
Output Resistance
TC
REF
Grade B
6.5
REF Output Noise
200
-70
μV
RMS
REF Power-Supply Rejection
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
PSRR
dB
V
0
500
+ 50mV
100
mV
V
REF-
V
1.0
V
DD
REF+
V
V
= 4.096V% ꢁ
= 4.096V% ꢁ
= 300ksps
= 0
40
REF+
REF+
SAMPLE
SAMPLE
REF+ Input Current
I
μA
REF+
0.1
5
_______________________________________________________________________________________
3
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V 5ꢀ% ꢁ
= 300kHz% ꢁ
= 4.8MHz (50ꢀ duty cycle)% V
= 4.096V% T = T
to T
% unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)(Note 8)
Input Voltage Low
V
0.8
V
V
IL
Input Voltage High
V
2.0
IH
Input Hysteresis
V
200
0.01
15
mV
μA
pF
HYST
Input Leakage Current
Input Capacitance
I
V
= 0V or V
DD
1.0
IN
IN
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
I
I
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Voltage Low
V
V
OL
SINK
Output Voltage High
V
= 1.5mA
V - 0.5
DD
V
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Supply Voltage
I
CS = V
CS = V
0.05
15
1
μA
pF
L
DD
DD
C
OUT
V
4.75
5.25
3200
2550
1350
5
V
DD
DD
During temp sense
2800
2300
1050
0.2
ꢁ
ꢁ
= 300ksps
SAMPLE
SAMPLE
Internal
reꢁerence
= 0% REF on
Supply Current (Note 9)
Power-Supply Rejection
I
Shutdown
μA
During temp sense
1800
1600
0.2
2300
1700
5
628/MAX130
External
reꢁerence
ꢁ
= 300ksps
SAMPLE
Shutdown
PSR
V
= 4.75V to 5.25V; ꢁull-scale input
0.2
1.4
mV
DD
Note 1: Tested at V
= +5V% unipolar input mode.
DD
Note 2: Oꢁꢁset nulled.
Note 3: Time ꢁor reꢁerence to power up and settle to within 1 LSB.
Note 4: Conversion time is deꢁined as the number oꢁ clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle.
Note 5: The operational input voltage range ꢁor each individual input oꢁ a diꢁꢁerentially conꢁigured pair is ꢁrom GND to V . The oper-
DD
ational input voltage diꢁꢁerence is ꢁrom -V
/ 2 to +V
/ 2.
REF
REF
Note 6: See Figure 3 (Input Equivalent Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
Note 7: Fast automated test% excludes selꢁ-heating eꢁꢁects.
Note 8: When CNVST is conꢁigured as a digital input% do not apply a voltage beween V and V
.
IH
IL
Note 9: Supply current is speciꢁied depending on whether an internal or external reꢁerence is used ꢁor voltage conversions.
Temperature measurements always use the internal reꢁerence.
4
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
TIMING CHARACTERISTICS (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
Externally clocked conversion
Data I/O
MIN
208
100
40
TYP
MAX
UNITS
SCLK Clock Period
t
ns
CP
SCLK Duty Cycle
t
60
40
40
40
40
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
CH
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
t
C
C
C
= 30pF
= 30pF
= 30pF
DOT
LOAD
LOAD
LOAD
t
DOD
t
DOE
DIN to SCLK Rise Setup
t
DS
DH
SCLK Rise to DIN Hold
t
0
C S Fall to SCLK Rise Setup Time
CS Fall to SCLK Rise Hold Time
CS Rise to SCLK Rise Hold Time
CS Rise to SCLK Rise Setup Time
t
40
CSS0
CSH0
t
0
0
t
CSH
t
0
CSS1
t
CKSEL = 00% CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
Temp sense
40
1.4
CSW
CNVST Pulse Width
t
t
55
7
TS
CS or CNVST Rise to EOC
Low (Note 10)
Voltage conversion
μs
Reꢁerence power-up
65
RP
Note 10: This time is deꢁined as the number oꢁ clock cycles needed ꢁor conversion multiplied by the clock period. Iꢁ the internal
reꢁerence needs to be powered up% the total time is additive. The internal reꢁerence is always used ꢁor temperature mea
surements.
Typical Operating Characteristics
(V
= +5V% V
= +4.096V% ꢁ
= 4.8MHz% C = 30pF% T = +25°C% unless otherwise noted.)
LOAD A
DD
REF
SCLK
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
SINAD vs. FREQUENCY
vs. OUTPUT CODE
100
0.4
0.3
0.2
0.1
0
0.4
90
80
70
60
50
40
30
20
10
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
0
256
512
768
1024
0
256
512
768
1024
0.1
1
10
100
1000
OUTPUT CODE
OUTPUT CODE
FREQUENCY (kHz)
_______________________________________________________________________________________
5
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Typical Operating Characteristics (continued)
(V
= +5V% V
= +4.096V% ꢁ
= 4.8MHz% C
= 30pF% T = +25°C% unless otherwise noted.)
DD
REF
SCLK
LOAD A
SFDR vs. FREQUENCY
SUPPLY CURRENT vs. SAMPLING RATE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
120
100
80
60
40
20
0
1200
1200
1150
1100
1050
1000
1000
800
600
400
200
0.1
1
10
100
1000
1
10
100
1000
4.75
4.85
4.95
5.05
5.15
5.25
FREQUENCY (kHz)
SAMPLING RATE (ksps)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1300
0.6
0.5
0.4
0.3
0.2
0.1
f
= 300ksps
S
1250
1200
1150
1100
1050
1000
628/MAX130
0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
4.0500
4.0499
4.0498
4.0497
4.0496
4.0495
4.0494
0.6
0.5
0.4
0.3
0.2
0.1
0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
Typical Operating Characteristics (continued)
(V
= +5V% V
= +4.096V% ꢁ
= 4.8MHz% C
= 30pF% T = +25°C% unless otherwise noted.)
A
DD
REF
SCLK
LOAD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. TEMPERATURE
4.051
0.6
0.5
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
0.2
0.1
0
4.050
4.049
4.048
4.047
0
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.5
0
0.5
0
-0.5
-1.0
-0.5
-1.0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
SAMPLING ERROR
vs. SOURCE IMPEDANCE
1.00
0.75
1
0
-1
-2
-3
-4
-5
0.50
0.25
0
-0.25
GRADE B
-0.50
-0.75
-1.00
-40
-15
10
35
60
85
0
2
4
6
8
10
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
_______________________________________________________________________________________
7
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Pin Description
PIN
FUNCTION
MAX1030 MAX1030
MAX1028 MAX1026
NAME
N.C.
TQFN
QSOP
1, 17, 19,
25
—
—
—
—
—
No Connection. Not internally connected.
Analog Inputs
2–12, 26,
27, 28
1–14
AIN0–13
—
—
—
—
1–10
—
—
AIN0–9
AIN0–5
Analog Inputs
Analog Inputs
1–6
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
13
—
—
14
—
—
15
—
—
16
—
—
—
11
—
—
12
—
—
—
7
REF-/AIN14
REF-/AIN10
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
—
—
8
CNVST/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
628/MAX130
15
16
18
17
18
19
13
14
15
9
REF+
GND
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
10
11
V
Power Input. Bypass to GND with a 0.1µF capacitor.
DD
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
20
20
16
12
SCLK
Active-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
21
22
23
21
22
23
17
18
19
13
14
15
CS
DIN
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling edge of
DOUT
SCLK. High impedance when CS is connected to V
.
DD
24
—
24
—
20
—
16
—
EOC
End of Conversion Output. Data is valid after EOC pulls low.
EP
Exposed Pad (TQFN Only). Connect EP to GND.
8
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
CS
t
CSH
t
t
t
CSH
t
CH
CP
CSS
t
CSS
SCLK
DIN
t
DH
t
DS
t
t
DOT
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interꢁace Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
EOC
OSCILLATOR
CONTROL
CNVST
AIN1
AIN2
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
T/H
AIN15
TEMP
SENSE
REF-
REF+
INTERNAL
REFERENCE
MAX1026
MAX1028
MAX1030
Figure 2. Functional Diagram
conꢁigurations. Microprocessor (μP) control is made
easy through a 3-wire SPI/QSPI/MICROWIRE-compati-
ble serial interꢁace.
Detailed Description
The MAX1026/MAX1028/MAX1030 are low-power% seri-
al-output% multichannel ADCs with temperature-sensing
capability ꢁor temperature-control% process-control% and
monitoring applications. These 10-bit ADCs have inter-
nal track and hold (T/H) circuitry that supports single-
ended and ꢁully diꢁꢁerential inputs. Data is converted
ꢁrom an internal temperature sensor or analog voltage
sources in a variety oꢁ channel and data-acquisition
Figure 2 shows a simpliꢁied ꢁunctional diagram oꢁ the
MAX1026/MAX1028/MAX1030 internal architecture. The
MAX1026 has eight single-ended analog input chan-
nels or ꢁour diꢁꢁerential channels. The MAX1028 has 12
single-ended analog input channels or six diꢁꢁerential
channels. The MAX1030 has 16 single-ended analog
input channels or eight diꢁꢁerential channels.
_______________________________________________________________________________________
9
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Tables 1–7 detail the register descriptions. Bits 5 and 4%
Converter Operation
The MAX1026/MAX1028/MAX1030 ADCs use a ꢁully diꢁ-
ꢁerential% successive-approximation register (SAR) con-
version technique and an on-chip T/H block to convert
temperature and voltage signals into a 10-bit digital
result. Both single-ended and diꢁꢁerential conꢁigurations
are supported% with a unipolar signal range ꢁor single-
ended mode and bipolar or unipolar ranges ꢁor diꢁꢁer-
ential mode.
CKSEL1 and CKSEL0% respectively% control the clock
modes in the setup register (see Table 3). Choose
between ꢁour diꢁꢁerent clock modes ꢁor various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to conꢁigure CNVST/AIN_ to act as a conver-
sion start and use it to request the programmed inter-
nally timed conversions without tying up the serial bus.
In clock mode 01% use CNVST to request conversions
one channel at a time% controlling the sampling speed
without tying up the serial bus. Request and start inter-
nally timed conversions through the serial interꢁace by
writing to the conversion register in the deꢁault clock
mode% 10. Use clock mode 11 with SCLK up to 4.8MHz
ꢁor externally timed acquisitions to achieve sampling
rates up to 300ksps. Clock mode 11 disables scanning
and averaging. See Figures 4–7 ꢁor timing speciꢁica-
tions and how to begin a conversion.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth% so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias preꢁiltering
oꢁ the input signals is necessary to avoid high-ꢁrequen-
cy signals aliasing into the ꢁrequency band oꢁ interest.
Analog Input Protection
These devices ꢁeature an active-low% end-oꢁ-conversion
output. EOC goes low when the ADC completes the
last-requested operation and is waiting ꢁor the next
input data byte (ꢁor clock modes 00 and 10). For clock
mode 01% EOC goes low aꢁter the ADC completes each
requested operation. EOC goes high when CS or CNVST
goes low. EOC is always high in clock mode 11.
Internal ESD protection diodes clamp all pins to V
DD
and GND% allowing the inputs to swing ꢁrom (GND -
0.3V) to (V + 0.3V) without damage. However% ꢁor
DD
accurate conversions near ꢁull scale% the inputs must
not exceed V by more than 50mV or be lower than
DD
GND by 50mV. Iꢁ an oꢁꢁ-channel analog input voltage
exceeds the supplies% limit the input current to 2mA.
Single-Ended/Differential Input
The MAX1026/MAX1028/MAX1030 use a ꢁully diꢁꢁeren-
tial ADC ꢁor all conversions. The analog inputs can be
conꢁigured ꢁor either diꢁꢁerential or single-ended con-
versions by writing to the setup register (see Table 3).
Single-ended conversions are internally reꢁerenced to
GND (see Figure 3).
3-Wire Serial Interface
The MAX1026/MAX1028/MAX1030 ꢁeature a serial
interꢁace compatible with SPI/QSPI and MICROWIRE
devices. For SPI/QSPI% ensure the CPU serial interꢁace
runs in master mode so it generates the serial clock
signal. Select the SCLK ꢁrequency oꢁ 10MHz or less%
and set clock polarity (CPOL) and phase (CPHA) in the
μP control registers to the same value. The MAX1026/
MAX1028/MAX1030 operate with SCLK idling high or
low% and thus operate with CPOL = CPHA = 0 or CPOL
= CPHA = 1. Set CS low to latch input data at DIN on
the rising edge oꢁ SCLK. Output data at DOUT is
updated on the ꢁalling edge oꢁ SCLK. Bipolar true-diꢁ-
ꢁerential results and temperature sensor results are
available in two’s complement ꢁormat% while all others
are in binary.
628/MAX130
In diꢁꢁerential mode% the T/H samples the diꢁꢁerence
between two analog inputs% eliminating common-mode
DC oꢁꢁsets and noise. IN+ and IN- are selected ꢁrom
the ꢁollowing pairs: AIN0/AIN1% AIN2/AIN3% AIN4/AIN5%
AIN6/AIN7% AIN8/AIN9% AIN10/AIN11% AIN12/AIN13%
and AIN14/AIN15. AIN0–AIN7 are available on the
MAX1026% MAX1028% and MAX1030. AIN8–AIN11 are
only available on the MAX1028 and MAX1030.
AIN12–AIN15 are only available on the MAX1030. See
Tables 2–5 ꢁor more details on conꢁiguring the inputs.
For the inputs that can be conꢁigured as CNVST or an
analog input% only one can be used at a time. For the
inputs that can be conꢁigured as REF- or an analog
input% the REF- conꢁiguration excludes the analog input.
Serial communication always begins with an 8-bit input
data byte (MSB ꢁirst) loaded ꢁrom DIN. Send a second
byte% immediately ꢁollowing the setup byte% to write to
the unipolar mode or bipolar mode registers (see
Tables 1% 3% 4% and 5). A high-to-low transition on CS ini-
tiates the data input operation. The input data byte and
the subsequent data bytes are clocked ꢁrom DIN into
the serial interꢁace on the rising edge oꢁ SCLK.
10 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
needed ꢁor a signal to be acquired% plus the power-up
time. It is calculated by the ꢁollowing equation:
REF
GND
AIN0-AIN15
(SINGLE ENDED);
AIN0, AIN2,
DAC
t
= 9 x R + R
x 24pF + t
PWR
(
)
AQC
S
IN
AIN4…AIN14
(DIFFERENTIAL)
CIN+
COMPARATOR
+
where R = 1.5kΩ% R is the source impedance oꢁ the
IN
S
PWR
input signal% and t
= 1μs% the power-up time oꢁ the
HOLD
device. The varying power-up times are detailed in the
explanation oꢁ the clock mode conversions.
-
GND
(SINGLE ENDED);
AIN1, AIN3,
AIN5…AIN15
(DIFFERENTIAL)
CIN-
t
is never less than 1.4μs% and any source imped-
ACQ
ance below 300Ω does not signiꢁicantly aꢁꢁect the
HOLD
HOLD
ADC’s AC perꢁormance. A high-impedance source can
be accommodated either by lengthening t
or by
ACQ
V
DD
/2
placing a 1μF capacitor between the positive and neg-
ative analog inputs.
Figure 3. Equivalent Input Circuit
Internal FIFO
The MAX1026/MAX1028/MAX1030 contain a FIFO
buꢁꢁer that can hold up to 16 ADC results plus one tem-
perature result. This allows the ADC to handle multiple
internally clocked conversions and a temperature mea-
surement% without tying up the serial bus.
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair oꢁ analog
channels ꢁor diꢁꢁerential operation by writing a 1 to the
appropriate bit oꢁ the bipolar or unipolar register.
Unipolar mode sets the diꢁꢁerential input range ꢁrom 0 to
Iꢁ the FIFO is ꢁilled and ꢁurther conversions are request-
ed without reading ꢁrom the FIFO% the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes% with the MSB preceded by 4
leading zeros and the LSB ꢁollowed by 2 sub-bits. Aꢁter
each ꢁalling edge oꢁ CS% the oldest available byte oꢁ
data is available at DOUT% MSB ꢁirst. When the FIFO is
empty% DOUT is zero.
V
. A negative diꢁꢁerential analog input in unipolar
REF
mode causes the digital output code to be zero.
Selecting bipolar mode sets the diꢁꢁerential input range
to
V
REF
/ 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode (see
the transꢁer ꢁunction graphs% Figures 8 and 9).
In single-ended mode% the MAX1026/MAX1028/
MAX1030 always operate in unipolar mode. The analog
inputs are internally reꢁerenced to GND with a ꢁull-scale
The ꢁirst 2 bytes oꢁ data read out aꢁter a temperature mea-
surement always contain the temperature result preceded
by 4 leading zeros% MSB ꢁirst. Iꢁ another temperature mea-
surement is perꢁormed beꢁore the ꢁirst temperature result
is read out% the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement) at a resolution oꢁ 1/8 oꢁ a degree. See
the Temperature Measurements section ꢁor details on
converting the digital code to a temperature.
input range ꢁrom 0 to V
.
REF
True Differential Analog Input T/H
The equivalent circuit oꢁ Figure 3 shows the
MAX1026/MAX1028/MAX1030s’ input architecture. In
track mode% a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode (and AIN0% AIN2%
AIN4…AIN14 in diꢁꢁerential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1% AIN3% AIN5…AIN15 in diꢁꢁerential mode). For
external track-and-hold timing% use clock mode 01.
Aꢁter the T/H enters hold mode% the diꢁꢁerence between
the sampled positive and negative input voltages is
converted. The time required ꢁor the T/H to acquire an
input signal is determined by how quickly its input
capacitance is charged. Iꢁ the input signal’s source
impedance is high% the required acquisition time length-
Internal Clock
The MAX1026/MAX1028/MAX1030 operate ꢁrom an inter-
nal oscillator% which is accurate within 10ꢀ oꢁ the
4.4MHz nominal clock rate. The internal oscillator is
active in clock modes 00% 01% and 10. Read out the data
at clock speeds up to 10MHz. See Figures 4–7 ꢁor details
on timing speciꢁications and starting a conversion.
ens. The acquisition time% t
% is the maximum time
ACQ
______________________________________________________________________________________ 11
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
t
= internal reꢁerence wake-up; set to zero iꢁ the inter-
RP
Applications Information
nal reꢁerence is already powered up or iꢁ the external
reꢁerence is being used
Register Descriptions
The MAX1026/MAX1028/MAX1030 communicate
between the internal registers and the external circuitry
through the SPI/QSPI-compatible serial interꢁace. Table
1 details the registers and the bit names. Tables 2–7
show the various ꢁunctions within the conversion regis-
ter% setup register% averaging register% reset register%
unipolar register% and bipolar register.
In clock mode 01% the total conversion time depends on
how long CNVST is held low or high% including any time
required to turn on the internal reꢁerence. Conversion
time in externally clocked mode (CKSEL1% CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set oꢁ eight SCLK cycles.
Conversion Register
Select active analog input channels% scan modes% and
a single temperature measurement per scan by writing
to the conversion register. Table 2 details channel
selection% the ꢁour scan modes% and how to request a
temperature measurement. Request a scan by writing
to the conversion register when in clock mode 10 or 11%
or by applying a low pulse to the CNVST pin when in
clock mode 00 or 01.
Conversion Time Calculations
The conversion time ꢁor each scan is based on a num-
ber oꢁ diꢁꢁerent ꢁactors: conversion time per sample%
samples per result% results per scan% iꢁ a temperature
measurement is requested% and iꢁ the external reꢁer-
ence is in use.
Use the ꢁollowing ꢁormula to calculate the total conver-
sion time ꢁor an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
A conversion is not perꢁormed iꢁ it is requested on a
channel that has been conꢁigured as CNVST or REF-.
Do not request conversions on channels 8–15 on the
MAX1026 and channels 12–15 on the MAX1028. Set
CHSEL3:CHSEL0 to the lower channel’s binary value. Iꢁ
the last two channels are conꢁigured as a diꢁꢁerential
pair and one oꢁ them has been reconꢁigured as CNVST
or REF-% the pair is ignored.
total conversion time = t
where:
x n
x n + t + t
result TS RP
cnv
avg
t
= t
(max) + t
(max)
conv
cnv
acq
n
n
= samples per result (amount oꢁ averaging)
avg
= number oꢁ FIFO results requested; determined
result
628/MAX130
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per diꢁꢁerential pair
within the requested range% plus one temperature result iꢁ
selected. Select scan mode 10 to scan a single input
channel numerous times% depending on NSCAN1 and
NSCAN0 in the averaging register (Table 6). Select scan
mode 11 to return only one result ꢁrom a single channel.
by number oꢁ channels being scanned or by NSCAN1%
NSCAN0
t
= time required ꢁor temperature measurement; set
TS
to zero iꢁ temp measurement is not requested
Table 1. Input Data Byte (MSB First)
REGISTER NAME
BIT 7
BIT 6
BIT 5
CHSEL2
CKSEL1
1
BIT 4
CHSEL1
CKSEL0
AVGON
1
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
BIT 2
SCAN1
REFSEL0
NAVG0
X
BIT 1
SCAN0
DIFFSEL1
NSCAN1
X
BIT 0
TEMP
Conversion
1
CHSEL3
Setup
0
0
1
0
DIFFSEL0
NSCAN0
X
Averaging
Reset
0
0
0
Unipolar mode (setup)
Bipolar mode (setup)
UCH0/1
BCH0/1
UCH2/3
BCH1/2
UCH4/5
BCH4/5
UCH6/7
BCH6/7
UCH8/9*
BCH8/9*
UCH10/11* UCH12/13** UCH14/15**
BCH10/11* BCH12/13** BCH14/15**
*Unipolar/bipolar channels 8–15 are only valid on the MAX1028 and MAX1030.
**Unipolar/bipolar channels 12–15 are only valid on the MAX1030.
X = Don’t care.
12 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
Setup Register
Table 2. Conversion Register*
Write a byte to the setup register to conꢁigure the clock%
reꢁerence% and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode% acquisition and sam-
pling% and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reꢁerence use.
Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the
unipolar mode and bipolar mode registers and conꢁigure
the analog input channels ꢁor diꢁꢁerential operation.
BIT
NAME
BIT
FUNCTION
—
7 (MSB) Set to 1 to select conversion register.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
6
5
4
3
2
1
Analog input channel select.
Analog input channel select.
Analog input channel select.
Analog input channel select.
Scan mode select.
Unipolar/Bipolar Registers
The ꢁinal 2 bits (LSBs) oꢁ the setup register control the
unipolar/bipolar mode address registers. Set bits 1 and
0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipo-
lar mode register. Set bits 1 and 0 to 11 to write to the
bipolar mode register. In both cases% the setup byte
must be ꢁollowed immediately by 1 byte oꢁ data written
to the unipolar register or bipolar register. Hold CS low
and run 16 SCLK cycles beꢁore pulling CS high. Iꢁ the
last 2 bits oꢁ the setup register are 00 or 01% neither the
unipolar mode register nor the bipolar mode register is
written. Any subsequent byte is recognized as a new
input data byte. See Tables 4 and 5 to program the
unipolar and bipolar mode registers.
Scan mode select.
Set to 1 to take a single temperature
TEMP 0 (LSB) measurement. The ꢁirst conversion result
oꢁ a scan contains temperature inꢁormation.
*See below ꢁor bit details.
SELECTED
CHSEL3 CHSEL2 CHSEL1 CHSEL0
CHANNEL (N)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
Iꢁ a channel is conꢁigured as both unipolar and bipolar%
the unipolar setting takes precedence. In unipolar
AIN3
AIN4
mode% AIN+ can exceed AIN- by up to V
. The out-
REF
AIN5
put ꢁormat in unipolar mode is binary. In bipolar mode%
AIN6
either input can exceed the other by up to V
output ꢁormat in bipolar mode is two's complement.
/ 2. The
REF
AIN7
AIN8
Averaging Register
Write to the averaging register to conꢁigure the ADC to
average up to 32 samples ꢁor each requested result%
and to independently control the number oꢁ results
requested ꢁor single-channel scans.
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Table 2 details the ꢁour scan modes available in the con-
version register. All ꢁour scan modes allow averaging as
long as the AVGON bit% bit 4 in the averaging register% is
set to 1. Select scan mode 10 to scan the same channel
multiple times. Clock mode 11 disables averaging.
SCAN MODE (CHANNEL N IS
SELECTED BY BITS CHSEL3–CHSEL0)
Reset Register
Write to the reset register (as shown in Table 7) to clear
the FIFO or to reset all registers to their deꢁault states.
Set the RESET bit to 1 to reset the FIFO. Set the reset
bit to zero to return the MAX1026/MAX1028/MAX1030
to the deꢁault power-up state.
SCAN1 SCAN0
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The averaging
register sets the number oꢁ results.
1
1
0
1
No scan. Converts channel N once only.
______________________________________________________________________________________ 13
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Table 3. Setup Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to zero to select setup register.
—
6
Set to 1 to select setup register.
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST conꢁiguration. Resets to 1 at power-up.
Clock mode and CNVST conꢁiguration.
4
3
Reꢁerence mode conꢁiguration.
2
1
Reꢁerence mode conꢁiguration.
Unipolar/bipolar mode register conꢁiguration ꢁor diꢁꢁerential mode.
Unipolar/bipolar mode register conꢁiguration ꢁor diꢁꢁerential mode.
0 (LSB)
*See below ꢁor bit details.
CKSEL1
CKSEL0
CONVERSION CLOCK
Internal
ACQUISITION/SAMPLING
Internally timed
CNVST CONFIGURATION
CNVST
0
0
1
1
0
1
0
1
Internal
Externally timed through CNVST
Internally timed
CNVST
Internal
AIN15/11/7
AIN15/11/7
External (4.8MHz max)
Externally timed through SCLK
REFSEL1 REFSEL0
VOLTAGE REFERENCE
Internal
AutoShutdown
REF- CONFIGURATION
AIN14/10/6
Reꢁerence oꢁꢁ aꢁter scan; need
wake-up delay.
0
0
1
1
0
1
0
1
628/MAX130
External single ended
Internal
Reꢁerence oꢁꢁ; no wake-up delay.
AIN14/10/6
Reꢁerence always on; no wake-up
delay.
AIN14/10/6
External diꢁꢁerential
Reꢁerence oꢁꢁ; no wake-up delay.
REF-
DIFFSEL1 DIFFSEL0
FUNCTION
0
0
1
1
0
1
0
1
No data ꢁollows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
No data ꢁollows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
One byte oꢁ data ꢁollows the setup byte and is written to the unipolar mode register.
One byte oꢁ data ꢁollows the setup byte and is written to the bipolar mode register.
14 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
The reꢁerence voltage used ꢁor the temperature mea-
surements is derived ꢁrom the internal reꢁerence source
to ensure a resolution oꢁ 1/8 oꢁ a degree.
Power-Up Default State
The MAX1026/MAX1028/MAX1030 power up with all
blocks in shutdown% including the reꢁerence. All registers
power up in state 00000000% except ꢁor the setup regis-
ter% which powers up in clock mode 10 (CKSEL1 = 1).
Output Data Format
Figures 4–7 illustrate the conversion timing ꢁor the
MAX1026/MAX1028/MAX1030. The 10-bit conversion
result is output in MSB-ꢁirst ꢁormat with 4 leading zeros
and 2 trailing sub-bits. The 12-bit temperature mea-
surement is output with 4 leading zeros. DIN data is
latched into the serial interꢁace on the rising edge oꢁ
SCLK. Data on DOUT transitions on the ꢁalling edge oꢁ
SCLK. Conversions in clock modes 00 and 01 are initiat-
ed by CNVST. Conversions in clock modes 10 and 11
are initiated by writing an input data byte to the conver-
sion register. Data is binary ꢁor unipolar mode and two’s
complement ꢁor bipolar mode.
Temperature Measurements
The MAX1026/MAX1028/MAX1030 perꢁorm tempera-
ture measurements with an internal diode-connected
transistor. The diode bias current changes ꢁrom 68μA
to 4μA to produce a temperature-dependent bias volt-
age diꢁꢁerence. The second conversion result at 4μA is
subtracted ꢁrom the ꢁirst at 68μA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the above digital
code minus an oꢁꢁset to adjust ꢁrom Kelvin to Celsius.
Table 4. Unipolar Mode Register (Addressed Through Setup Register)
BIT NAME
UCH0/1
BIT
FUNCTION
7 (MSB) Set to 1 to conꢁigure AIN0 and AIN1 ꢁor unipolar diꢁꢁerential conversion.
UCH2/3
6
Set to 1 to conꢁigure AIN2 and AIN3 ꢁor unipolar diꢁꢁerential conversion.
UCH4/5
5
Set to 1 to conꢁigure AIN4 and AIN5 ꢁor unipolar diꢁꢁerential conversion.
UCH6/7
4
Set to 1 to conꢁigure AIN6 and AIN7 ꢁor unipolar diꢁꢁerential conversion.
UCH8/9
3
Set to 1 to conꢁigure AIN8 and AIN9 ꢁor unipolar diꢁꢁerential conversion (MAX1028/MAX1030 only).
Set to 1 to conꢁigure AIN10 and AIN11 ꢁor unipolar diꢁꢁerential conversion (MAX1028/MAX1030 only).
Set to 1 to conꢁigure AIN12 and AIN13 ꢁor unipolar diꢁꢁerential conversion (MAX1030 only).
Set to 1 to conꢁigure AIN14 and AIN15 ꢁor unipolar diꢁꢁerential conversion (MAX1030 only).
UCH10/11
UCH12/13
UCH14/15
2
1
0 (LSB)
Table 5. Bipolar Mode Register (Addressed Through Setup Register)
BIT NAME
BIT
FUNCTION
BCH0/1
7 (MSB) Set to 1 to conꢁigure AIN0 and AIN1 ꢁor bipolar diꢁꢁerential conversion.
BCH2/3
6
Set to 1 to conꢁigure AIN2 and AIN3 ꢁor bipolar diꢁꢁerential conversion.
BCH4/5
5
Set to 1 to conꢁigure AIN4 and AIN5 ꢁor bipolar diꢁꢁerential conversion.
BCH6/7
4
Set to 1 to conꢁigure AIN6 and AIN7 ꢁor bipolar diꢁꢁerential conversion.
BCH8/9
3
Set to 1 to conꢁigure AIN8 and AIN9 ꢁor bipolar diꢁꢁerential conversion (MAX1028/MAX1030 only).
Set to 1 to conꢁigure AIN10 and AIN11 ꢁor bipolar diꢁꢁerential conversion (MAX1028/MAX1030 only).
Set to 1 to conꢁigure AIN12 and AIN13 ꢁor bipolar diꢁꢁerential conversion (MAX1030 only).
Set to 1 to conꢁigure AIN14 and AIN15 ꢁor bipolar diꢁꢁerential conversion (MAX1030 only).
BCH10/11
BCH12/13
BCH14/15
2
1
0 (LSB)
______________________________________________________________________________________ 15
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Table 6. Averaging Register*
BIT NAME
—
BIT
FUNCTION
7 (MSB) Set to zero to select averaging register.
—
6
Set to zero to select averaging register.
Set to 1 to select averaging register.
—
5
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to 1 to turn averaging on. Set to zero to turn averaging oꢁꢁ.
Conꢁigures the number oꢁ conversions ꢁor single-channel scans.
Conꢁigures the number oꢁ conversions ꢁor single-channel scans.
3
2
1
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
0 (LSB)
*See below ꢁor bit details.
AVGON
NAVG1
NAVG0
FUNCTION
Perꢁorms 1 conversion ꢁor each requested result.
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Perꢁorms 4 conversions and returns the average ꢁor each requested result.
Perꢁorms 8 conversions and returns the average ꢁor each requested result.
Perꢁorms 16 conversions and returns the average ꢁor each requested result.
Perꢁorms 32 conversions and returns the average ꢁor each requested result.
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
628/MAX130
Table 7. Reset Register
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to zero to select reset register.
—
6
Set to zero to select reset register.
Set to zero to select reset register.
Set to 1 to select reset register.
—
5
—
4
RESET
3
Set to zero to reset all registers. Set to 1 to clear the FIFO only.
Reserved. Don’t care.
x
x
x
2
1
Reserved. Don’t care.
0 (LSB)
Reserved. Don’t care.
16 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
the internal oscillator. See Figure 5 ꢁor clock mode 01
timing.
Internally Timed Acquisitions and
Conversions Using CNVST
Setting CNVST low begins an acquisition% wakes up the
ADC% and places it in track mode. Hold CNVST low ꢁor
at least 1.4μs to complete the acquisition. Iꢁ the internal
reꢁerence needs to wake up% an additional 65μs is
required ꢁor the internal reꢁerence to power up. Iꢁ a tem-
perature measurement is being requested% reꢁerence
power-up and temperature measurement are internally
timed. In this case% hold CNVST low ꢁor at least 40ns.
Performing Conversions in Clock Mode 00
In clock mode 00% the wake up% acquisition% conversion%
and shutdown sequences are initiated through CNVST
and perꢁormed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 ꢁor clock mode 00 timing.
Initiate a scan by setting CNVST low ꢁor at least 40ns
beꢁore pulling it high again. The MAX1026/MAX1028/
MAX1030 then wake up% scan all requested channels%
store the results in the FIFO% and shut down. Aꢁter the
scan is complete% EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low beꢁore
pulling CS low to communicate with the serial interꢁace.
EOC stays low until CS or CNVST is pulled low again. A
temperature measurement result% iꢁ requested% pre-
cedes all other FIFO results.
Set CNVST high to begin a conversion. Aꢁter the con-
version is complete% the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low beꢁore pulling CS or
CNVST low.
Iꢁ averaging is turned on% multiple CNVST pulses need
to be perꢁormed beꢁore a result is written to the FIFO.
Once the proper number oꢁ conversions has been per-
ꢁormed to generate an averaged FIFO result% as speci-
ꢁied by the averaging register% the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. Iꢁ a temperature measure-
ment is programmed% it is perꢁormed aꢁter the ꢁirst rising
edge oꢁ CNVST ꢁollowing the input data byte written to
the conversion register. The result is available on DOUT
once EOC has been pulled low.
Do not initiate a second CNVST beꢁore EOC goes low;
otherwise% the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01% conversions are requested one at a
time using CNVST and perꢁormed automatically using
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
LSB1
MSB2
MSB1
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. X = DON'T CARE.
Figure 4. Clock Mode 00
______________________________________________________________________________________ 17
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
CNVST
(CONVERSION2)
(ACQUISITION1)
(ACQUISITION2)
CS
(CONVERSION1)
SCLK
DOUT
EOC
LSB1
MSB1
MSB2
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. X = DON'T CARE.
Figure 5. Clock Mode 01
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DIN
CS
SCLK
628/MAX130
DOUT
EOC
MSB1
LSB1
MSB2
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. X = DON'T CARE.
Figure 6. Clock Mode 10
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX1026/MAX1028/MAX1030 then power up%
scan all requested channels% store the results in the
FIFO% and shut down. Aꢁter the scan is complete% EOC
is pulled low and the results are available in the FIFO. Iꢁ
a temperature measurement is requested% the tempera-
ture result precedes all other FIFO results. EOC stays
low until CS is pulled low again.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10% the wake-up% acquisition% conversion%
and shutdown sequences are initiated by writing an
input data byte to the conversion register% and are per-
ꢁormed automatically using the internal oscillator. This
is the deꢁault clock mode upon power-up. See Figure 6
ꢁor clock mode 10 timing.
18 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
(CONVERSION BYTE)
DIN
(ACQUISITION2)
(ACQUISITION1)
(CONVERSION1)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. X = DON'T CARE.
Figure 7. Clock Mode 11
is uncorrupted and can be read out normally aꢁter tak-
ing CS low again% as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values% starting at
the MSB up to the point that the partial write is stopped.
The part oꢁ the register that is not written contains previ-
ously written values. Iꢁ CS is pulled low beꢁore EOC
goes low% a conversion cannot be completed and the
FIFO is corrupted.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11% acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
ꢁormed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled% and the
conversion result is available at DOUT during the con-
version. See Figure 7 ꢁor clock mode 11 timing.
Transfer Function
Figure 8 shows the unipolar transꢁer ꢁunction ꢁor single-
ended or diꢁꢁerential inputs. Figure 9 shows the bipolar
transꢁer ꢁunction ꢁor diꢁꢁerential inputs. Code transitions
occur halꢁway between successive-integer LSB values.
Initiate a conversion by writing a byte to the conversion
register ꢁollowed by 16 SCLK cycles. Iꢁ CS is pulsed
high between the eighth and ninth cycles% the pulse
width must be less than 100μs. To continuously convert
at 16 cycles per conversion% alternate 1 byte oꢁ zeros
between each conversion byte.
Output coding is binary% with 1 LSB = V
/ 1024V ꢁor
REF
unipolar and bipolar operation% and 1 LSB = 0.125°C
ꢁor temperature measurements.
Iꢁ reꢁerence mode 00 is requested% or iꢁ an external reꢁer-
ence is selected but a temperature measurement is
being requested% wait 65μs with CS high aꢁter writing the
conversion byte to extend the acquisition and allow the
internal reꢁerence to power up. To perꢁorm a temperature
measurement% write 24 bytes (192 cycles) oꢁ zeros aꢁter
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes oꢁ the 192 cycles.
Layout, Grounding, and Bypassing
For best perꢁormance% use PC boards. Do not use wire-
wrap boards. For the TQFN package% connect its
exposed pad to GND. Board layout should ensure that
digital and analog signal lines are separated ꢁrom each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
neath the MAX1026/MAX1028/MAX1030 package. High-
Partial Reads and Partial Writes
Iꢁ the ꢁirst byte oꢁ an entry in the FIFO is partially read
(CS is pulled high aꢁter ꢁewer than eight SCLK cycles)%
the second byte oꢁ data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost ꢁor
that entry. Iꢁ the ꢁirst byte oꢁ an entry in the FIFO is read
out ꢁully% but the second byte is read out partially% the
rest oꢁ the entry is lost. The remaining data in the FIFO
ꢁrequency noise in the V
power supply can aꢁꢁect
DD
perꢁormance. Bypass the V
supply with a 0.1μF
DD
capacitor to GND% close to the V
pin. Minimize
DD
capacitor lead lengths ꢁor best supply-noise rejection. Iꢁ
the power supply is very noisy% connect a 10Ω resistor in
series with the supply to improve power-supply ꢁiltering.
______________________________________________________________________________________ 19
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
OUTPUT CODE
OUTPUT CODE
V
REF
2
FS
+ V
COM
=
FULL-SCALE
TRANSITION
011 . . . 111
011 . . . 110
11 . . . 111
11 . . . 110
ZS = COM
-V
2
REF
-FS =
11 . . . 101
000 . . . 010
000 . . . 001
000 . . . 000
V
1024
REF
1 LSB =
FS = V + V
REF
COM
111 . . . 111
111 . . . 110
111 . . . 101
ZS = V
COM
V
REF
1 LSB =
1024
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
COM*
0
- FS
+FS - 1 LSB
1
2
3
FS
(COM)
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
*V
COM
≥ V / 2
REF
Figure 8. Unipolar Transꢁer Function% Full Scale (FS) = V
Figure 9. Bipolar Transꢁer Function% Full Scale ( FS) =
V
REF
/ 2
REF
zation error (residual error). The ideal% theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly ꢁrom the ADC’s resolution
(N bits):
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation oꢁ the values
on an actual transꢁer ꢁunction ꢁrom a straight line. This
straight line can be either a best-straight-line ꢁit or a line
drawn between the end points oꢁ the transꢁer ꢁunction%
once oꢁꢁset and gain errors have been nulliꢁied. INL ꢁor
the MAX1026/MAX1028/MAX1030 is measured using
the end-point method.
628/MAX130
SNR = (6.02 x N + 1.76)dB
In reality% there are other noise sources besides quanti-
zation noise% including thermal noise% reꢁerence noise%
clock jitter% etc. Thereꢁore% SNR is calculated by taking
the ratio oꢁ the RMS signal to the RMS noise% which
includes all spectral components minus the ꢁundamen-
tal% the ꢁirst ꢁive harmonics% and the DC oꢁꢁset.
Differential Nonlinearity
Diꢁꢁerential nonlinearity (DNL) is the diꢁꢁerence between
an actual step width and the ideal value oꢁ 1 LSB. A
DNL error speciꢁication oꢁ less than 1 LSB guarantees
no missing codes and a monotonic transꢁer ꢁunction.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio oꢁ the
ꢁundamental input ꢁrequency’s RMS amplitude to the
RMS equivalent oꢁ all other ADC output signals:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
SINAD (dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
the time between the samples.
Effective Number of Bits
Eꢁꢁective number oꢁ bits (ENOB) indicates the global
accuracy oꢁ an ADC at a speciꢁic input ꢁrequency and
sampling rate. An ideal ADC error consists oꢁ quantiza-
tion noise only. With an input range equal to the ꢁull-
scale range oꢁ the ADC% calculate the eꢁꢁective number
oꢁ bits as ꢁollows:
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge oꢁ the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveꢁorm perꢁectly reconstructed ꢁrom digital
samples% signal-to-noise ratio (SNR) is the ratio oꢁ the
ꢁull-scale analog input (RMS value) to the RMS quanti-
ENOB = (SINAD - 1.76) / 6.02
20 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
628/MAX130
Pin Configurations (continued)
TOP VIEW
+
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
24 EOC
23 DOUT
21 20 19 18 17 16 15
22 DIN
14
13
DIN 22
DOUT 23
CNVST/AIN15
REF-/AIN14
21 CS
MAX1030
20 SCLK
12 AIN13
24
25
26
27
28
EOC
N.C.
AIN0
AIN1
AIN2
19
V
DD
AIN12
AIN11
AIN10
AIN9
11
10
9
MAX1030
18 GND
17 REF+
16 CNVST/AIN15
15 REF-/AIN14
14 AIN13
+
8
AIN9 10
AIN10 11
AIN11 12
1
2
3
4
5
6
7
13 AIN12
TQFN
QSOP
Total Harmonic Distortion
Ordering Information (continued)
Total harmonic distortion (THD) is the ratio oꢁ the RMS
sum oꢁ the ꢁirst ꢁive harmonics oꢁ the input signal to the
ꢁundamental itselꢁ. This is expressed as:
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
MAX1030BCEG+T
MAX1030BEEG+T
MAX1030BCTI+T
MAX1030BETI+T
24 QSOP
⎛
⎞
⎠
2
2
2
2
28 TQFN-EP*
28 TQFN-EP*
THD = 20 x log
V
+ V3 + V4 + V5 / V
⎜
⎝
⎟
(
)
2
1
*EP = Exposed paddle (connect to GND).
where V1 is the ꢁundamental amplitude% and V2–V5 are
the amplitudes oꢁ the ꢁirst ꢁive harmonics.
Package Information
For the latest package outline inꢁormation and land patterns%
go to www.maxim-ic.com/packages. Note that a “+”% “#”% or
“-” in the package code indicates RoHS status only. Package
drawings may show a diꢁꢁerent suꢁꢁix character% but the drawing
pertains to the package regardless oꢁ RoHS status.
Spurious-Free Dynamic Range
Spurious-ꢁree dynamic range (SFDR) is the ratio oꢁ the
RMS amplitude oꢁ the ꢁundamental (maximum signal
component) to the RMS value oꢁ the next-largest distor-
tion component.
LAND
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
Chip Information
PATTERN NO.
PROCESS: BiCMOS
90-0167
90-0168
90-0172
90-0026
16 QSOP
E16+1
21-0055
21-0055
21-0055
21-0140
20 QSOP
E20+1
24 QSOP
E24+1
28 TQFN-EP
T2855+6
______________________________________________________________________________________ 21
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
Removed the Grade A devices ꢁrom the Ordering Information table and Electrical
Characteristics table.
3
11/09
1% 3% 21
Revised Ordering Information% Electrical Characteristics% Timing Characteristics%
Typical Operating Characteristics% Pin Description% Package Information.
4
4/11
1–5% 7% 8% 21
628/MAX130
Maxim cannot assume responsibility ꢁor use oꢁ any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and speciꢁications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark oꢁ Maxim Integrated Products% Inc.
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