MAX1069_技术文档

19-2652; Rev 0; 10/02

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

General Description

Features

The MAX1069 is a low-power, 14-bit successive-

approximation analog-to-digital converter (ADC). The

device features automatic power-down, an on-chip

4MHz clock, a +4.096V internal reference, and an

I²C™-compatible 2-wire serial interface capable of both

fast and high-speed modes.

o High-Speed I²C-Compatible Serial Interface

400kHz Fast Mode

1.7MHz High-Speed Mode

o +4.75V to +5.25V Single Supply

o +2.7V to +5.5V Adjustable Logic Level

o Internal +4.096V Reference

The MAX1069 operates from a single supply and con-

sumes 5mW at the maximum conversion rate of

58.6ksps. AutoShutdown™ powers down the device

between conversions, reducing supply current to less

than 50µA at a 1ksps throughput rate. The option of a

separate digital supply voltage allows direct interfacing

with +2.7V to +5.5V digital logic.

o External Reference: 1V to AV

DD

o Internal 4MHz Conversion Clock

o 58.6ksps Sampling Rate

o AutoShutdown Between Conversions

The MAX1069 performs a unipolar conversion on its

single analog input using its internal 4MHz clock. The

full-scale analog input range is determined by the inter-

nal reference or by an externally applied reference volt-

o Low Power

5.0mW at 58.6ksps

4.2mW at 50ksps

2.0mW at 10ksps

0.23mW at 1ksps

3µW in Shutdown

age ranging from 1V to AV

.

DD

The four address select inputs (ADD0–ADD3) allow up

to sixteen MAX1069 devices on the same bus.

The MAX1069 is packaged in a 14-pin TSSOP and

offers both commercial and extended temperature

ranges. Refer to the MAX1169 for a 16-bit device in a

pin-compatible package.

o Small 14-Pin TSSOP Package

Ordering Information

Applications

Hand-Held Portable Applications

Medical Instruments

PIN-

PACKAGE

INL

(LSB)

PART

TEMP RANGE

MAX1069ACUD

MAX1069BCUD

MAX1069CCUD

0°C to +70°C

14 TSSOP

1

2

3

1

2

3

Battery-Powered Test Equipment

Solar-Powered Remote Systems

Receive Signal Strength Indicators

System Supervision

MAX1069AEUD* -40°C to +85°C

MAX1069BEUD* -40°C to +85°C

MAX1069CEUD* -40°C to +85°C

*Future product—contact factory for availability.

Pin Configuration

TOP VIEW

DGND

SCL

1

2

3

4

5

6

7

14 ADD3

13 REF

SDA

12 REFADJ

2

I C is a trademark of Philips Corp.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

ADD2

ADD1

ADD0

11 AGNDS

10 AIN

MAX1069

9

8

AGND

AV

DV

DD

TSSOP

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

ABSOLUTE MAXIMUM RATINGS

AV to AGND .........................................................-0.3V to +6V

Continuous Power Dissipation (T = +70°C)

DD

A

DV to DGND.........................................................-0.3V to +6V

AGND to DGND.....................................................-0.3V to +0.3V

AGNDS to AGND...................................................-0.3V to +0.3V

14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW

Operating Temperature Ranges:

MAX1069_CUD ..................................................0°C to +70°C

MAX1069_EUD................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

DD

AIN, REF, REFADJ to AGND....................-0.3V to (AV

+ 0.3V)

DD

SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V

Maximum Current into Any Pin............................................50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV = +4.75V to +5.25V, DV = +2.7V to +5.5V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external ref-

DD

SCL

SAMPLE

REF

erence applied to REF, REFADJ = AV , C

= 10µF, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD REF

A

MIN

PARAMETER

DC ACCURACY (Note 1)

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

14

MAX1069A

MAX1069B

MAX1069C

1

2

3

1

5

Relative Accuracy

(Note 2)

INL

LSB

MAX1069A, no missing codes

MAX1069B, no missing codes

MAX1069C, no missing codes

Differential Nonlinearity

Offset Error

DNL

LSB

2

mV

Offset-Error Temperature

Coefficient

1.0

ppm/°C

Gain Error

(Note 3)

0.25

0.1

0.5

-86

%FSR

Gain Temperature Coefficient

DYNAMIC PERFORMANCE (f

Signal-to-Noise Plus Distortion

Total Harmonic Distortion

Spurious-Free Dynamic Range

Signal-to-Noise Ratio

ppm/°C

= 1kHz, V = V

, f

= 58.6ksps)

IN(sine wave)

IN

REF(P-P) SAMPLE

SINAD

THD

81

84

-99

102

84

4

dB

Up to the 5th harmonic

SFDR

SNR

87

82

dB

Full-Power Bandwidth

FPBW

-3dB point

MHz

kHz

Full-Linear Bandwidth

SINAD > 81dB

20

CONVERSION RATE (Figure 11)

Fast mode

7.1

5.8

7.5

6

Conversion Time

(SCL Stretched Low)

t

µs

CONV

High-speed mode

Fast mode

19

Throughput Rate (Note 4)

f

ksps

SAMPLE

High-speed mode

58.6

Internal Clock Frequency

f

4

MHz

ns

CLK

Track/Hold Acquisition Time

t

(Note 5)

1100

ACQ

2

_______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

ELECTRICAL CHARACTERISTICS (continued)

(AV = +4.75V to +5.25V, DV = +2.7V to +5.5V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external ref-

DD

SCL

SAMPLE

REF

erence applied to REF, REFADJ = AV , C

= 10µF, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD REF

A

MIN

PARAMETER

Aperture Delay

SYMBOL

CONDITIONS

MIN

TYP

50

MAX

UNITS

Fast mode

t

ns

AD

(Figure 11c) (Note 6)

High-speed mode

Fast mode

30

100

Aperture Jitter

(Figure 11c)

t

ps

AJ

High-speed mode

ANALOG INPUT (AIN)

Input Voltage Range

V

0

V

AIN

REF

10

On/off-leakage current, V

= 0V or AV

,

DD

AIN

Input Leakage Current

0.01

35

µA

pF

no clock, f

= 0

SCL

Input Capacitance

C

IN

INTERNAL REFERENCE (Bypass REFADJ with 0.1µF to AGND and REF with 10µF to AGND)

REF Output Voltage

V

4.056

4.096

20

4.136

V

REF

T

= 0°C to +70°C

A

Reference Temperature

Coefficient

TC

ppm/°C

REF

REFSC

= -40°C to +85°C

35

Reference Short-Circuit Current

REFADJ Output Voltage

REFADJ Input Range

I

10

4.136

4.000

mA

V

4.056

4.096

60

For small adjustments, from 4.096V

mV

EXTERNAL REFERENCE (REFADJ = AV

)

DD

Pull REFADJ high to disable the internal

bandgap reference and reference buffer

REFADJ Buffer Disable Voltage

AV

- 0.1

V

DD

REFADJ Buffer Enable Voltage

Reference Input Voltage Range

AV - 0.4

V

DD

(Note 7)

1.0

AV

DD

V

f

= +4.096V, V = V

IN

REF

REF(P-P)

27

= 1kHz, f

= 62.1ksps

REF Input Current

I

µA

IN(sine wave)

SAMPLE

REF

V

= +4.096V, shutdown

0.1

REF

DIGITAL INPUTS/OUTPUTS (SCL, SDA)

Input High Voltage

Input Low Voltage

Input Hysteresis

Input Current

V

0.7 × DV

V

IH

DD

V

0.3 × DV

DD

IL

V

0.1 × DV

V

HYST

DD

I

10

µA

pF

V

IN

Input Capacitance

Output Low Voltage

C

15

IN

V

I

= 3mA

0.4

OL

SINK

ADDRESS SELECT INPUTS (ADD3, ADD2, ADD1, ADD0)

Input High Voltage

Input Low Voltage

Input Hysteresis

Input Current

0.7 × DV

V

DD

0.3 × DV

DD

0.1 × DV

V

DD

10

µA

pF

Input Capacitance

15

_______________________________________________________________________________________

3

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

ELECTRICAL CHARACTERISTICS (continued)

(AV = +4.75V to +5.25V, DV = +2.7V to +5.5V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external ref-

DD

SCL

SAMPLE

REF

erence applied to REF, REFADJ = AV , C

= 10µF, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD REF

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS (AV , AGND, DV , DGND)

DD

Analog Supply Voltage

Digital Supply Voltage

AV

DV

4.75

2.7

5.25

5.5

V

DD

f

= 58.6ksps

= 10ksps

= 1ksps

1.8

0.7

40

2.5

SAMPLE

Internal reference

(powered down

between conversions,

R/W = 0)

mA

µA

Shutdown

0.4

1.8

1.4

1.1

0.4

0.90

0.36

40

5.0

2.5

f

= 58.6ksps

= 10ksps

= 1ksps

SAMPLE

mA

Internal reference

(always on, R/W = 1)

Analog Supply Current

I

AVDD

mA

µA

Shutdown

5

f

= 58.6ksps

= 10ksps

= 1ksps

1.8

SAMPLE

mA

µA

External reference

(REFADJ = AV

)

DD

Shutdown

0.4

260

65

5

f

= 58.6ksps

= 10ksps

= 1ksps

400

SAMPLE

Digital Supply Current

I

µA

DVDD

6

Shutdown

AV = 5V 5%, full-scale input (Note 8)

0.2

2

5

6

Power-Supply Rejection Ratio

PSRR

LSB/V

DD

TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)

Serial Clock Frequency

f

400

kHz

µs

SCL

Bus Free Time Between a STOP

and a START Condition

t

1.3

BUF

Hold Time for Start Condition

Low Period of the SCL Clock

High Period of the SCL Clock

t

0.6

1.3

0.6

µs

HD,STA

t

LOW

t

HIGH

Setup Time for a Repeated

START Condition (Sr)

0.6

µs

SU,STA

Data Hold Time

Data Setup Time

t

(Note 9)

0

900

ns

HD,DAT

t

100

SU,DAT

Rise Time of Both SDA and SCL

Signals, Receiving

20 +

t

(Note 10)

300

ns

R

0.1C

B

20 +

Fall Time of SDA Transmitting

t

F

0.1C

B

Setup Time for STOP Condition

Capacitive Load for Each Bus Line

Pulse Width of Spike Suppressed

t

0.6

µs

pF

ns

SU,STO

C

400

50

B

t

SP

4

_______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

ELECTRICAL CHARACTERISTICS (continued)

(AV = +4.75V to +5.25V, DV = +2.7V to +5.5V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external ref-

DD

SCL

SAMPLE

REF

erence applied to REF, REFADJ = AV , C

= 10µF, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD REF

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)

Serial Clock Frequency

f

(Note 11)

1.7

MHz

ns

SCLH

Hold Time, (Repeated) Start

Condition

t

160

HD,STA

Low Period of the SCL Clock

High Period of the SCL Clock

t

320

120

ns

LOW

t

HIGH

Setup Time for a Repeated

START Condition

t

160

ns

SU,STA

Data Hold Time

Data Setup Time

t

(Note 9)

0

150

ns

HD,DAT

t

10

SU,DAT

Rise Time of SCL Signal

(Current Source Enabled)

t

(Note 10)

10

20

80

ns

RCL

Rise Time of SCL Signal After

Acknowledge Bit

t

160

RCL1

Fall Time of SCL Signal

t

(Note 10)

20

80

ns

pF

ns

FCL

Rise Time of SDA Signal

t

160

RDA

Fall Time of SDA Signal

t

20

FDA

Setup Time for STOP Condition

Capacitive Load for Each Bus Line

Pulse Width of Spike Suppressed

t

160

SU,STO

C

400

10

B

t

SP

Note 1: DC accuracy is tested at AV

= +5.0V and DV

= +3.0V. Performance at power-supply tolerance limits is guaranteed

DD

by power-supply rejection test.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: Offset nullified.

Note 4: One sample is achieved every 18 clocks in continuous conversion mode.

-1





18 clocks

f

=

+ t

CONV

SAMPLE





f





SCL

Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11.





1

t

= 2 ×

ACQ





f





SCL

Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and

50ns in fast mode.

Note 7: ADC performance is limited by the converter’s noise floor, typically 480µV

.

P-P

Note 8:

N

2

V

(5.25V)- V (4.75V) ×

[

]

FS

V

REF

PSRR =

where N is the number of bits (14).

5.25V - 4.75V

_______________________________________________________________________________________

5

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

ELECTRICAL CHARACTERISTICS (continued)

(AV = +4.75V to +5.25V, DV = +2.7V to +5.5V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external ref-

DD

SCL

SAMPLE

REF

erence applied to REF, REFADJ = AV , C

= 10µF, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD REF

A

MIN

Note 9: A master device must provide a data hold time for SDA (referred to V of SCL) in order to bridge the undefined region of

IL

SCL’s falling edge (see Figure 1).

Note 10: C = total capacitance of one bus line in pF. t and t measured between 0.3 ✕ DV

and 0.7 ✕ DV

.

B

R

F

DD

Note 11: f

must meet the minimum clock low time plus the rise/fall times.

SCL

2

A. F/S-MODE I C SERIAL INTERFACE TIMING

t

R

F

SDA

t

BUF

t

HD,DAT

SU,DAT

t

HD,STA

t

SU,STA

t

LOW

SU,STO

SCL

t

HIGH

t

HD,STA

t

F

R

S

Sr

A

P

S

2

B. HS-MODE I C SERIAL INTERFACE TIMING

t

FDA

RDA

SDA

t

BUF

t

HD,DAT

HD,STA

SU,DAT

t

SU,STO

SU,STA

t

LOW

SCL

t

HIGH

t

HD,STA

t

FCL

t

RCL

RCL1

P

S

Sr

A

S

F/S-MODE

HS-MODE

PARAMETERS ARE MEASURED FROM 30% TO 70%.

Figure 1. I²C Serial Interface Timing

V

DD

I

= 3mA

OL

DIGITAL

I/O

V

OUT

400pF

I

= 0mA

OH

Figure 2. Load Circuit

6

_______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Typical Operating Characteristics

(DV

= +3.0V, AV

= +5.0V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V = +4.096V, external reference applied to

REF

DD

SCL

SAMPLE

REF, REFADJ = AV , C

= 10µF, T = +25°C, unless otherwise noted.)

DD REF

A

ANALOG SUPPLY CURRENT vs. ANALOG

SUPPLY VOLTAGE (EXTERNAL REFERENCE)

ANALOG SHUTDOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

700

ANALOG SUPPLY CURRENT vs. ANALOG

SUPPLY VOLTAGE (INTERNAL REFERENCE)

830

820

810

800

790

780

770

760

1.75

1.73

1.71

1.69

1.67

1.65

1.63

DV = 3V

DD

DV = 3V

DD

DV = 3V

DD

f

= 0

SAMPLE

R/W = 0

600

500

400

300

T

= +85°C

= +70°C

= +25°C

= 0°C

T

= +85°C

= +70°C

= +25°C

= 0°C

A

T

= +85°C

= +70°C

= +25°C

= 0°C

A

200

100

0

A

= -40°C

4.75

4.85

4.95

5.05

5.15

5.25

4.75

4.85

4.95

5.05

5.15

5.25

4.75

4.85

4.95

5.05

5.15

5.25

AV (V)

DD

AV (V)

DD

AV (V)

DD

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

DIGITAL SHUTDOWN CURRENT

vs. DIGITAL SUPPLY VOLTAGE

280

260

240

220

200

180

160

140

120

100

350

AV = 5V

DD

SAMPLE

R/W = 0

f

= 0

300

250

T

= -40°C

A

T

= +85°C

A

T

= 0°C

A

200

150

T

= +25°C

A

T

= +70°C

A

T

= -40°C

A

100

50

0

T

= +85°C

A

2.7 3.1 3.5

3.9 4.3 4.7 5.1

5.5

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

DV (V)

DD

DV (V)

DD

GAIN ERROR

vs. TEMPERATURE

OFFSET ERROR

vs. TEMPERATURE

0.008

0.006

0.004

0.002

0

800

600

400

200

0

-0.002

-0.004

-0.006

-0.008

-200

-400

-600

-800

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

_______________________________________________________________________________________

7

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Typical Operating Characteristics (continued)

(DV

= +3.0V, AV

= +5.0V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external reference applied to

DD

SCL

SAMPLE

REF

REF, REFADJ = AV , C

= 10µF, T = +25°C, unless otherwise noted.)

DD REF

A

SUPPLY CURRENT vs. CONVERSION RATE

(HIGH-SPEED MODE, EXTERNAL REFERENCE)

SUPPLY CURRENT vs. CONVERSION RATE

(HIGH-SPEED MODE, INTERNAL REFERENCE)

900

2000

EXTERNAL REFERENCE, f = 1.7MHz

INTERNAL REFERENCE, f = 1.7MHz

SCL

1800

1600

1400

1200

1000

800

700

600

500

400

300

200

100

0

I

, R/W = 1

AVDD

I

, R/W = 1 OR 0

AVDD

I

, R/W = 0

AVDD

600

I

, R/W = 1 OR 0

DVDD

I

, R/W = 1 OR 0

DVDD

400

200

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

CONVERSION RATE (ksps)

SUPPLY CURRENT vs. CONVERSION RATE

(FAST MODE, EXTERNAL REFERENCE)

SUPPLY CURRENT vs. CONVERSION RATE

(FAST MODE, INTERNAL REFERENCE)

600

1800

1600

1400

1200

1000

800

600

400

200

0

EXTERNAL REFERENCE, f = 400kHz

SCL

INTERNAL REFERENCE, f = 400kHz

SCL

500

400

300

200

100

0

I

, R/W = 1

AVDD

I

, R/W = 1 OR 0

AVDD

I

, R/W = 0

AVDD

I

, R/W = 1 OR 0

DVDD

I

, R/W = 1 OR 0

15

DVDD

0

5

10

15

20

25

0

5

10

20

25

CONVERSION RATE (ksps)

8

_______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Typical Operating Characteristics (continued)

(DV

= +3.0V, AV

= +5.0V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V

= +4.096V, external reference applied to

DD

SCL

SAMPLE

REF

REF, REFADJ = AV , C

= 10µF, T = +25°C, unless otherwise noted.)

DD REF

A

INTERNAL +4.096V REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs. REF LOAD

4.100

4.095

4.090

4.085

4.080

4.075

4.20

4.15

4.10

4.05

4.00

3.95

3.90

f

= 0

DV = 3V

DD

SCL

INTERNAL REFERENCE MODE

LOAD APPLIED TO REF

T

= +85°C

A

T

= +70°C

= +25°C

A

T

= 0°C

A

T

= -40°C

A

4.75

4.85

4.95

5.05

5.15

5.25

0

1

2

3

4

5

6

AV (V)

DD

I

(mA)

REF

EXTERNAL REFERENCE CURRENT AND

EXTERNAL REFERENCE CURRENT

vs. EXTERNAL REFERENCE VOLTAGE

REFERENCE VOLTAGE vs. V

REFADJ

MAX1069 toc15

35

30

25

20

15

10

5

30

20

4.25

4.20

4.15

4.10

4.05

4.00

3.95

AIN = AGNDS

58.6ksps

= 1.7MHz

10

I

REFADJ

f

SCL

0

19ksps

= 400kHz

f

SCL

-10

-20

-30

V

REF

0

1

2

3

4

5

6

3.95 4.00 4.05 4.10 4.15 4.20 4.25

(V)

V

(V)

V

REF

REFADJ

_______________________________________________________________________________________

9

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Typical Operating Characteristics (continued)

(DV

= +3.0V, AV

= +5.0V, f

= 1.7MHz (33% duty cycle), f

= 58.6ksps, V = +4.096V, external reference applied to

REF

DD

SCL

SAMPLE

REF, REFADJ = AV , C

= 10µF, T = +25°C, unless otherwise noted.)

DD REF

A

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

SIGNAL-TO-NOISE RATIO

vs. FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE

vs. FREQUENCY

1.0

120

110

120

110

0.8

0.6

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

0

4096

8192

12288

16384

1

10

100

1

10

100

DIGITAL OUTPUT CODE

FREQUENCY (kHz)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

TOTAL HARMONIC DISTORTION

vs. FREQUENCY

SINAD vs. FREQUENCY

0

-10

1.0

0.8

120

110

-20

-30

100

90

80

70

60

50

40

30

20

10

0

0.6

0.4

-40

0.2

-50

-60

0

-70

-0.2

-0.4

-0.6

-0.8

-1.0

-80

-90

-100

-110

-120

1

10

100

1

10

100

0

4096

8192

12288

16384

FREQUENCY (kHz)

DIGITAL OUTPUT CODE

FREQUENCY (kHz)

FFT

0

f

= 58.6ksps

SAMPLE

f

= 1kHz

IN(SINE WAVE)

-20

-40

V

= V

IN

REF(P-P)

-60

-80

-100

-120

-140

0

5.86

11.72

17.56

23.44

29.30

FREQUENCY (kHz)

10 ______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Pin Description

1

NAME

DGND

SCL

FUNCTION

Digital Ground

2

Clock Input

3

SDA

Data Input/Output

4

ADD2

ADD1

ADD0

Address Select Input 2

5

Address Select Input 1

6

Address Select Input 0

7

DV

AV

Digital Power Input. Bypass to DGND with a 0.1µF capacitor.

Analog Power Input. Bypass to AGND with a 0.1µF capacitor.

Analog Ground

DD

8

9

AGND

AIN

10

11

Analog Input

AGNDS

Analog Signal Ground. Negative reference for analog input. Connect to AGND.

Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1µF capacitor.

12

REFADJ

Connect REFADJ to AV

to disable the internal bandgap reference and reference-buffer amplifier.

DD

Reference Buffer Output and External Reference Input. Bypass to AGND with a 10µF capacitor

when using the internal reference.

13

14

REF

ADD3

Address Select Input 3

from +2.7V to +5.5V to ensure compatibility with low-

Detailed Description

voltage ASICs. The MAX1069 wakes up in shutdown

The MAX1069 analog-to-digital converter (ADC) uses

successive-approximation conversion (SAR) tech-

niques and on-chip track-and-hold (T/H) circuitry to

capture and convert an analog signal to a serial 14-bit

digital output.

mode when power is applied irrespective of the AV

DD

and DV

sequence.

DD

Analog Input and Track/Hold

The MAX1069 analog input contains a track-and-hold

(T/H) capacitor, T/H switches, comparator, and a

switched capacitor digital-to-analog converter (DAC)

(Figure 5).

The MAX1069 performs a unipolar conversion on its

single analog input using its internal 4MHz clock. The

full-scale analog input range is determined by the inter-

nal reference or by an externally applied reference volt-

As shown in Figure 11c, the MAX1069 acquisition peri-

od is the two clock cycles prior to the conversion peri-

od. The T/H switches are normally in the hold position.

During the acquisition period the T/H switches are in

age ranging from 1V to AV

.

DD

The flexible 2-wire serial interface provides easy con-

nection to microcontrollers (µCs) and supports data

rates up to 1.7MHz. Figure 3 shows the simplified func-

tional diagram for the MAX1069 and Figure 4 shows the

typical application circuit.

the track position and C

charges to the analog input

T/H

signal. Before a conversion begins, the T/H switches

move to the hold position retaining the charge on C

as a sample of the analog input signal.

T/H

Power Supply

To maintain a low-noise environment, the MAX1069

provides separate analog and digital power-supply

inputs. The analog circuitry requires a +5V supply and

consumes only 900µA at sampling rates up to

58.6ksps. The digital supply voltage accepts voltages

During the conversion interval, the switched capacitive

DAC adjusts to restore the comparator input voltage to

zero within the limits of 14-bit resolution. This is equiva-

lent to transferring a charge of 35pF × (V

- V

)

AGNDS

AIN

from C

to the binary-weighted capacitive DAC,

T/H

______________________________________________________________________________________ 11

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

6

5

ADD0

ADD1

ADD2

ADD3

SDA

4

CONTROL

LOGIC

14

3

2

SCL

8

9

7

1

4MHz

INTERNAL

OSCILLATOR

AV

DV

DD

DGND

AGND

CLOCK

10

11

AIN

OUTPUT SHIFT

REGISTER

SAR

OUT

ADC

T/H

IN

A

AGNDS

REF

= 1.0

V

5kΩ

+4.096V

REFERENCE

MAX1069

12

13

REFADJ

REF

Figure 3. MAX1069 Simplified Functional Diagram

5.0V

8

µC

3.0V

MAX1069

AV

7

DD

DV

V

DD

6

5

4

0.1µF

ADD0

ADD1

0.1µF

R

P

R

P

13

12

ADD2

REF

3

2

10µF

SDA

SCL

SDA

SCL

REFADJ

0.1µF

10

11

ANALOG

SOURCE

AIN

14

AGNDS

ADD3

V

SS

AGND DGND

9

1

2

I C ADDRESS IS 0110111

Figure 4. Typical Application Circuit

forming a digital representation of the analog input sig-

nal. During the conversion period, the MAX1069 holds

SCL low (clock stretching).

acquisition time by reducing f

. The MAX1069 pro-

SCL

vides two SCL cycles (t

), in which the track-and-

ACQ

hold capacitance must acquire a charge representing

the input signal. Minimize the input source impedance

The time required for the T/H to acquire an input signal

is a function of the analog input source impedance. If

the input signal source impedance is high, lengthen the

(R

) to allow the track-and-hold capacitance to

SOURCE

charge within the allotted time. R

should be

SOURCE

less than 12.9kΩ for f

= 400kHz and less than 2.4kΩ

SCL

12 ______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

for f

= 1.7MHz. R

is calculated with the fol-

Internal Clock

The MAX1069 contains an internal 4MHz oscillator that

drives the SAR conversion clock. During conversion, SCL

is held low (clock stretching). An internal register stores

data when the conversion is in progress. When the

MAX1069 releases SCL, the master reads the conversion

results at any clock rate up to 1.7MHz (Figure 11).

SCL

SOURCE

lowing equation:

2

R

≤

− R

IN

SOURCE

N

( )

× In 2×2 ×C

IN

f

SCL

where R

is the analog input source impedance,

SOURCE

f

is the maximum system SCL frequency, N is 14

SCL

Digital Interface

The MAX1069 features an I²C-compatible, 2-wire serial

interface consisting of a bidirectional serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the

MAX1069 and the master at rates up to 1.7MHz. The

master (typically a microcontroller) initiates data trans-

fer on the bus and generates SCL.

(the number of bits of resolution), C is 35pF (the sum

IN

of C

and input stray capacitance), and R is 800Ω

T/H

IN

(the T/H switch resistances).

To improve the input-signal bandwidth under AC

conditions, drive AIN with a wideband buffer

(>4MHz) that can drive the ADC’s input capacitance

and settle quickly (see the Input Buffer section).

SDA and SCL require pullup resistors (500Ω or greater,

Figure 4). Optional resistors (24Ω) in series with SDA

and SCL protect the device inputs from high-voltage

spikes on the bus lines. Series resistors also minimize

crosstalk and undershoot of the bus signals.

An RC filter at AIN reduces the input track-and-hold

switching transient by providing charge for C

.

T/H

Analog Input Bandwidth

The MAX1069 features input-tracking circuitry with a

4MHz small-signal bandwidth. The 4MHz input band-

width makes it possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. Use anti-alias filtering to avoid

high-frequency signals being aliased into the frequency

band of interest.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. Nine clock cycles are required to transfer the

data into or out of the MAX1069. The data on SDA must

remain stable during the high period of the SCL clock

pulse as changes in SDA while SCL is high are control

signals (see the START and STOP Conditions section).

Both SDA and SCL idle high.

Analog Input Range and Protection

Internal ESD (electrostatic discharge) protection diodes

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), a high-to-low transition on SDA with SCL high.

The master terminates a transmission with a STOP con-

dition (P), a low-to-high transition on SDA while SCL is

high (Figure 7). The STOP condition frees the bus and

places all devices in F/S mode (see the Bus Timing

section). Use a repeated START condition (Sr) in place

clamp AIN, REF, and REFADJ to AV

and

DD

AGNDS/AGND (Figure 6). These diodes allow the ana-

log inputs to swing from (AGND - 0.3V) to (AV

+

DD

0.3V) without causing damage to the device. For accu-

rate conversions, the inputs must not go more than

50mV beyond their rails.

If the analog inputs exceed 300mV beyond their

rails, limit the current to 2mA.

HOLD

AV

REF

DD

*R

SOURCE

AIN

C

T/H

MAX1069

CAPACITIVE

DAC

AIN

REF

TRACK

MAX1069

ANALOG

SIGNAL

SOURCE

AGNDS

REFADJ

AGNDS

AGND

*MINIMIZE R

TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (C ) TO

T/H

SOURCE

CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (t ).

ACQ

Figure 6. Internal Protection Diodes

Figure 5. Equivalent Input Circuit

______________________________________________________________________________________ 13

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

S

Sr

P

SDA

SCL

Figure 7. START and STOP Conditions

S

NOT ACKNOWLEDGE

SDA

ACKNOWLEDGE

8

1

2

9

SCL

Figure 8. Acknowledge Bits

of a STOP condition to leave the bus active and in its

first three bits (MSBs) of the slave address have been

current timing mode (see the HS-Mode section).

factory programmed and are always 011. Connecting

ADD3–ADD0 to DV

or DGND, programs the last four

DD

Acknowledge Bits

Successful data transfers are acknowledged with an

acknowledge bit (A) or a not-acknowledge bit (A). Both

the master and the MAX1069 (slave) generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low during the high period of the clock pulse

(Figure 8). To generate a not acknowledge, the receiver

allows SDA to be pulled high before the rising edge of

the acknowledge-related clock pulse and leaves it high

during the high period of the clock pulse.

bits (LSBs) of the slave address high or low.

Since the MAX1069 does not require setup or configu-

ration, the least significant bit (LSB) of the address byte

(R/W) controls power-down. In external reference mode

(REFADJ = AV ), R/W is a don’t care. In internal refer-

DD

ence mode, setting R/W = 1 places the device in nor-

mal operation and setting R/W = 0 powers down the

internal reference following the conversion (see the

Internal Reference Shutdown section).

After receiving the address, the MAX1069 (slave)

issues an acknowledge by pulling SDA low for one

clock cycle.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the master should reattempt com-

munication at a later time.

Bus Timing

At power-up, the MAX1069 bus timing defaults to fast

mode (F/S-mode), allowing conversion rates up to

19ksps. The MAX1069 must operate in high-speed

mode (HS-mode) to achieve conversion rates up to

58.6ksps. Figure 1 shows the bus timing for the

MAX1069 2-wire interface.

Slave Address

A master initiates communication with a slave device by

issuing a START condition followed by a slave address

byte. As shown in Figure 9, the slave address byte con-

sists of 7 address bits and a read/write bit (R/W). When

idle, the MAX1069 continuously waits for a START con-

dition followed by its slave address. When the

MAX1069 recognizes its slave address, it acquires the

analog input signal and prepares for conversion. The

HS-Mode

At power-up, the MAX1069 bus timing is set for F/S-

mode. The master selects HS-mode by addressing all

devices on the bus with the HS-mode master code 0000

1XXX (X = don’t care). After successfully receiving the

HS-mode master code, the MAX1069 issues a not

acknowledge allowing SDA to be pulled high for one

14 ______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

S

ADD3

4

ADD2

5

ADD1

6

ADD0

7

R/W

0

1

A

9

SDA

SCL

ACKNOWLEDGE

8

1

2

3

Figure 9. MAX1069 Slave Address Byte

S

Sr

0

1

0

2

0

3

0

4

1

5

X

6

X

7

X

8

A

SDA

9

HS-MODE

F/S-MODE

Figure 10. F/S-Mode to HS-Mode Transfer

clock cycle (Figure 10). After the not acknowledge, the

MAX1069 is in HS-mode. The master must then send a

repeated START followed by a slave address to initiate

HS-mode communication. If the master generates a

STOP condition, the MAX1069 returns to F/S-mode.

Applications Information

Power-On Reset

When power is first applied, internal power-on reset cir-

cuitry activates the MAX1069 in shutdown. When the

internal reference is used, allow 12ms for the reference

Data Byte (Read Cycle)

Initiate a read cycle to begin a conversion. A read

cycle begins with the master issuing a START condition

followed by seven address bits and a read bit (R/W).

The standard I²C-compatible interface requires that

R/W = 1 to read from a device, however, since the

MAX1069 does not require setup or configuration, the

read mode is inherent and R/W controls power-down

(see the Internal Reference Shutdown section). If the

address byte is successfully received, the MAX1069

(slave) issues an acknowledge and begins conversion.

to settle when C

= 10µF and C

= 0.1µF.

REF

REFADJ

Automatic Shutdown

The MAX1069 automatic shutdown reduces the supply

current to less than 0.6µA between conversions. The

MAX1069 I²C-compatible interface is always active.

When the MAX1069 receives a valid slave address the

device powers up. The device is then powered down

again when the conversion is complete. The automatic

shutdown function does not change with internal or

external reference. When the internal reference is cho-

sen, the internal reference remains active between con-

versions unless internal reference shutdown is requested

(see the Internal Reference Shutdown section).

As seen in Figure 11, the MAX1069 holds SCL low dur-

ing conversion. When the conversion is complete, SCL

is released and the master can clock data out of the

device. The most significant byte of the conversion is

available first and contains D13 to D6. The least signifi-

cant byte contains D5 to D0 plus two trailing sub bits

S1 and S0. Data can be continuously converted as long

as the master acknowledges the conversion results.

Issuing a not acknowledge frees the bus allowing the

master to generate a STOP or repeated START.

Internal Reference Shutdown

The R/W bit of the slave address controls the MAX1069

internal reference shutdown. In external reference

mode (REFADJ = AV ), R/W is a don’t care. In internal

DD

reference mode, setting R/W = 1 places the device in

normal operation and setting R/W = 0 prepares the

internal reference for shutdown.

______________________________________________________________________________________ 15

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

MASTER TO SLAVE

SLAVE TO MASTER

A. SINGLE CONVERSION

NUMBER OF BITS

1

7

1

8

1

8

1

CLOCK STRETCH

S

SLAVE ADDRESS

R

A

RESULT

A

RESULT

A

P OR Sr

(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)

t

CONV

ACQ

B. CONTINUOUS CONVERSIONS

NUMBER OF BITS

8

1

8

1

8

1

7

1

CLOCK STRETCH

RESULT #1

A

RESULT #1

A

RESULT #2

A

CLOCK STRETCH

S

SLAVE ADDRESS

R

A

(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)

(MOST SIGNIFICANT BYTE)

t

CONV

ACQ

CONV

ACQ

NUMBER OF BITS

8

1

8

1

8

1

CLOCK STRETCH

RESULT #N

A

RESULT #N

A

P OR Sr

RESULT #2

A

(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)

(LEAST SIGNIFICANT BYTE)

t

CONV

ACQ

C. ACQUISITION DETAIL

SDA

BIT3

5

BIT2

6

BIT1

7

BIT0

A

D13

1

D12

2

D11

3

D10

4

SCL

8

9

CLOCK STRETCH

t

AJ

t

AD

t

ACQ

CONV

ANALOG INPUT

TRACK AND HOLD

HOLD

TRACK

HOLD

Figure 11. Read Cycle

valid address byte. Allow 12ms for the internal refer-

ence to settle before obtaining valid conversion results.

If the internal reference is used and R/W = 0, shutdown

occurs when the master issues a not-acknowledge bit

while reading the conversion results. The internal refer-

ence and internal reference buffer are disabled during

shutdown, reducing the analog supply current to less

than 1µA.

Reference Voltage

The MAX1069 provides an internal or accepts an exter-

nal reference voltage. The ADC input range is from

V

to V

(see the Transfer Function section).

REF

AGNDS

A dummy conversion is required to power up the inter-

nal reference. The MAX1069 internal reference begins

powering up from shutdown on the 9th falling edge of a

16 ______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Internal Reference

The MAX1069 contains an internal 4.096V bandgap ref-

erence. This bandgap reference is connected to

REFADJ through a 5kΩ resistor. Bypass REFADJ with a

0.1µF capacitor to AGND. The MAX1069 reference

buffer has a unity gain to provide +4.096V at REF.

Bypass REF with a 10µF capacitor to AGND when the

internal reference is used (Figure 12).

4.096V

= 1.0

REF 13

SAR

ADC

REF

10µF

A

V

REFADJ

12

MAX1069

The internal reference is adjustable to 1.5% using the

Figure 13 circuit.

0.1µF

5kΩ

4.096V

External Reference

BANDGAP

REFERENCE

For external reference operation, disable the internal

reference by connecting REFADJ to AV . During con-

DD

DGND

1

AGND

9

version, an external reference at REF must deliver up to

100µA of DC load current and have an output imped-

ance of less than 10Ω.

For optimal performance, buffer the reference through

an op amp and bypass REF with a 10µF capacitor.

Consider the MAX1069’s equivalent input noise

Figure 12. Internal Reference

(80µV

) when choosing a reference.

RMS

LSB values. Figure 14 shows the MAX1069 input/output

(I/O) transfer function.

Transfer Function

The MAX1069 has a standard unipolar transfer function

with a valid analog input voltage range from V to

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multi-

plexed, the input channel should be switched immedi-

ately after acquisition, rather than near the end of or

AGNDS

V

. Output data coding is binary with 1LSB =

REF

(V

/2^N) where ‘N’ is the number of bits (14). Code

REF

transitions occur halfway between successive-integer

5.0V

8

AV

DD

MAX1069

0.1µF

4.096V

= 1.0

REF 13

SAR

REF

ADC

10µF

A

V

68kΩ

REFADJ

12

100kΩ

POTENTIOMETER

0.1µF

5kΩ

4.096V

150kΩ

BANDGAP

REFERENCE

DGND

1

AGND

9

Figure 13. Adjusting the Internal Reference

______________________________________________________________________________________ 17

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

grounds to the star analog ground. Connect the digital

V

REF

grounds to the star digital ground. Connect the digital

ground plane to the analog ground plane at one point.

For lowest-noise operation, make the ground return to

the star ground’s power-supply low impedance and

make it as short as possible.

1LSB =

16384

V

REF

1...111

1...110

1...101

1...100

High-frequency noise in the AV

power supply

DD

degrades the ADC’s high-speed comparator perfor-

mance. Bypass AV to AGND with a 0.1µF ceramic

DD

surface-mount capacitor. Make bypass capacitor con-

nections as short as possible. If the power supply is

very noisy, connect a 10Ω resistor in series with AV

DD

0...011

0...010

0...001

0...000

and a 4.7µF capacitor from AV

lowpass RC filter.

to AGND to create a

DD

0

1

2

3

16381 16383

Definitions

INPUT VOLTAGE (LSB)

AGNDS

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function

once offset and gain errors have been nullified. The

MAX1069 INL is measured using the endpoint method.

Figure 14. Unipolar Transfer Function

after a conversion. This allows more time for the input

buffer amplifier to respond to a large step-change in

input signal. The input amplifier must have a high

enough slew rate to complete the required output volt-

age change before the beginning of the acquisition

time. At the beginning of acquisition, the internal sam-

pling capacitor array connects to AIN (the amplifier out-

put), causing some output disturbance.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

Ensure that the sampled voltage has settled to within

the required limits before the end of the acquisition

time. If the frequency of interest is low, AIN can be

bypassed with a large enough capacitor to charge the

internal sampling capacitor with very little ripple.

However, for AC use, AIN must be driven by a wide-

band buffer (at least 4MHz), which must be stable with

the ADC’s capacitive load (in parallel with any AIN

bypass capacitor used) and also settle quickly. Refer to

Maxim’s website at www.maxim-ic.com for application

notes on how to choose the optimum buffer amplifier for

your ADC application.

Aperture Jitter

Aperture jitter (t ) is the sample-to-sample variation in

AJ

the time between the samples (Figure 11).

Aperture Delay

Aperture delay (t ) is the time from the falling edge of

AD

SCL to the instant when an actual sample is taken

(Figure 11).

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam-

ples, signal-to-noise ratio (SNR) is the ratio of full-scale

analog input (RMS value) to the RMS quantization error

(residual error). The ideal, theoretical minimum analog-

to-digital noise is caused by quantization error only and

results directly from the ADC’s resolution (N bits):

Layout, Grounding, and Bypassing

Careful printed circuit (PC) layout is essential for the

best system performance. Boards should have sepa-

rate analog and digital ground planes and ensure that

digital and analog signals are separated from each

other. Do not run analog and digital (especially clock)

lines parallel to one another, or digital lines underneath

the device package.

SNR = ((6.02 ✕ N) + 1.76)dB

In reality, noise sources besides quantization noise

exist, including thermal noise, reference noise, clock jit-

ter, etc. Therefore, SNR is computed by taking the ratio

of the RMS signal to the RMS noise, which includes all

spectral components minus the fundamental, the first

five harmonics, and the DC offset.

Figure 4 shows the recommended system ground con-

nections. Establish an analog ground point at AGND

and a digital ground point at DGND. Connect all analog

18 ______________________________________________________________________________________

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Signal-to-Noise Plus Distortion

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion

component.

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to RMS

equivalent of all other ADC output signals.





Signal

Noise

RMS

=

SINAD(db) 20 × log









RMS

Chip Information

TRANSISTOR COUNT: 18,269

PROCESS: BiCMOS

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the

ADC’s full-scale range, calculate the ENOB as follows:

SINAD - 1.76

6.02





=

ENOB









Total Harmonic Distortion

Total harmonic distortion (THD) is the RMS sum ratio of

the input signal’s first five harmonics to the fundamental

itself, expressed as:













2

V

+ V + V + V

3 4 5

2

=

THD 20 × log

V

1

where V₁is the fundamental amplitude, and V₂through

V₅are the amplitudes of the 2nd- through 5th-order

harmonics.

______________________________________________________________________________________ 19

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1069
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	58.6ksps, 14-Bit, 2-Wire Serial ADC 58.6ksps ， 14位， 2线串行ADC
文件：	总20页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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