MAX1071CTC+ [MAXIM]
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| 型号： | MAX1071CTC+ |
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MAXIM INTEGRATED PRODUCTS |
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19-3292; Rev 1; 4/09
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
General Description
Features
The MAX1070/MAX1071 low-power, high-speed, serial-
output, 10-bit, analog-to-digital converters (ADCs) oper-
ate at up to 1.5Msps. These devices feature true-differen-
tial inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over single-
ended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
o 1.5Msps Sampling Rate
o Only 18mW (typ) Power Dissipation
o Only 1µA (max) Shutdown Current
o High-Speed, SPI-Compatible, 3-Wire Serial Interface
o 61dB S/(N + D) at 525kHz Input Frequency
o Internal True-Differential Track/Hold (T/H)
o External Reference
The MAX1070/MAX1071 operate from a single +2.7V to
+3.6V supply voltage and require an external reference.
The MAX1070 has a unipolar analog input, while the
MAX1071 has a bipolar analog input. These devices fea-
ture a partial power-down mode and a full power-down
mode for use between conversions, which lower the sup-
ply current to 1mA (typ) and 1µA (max), respectively. Also
o No Pipeline Delays
o Small 12-Pin TQFN Package
featured is a separate power-supply input (V ), which
L
allows direct interfacing to +1.8V to V
digital logic. The
DD
fast conversion speed, low-power dissipation, excellent
AC performance, and DC accuracy ( 0.5 LSꢀ IꢁL) make
the MAX1070/MAX1071 ideal for industrial process con-
trol, motor control, and base-station applications.
The MAX1070/MAX1071 come in a 12-pin TQFꢁ pack-
age, and are available in the extended (-40°C to +85°C)
temperature range.
Ordering Information
Applications
PIN-
PACKAGE
PART
TEMP RANGE
INPUT
Data Acquisition
ꢀill Validation
MAX1070ETC+T
MAX1071ETC+T
-40°C to +85°C 12 TQFꢁ
-40°C to +85°C 12 TQFꢁ
Unipolar
ꢀipolar
Motor Control
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Communications
Portable Instruments
Typical Operating Circuit
Pin Configuration
TOP VIEW
AIN+
12
N.C.
11
SCLK
10
+1.8V TO V
DD
+2.7V TO +3.6V
0.01μF
0.01μF
10μF
10μF
AIN-
REF
1
2
3
9
8
7
CNVST
DOUT
V
V
L
DD
DIFFERENTIAL
INPUT
+
-
DOUT
AIN+
AIN-
MAX1070
MAX1071
VOLTAGE
μC/DSP
RGND
V
L
MAX1070
MAX1071
CNVST
SCLK
REF
4.7μF
REF
4
5
6
0.01μF
V
N.C.
GND
RGND
GND
DD
TQFN
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of ꢁational Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GꢁD..............................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
V to GꢁD ................-0.3V to the lower of (V
Digital Inputs
to GꢁD .................-0.3V to the lower of (V
Digital Output
to GꢁD....................-0.3V to the lower of (V + 0.3V) and +6V
Analog Inputs and
REF to GꢁD..........-0.3V to the lower of (V
+ 0.3V) and +6V
Continuous Power Dissipation (T = +70°C)
12-Pin TQFꢁ (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Range
MAX107_ ETC.................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
L
DD
A
+ 0.3V) and +6V
DD
L
+ 0.3V) and +6V
DD
RGꢁD to GꢁD .......................................................-0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V, V = V , V
= 2.048V, f
= 24.0MHz, 50% duty cycle, T = -40°C to +85°C, unless otherwise noted.
SCLK A
DD
L
DD REF
Typical values are at V
= 3V and T = +25°C.)
DD
A
/MAX071
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
10
ꢀits
LSꢀ
LSꢀ
LSꢀ
Relative Accuracy
Differential ꢁonlinearity
Offset Error
IꢁL
(ꢁote 1)
(ꢁote 2)
0.5
0.5
2
DꢁL
Offset-Error Temperature
Coefficient
1
2
ppm/°C
Gain Error
Offset nulled
2
LSꢀ
Gain Temperature Coefficient
DYNAMIC SPECIFICATIONS (f = 525kHz sine wave, V = V , unless otherwise noted.)
REF
ppm/°C
IN
IN
SIꢁAD
THD
60
61
-80
-80
-78
15
2
dꢀ
dꢀ
Signal-to-ꢁoise Plus Distortion
Total Harmonic Distortion
Up to the 5th harmonic
-74
-74
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power ꢀandwidth
SFDR
IMD
dꢀ
f
= 250kHz, f
= 300kHz
Iꢁ2
dꢀ
Iꢁ1
-3dꢀ point
MHz
MHz
Full-Linear ꢀandwidth
S/(ꢁ + D) > 56dꢀ, single ended
CONVERSION RATE
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
t
(ꢁote 3)
0.667
µs
Msps
ksps
ns
COꢁV
1.5
10
(ꢁote 4)
(ꢁote 5)
Track-and-Hold Acquisition Time
Aperture Delay
t
125
5
ACQ
ns
Aperture Jitter
(ꢁote 6)
(ꢁote 7)
30
ps
External Clock Frequency
f
24.0
MHz
SCLK
2
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V, V = V , V
= 2.048V, f
= 24.0MHz, 50% duty cycle, T = -40°C to +85°C, unless otherwise noted.
SCLK A
DD
L
DD REF
Typical values are at V
= 3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-)
AIꢁ+ - AIꢁ-, MAX1070
AIꢁ+ - AIꢁ-, MAX1071
0
V
REF
Differential Input Voltage Range
V
V
Iꢁ
-V
/ 2
+V
/ 2
REF
REF
Absolute Input Voltage Range
DC Leakage Current
0
V
V
DD
1
µA
pF
µA
Input Capacitance
Per input pin
16
50
Input Current (Average)
REFERENCE INPUT (REF)
Time averaged at maximum throughput rate
V
+
DD
REF Input Voltage Range
V
1.0
V
REF
50mV
Input Capacitance
20
pF
µA
µA
DC Leakage Current
1
Input Current (Average)
DIGITAL INPUTS (SCLK, CNVST)
Input-Voltage Low
Time averaged at maximum throughput rate
200
VIL
0.3 x V
10
V
V
L
Input-Voltage High
VIH
0.7 x V
L
Input Leakage Current
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
Output-Voltage Low
I
0.05
0.2
µA
IL
C
For stated timing performance
30
pF
V
OUT
V
I
I
= 5mA, V ≥ 1.8V
0.4
OL
OH
OL
SIꢁK
L
Output-Voltage High
V
= 1mA, V ≥ 1.8V
V - 0.5V
L
V
SOURCE
L
Output Leakage Current
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
I
Output high impedance
10
µA
V
I
2.7
1.8
3.6
V
V
DD
V
V
L
DD
7
5
4
Static, f
= 24.0
SCLK
Analog Supply Current,
ꢁormal Mode
mA
Static, no SCLK
5
8
DD
Operational, 1.5Msps
6
f
= 24.0MHz
1
Analog Supply Current,
Partial Power-Down Mode
SCLK
I
I
mA
µA
DD
ꢁo SCLK
= 24.0MHz
1
f
1
Analog Supply Current,
Full Power-Down Mode
SCLK
DD
ꢁo SCLK
1
1
0.3
0.3
0.15
Operational, full-scale input at 1.5Msps
Static, f
= 24.0MHz
0.5
SCLK
mA
Digital Supply Current (ꢁote 8)
Positive-Supply Rejection
Partial/full power-down mode,
= 24.0MHz
0.1
0.3
f
SCLK
Static, no SCLK (all modes)
1
0.1
0.2
µA
PSR
Full-scale input, 3V +20%, -10%
3.0
mV
_______________________________________________________________________________________
3
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
TIMING CHARACTERISTICS
(V
= +2.7V to +3.6V, V = V , V
= 2.048V, f = 24.0MHz, 50% duty cycle, T = -40°C to +85°C, unless otherwise noted.
SCLK A
DD
L
DD REF
Typical values are at V
= 3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V = 2.7V to V
18.7
L
DD
SCLK Pulse-Width High
t
ns
CH
V = 1.8V to V , minimum recommended
(ꢁote 7)
L
DD
22.5
V = 2.7V to V
18.7
L
DD
SCLK Pulse-Width Low
t
ns
ns
CL
V = 1.8V to V , minimum recommended
(ꢁote 7)
L
DD
22.5
C = 30pF, V = 2.7V to V
17
24
L
L
DD
SCLK Rise to DOUT Transition
t
DOUT
C = 30pF, V = 1.8V to V
L
L
DD
DOUT Remains Valid After SCLK
CꢁVST Fall to SCLK Fall
t
V = 1.8V to V
4
ns
ns
DHOLD
L
DD
DD
DD
t
V = 1.8V to V
L
10
20
SETUP
CꢁVST Pulse Width
t
V = 1.8V to V
L
ns
CSW
/MAX071
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
t
2
ms
PWR-UP
t
16
Cycles
RCV
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: ꢁo missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CꢁST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SIꢁAD performance.
Note 7: 1.5Msps operation guaranteed for V > 2.7V. See the Typical Operating Characteristics section for recommended sampling
L
speeds for V < 2.7V.
L
Note 8: Digital supply current is measured with the V level equal to V , and the V level equal to GꢁD.
IH
L
IL
V
L
CNVST
SCLK
t
CSW
6kΩ
t
CL
t
SETUP
t
CH
DOUT
DOUT
6kΩ
C
L
C
L
t
DHOLD
t
DOUT
DOUT
GND
b) HIGH-Z TO V , V TO V ,
OL
GND
a) HIGH-Z TO V , V TO V
,
OH OL
OH
OL OH
AND V TO HIGH-Z
OH
AND V TO HIGH-Z
OL
Figure 1. Detailed Serial-Interface Timing
Figure 2. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
Typical Operating Characteristics
(V
DD
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = -40°C to +85°C, unless otherwise noted. Typical val-
L
DD REF
SCLK
SAMPLE A
ues are at T = +25°C.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1070)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1071)
MAXIMUM RECOMMENDED f
vs. V
L
SCLK
25
23
21
19
17
0.2
0.1
0
0.2
0.1
0
-0.1
-0.2
-0.1
-0.2
1.8
2.1
2.4
2.7
3.0
3.3
3.6
0
256
512
768
1024
-512
-256
0
256
512
V (V)
L
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1070)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1071)
OFFSET ERROR
vs. TEMPERATURE (MAX1070)
0.2
0.1
0
0.2
0.1
0
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.1
-0.2
-0.1
-0.2
0
256
512
768
1024
-512
-256
0
256
512
-40
-15
10
35
60
85
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE (MAX1070)
GAIN ERROR
vs. TEMPERATURE (MAX1071)
OFFSET ERROR
vs. TEMPERATURE (MAX1071)
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Typical Operating Characteristics (continued)
(V
DD
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = -40°C to +85°C, unless otherwise noted. Typical val-
L
DD REF
SCLK
SAMPLE A
ues are at T = +25°C.)
A
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1071)
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1070)
THD vs. INPUT FREQUENCY
-82
-84
-86
-88
-90
-92
61.5
61.4
61.3
61.2
61.1
61.0
61.5
61.4
61.3
61.2
61.1
61.0
MAX1070
SNR
SNR
MAX1071
SINAD
SINAD
100
200
300
400
500
100
200
300
400
500
100
200
300
400
500
/MAX071
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
SFDR vs. INPUT FREQUENCY
FFT PLOT (MAX1070)
FFT PLOT (MAX1071)
90
88
86
84
82
80
0
-20
0
-20
f
= 500kHz
f = 500kHz
IN
IN
SINAD = 61.2dB
SNR = 61.2dB
THD = -83.5dB
SFDR = 83.8dB
SINAD = 61.3dB
SNR = 61.3dB
THD = -90dB
-40
-40
SFDR = 85.4dB
MAX1070
MAX1071
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
100
200
300
400
500
0
125
250
375
500
625
750
0
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
TWO-TONE IMD PLOT (MAX1071)
TWO-TONE IMD PLOT (MAX1070)
0
0
-20
-50
-60
f
f
= 250.102kHz
= 299.966kHz
f
f
= 250.102kHz
= 299.966kHz
IN1
IN2
IN1
IN2
-20
-40
IMD = -83.4dB
IMD = -86.6dB
-40
f
= 500kHz
IN
f
f
IN1
IN2
f
IN2
f
IN1
-70
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-140
f
= 100kHz
IN
-90
-100
0
125
250
375
500
625
750
0
125
250
375
500
625
750
10
100
SOURCE IMPEDANCE (Ω)
1000
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
6
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
Typical Operating Characteristics (continued)
(V
DD
= +3V, V = V , V
= 2.048V, f
= 24MHz, f
= 1.5Msps, T = -40°C to +85°C, unless otherwise noted. Typical val-
L
DD REF
SCLK
SAMPLE A
ues are at T = +25°C.)
A
V PARTIAL/FULL POWER-DOWN
L
V
DD
/V FULL POWER-DOWN
L
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
V
DD
SUPPLY CURRENT vs. TEMPERATURE
100
75
50
25
0
9
6
3
0
1.0
0.8
0.6
0.4
0.2
0
CONVERSION
V = 3V, f
= 24MHz
SCLK
V
, f
= 24MHz
L
DD SCLK
V = 1.8V, f
L
= 24MHz
SCLK
PARTIAL POWER-DOWN
V , NO SCLK
L
V
, NO SCLK
60
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V SUPPLY CURRENT
vs. CONVERSION RATE
L
V
SUPPLY CURRENT
DD
V SUPPLY CURRENT vs. TEMPERATURE
L
vs. CONVERSION RATE
250
200
150
100
50
0.5
0.4
0.3
0.2
0.1
0
9
6
3
0
CONVERSION, V = 3V
L
V = 3V
L
CONVERSION, V = 1.8V
L
V = 1.8V
L
0
0
250
500
750
100 1250 1500
-40
-15
10
35
60
85
0
250
500
750 1000 1250 1500
(kHz)
f
(kHz)
TEMPERATURE (°C)
SAMPLE
f
SAMPLE
_______________________________________________________________________________________
7
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
1
AIꢁ-
ꢁegative Analog Input
External Reference Voltage Input. V
capacitor and a 4.7µF capacitor to RGꢁD.
sets the analog input range. ꢀypass REF with a 0.01µF
REF
2
3
4
REF
RGꢁD
Reference Ground. Connect RGꢁD to GꢁD.
Positive Analog Supply Voltage (+2.7V to 3.6V). ꢀypass V
capacitor to GꢁD.
with a 0.01µF capacitor and a 10µF
DD
V
DD
5, 11
6
ꢁ.C.
ꢁo Connection
GꢁD
Ground. GꢁD is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V ). ꢀypass V with a 0.01µF capacitor and a 10µF capacitor
to GꢁD.
DD
L
7
8
9
V
L
DOUT
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CꢁVST high prepares the part for a conversion. Conversion begins on the
falling edge of CꢁVST. The sampling instant is defined by the falling edge of CꢁVST.
CꢁVST
/MAX071
10
12
—
SCLK
AIꢁ+
EP
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GꢁD.
time needed for the signal to be acquired. It is calculated
by the following equation:
Detailed Description
The MAX1070/MAX1071 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 10-bit output. The
serial interface requires only three digital lines (SCLK,
CꢁVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1070/MAX1071.
t
≥ 8 x (RS + R ) x 16pF
Iꢁ
ACQ
where R = 200Ω, and RS is the source impedance of
the input signal.
Iꢁ
Note: t
is never less than 125ns, and any source
ACQ
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1070/MAX1071, which is composed of
a T/H, a comparator, and a switched-capacitor digital-to-
analog converter (DAC). The T/H enters its tracking mode
on the 14th SCLK rising edge of the previous conversion.
Upon power-up, the T/H enters its tracking mode immedi-
ately. The positive input capacitor is connected to AIꢁ+.
The negative input capacitor is connected to AIꢁ-. The
T/H enters its hold mode on the falling edge of CꢁVST
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to V
and GꢁD allow the analog input pins to swing
DD
from GꢁD - 0.3V to V
+ 0.3V without damage. ꢀoth
DD
inputs must not exceed V
accurate conversions.
or be lower than GꢁD for
DD
lengthens. The acquisition time, t
, is the minimum
ACQ
8
_______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
V
L
V
DD
CAPACITIVE
DAC
C
IN+
R
IN+
REF
AIN+
AIN+
10-BIT
SAR
OUTPUT
BUFFER
T/H
DOUT
CONTROL
LOGIC
V
COMP
AZ
ADC
AIN-
AIN-
AIN+
CNVST
SCLK
CONTROL
LOGIC AND
TIMING
R
IN-
C
IN-
ACQUISITION MODE
MAX1070
MAX1071
CAPACITIVE
DAC
C
IN+
R
IN+
RGND
GND
Figure 3. Functional Diagram
CONTROL
LOGIC
V
COMP
AZ
Serial Interface
Initialization After Power-Up
and Starting a Conversion
AIN-
R
Upon initial power-up, the MAX1070/MAX1071 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
IN-
C
IN-
HOLD CONVERSION MODE
Figure 4. Equivalent Input Circuit
leading zeros, at least 16 rising clock edges are need-
ed to shift out these bits. For continuous operation, pull
CꢁVST high between the 14th and the 16th SCLK ris-
ing edges. If CꢁVST stays low after the falling edge of
the 16th SCLK cycle, the DOUT line goes to a high-
impedance state on either CꢁVST’s rising edge or the
next SCLK’s rising edge.
To start a conversion, pull CꢁVST low. At CꢁVST’s
falling edge, the T/H enters its hold mode and a con-
version is initiated. SCLK runs the conversion and the
data can then be shifted out serially on DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CꢁVST and SCLK digital inputs. Figures
1 and 5 show timing diagrams, which outline the serial-
interface operation.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by
placing the MAX1070/MAX1071 in either partial power-
down mode or full power-down mode. Partial power-
down mode is ideal for infrequent data sampling and
fast wake-up time applications. Pull CꢁVST high after
the 3rd SCLK rising edge and before the 14th SCLK
rising edge to enter and stay in partial power-down
mode (see Figure 6). This reduces the supply current
to 1mA. Drive CꢁVST low and allow at least 14 SCLK
cycles to elapse before driving CꢁVST high to exit par-
tial power-down mode.
A CꢁVST falling edge initiates a conversion sequence:
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance
to logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the con-
version is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t
after each
DOUT
SCLK’s rising edge and remains valid 4ns (t
)
DHOLD
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1070/MAX1071 have to be in partial power-down
mode in order to enter full power-down mode. Perform the
SCLK/CꢁVST sequence described above to enter partial
after the next rising edge. The 4th rising clock edge
produces the MSꢀ of the conversion at DOUT, and the
MSꢀ remains valid 4ns after the 5th rising edge. Since
there are 10 data bits, 2 sub-bits (S1 and S0), and 3
_______________________________________________________________________________________
9
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
CNVST
t
SETUP
t
POWER-MODE SELECTION WINDOW
8
ACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
1
2
3
4
14
16
SCLK
HIGH IMPEDANCE
DOUT
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
Figure 5. Interface-Timing Sequence
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST
SCLK
ONE 8-BIT TRANSFER
/MAX071
1ST SCLK RISING EDGE
DOUT
MODE
0
0
0
D9
D8
D7
D6
D5
NORMAL
PPD
Figure 6. SPI Interface—Partial Power-Down Mode
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
CNVST
FIRST 8-BIT TRANSFER
SCLK
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
D6 D5
DOUT
0
0
0
D9
D8
D7
0
0
0
0
0
0
0
0
MODE
NORMAL
PPD
RECOVERY
FPD
Figure 7. SPI Interface—Full Power-Down Mode
power-down mode. Then repeat the same sequence to
enter full power-down mode (see Figure 7). Drive CꢁVST
low, and allow at least 14 SCLK cycles to elapse before
driving CꢁVST high to exit full power-down mode. In par-
tial/full power-down mode, maintain a logic low or a logic
high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1070. Figure 9 shows the bipolar transfer function for
the MAX1071. The MAX1070 output is straight binary,
while the MAX1071 output is two’s complement.
10 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
Applications Information
OUTPUT CODE
External Reference
An external reference is required for the MAX1070/
MAX1071. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
FULL-SCALE
TRANSITION
111...111
111...110
111...101
structure allows a voltage range of +1V to V
.
DD
How to Start a Conversion
An analog-to-digital conversion is initiated by CꢁVST
and clocked by SCLK, and the resulting data is clocked
out on DOUT by SCLK. With SCLK idling high or low, a
falling edge on CꢁVST begins a conversion. This causes
the analog input stage to transition from track to hold
mode, and DOUT to transition from high impedance to
being actively driven low. A total of 16 SCLK cycles are
required to complete a normal conversion. If CꢁVST is
low during the 16th falling SCLK edge, DOUT returns to
high impedance on the next rising edge of CꢁVST or
SCLK, enabling the serial interface to be shared by multi-
ple devices. If CꢁVST returns high after the 14th, but
before the 16th SCLK rising edge, DOUT remains active
so continuous conversions can be sustained. The high-
est throughput is achieved when performing continuous
conversions. Figure 10 illustrates a conversion using a
typical serial interface.
FS = V
REF
REF
ZS = 0
V
1 LSB =
1024
000...011
000...010
000...001
000...000
0
1
2
3
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function (MAX1070 Only)
Connection to
Standard Interfaces
OUTPUT CODE
The MAX1070/MAX1071 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
V
FULL-SCALE
TRANSITION
REF
2
FS =
ZS = 0
-V
011...111
011...110
REF
- FS =
2
V
1024
REF
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1070/MAX1071
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CꢁVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
10 bits from the ADC. DOUT transitions on SCLK rising
1 LSB =
000...010
000...001
000...000
111...111
111...110
111...101
edges. DOUT is guaranteed to be valid t
later and
DOUT
remains valid until t
after the following SCLK rising
DHOLD
100...001
100...000
edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1 or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
-FS
0
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
Figure 9. ꢀipolar Transfer Function (MAX1071 Only)
______________________________________________________________________________________ 11
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
0
0
Figure 10. Continuous Conversion with ꢀurst/Continuous Clock
I/O
CNVST
SCLK
SCK
MISO
DOUT
+3V TO +5V
/MAX071
MAX1070
MAX1071
SS
A) SPI
CS
CNVST
SCLK
SCK
MISO
DOUT
+3V TO +5V
MAX1070
MAX1071
SS
B) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1070
MAX1071
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1070/MAX1071
12 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
CNVST
8
9
16
1
SCLK
DOUT
HIGH-Z
HIGH-Z
D9
D6
D5
D4
D3
D2
D1
D0
S1
S0
D8
D7
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
DOUT
14
16
1
1
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
2
16
SCLK
DOUT
HIGH-Z
HIGH-Z
S1
D9
D6
D5
D4
D3
D2
D1
D0
S0
D8
D7
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
QSPI
DSP Interface to the TMS320C54_
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1070/MAX1071 require 16 clock cycles
from the µP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSꢀ-first format.
The MAX1070/MAX1071 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1070/MAX1071 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CꢁVST.
______________________________________________________________________________________ 13
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
V
L
DV
DD
MAX1070
MAX1071
TMS320C54_
V
L
DV
DD
SCLK
CNVST
DOUT
CLKR
FSR
DR
MAX1070
MAX1071
TMS320C54_
SCLK
CNVST
DOUT
CLKX
CLKR
FSX
FSR
DR
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
/MAX071
intervention. Connect the V pin to the TMS320C54_
L
supply voltage when the MAX1070/MAX1071 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
This setup allows continuous conversions provided that
the data-transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
The MAX1070/MAX1071 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CꢁVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CꢁVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
read the data without CPU intervention. Connect the V
L
pin to the TMS320C54_ supply voltage when the
MAX1070/MAX1071 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CꢁVST pin must idle
high to remain in either power-down state.
DSP Interface to the ADSP21_ _ _
The MAX1070/MAX1071 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1070/MAX1071 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1070/MAX1071. For continuous conver-
sions, idle CꢁVST low and pulse it high for one clock
cycle during the LSꢀ of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CꢁVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL
Another method of connecting the MAX1070/MAX1071
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the CLKR
and SCLK and the convert signal (COꢁVERT) drives
the FSR and CꢁVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
14 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
CNVST
SCLK
1
1
S0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
0
0
DOUT
Figure 17. DSP Interface—Continuous Conversion
CNVST
SCLK
DOUT
1
1
0
0
0
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
S1 S0
0
0
0
Figure 18. DSP Interface—Single-Conversion, Continuous/ꢀurst Clock
registers should be configured for late framing (LAFR =
1) and for an active-low frame (LTFS = 1, LRFS = 1) sig-
nal. This is also the best way to enter the power-down
modes by setting the word length to 8 bits (SLEꢁ =
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
1001). Connect the V pin to the ADSP21_ _ _ supply
L
voltage when the MAX1070/MAX1071 are operating with
a supply voltage higher than the DSP supply voltage
(see Figures 17 and 18).
Integral Nonlinearity
Integral nonlinearity (IꢁL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1070/MAX1071 are mea-
sured using the end-points method.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. ꢀoard layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Differential Nonlinearity
Differential nonlinearity (DꢁL) is the difference between
an actual step width and the ideal value of 1 LSꢀ. A DꢁL
error specification of 1 LSꢀ or less guarantees no missing
codes and a monotonic transfer function.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GꢁD, separate from the logic
ground. Connect all other analog grounds and DGꢁD
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of CꢁVST and the instant when an actual
sample is taken.
High-frequency noise in the V
power supply can
DD
affect the ADC’s high-speed comparator. ꢀypass this
______________________________________________________________________________________ 15
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
V
L
VDDINT
TCLK
RCLK
TFS
SUPPLIES
GND
MAX1070
MAX1071
SCLK
CNVST
DOUT
ADSP21_ _ _
V
DD
V
L
10μF
RFS
10μF
DR
0.1μF
0.1μF
Figure 19. Interfacing to the ADSP21_ _ _
V
DD
V
L
GND RGND
DGND
V
L
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SꢁR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The theoretical minimum analog-to-digital
noise is caused by quantization error, and results directly
from the ADC’s resolution (ꢁ bits):
DIGITAL
CIRCUITRY
MAX1070
MAX1071
/MAX071
Figure 20. Power-Supply Grounding Condition
SꢁR = (6.02 x ꢁ + 1.76)dꢀ
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SꢁR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
⎛
⎜
⎞
⎟
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 x log
⎜
⎜
⎝
⎟
⎟
⎠
V
1
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SIꢁAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
harmonics.
5
SIꢁAD(dꢀ) = 20 x log (Signal
/ ꢁoise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (EꢁOꢀ) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the EꢁOꢀ as follows:
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dꢀ for a full-scale input.
(SIꢁAD − 1.76)
EꢁOꢀ =
6.02
16 ______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
/MAX071
The intermodulation products are as follows:
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal-to-noise plus distortion (SIꢁAD) is equal to 56dꢀ.
• 2nd-order intermodulation products (IM2): f + f ,
1
2
f - f
2
1
Intermodulation Distortion
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the ꢁyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dꢀFS.
• 3rd-order intermodulation products (IM3): 2f - f ,
1
2
2f - f , 2f + f , 2f + f
1
2
1
1
2
2
• 4th-order intermodulation products (IM4): 3f - f ,
1
2
3f - f , 3f + f , 3f + f
1
2
1
1
2
2
• 5th-order intermodulation products (IM5): 3f - 2f ,
1
2
3f - 2f , 3f + 2f , 3f + 2f
1
2
1
1
2
2
Package Information
Chip Information
TRAꢁSISTOR COUꢁT: 13,016
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PROCESS: ꢀiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
12 TQFꢁ
T1244+3
21-0139
______________________________________________________________________________________ 17
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
5/04
4/09
Initial release
Removed commercial temperature grade parts from data sheet
—
1–7
/MAX071
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. ꢁo circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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