MAX108EVKIT_技术文档

19-1503; Rev 0; 6/99

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

Ge n e ra l De s c rip t io n

Fe a t u re s

The MAX104/MAX106/MAX108 evaluation kits (EV kits)

are designed to simplify evaluation of the devices’ ana-

log-to-digital converters (ADCs). Each EV kit contains

all circuitry necessary to evaluate the dynamic perfor-

mance of these ultra-high-speed converters, including

the power-supply generation for the PECL termination

♦ 50Ω Clock and Analog Inputs Through SMA

Coaxial Connectors

♦ ±250mV Input Signal Range

♦ Demultiplexed Differential PECL Outputs

♦ On-Board Generation of PECL Termination

voltage (PECLV ). Since the design combines high-

TT

speed analog and digital circuitry, the board layout

calls for special precautions and design features.

Voltage (PECLV

)

TT

♦ On-Board Generation of ECL Termination Voltage

(ECLV

Connectors for the power supplies (V A/V I, V D,

CC

)

TT

V

CC

O, V ), SMA connectors for analog and clock

EE

♦ Separate Analog and Digital Power and Ground

inputs (VIN+, VIN-, CLK+, CLK-), and all digital PECL

outputs simplify connection to the EV kit. The four-layer

board layout (GETek™ material) is optimized for best

dynamic performance of the MAX104 family.

Connections with Optimized Four-Layer PCB

♦ Square-Pin Headers for Easy Connection of Logic

Analyzer to Digital Outputs

The EV kits come with a MAX104/MAX106/MAX108

installed on the board with a heatsink attached for oper-

ation over the full commercial temperature range.

♦ Fully Assembled and Tested

Ord e rin g In fo rm a t io n

TEMP.

RANGE

PIN-

PACKAGE

SAMPLING

RATE

PART

MAX104EVKIT

MAX106EVKIT

0°C to +70°C 192 ESBGA

1Gsps

600Msps

1.5Gsps

MAX108EVKIT* 0°C to +70°C 192 ESBGA

*Future product—contact factory for availability.

Co m p o n e n t Lis t

DESIGNATION QTY

DESCRIPTION

DESIGNATION QTY

DESCRIPTION

R5–R38,

38

C1, C13, C20, C31,

C40, C46, C48

10µF ±10%, 16V tantalum caps

AVX TAJD106D016

49.9Ω ±1% resistors (0603)

7

R44–R47

C2, C7–C12, C14,

C17, C18, C19,

C21, C26–C30,

C32, C41, C47,

C49, C51–C59

R51, R53

R52, R54

2

243Ω ±1% resistors (0603)

158Ω ±1% resistors (0603)

SMA connectors (edge mounted)

3-pin headers

0.01µF ±10% ceramic capacitors

(0603)

30

J1–J10

10

5

JU3, JU6–JU9

C3–C6, C15, C16,

C22–C25,

C33–C37,

C42–C45, C50

47pF ±10% ceramic capacitors

(0402)

20

JU2, JU4, JU5,

JUA0- to JUA7-,

JUA0+ to JUA7+,

JUP0- to JUP7-,

JUP0+ to JUP7+,

JUOR+, JUOR-,

JUDR-, JUDR+,

JURO-, JURO+

D1

R2

1

1N5819 Schottky diode

41

2-pin headers

10kΩ potentiometer

Not populated; see text for descrip-

tion of reset input operation.

R3, R4

2

GETek is trademark of GE Electromaterials.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

3) Connect a +5V power supply capable of providing

Co m p o n e n t Lis t (c o n t in u e d )

250mA to the V D p a d . Conne c t the s up p ly’s

CC

DESIGNATION QTY

DESCRIPTION

ground to the GNDD pad.

None

O, V D,

4

Protective feet

4) Connect a +3.3V or +5V power supply capable of

V

CC

providing approximately 600mA to the V O pad.

CC

GNDD, PECLV

,

TT

Connect the supply’s ground to the GNDD pad.

5) Connect GNDI to GNDD at the power supplies.

GNDA, V A,

I, GNDI, V ,

EE

24

Test points

Shunts

CC

V

CC

ECLV

TT

6) Connect an RF source with low phase jitter, such as

an HP8662A (up to 1.28GHz) or an HP8663A (up to

2.56GHz), to clock inputs CLK- and CLK+. For sin-

g le -e nd e d c loc k inp uts , fe e d a +4d Bm (500mV

amplitude) power level from the signal generator

into the CLK+ input and terminate the unused CLK-

input with 50Ω to GNDI.

None

7

1

Heatsink

International Electronic Research

Corp. BDN09-3CB/A01

None

MAX104CHC, MAX106CHC, or

MAX108CHC (192-contact ESBGA™)

U1

1

7) Connect a ±225mV (approximately -1dB below FS)

sine -wa ve te st signa l to the a na log inputs. Use

VIN+ and VIN- through a balun if the test signal is

differential, or either VIN+ or VIN- if the signal is sin-

gle-ended (see the sections Single-Ended Analog

Inputs and Differential Analog Inputs in the devices’

data sheets). For best results, use a narrow band-

pass filter designed for the frequency of interest to

reduce the harmonic distortion from the signal gen-

erator.

LM2991S, low-dropout adjustable

linear regulator

U3, U4

None

2

1

MAX104EVKIT circuit board

MAX104, MAX106, or MAX108 data

sheet

None

_________________________Qu ic k S t a rt

The EV kit is delivered fully assembled, tested, and

sealed in an antistatic bag. To ensure proper operation,

open the antistatic bag only at a static-safe work area

and follow the instructions below. Do not turn on the

power supplies until all power connections to the

EV kit are established. Figure 1 shows a typical evalu-

ation setup with differential analog inputs and single-

ended sine -wave (CLK- is 50Ω reverse-terminated to

GNDI) clock drive. Figure 2 shows a typical evaluation

setup with single-ended analog inputs (VIN- is 50Ω

reverse-terminated to GNDI) and a single-ended sine-

wave clock drive.

8) Connect a logic analyzer, such as an HP16500C

with an HP16517A plug-in card for monitoring all 16

outp ut c ha nne ls (8 c ha nne ls for p rima ry a nd 8

channels for auxiliary outputs) of the device.

9) Connect the logic analyzer clock to the DREADY+

output on the EV kit, and set the logic analyzer to

trigger on the falling edge of the acquisition clock.

Set the logic analyzer’s threshold voltage to the

V

CC

O supply voltage -1.3V. For example, if V O =

CC

Evluate:46/MAX108

+ 3.3V, the thre s hold volta g e s hould b e s e t to

+2.0V.

1) Connect a -5V power supply capable of providing

10) Turn on the supplies and signal sources. Capture

the digitized outputs from the ADC with the logic

analyzer and transfer the digital record to a PC for

data analysis.

-250mA to the pad marked V . Connect the sup-

EE

ply’s ground to the GNDI pad. Set the current limit

to 500mA or less.

2) Connect a +5V power supply capable of providing

600mA to the V I p a d . Conne c t the s up p ly’s

CC

ground to the GNDI pad.

ESBGA is a trademark of Amkor/Anam.

2

_______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

HP8662/3A

SINE-WAVE SOURCE

BALUN

BPF

PHASE

LOCKED

VIN-

VIN+

+5V ANALOG

f

, + 4dBm

CLK+

CLK-

SAMPLE

HP8662/3A

SINE-WAVE SOURCE

-5V ANALOG

+5V DIGITAL

+3.3V DIGITAL

MAX104

MAX106

MAX108

EV KIT

EXTERNAL 50Ω

TERMINATION TO GNDI

PC

16 DATA

DREADY+

GNDD

GNDI

HP16500C

DATA ANALYSIS

SYSTEM

GPIB

POWER

SUPPLIES

Figure 1. Typical Evaluation Setup with Differential Analog Inputs and Single-Ended Clock Drive

HP8662/3A

SINE-WAVE SOURCE

BPF

EXTERNAL 50Ω

TERMINATION

TO GNDI

PHASE

LOCKED

VIN-

VIN+

+5V ANALOG

f

, + 4dBm

CLK+

SAMPLE

HP8662/3A

SINE-WAVE SOURCE

-5V ANALOG

+5V DIGITAL

MAX104

MAX106

MAX108

EV KIT

EXTERNAL 50Ω

TERMINATION TO GNDI

+3.3V DIGITAL

CLK-

PC

16 DATA

DREADY+

GNDD

GNDI

HP16500C

DATA ANALYSIS

SYSTEM

GPIB

POWER

SUPPLIES

Figure 2. Typical Evaluation Setup with Single-Ended Analog Inputs and Single-Ended Clock Drive

_______________________________________________________________________________________

3

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Single-Ended Clock Inputs

_______________De t a ile d De s c rip t io n

(Sine-Wave Drive)

To obtain the lowest jitter clock drive, AC- or DC-couple

a low-phase-noise sine-wave source into a single clock

input. Clock amplitudes of up to 1V (2Vp-p or +10dBm)

can be accommodated with CLKCOM connected to

GNDI.

Clo c k In p u t Re q u ire m e n t s

The MAX104/MAX106/MAX108 feature clock inputs

designed for either single-ended or differential opera-

tion with very flexible input drive requirements. Each

clock input is terminated with an on-chip, laser-trimmed

50Ω resistor to CLKCOM (clock termination return). The

traces from the SMA inputs to the high-speed data con-

verter are 50Ω microstrip transmission lines.

The d yna mic p e rforma nc e of the d a ta c onve rte r is

essentially unaffected by clock-drive power levels from

-10dBm to +10dBm (100mV to 1V clock signal ampli-

tude). The dynamic performance specifications are

measured with a single-ended clock drive of +4dBm

(500mV clock signal amplitude). To avoid saturation of

the input amplifier stage, limit the clock power level to a

maximum of +10dBm.

The CLKCOM termination voltage may be connected

anywhere between ground and -2V for compatibility

with standard ECL drive levels. The side-launched SMA

connectors for the clock signals are located at the

lower left corner of the EV board and are labeled J3

(CLK+) and J4 (CLK-).

Differential Clock Inputs (ECL Drive)

The MAX104/MAX106/MAX108 clock inputs may also

be driven with standard ground-referenced ECL logic

An on-board bias generator, located between the ana-

log and clock inputs, creates a -2V termination voltage

(ECLV ) for operation with ECL clock sources. The

TT

levels by using the on-board ECLV -2V bias genera-

TT

voltage is generated by an LM2991 voltage regulator

tor as described above. It is also possible to drive the

clock inputs with positive supply referenced (PECL)

levels if the clock inputs are AC-coupled. With AC-cou-

pled clock inputs, the CLKCOM termination voltage

should be grounded. Single-ended DC-coupled ECL

drive is possible as well, if the undriven clock input is

operated from the board’s -5V V power supply. To

EE

enable this ECLV bias generator, first remove short-

TT

ing jumper JU2, then move jumper JU3 into its ON

position.

The volta g e re g ula tor ha s a s hutd own c ontrol tha t

requires a TTL logic-high level to enter the shutdown

state. This logic level is derived from the +5V analog

tied to the ECL V voltage (-1.3V nominal).

BB

An a lo g In p u t Re q u ire m e n t s

s up p ly (V I). The EV kits a re d e live re d with the

CC

The analog inputs to the ADC on the EV board are pro-

vided by two side-launch SMA connectors located on

the middle left side of the EV kit. They are labeled J1

(VIN+) and J2 (VIN-). The analog inputs are terminated

on-chip with precision laser-trimmed 50Ω NiCr resistors

to GNDI. Although the analog (and clock) inputs are

ESD protected, good ESD practices should always be

observed. The traces from the SMA inputs to the device

a re 50Ω mic ros trip tra ns mis s ion line s . The a na log

inputs can be driven either single-ended or differential.

Optimal performance is obtained with differential input

drive due to reduction of even-order harmonic distor-

tion. Table 1 represents single-ended input drive, and

Table 2 displays differential input drive.

ECLV bias generator turned off and CLKCOM tied to

GNDI (JU2 installed).

TT

NOTE: If the regulator’s shutdown logic level is not

present (V I on first) before the V

supply is

CC

EE

turned on, the regulator will momentarily turn on

until the V I supply is energized. If JU2 is installed,

CC

Evluate:46/MAX108

this will momentarily short the regulator’s output to

ground. The regulator is short-circuit protected so

no damage will result. The regulator is further pro-

tected by limiting the V supply current to 500mA.

EE

Table 1. Input Setup and Output Code Results for Single-Ended Analog Inputs

VIN+

VIN-

0V

OVERRANGE BIT

OUTPUT CODE

11111111 (full scale)

11111111

+250mV

1

0

+250mV - 1LSB

0V

01111111

toggles 10000000

0V

0

-250mV + 1LSB

-250mV

0V

0

00000001

00000000 (zero scale)

4

_______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

Table 2. Input Setup and Output Code Results for Differential Analog Inputs

VIN+

VIN-

OVERRANGE BIT

OUTPUT CODE

11111111 (full scale)

11111111

+125mV

-125mV

1

0

+125mV - 0.5LSB

-125mV + 0.5LSB

01111111

toggles 10000000

0V

0

-125mV + 0.5LSB

-125mV

+125mV - 0.5LSB

+125mV

0

00000001

00000000 (zero scale)

The PECL outputs are standard open-emitter types and

re q uire e xte rna l 50Ω te rmina tion re s is tors to the

In t e rn a l Re fe re n c e

The MAX104 family features an on-chip +2.5V precision

bandgap reference, which can be used by shorting

jump e r J U5 to c onne c t REFOUT with REFIN. If

required, REFOUT can also source up to 2.5mA to sup-

ply other peripheral circuitry.

PECLV voltage for proper biasing. The termination

TT

re s is tors a re loc a te d a t the fa r e nd of e a c h 50 Ω

microstrip transmission line, very close to the square

pin headers for the logic analyzer interface. Every EV

board is delivered with the PECL termination resistors

installed on the back side of the board. Each output

links to a 0.100 inch square 2-pin header to ease the

connection to a high-speed logic analyzer such as

Hewlett Packard’s HP16500C.

To us e a n e xte rna l re fe re nc e , re move the s horting

jumper on JU5 and connect the new reference voltage

source to the REFIN side of JU5. Leave the REFOUT

side of JU5 floating. Connect the ground of the external

reference to GNDI on the EV kit. REFIN accepts an

input voltage range of +2.3V to +2.7V.

To capture the digital data from the device in demulti-

plexed 1:2 format, each of the 16 channels from the

logic analyzer is connected to the eight primary (P0 to

P7) and eight auxiliary (A0 to A7) outputs. The ADC

provides differential PECL outputs, but most logic ana-

lyze rs (s uc h a s the HP16500C) ha ve s ing le -e nd e d

acquisition pods. Connect all single-ended logic ana-

lyzer pods to the same phase (either “+” or “-”) of the

PECL outputs.

CAUTION: With an external reference connected,

JU5 must not be installed at any time to avoid dam-

aging the internal reference with the external refer-

ence supply.

Offs e t Ad ju s t

The devices also provide a control input (VOSADJ) to

eliminate any offset from additional preamplifiers dri-

ving the ADC. The VOSADJ c ontrol inp ut is a se lf-

biased voltage divider from the internal +2.5V precision

reference. Under normal-use conditions, the control

input is left floating.

Da t a Re a d y (DREADY) Ou t p u t

The clock pod from the logic analyzer should be con-

nected to the DREADY+ output at JUDR+ on the EV

kits . Sinc e b oth the p rima ry a nd a uxilia ry outp uts

change on the rising edge of DREADY+, set the logic

analyzer to trigger on the falling edge. The DREADY

and data outputs are internally time-aligned, which

places the falling edge of DREADY+ in the approximate

center of the valid data window, resulting in the maxi-

mum setup and hold time for the logic analyzer. Set the

The EV kits include a 10kΩ potentiometer that is biased

from the ADC’s +2.5V re fe re nc e . The wip e r of the

potentiometer connects to the VOSADJ control input

through JU4. To enable the offset-adjust function, install

a shorting jumper on JU4 and adjust potentiometer R2

while observing the resulting offset in the reconstructed

digital outputs. The offset-adjust potentiometer offers

about ±5.5LSB of adjustment range. The EV kits are

shipped from the factory without a shorting jumper

installed on JU4.

logic analyzer’s threshold voltage to V O - 1.3V. For

CC

e xa mp le , if V O is + 3.3V, the thre s hold volta g e

CC

s hould b e s e t to +2.0V. The s a mp le offs e t (trig g e r

delay) of the logic analyzer should be set to 0ps under

these conditions.

P rim a ry a n d Au x ilia ry

P ECL Ou t p u t s

All PECL outputs on the EV kits are powered from the

It is also possible to use the DREADY- output for the

acquisition clock. Under this condition, set the logic

analyzer to trigger on the rising edge of the clock.

Table 3 summarizes the digital outputs and their func-

tions.

V

CC

O power supply, which may be operated from any

voltage between +3.0V to +5.0V for flexible interfacing

with either +3.3V or +5V systems. The nominal V

O

CC

supply voltage is +3.3V.

_______________________________________________________________________________________

5

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Table 3. PECL Outputs and Functions

EV KIT JUMPER

LOCATION

PECL OUTPUT

SIGNALS

FUNCTION

Primary Port Differential Outputs from LSB to

MSB. A “+” indicates the true value; a “-”

denotes the complementary outputs.

P0+ to P7+,

P0- to P7-

JUP0+ to JUP7+,

J UP0- to J UP7-

Auxiliary Port Differential Outputs from LSB to

MSB. A “+” indicates the true value; a “-”

denotes the complementary outputs.

A0+ to A7+,

A0- to A7-

JUA0+ to JUA7+,

J UA0- to J UA7-

OR+, OR-

JUOR+, JUOR-

JUDR+, JUDR-

Overrange’s True and Complementary Outputs.

Data-Ready PECL Output Latch Clock. Output

data changes on the rising edge of DREADY+.

DREADY+, DREADY-

Demux Reset Input Signals. Resets the internal

demux when asserted.

RSTIN+, RSTIN-

J5, J6 (SMA connectors)

JURO+, JURO-

Reset Outputs—for resetting additional external

demux devices.

RSTOUT+, RSTOUT-

Non-Demultiplexed DIV1 Mode

De m u lt ip le x e r S e t t in g s

It is also possible to operate the ADC in a non-demulti-

plexed mode. In this mode, the internal demultiplexer is

disabled and the sampled data is presented to the pri-

mary output port only. To consume less power, the aux-

iliary port can be shut down by two separate inputs

(AUXEN1 and AUXEN2). To enter this mode, place

jumpers JU7 (DEMUXEN), JU8 (AUXEN2), and JU9

(AUXEN1) in the OFF position. The position of the DIVS-

ELECT (JU6) jumper is a don’t care. To save additional

power, remove all the 50Ω pull-down resistors (R5–R20)

on the a uxilia ry outp ut p ort. It is not ne c e s s a ry to

remove the resistors; however, both the true and com-

Demultiplexed DIV2 Mode

This mode reduces the output data rate to one-half the

sample clock rate. The demultiplexed outputs are pre-

sented in dual 8-bit format with two consecutive sam-

ples in the primary and auxiliary output ports on the ris-

ing e d g e of the d a ta re a d y c loc k. To a c tiva te this

mode, jumpers JU7 (DEMUXEN), JU8 (AUXEN2), and

J U9 (AUXEN1) ha ve to b e in the ON p os ition, a nd

DIVSELECT (JU6) must be set to position 2.

NOTE: Each EV kit is shipped with jumpers JU7,

JU8, and JU9 installed in the ON position and JU6

set to 2.

plementary PECL outputs will pull up to the V level.

OH

Evluate:46/MAX108

DEMUXEN (JU7)

•

OFF

ON

OFF

ON

AUXEN2 (JU8)

•

OFF

ON

AUXEN1 (JU9)

•

OFF

ON

DIVSELECT (JU6)

X

DIVSELECT (JU6)

X

•

2

4

2

4

X = Leave open or don’t care

6

_______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

Decimation DIV4 Mode

In this special decimated, demultiplexed output mode,

Table 4. Selection Table for

Demultiplexer Operation

the ADC discards every other input sample and outputs

data at one-quarter the input sampling rate. This mode

is useful for system debugging at the resulting slower

output data rates, and may be required to capture data

successfully when testing the MAX108. To activate the

EV board’s DIV4 mode, jumpers JU7 (DEMUXEN), JU8

(AUXEN2), and JU9 (AUXEN1) have to be in the ON

position, and DIVSEL has to be in position 4. Since

every other sample at the input is discarded, the con-

DEMUX

DEMUXEN DIVSELECT

MODE

OVERRANGE BIT

OUTPUT MODE

Only primary port

active (auxiliary port

off)

OFF

ON

X

DIV1

Primary OR auxiliary

port

2

4

DIV2

DIV4

verter’s effective sample rate will be f /2.

SAMPLE

Primary OR auxiliary

port

ON

DEMUXEN

X = Don’t care

•

The signals associated with the demultiplexer reset

operation and the control of this section are listed in

Table 5. Consult the data sheet for a more detailed

description of the demultiplexer reset function, includ-

ing timing diagrams.

OFF

ON

AUXEN2

•

OFF

ON

Reset Inputs

AUXEN1

The reset circuitry accepts differential PECL inputs ref-

•

erenced to the same V O power supply that powers

CC

OFF

ON

the ADC’s PECL outputs. The reset input side-launched

SMA connectors are located at the lower left side of the

EV kits and are labeled RSTIN+ and RSTIN-.

DIVSELECT

•

For applications that do not require a synchronizing

reset, the reset inputs must be left open and resistors

R3 and R4 removed. In this case, they will self-bias to a

proper level with internal 50kΩ resistors and a 20µA

current source. This combination creates a -1V voltage

difference between RSTIN+ and RSTIN- to disable the

internal reset circuitry. When driven with PECL logic

2

4

Ove rra n g e Op e ra t io n

A single differential PECL overrange output bit (OR+,

OR-) is provided for both primary and auxiliary demulti-

plexed outputs. The operation of the overrange bit

depends on the status of the internal demultiplexer. In

demultiplexed DIV2 mode and decimation DIV4 mode,

the OR bit will flag an overrange condition if either the

primary or auxiliary port contains an overranged sam-

ple (Table 4). In non-demultiplexed DIV1 mode, the OR

port will flag an overrange condition only when the pri-

mary output port contains an overranged sample.

levels terminated with 50Ω to V O - 2V, the internal

CC

biasing network can easily be overdriven. The EV kits

are shipped with these resistor positions open to allow

the internal self-bias circuitry to disable the reset con-

trol input.

NOTE: Do not install the 50Ω RSTIN termination

resistors R3 and R4 unless the RSTIN input is dri-

ven with valid PECL logic levels. If the RSTIN inputs

are open circuited with the 50Ω resistors installed,

intermittent resetting of the internal demultiplexer

will occur and unpredictable operation will result.

Re s e t Op e ra t io n Re q u ire m e n t s

A detailed description of the reset circuitry and its oper-

ation is located in each device’s data sheet. To use the

reset input function, install two 50Ω pull-down resistors

at positions R3 and R4 on the back side of the EV

board. These resistors are connected to the on-board

PECLV termination generator. The RSTIN logic levels

TT

are compatible with standard PECL levels referenced

from the V O power supply.

CC

_______________________________________________________________________________________

7

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Table 5. Demultiplexer Operation and Reset Control Signals

EV KIT JUMPER

LOCATION

SIGNAL NAME

CLK+, CLK-

FUNCTION

J3, J4

Master ADC Timing Signal. The ADC samples on the rising edge of CLK+.

Data-Ready PECL Output. Output data changes on the rising edge of

DREADY+.

DREADY+, DREADY-

JUDR+, JUDR-

RSTIN+, RSTIN-

J5, J6

Demux Reset Input Signal. Resets the internal demux when asserted.

Reset Output—for resetting additional external demux devices.

RSTOUT+, RSTOUT-

JURO+, JURO-

Table 6. Power-Supply and Ground Requirements and Location

EV KIT JUMPER

LOCATION

GROUND

REFERENCE

EV KIT JUMPER

LOCATION

POWER SUPPLY

= -5V

V

EE

J17

J13, J15

J11

GNDI

GNDA/GNDI

GNDD

J16

J14, J16

J12

V

CC

A = V I = +5V

CC

V

CC

D = +5V

V

CC

O = +3.0V to +5V

J18

GNDD

J12

Reset Outputs

The EV kits are tested with the V A and V I supplies

CC CC

With a single device, no synchronizing reset is required

since the order of the samples in the output ports is

unchanged regardless of the phase of the DREADY

(DREADY+, DREADY-) clock (as described in the data

s he e ts ). DREADY+ (jump e r J UDR+) a nd DREADY-

(jumper JUDR-) can be found in the middle of the PECL

output arc in the right center of the EV board.

shorted by SP1 and SP2. There is no measurable differ-

ence in the parts’ dynamic performance with the sup-

plies separated, therefore Maxim recommends leaving

the supplies connected together.

CAUTION: There are no connections between

GNDA/GNDI and GNDD on the EV kits. These

grounds must be referenced together at the power

supply to the board, or damage to the device may

result!

On the EV kits , the re s e t outp ut 2-p in he a d e rs for

RSTOUT+ (jump e r J URO+) a nd RSTOUT- (jump e r

JURO-) are located above the reset input SMA connec-

tors on the lower left side of the board.

Referencing analog (GNDA/GNDI) and digital (GNDD)

grounds together at a single point avoids ground loops

and reduces noise pickup from the digital signals or

power lines.

Evluate:46/MAX108

P o w e r S u p p lie s

The EV kits feature separate analog and digital power

supplies and grounds for best dynamic performance. The

power-supply connectors are located at the top of the

board and require the power supplies listed in Table 6.

To avoid a possible latchup condition when disassem-

bling an application, a high-speed Schottky diode (D1,

1N5819) wa s a d d e d b e twe e n V a nd GNDI. This

EE

diode prevents the substrate (which is connected to

To simplify use of the EV kits and reduce the number of

V

EE

) from forwa rd b ia s ing a nd p os s ib ly c a us ing a

power sources required to drive the EV board, V

A

CC

latchup condition when the V connector is opened.

EE

and V I, as well as GNDA and GNDI, are connected

CC

together by shorting straps SP1 and SP2. To separate

the supplies, cut the traces at SP1 and SP2. Be sure to

observe the absolute maximum voltage difference of

±0.3V between the supplies if separate supplies are

used. This may require back-to-back Schottky diodes

Bo a rd La yo u t

Each EV kit is a four-layer board design, optimized for

high-speed signals. The board is constructed from low-

loss GETek core material, which has a relative dielec-

tric constant of 3.9 (ε = 3.9). The GETek material used

r

between V A and V I to prevent violation of the

CC

for the EV board offers improved high-frequency and

thermal properties over standard FR4 board material.

All high-speed signals are routed with 50Ω microstrip

absolute maximum ratings during power-up/down.

8

_______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

Table 7. EV Kit PCB Layers

LAYER

DESCRIPTION

Components, jumpers, connectors, test pads, V O, GNDD, GNDI, analog 50Ω

microstrip lines, de-embedding fixtures

CC

Layer I, top layer

Layer II, ground plane

Layer III, power plane

Layer IV, bottom layer

Ground for analog 50Ω microstrips, GNDA, GNDD, GNDI, V

D

CC

V , PECLV (V O - 2V), GNDD

EE TT CC

V

CC

A, V O, GNDI, digital 50Ω microstrip lines, 50Ω termination resistors

CC

transmission lines. The line width for 50Ω microstrip is

18 mils with a ground plane height of 10 mils, which is

a standard GETek core thickness. Figure 3 shows a

cross-section of the EV kit layer profile.

Special Layout Considerations

A special effort was made in the board layout to sepa-

rate the analog and digital portions of the circuit. 50Ω

microstrip transmission lines are used for the analog

and clock inputs as well as for the high-speed PECL

digital outputs. The analog and clock transmission lines

are formed on the top side of the board, while the digi-

tal transmission lines are located on the back side of

the board. This reduces coupling of the high-speed

digital outputs to the analog inputs. The analog and

clock inputs provide on-chip, laser-trimmed 50Ω termi-

nation resistors for the best VSWR performance.

The board also features a de-embedding fixture formed

from two lengths of microstrip transmission line con-

ne c te d b e twe e n SMA c onne c tors J 9-10 a nd J 7-8,

located on the right edge of the board. The 1.50-inch

line length difference between the two paths exactly

matches the line length of the microstrip connecting the

analog inputs. By measuring the power-loss difference

between the two paths at the frequency of interest, it is

p os s ib le to e s tima te the a tte nua tion of the a na log

inputs caused by PCB losses. Figure 4 shows the mea-

sured attenuation vs. frequency for the microstrip lines

connecting the analog inputs.

Wherever large ground or power planes are used, care

was taken to ensure that the analog planes were not

overlapping with any digital planes. This eliminates the

possibility of capacitively coupling digital noise through

the circuit board to sensitive analog areas.

BOARD LOSS vs. INPUT FREQUENCY

0

18 MILS

50Ω

1 oz. Cu

-0.05

-0.10

-0.15

-0.20

-0.25

-0.30

LAYER #1 (TOP)

10 MIL GETek CORE

LAYER #2

GETek PREPREG AS NEEDED

LAYER #3

-0.35

-0.40

-0.45

-0.50

10 MIL GETek CORE

LAYER #4 (BOTTOM)

18 MILS

50Ω

1

500

1500 2500

ANALOG INPUT FREQUENCY (MHz)

Figure 3. EV Kit Layer Profile for 50Ω Microstrip Design

Figure 4. Analog Input Attenuation from PCB Losses

_______________________________________________________________________________________

9

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Figure 5a. BGA PCB Pad Designs (SMD Pad)

Figure 5b. BGA PCB Pad Designs (Non-SMD Pad)

All differential digital outputs are properly terminated

with 50Ω termination resistors on both phases of the

output, even though most logic analyzers are single

ended. By terminating both sides of the differential out-

copper etch quality control. The SMD pad (Figure 5a)

has a solder-mask opening that is smaller than the cop-

per land area. This means that the solder-mask align-

ment and etch quality will control the pad dimensions.

puts, the AC current in the V O and GNDD supplies is

CC

Since the edges of the copper do not need to extend

under the solder mask as with the SMD pad, the pad

can either be made larger or can provide more line

routing space between adjacent pads. There is room to

route a s ing le 50Ω mic ros trip tra c e (18 mils wid e )

between the BGA mounting pads on the EV kits. The

copper land diameter is 25 mils, while the solder mask

opening is 30 mils.

reduced. This also reduces coupling of the ADC out-

p uts b a c k to the a na log inp uts a nd p re s e rve s the

excellent SNR performance of the converter.

The PECL digital outputs are arranged in an arc to match

the line lengths between the ADC outputs and the logic

analyzer connectors. The lengths of the 50Ω microstrip

lines are matched to within 0.050 inch to minimize layout-

dependent data skew between the bits. The propagation

delay on the EV board is about 134ps per inch.

Die Te m p e ra t u re Me a s u re m e n t

It is possible to determine the die temperature of the

ADC under normal operating conditions by observing

ESBGA Device Pad Design

An excellent reference on the assembly and design of

PCBs with BGA d e vic e s is “Ap p lic a tion Note s on

Surfa c e Mount As s e mb ly of Amkor/Ana m BGA

Pa c ka g e s .” This p ub lic a tion is a va ila b le from

Amkor/Anam, 1900 S. Price Road, Chandler AZ, 85248,

phone: (602) 821-5000.

the currents I

and I . These are two nominally

PTAT

CONST

Evluate:46/MAX108

100µA currents designed to be equal at 27°C. The cur-

rents are derived from the internal precision +2.5V

bandgap reference of the ADC. Their test pads (J21

and J22) are labeled ICONST and IPTAT and are locat-

ed just above the analog inputs.

As described in the above applications note, there are

two possibilities for defining PCB pads for mounting

BGA devices: solder mask defined (SMD) and nonsol-

der mask defined (non-SMD, copper defined). The EV

kits’ design employs nonsolder mask defined pads.

Figure 5 shows the layout of each of these pad types.

The simplest method of determining die temperature is

to measure each current with an ammeter referenced to

GNDI, as described in the data sheets. The die temper-

ature in °C is then calculated by the expression:

I

PTAT

T

= 300

− 273

DIE

I

The non-SMD (Figure 5b) pad has a solder-mask open-

ing that is larger than the copper land area. This means

that the size of the mounting pad is controlled by the

CONST

10 ______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

D 1

Figure 6. MAX104/MAX106/MAX108 EV Kits Schematic

______________________________________________________________________________________ 11

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

J7

J9

J8

V

TT

V O

CC

V

TT

V O

CC

C51

0.01µF

C12

0.01µF

C53

0.01µF

C18

0.01µF

J10

GNDD

NOTE: THESE JUMPERS FORM

THE DE-EMBEDDING FIXTURE.

V

TT

V O

CC

V

TT

V O

CC

C58

0.01µF

C29

0.01µF

C52

0.01µF

C17

0.01µF

TERMINATION

JUMPER

RESISTOR TO V

TT

GNDD

JUOR+

JUOR-

JUP7+

JUP7-

JUP6+

JUP6-

JUP5+

JUP5-

JUP4+

JUP4-

JUP3+

JUP3-

JUP2+

JUP2-

JUP1+

JUP1-

JUP0+

JUP0-

JUA7+

JUA7-

JUA6+

JUA6-

JUA5+

JUA5-

JUA4+

JUA4-

JUA3+

JUA3-

JUA2+

JUA2-

JUA1+

JUA1-

JUA0+

JUA0-

JUDR-

JUDR+

JURO-

JURO+

R28

R29

R30

R38

R37

R36

R35

R34

R33

R32

R31

R27

R26

R25

R24

R23

R22

R21

R20

R19

R18

R17

R16

R15

R14

R13

R12

R11

R10

R9

V

V O

CC

TT

C59

0.01µF

C30

0.01µF

GNDD

EXAMPLE FOR PECL OUTPUT

JUMPER AND TERMINATION.

(EACH OUTPUT ON THE EV KIT

IS TERMINATED LIKE THIS.)

V

TT

V O

CC

C57

0.01µF

C28

0.01µF

JUOR+

GNDD

JUOR+

V

TT

V O

CC

R28

49.9Ω

C58

0.01µF

C27

0.01µF

GNDD

PECLV

TT

GNDD

Evluate:46/MAX108

V

TT

V O

CC

C55

0.01µF

C26

0.01µF

GNDD

R8

V

TT

V O

CC

R7

C54

C19

0.01µF

R6

0.01µF

R5

R44

R45

R46

R47

GNDD

Figure 6. MAX104/MAX106/MAX108 EV Kits Schematic (continued)

12 ______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

V

D

CC

JU7

GNDD

V

D

CC

GNDD

JU5

GNDD

GNDI

P2

D17

E18

V12

U12

V14

U14

V16

U16

N18

N17

L18

L17

H18

H17

F18

F17

B14

C14

B12

C12

V13

U13

V15

U15

P18

P17

M18

M17

J18

REFOUT

DIVSEL

DEMUXEN

OR+

OR-

T.P.

1

3

2

F1

VOSADJ

R2

10k

JUOR+

JUOR-

JUP7+

JUP7-

JUP6+

JUP6-

JUP5+

JUP5-

JUP4+

JUP4-

JUP3+

JUP3-

JUP2+

JUP2-

JUP1+

JUP1-

JUP0+

JUP0-

JUA7+

JUA7-

JUA6+

JUA6-

JUA5+

JUA5-

JUA4+

JUA4-

JUA3+

JUA3-

JUA2+

JUA2-

JUA1+

JUA1-

JUA0+

JUA0-

JU4

ICONST

J21

IPTAT

E1

E2

L1

J1

T1

P1

R1

V10

U10

ICONST

IPTAT

VIN+

VIN-

CLK+

P7+

P7-

P6+

P6-

P5+

P5-

P4+

P4-

P3+

P3-

P2+

P2-

P1+

P1-

P0+

P0-

A7+

A7-

A6+

A6-

A5+

A5-

A4+

A4-

A3+

A3-

A2+

A2-

A1+

A1-

A0+

A0-

GNDI

J22

J1

J2

CLK-

V

CLKCOM

RSTIN+

RSTIN-

J3

GNDI

J4

GNDI

JU2

A9

B5

B10

R19

D18

A12

GNDI

V

A

I

D

CC

GNDI

AUXEN1

AUXEN2

V

TT

U1

O

R3*

CC

49.9Ω

J5

MAX104

MAX106

MAX108

J6

GNDI

R4*

49.9Ω

GNDI

V

TT

J17

G18

G17

B15

C15

B13

C13

V

A

CC

SP1

V

I

CC

V

D

CC

JUDR-

JUDR+

JURO-

JURO+

SP2

OFF

3

ON

2

JU9

1

V

EE

OFF

3

ON

GNDI

JU5

2

1

JU8

GNDI

GNDD

GNDA

REFOUT

GNDD

V

O

CC

*NOT INSTALLED

Figure 6. MAX104/MAX106/MAX108 EV Kits Schematic (continued)

______________________________________________________________________________________ 13

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 7. MAX104/MAX106/MAX108 EV Kits Component Placement Guide—Component Side (Layer I)

14 ______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 8. MAX104/MAX106/MAX108 EV Kits Component Placement Guide—Solder Side (Layer IV)

______________________________________________________________________________________ 15

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 9. MAX104/MAX106/MAX108 EV Kits PC Board Layout—Component Side (Layer I)

16 ______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 10. MAX104/MAX106/MAX108 EV Kits PC Board Layout—GND Plane (Layer II)

______________________________________________________________________________________ 17

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 11. MAX104/MAX106/MAX108 EV Kits PC Board Layout—Power Plane (Layer III)

18 ______________________________________________________________________________________

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

Evluate:46/MAX108

1.0"

Figure 12. MAX104/MAX106/MAX108 EV Kits PC Board Layout—Solder Side (Layer IV)

______________________________________________________________________________________ 19

MAX1 0 4 /MAX1 0 6 /MAX1 0 8 Eva lu a t io n Kit s

NOTES

Evluates:46/MAX108

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX108EVKIT
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Evaluation Kits for the MAX104/MAX106/MAX108 评估套件为MAX104 / MAX106 / MAX108\n
文件：	总20页 (文件大小：782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX108EVKIT [MAXIM]

相关型号：

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