MAX11014BGTM [MAXIM]
Automatic RF MESFET Amplifier Drain-Current Controllers; 自动RF MESFET放大器漏极电流控制器
| 型号： | MAX11014BGTM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Automatic RF MESFET Amplifier Drain-Current Controllers |
| 文件： | 总69页 (文件大小：946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3985; Rev 0; 2/06
Automatic RF MESFET Amplifier
Drain-Current Controllers
General Description
Features
♦ Dual Drain-Current-Sense Gain Amplifier
The MAX11014/MAX11015 set and control bias condi-
tions for dual MESFET power devices found in point-to-
point communication and other microwave base
stations. The MAX11014 integrates complete dual ana-
log closed-loop drain-current controllers for Class A
MESFET amplifier operation, while the MAX11015 tar-
gets Class AB operation. Both devices integrate SRAM
lookup tables (LUTs) that can be used to store temper-
ature and drain-current compensation data.
Preset Gain of 4
±±0.5 Aꢀꢀuraꢀc for Sense ꢁoltaꢂes ꢃetꢄeen
7.mꢁ and 62.mꢁ (MAX11±14)
♦ Common-Mode Sense-Resistor ꢁoltaꢂe Ranꢂe
±0.ꢁ to 11ꢁ (MAX11±14)
.ꢁ to 32ꢁ (MAX11±1.)
♦ Loꢄ-Noise Output GATE ꢃias ꢄith ±1±mA GATE
Each device includes dual high-side current-sense
amplifiers to monitor the MESFET drain currents through
the voltage drop across the sense resistors in the 0 to
625mV range. External diode-connected transistors mon-
itor the MESFET temperatures while an internal tempera-
ture sensor measures the local die temperature of the
MAX11014/MAX11015. The internal DAC sets the volt-
ages across the current-sense resistors by controlling
the GATE voltages. The internal 12-bit SAR ADC digitizes
internal and external temperature, internal DAC voltages,
current-sense amplifier voltages, and external GATE volt-
ages. Two of the 11 ADC channels are available as gen-
eral-purpose analog inputs for analog system monitoring.
Drive
♦ Fast Clamp and Poꢄer-On Reset
♦ 12-ꢃit DAC Controls MESFET GATE ꢁoltaꢂe
♦ Internal Temperature Sensor/Dual Remote Diode
Temperature Sensors
♦ Internal 12-ꢃit ADC Measures Temperature and
ꢁoltaꢂe
♦ Pin-Seleꢀtable Serial Interfaꢀe
304MHz I2C-Compatible Interfaꢀe
2±MHz SPI-/MICROWIRE-Compatible Interfaꢀe
The MAX11014’s gate-drive amplifier functions as an
integrator for the Class A drain-current control loop
while the MAX11015’s gate-drive amplifier functions
with a gain of -2 for Class AB applications. The current-
limited gate-drive amplifier can be fast clamped to an
external voltage independent of the digital input from
the serial interface. Both the MAX11014 and the
MAX11015 include self-calibration modes to minimize
error over time, temperature, and supply voltage.
Ordering Information
PKG
PART
PIN-PACKAGE
AMPLIFIER
CODE
MAX11±14BGTM+ 48 Thin QFN-EP** T4877-6
Class A
MAX11±1.BGTM+* 48 Thin QFN-EP** T4877-6 Class AB
+ Denotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
Note: All devices are specified over the -40°C to +105°C operating
temperature range.
The MAX11014/MAX11015 feature an internal reference
and can operate from separate ADC and DAC external
references. The internal reference provides a well-regu-
lated, low-noise +2.5V reference for the ADC, DAC, and
temperature sensors. These integrated circuits operate
from a 4-wire 20MHz SPI™-/MICROWIRE™-compatible
Pin Configuration and Typical Operating Circuit appear at end
of data sheet.
2
or 3.4MHz I C*-compatible serial interface (pin-selec-
table). Both devices operate from a +4.75V to +5.25V
analog supply (2.8mA typical supply current), a +2.7V
to +5.25V digital supply (1.5mA typical supply current),
and a -4.5V to -5.5V negative supply (1.1mA supply
current). The MAX11014/MAX11015 are available in a
48-pin thin QFN package specified over the -40°C to
+105°C temperature range.
Applications
Cellular Base-Station RF MESFET Bias Controllers
Point-to-Point or Point-to-Multipoint Links
Industrial Process Control
2
*Purchase of I C components from Maxim Integrated Products,
Inc. or one of its sublicensed Associated Companies, conveys
2
a license under the Phillips I C Patent Rights to use these com-
SPI is a trademark of Motorola, Inc.
2
ponents in an I C system, provided that the system conforms to
the I C Standard Specification as defined by Phillips.
MICROWIRE is a trademark of National Semiconductor Corp.
2
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Automatic RF MESFET Amplifier
Drain-Current Controllers
AꢃSOLUTE MAXIMUM RATINGS
AV
DV
to AGND .........................................................-0.3V to +6V
to DGND.........................................................-0.3V to +6V
PGAOUT1, PGAOUT2 to AGND ..............-0.3V to (AV
SCLK/SCL, DIN/SDA, CS/A0, N.C./A2, CNVST, OPSAFE1,
+ 0.3V)
DD
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
AV to AGND...........................................................-0.3V to -6V
OPSAFE2 to DGND.............................-0.3V to (DV
DOUT/A1, SPI/I2C, ALARM, BUSY
to DGND ..............................................-0.3V to (DV
+ 0.3V)
DD
SS
RCS1+, RCS1-, RCS2+, RCS2- to GATEV
+ 0.3V)
SS
DD
(MAX11014) ........................................................-0.3V to +13V
RCS1+, RCS1-, RCS2+, RCS2- to AGND
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T = +70°C)
A
(MAX11015) ........................................................-0.3V to +34V
RCS1- to RCS1+.......................................................-6V to +0.3V
RCS2- to RCS2+.......................................................-6V to +0.3V
48-Pin Thin QFN (derate 27.0mW/°C
above +70°C)..........................................................2162.2mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range ...............................-60°C to 150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
GATEV to AGND...................................................+0.3V to -6V
SS
GATE1, GATE2 to AGND .....(GATEV - 0.3V) to (AV
to AV ..........................................-0.3V to (AV
All Other Analog Inputs to AGND ............-0.3V to (AV
+ 0.3V)
+ 0.3V)
+ 0.3V)
SS
DD
DD
DD
DV
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= -5.5V to -4.75V, V
= +4.75V to +5.25V, V
= +2.7V to V
, external V
AVDD
= +2.5V, external
REFADC
GATEVSS
AVSS
AVDD
DVDD
V
C
= +2.5V, C
= C
= 0.1µF, V
= V
= 0, V
= V
= -5V, T = T
= +5V, C
= C
= 1nF, C
=
REFDAC
FILT4
REFADC
= V
REFDAC
OPSAFE1
OPSAFE2
RCS1+
RCS2+
FILT1
MAX
FILT3
FILT2
= 1nF, V
= 0, V
= V
= 0, V
= V
to T
, unless otherwise noted.
AGND
DGND
ADCIN0
ADCIN1
ACLAMP1
ACLAMP2
J
MIN
All typical values are at T = +25°C.)
J
PARAMETER
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-SENSE AMPLIFIER (Note 1)
MAX11014
MAX11015
0.5
5
11.0
32
Common-Mode Input Voltage
Range
V
V
RCS+
0.5V < V
< 11V for the MAX11014
90
90
RCS_+
Common-Mode Rejection Ratio
CMRR
dB
5V < V
< 32V for the MAX11015
RCS_+
I
200
2
RCS+
V
< 100mV over the common-mode
SENSE
Input-Bias Current
µA
range
I
RCS-
Full-Scale Sense Voltage
V
V
= V
- V
RCS-
625
625
625
625
0.5
mV
SENSE
SENSE
RCS+
To within 0.5ꢀ accuracy
To within 2ꢀ accuracy
To within 20ꢀ accuracy
75
20
2
Sense Voltage Range
mV
Total Current Set Error
V
= 75mV
0.1
ꢀ
SENSE
Current-Sense Settling Time
t
Settles to within 0.5ꢀ of final value
< 25
µs
HSCS
Settles to within 0.5ꢀ accuracy, from
Saturation Recovery Time
< 45
µs
V
= 1.875V
SENSE
CLASS Aꢃ INPUT CHANNEL
Untrimmed Offset
Offset Temperature Coefficient
Gain
19
0
Bits
Bits/oC
4
Gain Error
0.1
ꢀ
2
_______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V
= V
= -5.5V to -4.75V, V
= +4.75V to +5.25V, V
= +2.7V to V , external V
AVDD
= +2.5V, external
REFADC
GATEVSS
AVSS
AVDD
DVDD
V
C
= +2.5V, C
= C
= 0.1µF, V
= V
= 0, V
= V
= -5V, T = T
= +5V, C
= C
= 1nF, C
=
REFDAC
FILT4
REFADC
= V
REFDAC
OPSAFE1
OPSAFE2
RCS1+
RCS2+
FILT1
MAX
FILT3
FILT2
= 1nF, V
= 0, V
= V
= 0, V
= V
to T
, unless otherwise noted.
AGND
DGND
ADCIN0
ADCIN1
ACLAMP1
ACLAMP2
J
MIN
All typical values are at T = +25°C.)
J
PARAMETER
CLASS Aꢃ OUTPUT CHANNEL
Untrimmed Offset
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 1)
50
0
µV
mV/oC
Offset Temperature Coefficient
Gain
-2
Gain Error
0.1
ꢀ
GATE-DRIꢁE AMPLIFIER/INTEGRATOR
V
V
+
+
GATEVSS
1
I
I
I
I
= -1mA
V
GATE
GATE
GATE
GATE
= +1mA
-0.15
-4
mV
V
Output Gate-Drive Voltage Range
(Note 2)
V
GATE
GATEVSS
1.2
= -10mA
= +10mA
-1
-20
mV
Settles to within 0.5ꢀ of final value, R =
S
Gate Voltage Settling Time—
MAX11015
50Ω, C
= 15µF, see GATE Output
GATE
t
1.1
ms
GATE
Resistance vs. GATE Voltage in the Typical
Operating Characteristics
No series resistance, R = 0Ω
0
0
0.5
3.6
S
Output Capacitive Load (Note 3)
C
GATE
nF
15,000
250
R = 500Ω
S
Gate Voltage Noise
RMS noise, 1kHz to 1MHz
nV/√Hz
mV
Maximum Power-On Transient
Output Short-Circuit Current Limit
C
= 1nF
100
LOAD
I
Sinking or sourcing
25
mA
SC
Output Safe Switch On-
Resistance
Clamp GATE1 to ACLAMP1, GATE2 to
ACLAMP2 (Note 4)
R
OPSW
kΩ
ADC DC ACCURACY
Resolution
12
Bits
LSB
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
No missing codes
(Note 5)
1
1.25
4
ADC
INL
LSB
ADC
2
LSB
Gain Error
(Note 6)
2
4
LSB
Gain Temperature Coefficient
Offset Temperature Coefficient
0.4
0.4
ppm/oC
ppm/oC
Channel-to-Channel Offset
Matching
0.1
0.1
LSB
LSB
Channel-to-Channel Gain
Matching
_______________________________________________________________________________________
3
Automatic RF MESFET Amplifier
Drain-Current Controllers
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V
= V
= -5.5V to -4.75V, V
= +4.75V to +5.25V, V
= +2.7V to V
, external V
= +2.5V, external
GATEVSS
AVSS
AVDD
DVDD
AVDD
REFADC
V
C
= +2.5V, C
= C
= 0.1µF, V
= V
= 0, V
= V
= -5V, T = T
= +5V, C
= C
= 1nF, C
=
REFDAC
FILT4
REFADC
= V
REFDAC
OPSAFE1
OPSAFE2
RCS1+
RCS2+
FILT1
MAX
FILT3
FILT2
= 1nF, V
= 0, V
= V
= 0, V
= V
to T
, unless otherwise noted.
AGND
DGND
ADCIN0
ADCIN1
ACLAMP1
ACLAMP2
J
MIN
All typical values are at T = +25°C.)
J
PARAMETER
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DYNAMIC ACCURACY (1kHz sine-ꢄave input, -±0.dꢃ from full sꢀale, 9404ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
70
-84
86
76
1
dB
dB
Up to the 5th harmonic
SFDR
IMD
dB
f
= 9.9kHz, f
= 10.2kHz
dB
IN1
IN2
-3dB point
MHz
kHz
Full-Linear Bandwidth
S / (N + D) > 68dB
100
ADC CONꢁERSION RATE
External reference
Internal reference
0.8
50
Power-Up Time
t
µs
µs
PU
GATE_ and sense voltage measurements
All other measurements
40
Acquisition Time (Note 3)
t
ACQ
1.5
Conversion Time
t
Internally clocked
6.5
µs
ns
CONV
Aperture Delay
30
ADCIN1, ADCIN2 INPUTS
Input Range
V
Relative to AGND (Note 7)
0
V
V
ADCIN_
REFADC
1
Input Leakage Current
V
= 0V or V
0.01
34
µA
pF
ADCIN_
AVDD
Input Capacitance
C
ADCIN_
TEMPERATURE MEASUREMENTS
T = +25°C
0.25
1.0
J
Internal Sensor Measurement
Error
°C
°C
T = -40°C to +85°C (Note 3)
J
2.5
3.5
T = -40°C to +105°C (Note 3)
J
1.0
T = +25°C
1.0
J
External Sensor Measurement
Error (Note 8)
T = -40°C to +105°C
J
3
Temperature Resolution
External Diode Drive
0.125
°C/LSB
µA
3.26
75.00
External Temperature Sensor
Drive Current Ratio
16.6
INTERNAL REFERENCE
Reference Output Voltage
V
V
= V
+2.490
+2.500 +2.510
15
V
REFADC
REFDAC
Reference Output Temperature
Coefficient
ppm/oC
Reference Output Impedance
Power-Supply Rejection Ratio
6.5
-83
kΩ
PSRR
= +5V 5ꢀ
dB
AVDD
4
_______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V
= V
= -5.5V to -4.75V, V
= +4.75V to +5.25V, V
= +2.7V to V
, external V
= +2.5V, external
GATEVSS
AVSS
AVDD
DVDD
AVDD
REFADC
V
C
= +2.5V, C
= V
= -5V, T = T
= C
= 1nF, C
=
REFDAC
FILT4
REFADC
= V
REFDAC
OPSAFE1
OPSAFE2
RCS1+
RCS2+
FILT1
MAX
FILT3
FILT2
= 1nF, V
, unless otherwise noted.
AGND
J
All typical values are at T = +25°C.)
J
PARAMETER
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCES
REFADC Input Voltage Range
V
+1.0
+0.50
12
V
V
REFADC
AVDD
V
= +2.5V, f
= 178ksps
60
REFADC
SAMPLE
REFADC Input Current
I
µA
REFADC
Acquisition/between conversions
0.01
REFDAC Input Voltage Range
REFDAC Input Current
DAC DC ACCURACY
Resolution
V
+2.52
V
REFDAC
26
µA
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
INL
Measured at FILT_
Measured at FILT_, guaranteed monotonic
1
DAC
DNL
0.4
1
DAC
V
V
+4.75
+2.7
+5.25
V
V
AVDD
AV
DVDD
DD
V
I
,
GATEVSS
Negative Supply Voltage
V
= V
-5.50
-4.75
V
GATEVSS
AVSS
V
AVSS
Analog Supply Current
Digital Supply Current
I
V
V
= +5.25V
= +5.25V
2.8
1.5
5
5
mA
mA
AVDD
AVDD
DVDD
I
DVDD
GATEVSS
Negative Supply Current
V
= V
= -5.5V
= -5.5V
1.1
1.7
mA
GATEVSS
AVSS
+ I
AVSS
Analog Shutdown Current
Digital Shutdown Current
V
V
V
= +5.25V
= +5.25V
0.8
0.2
0.6
µA
µA
µA
AVDD
DVDD
Negative Shutdown Current
SERIAL-INTERFACE SUPPLIES
= V
AVSS
GATEVSS
0.3 x
V
IL
DV
DD
Input Voltage
V
0.7 x
DV
V
IH
DD
0.05 x
Input Hysteresis
V
V
V
HYS
DV
DD
BUSY: I
DOUT, ALARM: I
= 0.5mA;
SINK
Output Low Voltage
V
0.4
OL
= 3mA
SINK
SPI/ I2C = DV
;
DD
DV
0.5V
-
DD
Output High Voltage
V
BUSY: I
= 0.5mA;
SOURCE
V
OH
DOUT, ALARM: I
= 2mA
SOURCE
Input Current
I
0.01
5
10
µA
pF
IN
Input Capacitance
C
IN
_______________________________________________________________________________________
.
Automatic RF MESFET Amplifier
Drain-Current Controllers
SPI-INTERFACE TIMING CHARACTERISTICS
(Note 9) (See Figure 1.)
PARAMETER
SCLK Clock Period
SYMꢃOL
CONDITIONS
MIN
40
16
16
10
0
TYP
MAX
UNITS
ns
t
CP
CH
SCLK High Time
t
ns
SCLK Low Time
t
ns
CL
DS
DH
DO
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Rise or Fall to SCLK Rise
CS Pulse-Width High
t
ns
t
ns
t
C = 30pF
20
40
40
ns
L
t
C = 30pF (Note 3)
ns
DV
L
t
C = 30pF (Note 10)
L
ns
TR
t
10
40
0
ns
CSS
t
(Note 3)
(Note 3)
ns
CSW
Last SCLK Rise to CS Rise
t
ns
CSH
2
I C-INTERFACE SLOW-/FAST-MODE TIMING CHARACTERISTICS
(Note 9) (See Figure 2.)
PARAMETER
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Time (Repeated) for START
Condition
After this period, the first clock
pulse is generated
t
HD;STA
Setup Time for a Repeated START
Condition
t
SU;STA
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t
1.3
0.6
100
0
µs
µs
ns
µs
LOW
t
HIGH
t
SU;DAT
HD;DAT
Data Hold Time
t
(Note 11)
0.9
SDA, SCL Rise Time, Receiving
t
(Notes 3, 12)
0
300
ns
R
SDA, SCL Fall Time, Receiving
SDA Fall Time, Transmitting
t
t
(Notes 3, 12)
0
300
250
ns
ns
F
F
(Notes 3, 12, 13)
20 + 0.1 x C
B
Setup Time for STOP Condition
t
0.6
µs
pF
ns
SU;STO
Capacitive Load for Each Bus Line
C
(Notes 3, 14)
(Note 15)
400
50
B
Pulse Width of Spikes Suppressed
By the Input Filter
t
SP
6
_______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
2
I C-WIRE-INTERFACE HIGH-SPEED-MODE TIMING CHARACTERISTICS
(Note 9) (See Figure 3.)
C
= 1±±pF max
C = 4±±pF
ꢃ
ꢃ
PARAMETER
SYMꢃOL
CONDITIONS
UNITS
MHz
ns
MIN
MAX
MIN
MAX
Serial Clock Frequency
f
0
3.4
0
1.7
SCL
Setup Time (Repeated) START
Condition
t
160
160
160
160
SU;STA
Hold Time (Repeated) START
Condition
t
ns
HD;STA
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
Data Hold Time
t
160
60
10
0
320
120
10
0
ns
ns
ns
ns
ns
LOW
t
HIGH
t
SU;DAT
HD;DAT
t
(Note 11)
70
40
150
80
SCL Rise Time
t
(Note 3)
10
20
RCL
SCL Rise Time, After a Repeated
START Condition and After an
Acknowledge Bit
t
(Note 3)
10
80
20
160
ns
RCL1
SCL Fall Time
t
(Note 3)
(Note 3)
(Note 3)
10
10
40
80
80
20
20
80
ns
ns
ns
ns
pF
FCL
SDA Rise Time
t
160
160
RDA
SDA Fall Time
t
10
20
FDA
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
t
160
160
SU;STO
C
(Note 14)
(Note 15)
100
10
400
10
B
Pulse Width of Spikes Suppressed
By the Input Filter
t
0
0
ns
SP
_______________________________________________________________________________________
7
Automatic RF MESFET Amplifier
Drain-Current Controllers
MISCELLANEOUS TIMING CHARACTERISTICS
PARAMETER
SYMꢃOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Time to Wait After a
Write Command Before
Reading Back Data from the
Same Location
t
(Note 16)
(Note 3)
(Note 3)
1
µs
RDBK
CNVST Active-Low Pulse
Width in ADC Clock Mode 01
t
20
20
ns
ns
CNV01
CNV11
CNVST Active-Low Pulse
Width in ADC Clock Mode 11
to Initiate a Temperature
Conversion
t
CNVST Active-Low Pulse
Width in ADC Clock Mode 11
for ADCIN1/2 Acquisition
t
(Note 3)
1.5
µs
ACQ11A
ADC Power-Up Time (External
Reference)
t
t
0.8
50
2
µs
µs
µs
µs
APUEXT
ADC Power-Up Time (Internal
Reference)
t
APUINT
DPUEXT
DAC Power-Up Time (External
Reference)
DAC Power-Up Time (Internal
Reference)
t
50
DPUINT
Acquisition Time (Internally
Timed in ADC Clock Modes
00 or 01)
t
0.6
6.5
µs
ACQ
Conversion Time (Internally
Clocked)
t
µs
µs
µs
CONV
Delay to Start of Conversion
Time
t
(Note 17)
1
CONVW
Temperature Conversion Time
(Internally Clocked)
t
30
CONVT
8
_______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
MISCELLANEOUS TIMING CHARACTERISTICS (ꢀontinued)
Note 1: All current-sense amplifier specifications are tested after a current-sense calibration (valid when drain current = 0mA). See
RCS Error vs. GATE Current in the Typical Operating Characteristics. The calibration is valid only at one temperature and
supply voltage and must be repeated if either the temperature or supply voltage changes.
Note 2: The hardware configuration register’s CH_OCM1 and CH_OCM0 bits are set to 0. See Table 10a. The max specification is
limited by tester limitations.
Note 3: Guaranteed by design. Not production tested.
Note 4: At power-on reset, the output safe switch is closed. See the ALMHCFG (Read/Write) section.
Note .: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been calibrated out.
Note 6: Offset nulled.
Note 7: Absolute range for analog inputs is from 0 to V
.
AVDD
Note 8: Device and sensor at the same temperature. Verified by the current ratio (see the Temperature Measurements section).
Note 9: All timing specifications referred to V or V levels.
IH
IL
Note 1±:D
goes into tri-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled
OUT
before it goes to tri-state.
Note 11:A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 12:t and t measured between 0.3 x DV
and 0.7 x DV
.
R
F
DD
DD
Note 13:C = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
B
linearly interpolated.
Note 14:An appropriate bus pullup resistance must be selected depending on board capacitance. For more information, refer to the
2
I C documentation on the Philips website.
Note 1.:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 16:When a command is written to the serial interface, it is passed to the internal oscillator clock to be executed. There is a
small synchronization delay before the new value is written to the appropriate register. If the user attempts to read the new
value back before t , no harm will be caused to the data, but the read command may not yet show the new value.
RDBK
Note 17:This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from
the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the
write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of
the wrong ADC channel).
_______________________________________________________________________________________
9
Automatic RF MESFET Amplifier
Drain-Current Controllers
t
CSW
CS
t
t
CSS
CSS
t
CL
t
t
CP
t
CH
CSH
SCLK
t
t
DS
DH
C6
D1
D0
C7
DIN
t
t
TR
DO
t
DV
DOUT
Figure 1. SPI Serial-Interface Timing Diagram
SDA
t
SU;DAT
t
t
t
LOW
t
t
F
t
t
SP
t
R
BUF
F
R
HD;STA
SCL
t
t
SU;STO
t
SU;STA
HD;STA
t
t
HIGH
HD;DAT
S
r
S
P
S
S = START, S = REPEATED START, P = STOP
r
Figure 2. Slow-/Fast-Speed Timing Diagram
S
r
Sr P
t
RDA
t
FDA
SDA
SCL
t
SU;STA
t
HD;DAT
t
SU;STO
t
HD;STA
t
SU;DAT
t
RCL1
t
FCL
t
RCL
t
RCL1
t
t
t
t
HIGH
HIGH
LOW
LOW
S = REPEATED START, P = STOP
r
Figure 3. High-Speed Timing Diagram
1± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Typical Operating Characteristics
(V
= -5.5V; V
= V
= +5V, GATEV = AV = -5V, external V
= +2.5V; external V
= +2.5V; C
=
GATEVSS
AVDD
DVDD
SS
SS
REFADC
REFDAC
REF
0.1µF; T = T
to T
, unless otherwise noted.)
A
MIN
MAX
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
RCS ERROR vs. TEMPERATURE
0.4
0.2
0
8
6
4
2
0
2.45
2.44
2.43
2.42
2.41
2.40
AV = 5.25V
DD
AFTER CALIBRATION
BEFORE CALIBRATION
-0.2
-0.4
-50 -25
0
25
50
75 100 125
4.750
4.875
5.000
5.125
5.250
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
DV SUPPLY VOLTAGE (V)
DD
AV SUPPLY VOLTAGE (V)
DD
FILT1/FILT3 SETTLING TIME
vs. FILT1/FILT3 CAPACITIVE LOAD
RCS ERROR vs. GATE CURRENT
GATE VOLTAGE POWER-UP
MAX11014 toc04
0.50
0.25
0
600
500
400
300
200
100
0
10% TO 90%
t
FALL
t
RISE
V
GATE
1V/div
SOURCING
SINKING
-0.25
-0.50
-5V
40μs/div
-10
-5
0
5
10
0
100
200
300
400
500
GATE CURRENT (mA)
CAPACITIVE LOAD (pF)
DAC INTEGRAL NONLINEARITY
vs. OUPUT CODE
GATE OUTPUT RESISTANCE
vs. GATE VOLTAGE
GLITCH IMPULSE
MAX11014 toc08
1.00
0.75
0.50
0.25
0
20
15
10
5
GATEV = AV = -5V
SS
SS
FILT1
1mV/div
AC-COUPLED
-0.25
-0.50
-0.75
-1.00
0
0
1024
2048
3072
4096
-5
-4
-3
-2
(V)
-1
0
1μs/div
OUTPUT CODE
V
GATE
______________________________________________________________________________________ 11
Automatic RF MESFET Amplifier
Drain-Current Controllers
Typical Operating Characteristics (continued)
(V
= -5.5V; V
= V
= +5V, GATEV = AV = -5V, external V
= +2.5V; external V
= +2.5V; C
REF
=
GATEVSS
AVDD
DVDD
SS
SS
REFADC
REFDAC
0.1µF; T = T
to T
, unless otherwise noted.)
A
MIN
MAX
DAC DIFFERTIAL NONLINEARITY
vs. OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.00
0.75
0.50
0.25
0
1.00
1.00
0.75
0.50
0.25
0
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1024
2048
3072
4096
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC TOTAL HARMONIC DISTORTION
vs. FREQUENCY
ADC SINAD vs. FREQUENCY
ADC SFDR vs. FREQUENCY
0.1
80
75
70
100
90
80
70
60
50
0.01
65
60
0.001
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
ADC INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. SAMPLING RATE
ADC FFT PLOT
2.5026
2.5024
2.5022
2.5020
2.5018
0
-20
8
7
6
5
4
3
f
= 9.982kHz
AV = DV
DD
AV = DV = 5V
ANALOG_IN
DD
DD
DD
f
= 3.052MHz
CLK
SINAD = 71.28dBc
SNR = 71.51dBc
THD = -84.18dBc
SFDR = -86.94dBc
-40
-60
-80
-100
-120
0
10
20
30
40
50
4.750
4.875
5.000
5.125
5.250
0.1
1
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
SAMPLING RATE (ksps)
12 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Typical Operating Characteristics (continued)
(V
= -5.5V; V
= V
= +5V, GATEV = AV = -5V, external V
= +2.5V; external V
= +2.5V; C
REF
=
GATEVSS
AVDD
DVDD
SS
SS
REFADC
REFDAC
0.1µF; T = T
to T
, unless otherwise noted.)
A
MIN
MAX
DAC INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
2.5018
2.5016
2.5014
2.5012
2.5010
2.52
2.0
1.5
1.0
0.5
0
AV = DV
DD
DD
2.51
2.50
2.49
2.48
V
REFADC
V
REFDAC
4.750
4.875
5.000
5.125
5.250
-50 -25
0
25
50
75 100 125
4.750
4.875
5.000
5.125
5.250
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
AV (V)
DD
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR vs. TEMPERATURE
ADC GAIN EROR vs. TEMPERATURE
4
3
2
1
0
4
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
-1
-2
-3
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
4.750
4.875
5.000
AV (V)
5.125
5.250
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
INTERNAL TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
0 TO 100mV V
TRANSIENT RESPONSE
0 TO 250mV V
SENSE
TRANSIENT RESPONSE
SENSE
MAX11014 toc26
MAX11014 toc27
1.00
0.75
0.50
0.25
0
V
V
RCS1-
200mV/div
RCS1-
100mV/div
V
V
PGAOUT1
500mV/div
PGAOUT1
200mV/div
GND
GND
-0.25
-0.50
V
V
FILT1
500mV/div
FILT1
200mV/div
-0.75
-1.00
GND
-50 -25
0
25
75 100 125
50
10ms/div
10ms/div
TEMPERATURE (°C)
______________________________________________________________________________________ 13
Automatic RF MESFET Amplifier
Drain-Current Controllers
Pin Description
PIN
NAME
FUNCTION
Serial Data Input. Data is latched into the serial interface on the rising edge of SCLK in SPI mode.
Connect a pullup resistor to SDA in I C mode.
1
DIN/SDA
2
2
Serial Data Output in SPI Mode/Address Select 1 in I C Mode. Data transitions on the falling edge of
2
DOUT/A1
SCLK. DOUT is high impedance when CS is high. Connect A1 to DV
address to I C mode.
or DGND to set the device
DD
2
3
4
ADCIN1
ADCIN2
Analog Input 1
Analog Input 2
Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to
DXN1.
5
DXN1
DXP1
Remote-Diode Current Source. Connect DXP1 to the base/collector of a remote temperature-sensing
npn transistor. Do not leave DXP1 open; connect to DXN1 if no remote diode is used.
6
Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to
DXN2.
7
8
DXN2
Remote-Diode Current Source. Connect DXP2 to the base/collector of a remote temperature-sensing
npn transistor. Do not leave DXP2 open; connect to DXN2 if no remote diode is used.
DXP2
DAC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See
the HCFG (Read/Write) section.
9
REFDAC
REFADC
ADC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See
the HCFG (Read/Write) section.
10
Positive Analog Supply Voltage. Set AV
0.1µF capacitor in parallel to AGND.
between +4.75V and +5.25V. Bypass with a 1µF and a
DD
11, 27
AV
DD
12, 26
13
AGND
Analog Ground
ACLAMP2 MESFET2 External Clamping Voltage Input
GATE2 MESFET2 Gate Connection. See the Gate-Drive Amplifiers section.
Gate-Drive Amplifier Negative Power-Supply Input. Set GATEV between -4.75V and -5.5V. Connect
14
SS
15
GATEV
SS
externally to AV . Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND.
SS
16, 28, 29,
34–37
N.C.
No Connection. Not internally connected.
17
18
19
20
21
22
23
24
ACLAMP1 MESFET1 External Clamping Voltage Input
GATE1
FILT1
FILT2
FILT3
FILT4
MESFET1 Gate Connection. See the Gate-Drive Amplifiers section.
Channel 1 Filter 1 Input. See Figures 5 and 6.
Channel 1 Filter 2 Input. See Figures 5 and 6.
Channel 2 Filter 3 Input. See Figures 5 and 6.
Channel 2 Filter 4 Input. See Figures 5 and 6.
PGAOUT1 Channel 1 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6.
PGAOUT2 Channel 2 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6.
Negative Analog Supply Voltage. Set AV between -4.75V and -5.5V. Connect externally to
SS
25
AV
SS
GATEV . Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND.
SS
14 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
Channel 2 Current-Sense-Resistor Connection. Connect to the external supply powering channel 2’s
MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with
a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS1+.
30
RCS2+
Channel 2 Current-Sense-Resistor Connection. Connect to the channel 2 MESFET drain. Decouple as
required by the application. If unused, connect to RCS2+.
31
32
RCS2-
RCS1-
Channel 1 Current-Sense-Resistor Connection. Connect to the channel 1 MESFET drain. Decouple as
required by the application. If unused, connect to RCS1+.
Channel 1 Current-Sense-Resistor Connection. Connect to the external supply powering channel 1’s
MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with
a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS2+.
33
RCS1+
Operating Safe Channel 1 Input. Set OPSAFE1 high to clamp GATE1 to ACLAMP1 for fast protection
of enhancement FET power transistors.
38
39
40
OPSAFE1
OPSAFE2
BUSY
Operating Safe Channel 2 Input. Set OPSAFE2 high to clamp GATE2 to ACLAMP2 for fast protection
of enhancement FET power transistors.
BUSY Output. BUSY asserts high under certain conditions when the device is busy. See the BUSY
Output section.
Digital Supply Voltage. Set DV
in parallel to DGND.
between +2.7V and AV . Bypass with a 1µF and a 0.1µF capacitor
DD
DD
41
42
43
DV
DD
DGND
Digital Ground
Active-Low Conversion Start Input. Set CNVST low to begin a conversion in clock modes 01 and 11.
Connect CNVST to DV when issuing conversion commands through the serial interface.
CNVST
DD
Alarm Output. ALARM asserts when the temperature or voltage measurements exceed their preset
high or low thresholds.
44
45
ALARM
2
Chip-Select Input in SPI Mode/Address Select 0 in I C Mode. CS is an active-low input. When CS is
low, the serial interface is enabled. When CS is high, DOUT is high impedance. Connect A0 to DV
or DGND to set the device address in I C mode.
CS/A0
DD
2
2
SPI-/I C-Interface Select Input. Connect SPI/I2C to DV
to select SPI mode. Connect SPI/I2C to
DD
46
47
SPI/I2C
2
DGND to select I C mode.
2
No Connection in SPI Mode/Address Select 2 in I C Mode. Connect A2 to DV
device address in I C mode.
or DGND to set the
DD
N.C./A2
2
Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40ꢀ to 60ꢀ.)
2
48
—
SCLK/SCL Connect a pullup resistor to SCL in I C mode. See Table 10 for details on programming the clock
mode.
Exposed Pad. Connect to AGND and a large copper plane to meet power dissipation specifications.
Do not use as a ground connection.
EP
______________________________________________________________________________________ 1.
Automatic RF MESFET Amplifier
Drain-Current Controllers
2) Calibration
Detailed Description
In production of the power amplifier, measure the
quiescent drain current at a fixed calibration temper-
ature (probably room) and adjust the V
The MAX11014/MAX11015 set and monitor the bias con-
ditions for dual MESFET power devices found in cellular
base stations and point-to-point microwave links. The
internal DAC sets the voltage across the current-sense
resistor by controlling the GATE voltage. These devices
integrate a 12-bit ADC to measure voltage, internal and
external temperature, and communicate through a 4-wire
20MHz SPI-/MICROWIRE-compatible serial interface or
2-wire 3.4MHz I2C-compatible serial interface
(pin-selectable).
SET(CODE)
value until the drain current is within the specified
limits for that temperature. The V value is
SET(CODE)
stored for loading after power-up. Prior to operation,
command a PGA calibration after powering up by
writing to the PGA calibration control register, setting
the TRACK bit to 0 and the DOCAL bit to 1 (see
Table 18).
The MAX11014/MAX11015 operate from an internal
+2.5V reference or individual ADC and DAC external
references. The external current-sense resistors moni-
3) Operation
Upon request, the MAX11014 measures the temper-
ature of the MESFET and compares it with the previ-
ous reading. If the temperature reading has
changed, the MAX11014 reads the LUTs with the
characterization data and updates the DAC to cor-
rect the drain current. Setting the TRACK, DOCAL,
and SELFTIME bits to 1 in the PGA calibration con-
trol register starts automatic monitoring and adjust-
ment of drain current for variations in temperature.
tor voltages over the 0 to (V
/ 4) range. Two cur-
DACREF
rent-sense amplifiers with a preset gain of four monitor
the voltage across the sense resistors. The
MAX11014/MAX11015 accurately measure their inter-
nal die temperature and two external remote diode tem-
perature sensors. The remote pn junctions are typically
the base-emitter junction of an npn transistor, either
discrete or integrated on a CPU, FPGA, or ASIC.
The MAX11014/MAX11015 also feature an alarm output
that can be triggered during an internal or external
overtemperature condition, an excessive current-sense
voltage, or an excessive GATE voltage. Figure 4 shows
the MAX11014’s functional diagram.
Also, if the K LUTs are used, their values are monitored
for changes. A DAC correction is then made ifnecessary.
For Class AB operation with the MAX11015, measure
the MESFET temperature and set the GATE_ voltage
through the LUTs and DAC to control the drain current.
See the MAX11015 Class AB Control section.
Implement Class AB amplifier operation with the same
three steps as Class A operation, with the exception
that the LUTs set the GATE_ voltage for constant drain
current with varying temperature.
The MAX11014 integrates complete dual analog
closed-loop drain-current controllers for Class A
MESFET amplifier operation. See the MAX11014 Class
A Control Loop section. The analog control loop sets
the drain current through the current-sense resistors.
The MESFET gate-drive amplifier can vary the DAC
code accordingly if the temperature or other system
variables change.
Power-On Reset
On power-up, the MAX11014/MAX11015 are in full
power-down mode (see the SHUT (Write) section). To
change to normal power mode, write two commands to
the shutdown register. Set the FULLPD bit to 0 (other
bits in the shutdown register are ignored) on the first
command. A second command to this register then
activates the internal blocks.
Implement Class A amplifier operation with the follow-
ing three steps:
1) Characterization
Characterize the MESFET over temperature to deter-
mine the amplifier’s set of drain-current values,
assuming the part-to-part calibration curve is consis-
tent. There may be an offset shift, but no important
change in the shape of the function. Load these val-
ues into the MAX11014 LUTs at power-up. In opera-
tion, there is a linear interpolation between the
values stored in the LUTs.
MAX11014 Class A Control Loop
The MAX11014 is designed to set and continuously
control the drain current for MESFET power amplifiers
configured to operate in Class A. Set the DAC code to
control the voltage across the RCS_+ and RCS_- cur-
rent-sense resistor connections. The MAX11014 inter-
nal control loop automatically keeps the voltage across
the current-sense resistor to the value set by the DAC.
See the 12-Bit DAC section.
Adjust the drain current for other variables such as
output power or drain voltage by loading values into
the numerical K LUTs.
16 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
DRAIN
SUPPLY
RCS1+
BIAS CURRENT
GENERATOR
RCS1-
POWER
POR
GOOD
FILT1
FILT2
SERIAL
INTERFACE
CHANNEL
D
1 DAC
G
GATE1
S
12-BIT
REGISTER
OPSAFE1
OPSAFE2
ACLAMP1
DRAIN
SUPPLY
DV
DD
RCS2+
DGND
DIGITAL
CONTROL
MAX11014
MAX11015
RCS2-
FILT3
FILT4
12-BIT
REGISTER
CHANNEL
2 DAC
D
S
G
GATE2
REGISTER
MAP
ADC
CONTROL
ADC
CHANNEL
SELECT
ACLAMP2
DAC
CONTROL
AV
DD
DAC
CHANNEL
SELECT
AGND
AV
SS
SENSE
VOLTAGE
CONTROL
GATEV
SS
ALARM
ALARM
LIMIT
INTERNAL
+2.5V
REFERENCE
REFADC
RESET
INTERNAL
TEMPERATURE
SENSOR
VOLTAGE/TEMPERATURE DIGITAL
COMPARATOR
ALARM
12-BIT ADC
DXP1
12-BIT DAC CODE
CONVERSION, SCAN,
OSCILLATOR, AND CONTROL
48-ENTRY INTERPOLATING
TEMPERATURE SRAM LUT
48-ENTRY INTERPOLATING
TEMPERATURE SRAM LUT
MUX
DXN1
DXP2
EXTERNAL
TEMPERATURE
SENSOR
ALU
PROCESSING
48-ENTRY INTERPOLATING K
SRAM LUT
48-ENTRY INTERPOLATING K
SRAM LUT
DXN2
CHANNEL 1
CHANNEL 2
ADCIN2
ADCIN1
Figure 4. Functional Diagram
______________________________________________________________________________________ 17
Automatic RF MESFET Amplifier
Drain-Current Controllers
Once the control loop has been set, the MAX11014
automatically maintains the drain-current value. Figure
5 details the amplifiers that bias the channel 1 and
channel 2 control loops.
MAX11015 Class AB Control
The MAX11015 is designed to be used with a Class AB
amplifier configuration to independently measure the
drain current and set the GATE_ output voltages through
the serial interface. After sensing the drain current with
no RF signal applied, set the DAC code to obtain the
desired GATE_ voltage. Figure 6 details the amplifiers
that bias the channel 1 and channel 2 control.
The dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- by four and add an offset
voltage (+12mV nominally). These current-sense ampli-
fiers amplify sense voltages between 0 and 625mV
when V
= +2.5V. See the Current-Sense
REFDAC
Amplifiers section.
The MAX11015 internal 12-bit DAC voltage is applied
to the gate-drive amplifier, which has a preset gain of
-2. See the Gate-Drive Amplifiers section. Setting the
DAC code between FFFh and 000h typically produces
The current-sense amplifier output injects a scaled-down
replica of the MESFET drain current at the summing
node to complete the internal analog feedback loop. The
summing node drives the gate-drive amplifier through a
100kΩ series resistor. The gate-drive amplifier is config-
ured as an integrator by the external capacitor connect-
ed between GATE1/GATE2 and FILT2/FILT4. The
gate-drive amplifier includes automatic offset cancella-
tion between 0 and 24mV to null the 12mV offset from the
current-sense amplifier. See the Register Descriptions
and PGACAL (Write) sections.
a GATE_ voltage between 0 and (-2 x V
). See
REFDAC
the HCFG (Read/Write) section for details on adjusting
the GATE_ maximum voltage.
The channel 1 DAC voltage is output to FILT1 through a
series 580kΩ resistor. The channel 2 DAC voltage is
output to FILT3 through a series 580kΩ resistor.
Connect a capacitor from FILT1 to AGND and FILT3 to
AGND to set the filter’s time constant for the respective
channel. Connect FILT2 and FILT4 to AGND
(MAX11015 only).
The MAX11014’s analog control loop setpoint is
described by the following equation:
The dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- by four and add an offset
voltage (+12mV nominally). The current-sense ampli-
fiers amplify sense voltages between 0 and 625mV
V
(CODE = 000h)− V
FILT
FILT
V
− V
=
RCS+
RCS−
4
when V
= +2.5V. See the Current-Sense
REFDAC
Amplifiers section.
where:
(CODE = 000h) = V
V
(channel 1) and V
FILT3
FILT
FILT1
Current-Sense Amplifiers
(channel 2) when the THRUDAC1/THRUDAC2 register
code is set to 000h.
The dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- and add an offset voltage.
Connect a resistor between RCS_+ and RCS_- to sense
the MESFET drain current. The current-sense amplifiers
scale the sense voltage by four. These amplifiers also
reject the drain supply voltage that appears as a DC
common-mode level on the current signal.
V
V
= V
(channel 1) and V
(channel 2).
FILT
FILT1
FILT3
- V
= the voltage drop across the current-
RCS+
RCS-
sense resistor.
Connect a capacitor from FILT2 to GATE1 to form an
integrator (setting the control-loop dominant pole) with
the channel 1 internal 100kΩ resistor. Connect a
capacitor from FILT4 to GATE2 to form an integrator
(setting the control-loop dominant pole) with the chan-
nel 2 internal 100kΩ resistor. The gate-drive amplifier’s
output drives the MESFET gates. See the Gate-Drive
Amplifiers section.
The gate-drive amplifier includes automatic offset can-
cellation between 0 and 24mV to null the 12mV offset
from the current-sense amplifier. See the PGACAL
(Write) section.
Gate-Drive Amplifiers
The gate-drive amplifiers control the MESFET gate bias
settings. The MAX11014’s channel 1 and channel 2
DAC voltages are routed through a summing node and
into the gate-drive amplifiers. The MAX11015’s channel
1 and channel 2 DAC voltages are routed directly to the
gate-drive amplifiers, which have a preset gain of -2.
See the 12-Bit DAC section for details on setting the
DAC codes.
The channel 1 DAC voltage is output to FILT1 through a
series 580kΩ resistor. The channel 2 DAC voltage is
output to FILT3 through a series 580kΩ resistor.
Connect a capacitor from FILT1 to AGND and FILT3 to
AGND to set the filter’s time constant for the respective
channel.
18 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
PGAOUT1
+0.5V TO +11V
RCS1+
RCS1-
CURRENT-SENSE
AMPLIFIER
CS/A0
CHANNEL 1
ADC
SCLK/SCL
DIN/SDA
FILT2
SERIAL
INTERFACE
DOUT/A1
N.C./A2
C
FILT2
GATE1
POWER
MESFET
100kΩ
GATE-DRIVE
AMPLIFIER
580kΩ
CHANNEL 1
DAC
+
C
FILT1
FILT1
PGAOUT2
+0.5V TO +11V
RCS2+
RCS2-
CURRENT-SENSE
AMPLIFIER
CHANNEL 2
ADC
FILT4
C
FILT4
GATE2
POWER
MESFET
100kΩ
GATE-DRIVE
AMPLIFIER
580kΩ
CHANNEL 2
DAC
+
C
FILT3
FILT3
MAX11014
Figure 5. MAX11014 Class A Analog Control Loop
______________________________________________________________________________________ 19
Automatic RF MESFET Amplifier
Drain-Current Controllers
PGAOUT1
CS/A0
+5V TO +32V
CHANNEL 1
ADC
CURRENT-SENSE
AMPLIFIER
RCS1+
RCS1-
SCLK/SCL
DIN/SDA
DOUT/A1
N.C./A2
SERIAL
INTERFACE
GATE1
POWER
MESFET
GAIN = -2
GATE-DRIVE
AMPLIFIER
C
FILT1
580kΩ
FILT1
FILT2
CHANNEL 1
DAC
PGAOUT2
+5V TO +32V
CHANNEL 2
ADC
CURRENT-SENSE
AMPLIFIER
RCS2+
RCS2-
GATE2
POWER
MESFET
GAIN = -2
GATE-DRIVE
AMPLIFIER
C
FILT3
580kΩ
FILT3
FILT4
CHANNEL 2
DAC
MAX11015
Figure 6. MAX11015 Class AB Analog Control
2± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
ADC CODE
READ
FROM
RCS_+ TO
RCS_- SENSE
ꢁOLTAGE
GATE ꢁOLTAGE
ALARM
THRESHOLDS
USER
ENTERED
DAC CODE
GATE
ꢁOLTAGE
PGAOUT
ꢁOLTAGE
MESFET
THE FIFO
DEFAULT
0V
FFFh
FFFh
0mV
V
FULLY
ON
REFDAC
V
= FFFh
H
TOO HIGH
NEW HIGH GATE
VOLTAGE ALARM
THRESHOLD
V
GATE
WITHIN
THRESHOLDS
NEW LOW GATE
VOLTAGE ALARM
THRESHOLD
TOO LOW
DEFAULT
-2 x V
000h
000h
V
/ 4
REFDAC
0V
OFF
REFDAC
V = 000h
L
Figure 7. DAC Code Range
Connect the MESFET drain to the RCS_- input. Connect
the MESFET’s gate to the GATE_ output. Set the GATE_
conversion results are written to the FIFO memory. The
FIFO holds up to 15 words (each word of 16 bits) with a
leading 4-bit channel tag to indicate which channel the
12-bit data comes from. See Table 25. The FIFO reads
back data words either one at a time or continuously.
See the ADCCON (Write) section. The FIFO always
stores the most recent conversion results and allows
the oldest data to be overwritten. The FIFO indicates an
overflow condition and underflow condition (read of an
empty FIFO) through the flag register. See the FLAG
(Read) section.
voltage to -2 x V
to turn the MESFET fully off.
REFDAC
Set the GATE_ voltage to 0V to turn the MESFET fully
on. See Figure 7.
The MAX11014/MAX11015 GATE_ output voltage can
be clamped to the external voltage applied at
ACLAMP_. Setting OPSAFE_ high clamps the GATE_
voltage unconditionally. The GATE_ can also be
clamped by different commands issued through the
serial interface. These devices can also monitor the
alarms through the software to modify the clamping
mechanism. See the Automatic GATE Clamping and
ALMHCFG (Read/Write) sections.
Analog Input Track and Hold
The equivalent circuit of Figure 8 details the
MAX11014/MAX11015’s ADCIN_ input architecture. In
track mode, a positive input capacitor is connected to
ADCIN1/ADCIN2. A negative input capacitor is con-
nected to AGND. After the T/H enters hold mode, the
difference between the sampled input voltages and
AGND is converted. The input-capacitance charging
rate determines the time required for the T/H to acquire
an input signal. The required acquisition time lengthens
with the increase of the input signal’s source imped-
ance. Any source impedance below 300Ω does not
significantly affect the ADC’s AC performance. A high-
impedance source can be accommodated either by
placing a 1µF capacitor between ADCIN_ and AGND.
The combination of the analog-input source impedance
and the capacitance at the analog input creates an RC
filter that limits the analog-input bandwidth.
12-Bit ADC Description
The MAX11014/MAX11015 ADCs use a fully differential
successive-approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the ADC Transfer
Function section for more details.
The internal ADC block converts the results of the inter-
nal die temperature, remote diode temperature read-
ings, current-sense voltages, and ADCIN_ voltages.
The ADC block also reads back the GATE_ analog out-
put voltage and converts it to a 12-bit digital result. The
______________________________________________________________________________________ 21
Automatic RF MESFET Amplifier
Drain-Current Controllers
REFADC
DAC
ACQ
AGND
ADCIN1,
ADCIN2
CIN+
COMPARATOR
HOLD
CIN-
ACQ
AGND
HOLD
ACQ
HOLD
AV / 2
DD
Figure 8. ADC Equivalent Input Circuit
Analog Input Protection
produce a temperature-dependent bias voltage differ-
ence. The second conversion result at 4µA is subtract-
ed from the first at 66µA to calculate a digital value that
is proportional to absolute temperature. The stored
data result is the above digital code minus an offset to
adjust from Kelvin to Celsius. The reference voltage for
the temperature measurements is derived from the
internal reference source to ensure the temperature
calibration of 1 LSB corresponding to +0.125°C.
Internal ESD protection diodes clamp ADCIN1/ADCIN2
to AV
and AGND, allowing them to swing from
DD
(AGND - 0.3V) to (AV
+ 0.3V) without damage.
DD
However, for accurate conversions near full scale, the
inputs must not exceed AV by more than 50mV or be
DD
lower than AGND by 50mV. If an analog input voltage
exceeds the supplies, limit the input current to 2mA.
Temperature Measurements
The MAX11014/MAX11015 measure their internal die
temperature and two external remote-diode tempera-
tures. Write to the ADC conversion register to com-
mand a temperature conversion. See Table 19. Set the
CH6 bit to 1 to calculate the remote-diode DXP2/DXN2
temperature sensor reading and load the data into the
FIFO. Set the CH1 bit to 1 to calculate the remote-diode
DXP1/DXN1 temperature-sensor reading and load the
data into the FIFO. Set the CH0 bit to 1 to calculate the
internal die temperature-sensor reading and load the
data into the FIFO. Temperature data is output in
signed two’s-complement format at DOUT in SPI mode
For external temperature readings, connect an npn
transistor between DXP_ and DXN_. Connect the base
and collector together as shown in Figure 4 to form a
base-emitter pn junction. The MAX11014/MAX11015
feature an ALARM output that trips when the internal or
external temperature rises above an upper threshold
value or drops below a lower threshold value. Set the
high and low temperature thresholds through the chan-
nel 1/channel 2 high/low temperature ALARM threshold
registers. See Tables 3, 4, and 5.
The temperature-sensing circuits power up for the first
temperature measurement in an ADC conversion scan.
The temperature-sensing block remains on until the
end of the scan to avoid an additional 50µs power-up
delay for each individual temperature channel. See the
ADCCON (Write) section, Figure 31, and Figure 32. The
temperature-sensor circuits remain powered up when
2
and SDA in I C mode. See Figure 22 for the tempera-
ture transfer function.
The MAX11014/MAX11015 perform internal tempera-
ture measurements with a diode-connected transistor.
The diode bias current changes from 66µA to 4µA to
22 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
the ADC conversion register’s continuous convert bit
(CONCONV) is set to 1 and the current ADC conver-
sion includes a temperature channel. The temperature-
sensor circuits remain powered up until the CONCONV
bit is set low.
V
= V
= (1 + LUT [K] x LUT
[TEMP])
TEMP
DAC(CODE)
SET(CODE)
K
where
V
= The modified channel1/channel 2 12-bit
= The 12-bit DAC code written to the chan-
DAC(CODE)
DAC code.
The external temperature sensor drive current ratio has
been optimized for a 2N3904 npn transistor with an ide-
ality factor of 1.0065. The nonideality offset is removed
internally by a preset digital coefficient. Using a transis-
tor with a different ideality factor produces a proportion-
ate difference in the absolute measured temperature.
For more details on this topic and others related to
using an external temperature sensor, see Application
Note 1057 “Compensating for Ideality Factor and
Series Resistance Differences between Thermal-Sense
Diodes” and Application Note 1944 “Temperature
Monitoring Using the MAX1253/54 and MAX1153/54”
on Maxim’s website: www.maxim-ic.com.
V
SET(CODE)
nel 1/channel 2 V
registers.
SET
LUT [K] = The interpolated, fractional 12-bit K LUT
K
value. The K LUT data is derived from a variety of
sources, including: the V
register value, the K para-
SET
meter register value, or various ADC channels. See the
SRAM LUTs section.
LUT
[TEMP] = The interpolated, fractional 12-bit
TEMP
two’s-complement temperature LUT value. The tempera-
ture LUT data is derived from either internal or external
temperature values. See the SRAM LUTs section.
The V
equation code is then loaded into the
DAC(CODE)
12-Bit DAC
The MAX11014/MAX11015 include two voltage-output,
12-bit monotonic DACs with 1 LSB integral nonlineari-
ty error and 0.4 LSB differential nonlinearity error. The
DAC operates from the internal +2.5V reference or an
external reference voltage supplied at REFDAC. When
using an external voltage reference, bypass REFDAC
with a 0.1µF capacitor to AGND. The REFDAC external
voltage range is +0.7V to +2.5V.
DAC input register or DAC output register, depending
on the corresponding channel’s LDAC bit in the soft-
ware configuration register. See Table 11.
Self-Calibration
Calibrate channel 1 and channel 2 by writing
to the PGA calibration control register. The
MAX11014/MAX11015 function after power-up without
a calibration. However, for best performance after pow-
ering up, command a calibration by setting the TRACK
bit to 0 and the DOCAL bit to 1 (see Table 18).
Subsequently, set the TRACK, DOCAL, and SELFTIME
bits to 1 to minimize loss of performance over tempera-
ture and supply voltage.
The MAX11014’s channel 1/channel 2 DACs set the
sense voltage between RCS_+ and RCS_- by control-
ling the GATE_ bias. See the MAX11014 Class A
Control Loop section. The MAX11015’s channel 1/chan-
nel 2 DACs drive the GATE_ outputs directly, indepen-
dent of the current-sense voltages, through the
gate-drive amplifier with a gain of -2. See the MAX11015
Class AB Control section.
The self-calibration algorithm cancels offsets at the
gate-drive amplifier inputs in approximately 95µV incre-
ments to improve accuracy. The self-calibration routine
can be commanded when the DACs are powered
down, but the results will not be accurate. For best
results, run the calibration after the DAC power-up time,
Set the channel 1/channel 2 DAC code by writing to the
respective channel’s DAC input registers, DAC input
and output registers, or V
registers. Write to the
SET
t
. The ADC’s operation is suspended during a
DPUEXT
DAC input registers (Table 16) and use a subsequent
write to the software load DAC register (Table 21) to
control the timing of the update. Write to the DAC input
and output registers (Table 17) to set the DAC output
voltage code directly, independent of the software load
self-calibration. The end of the self-calibration routine is
indicated by the BUSY output returning low. See the
BUSY Output section. Wait until the end of the self-cali-
bration routine before requesting an ADC conversion.
DAC register bits. Write to the V
registers (Table 14)
SET
to include LUT data in the DAC code. Writing to the
registers triggers a V calculation as
V
SET
DAC(CODE)
shown in the following equation:
______________________________________________________________________________________ 23
Automatic RF MESFET Amplifier
Drain-Current Controllers
ADC/DAC References
The MAX11014/MAX11015 provide an internal low-
noise +2.5V reference for the ADCs, DACs, and tem-
perature sensors. Set bits D3–D0 within the hardware
configuration register to control the source of the DAC
and ADC references. See Tables 10c and 10d.
SPI Compatibility (SPI/I2C = DV
)
DD
The MAX11014/MAX11015 communicate through a ser-
ial interface, compatible with SPI and MICROWIRE
devices. For SPI, ensure that the SPI bus master (typi-
cally a µC) runs in master mode so it generates the ser-
ial clock signal. Set the SCLK frequency to 20MHz or
less, and set the clock polarity (CPOL) and phase
(CPHA) in the µC control registers to the same value.
The MAX11014/MAX11015 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CS low to latch input data at
DIN on the rising edge of SCLK. Output data at DOUT
is updated on the falling edge of SCLK. See Figure 1.
Temperature values are available in signed two’s-com-
plement format, while all others are in straight binary.
Connect a voltage source to REFADC between +1.0V
and AV
in external ADC reference mode. Connect a
DD
voltage source to REFDAC between +0.7V to +2.5V in
external DAC reference mode. When using an external
voltage reference, bypass REFADC and REFDAC with
0.1µF capacitors to AGND.
Power Supplies
The MAX11014/MAX11015 operate from separate ana-
log and digital power supplies. Set the analog supply
A high-to-low transition on CS initiates the 24-bit data
input cycle. Once CS is low, write an 8-bit command
byte (MSB first) at DIN to indicate which internal regis-
ter is being accessed. The command byte also identi-
fies whether the data to follow is to be written into the
serial interface or read out. See the Register
Descriptions section. After writing the command byte,
write two data bytes at DIN or read two data bytes at
DOUT. Keep CS low throughout the entire 24-bit word
write. The serial-interface circuitry is common to the
ADC and DAC sections.
voltage, AV , between +4.75V and +5.25V. Set the
DD
digital supply voltage, DV , between +2.7V and
DD
AV . Bypass AV
with a 0.1µF and 1µF capacitor to
with a 0.1µF and 1µF capacitor to
DD
DD
AGND and DV
DD
DGND. The analog circuitry typically consumes 2.8mA
of supply current and the digital circuitry 3.7mA.
Set the negative analog supply voltages, AV
and
SS
GATEV , between -4.75V and -5.5V. Connect AV and
SS
SS
GATEV together externally. Bypass each of these neg-
SS
ative supplies with a 0.1µF and 1µF capacitor to AGND.
The RCS_+ inputs supply the power to the input section
of the current-sense amplifiers. Set RCS_+ between
+0.5V and +11V on the MAX11014 and +5V to +32V on
the MAX11015. Bypass RCS_+ with a 0.1µF and 1µF
capacitor to AGND.
When writing data, write an 8-bit command word and
16 data bits at DIN. See Figure 9. Data is input to the
serial interface on the rising edge of SCLK. When read-
ing data, write an 8-bit command byte at DIN and read
the following 16 data bits at DOUT. See Figure 10. Data
transitions at DOUT on the falling edge of SCLK. DIN
can be set high or low while data is being transferred
out at DOUT.
Serial Interface
The MAX11014/MAX11015 feature a pin-selectable
2
I C/SPI serial interface. Connect SPI/I2C to GND to
2
select I C mode, or connect SPI/I2C to V
to select
DD
2
SPI mode. SDA and SCL (I C mode) and DIN, SCLK,
and CS (SPI mode) facilitate communication between
the MAX11014/MAX11015 and the master.
24 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
CS
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
23
24
C7
(MSB)
C0
D15
D0
(LSB)
C6
C5
C4
C3
C2
C1
D14
D1
(LSB) (MSB)
THE COMMAND BYTE
INITIALIZES THE
INTERNAL REGISTERS.
THE NEXT 16 BITS
ARE DATA BITS.
Figure 9. MAX11014/MAX11015 Write Timing
CS
SCLK
1
2
3
4
5
6
7
8
9
23
10
24
C7
(MSB)
C0
(LSB)
C6
C5
C4
C3
C2
C1
DIN
THE COMMAND BYTE
INITIALIZES THE
INTERNAL REGISTERS.
THE NEXT 16 DATA
BITS ARE READ OUT.
DOUT
D15
(MSB)
D0
(LSB)
D14
D1
X = DON'T CARE.
NOTE: DOUT MAY BE DRIVEN UP TO 2 CLOCK CYCLES BEFORE D15 IS AVAILABLE.
ANY DATA ON DOUT BEFORE D15 IS AVAILABLE, SHOULD BE IGNORED.
Figure 10. MAX11014/MAX11015 Read Timing
______________________________________________________________________________________ 2.
Automatic RF MESFET Amplifier
Drain-Current Controllers
I2C Compatibility (SPI/I2C = DGND)
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high (Figure 11). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
High-Speed Mode section).
The MAX11014/MAX11015 communicate through an
I2C-compatible 2-wire serial interface consisting of a
serial data line (SDA) and a serial clock line (SCL). SDA
and SCL facilitate bidirectional communication between
the MAX11014/MAX11015 and the master at data rates
up to 3.4MHz. The master (typically a µC) initiates data
transfer on the bus and generates the SCL signal to per-
mit data transfer. The MAX11014/MAX11015 behave as
I2C slave devices that transfer and receive data.
SCL and SDA must be pulled high for proper I2C oper-
ation. This is typically done with pullup resistors (1kΩ or
greater). Series resistors are optional. The series resis-
tors protect the input architecture from high-voltage
spikes on the bus lines and minimize crosstalk and
undershoot of the bus signals.
The address byte, command byte, and data bytes are
transmitted between the START and STOP conditions.
Nine clock cycles are required to transfer the data in or
out of the MAX11014/MAX11015. See Figures 15 and
16. If the receiver returns a not-acknowledge bit
(NACK), the MAX11014/MAX11015 releases the bus. If
the not acknowledge occurs in the middle of a 16-bit
word, the remaining bits are lost.
One data bit transfers during each SCL clock cycle. A
minimum of 9 bytes is required to transfer a byte in or
out of the MAX11014/MAX11015 (8 bits and an
ACK/NACK). Data is latched in on SCL’s rising edge
and read out on SCL’s falling edge. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is stable and
high are considered control signals (see the START
and STOP Conditions section). Both SDA and SCL
remain high when the bus is not busy.
S
Sr
P
SDA
SCL
S = START
S = REPEATED START
r
P = STOP
Figure 11. START and STOP Conditions
26 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
NOT
ACKNOWLEDGE
S
SDA
SCL
ACKNOWLEDGE
8
1
2
9
Figure 12. Acknowledge Bits
SLAVE ADDRESS
S
0
1
0
1
A2
A1
A0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF ADDRESS-SELECT INPUT PINS A2, A1, AND A0.
Figure 13. Slave Address Byte
Acknowledge and Not-Acknowledge Conditions
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX11014/MAX11015 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device pulls SDA low before the rising edge
of the acknowledge-related clock pulse (ninth pulse)
and keeps it low during the high period of the clock
pulse (Figure 12).
Slave Address
The MAX11014/MAX11015 have a 7-bit I2C slave
address. The MSBs of the slave address are factory
programmed to 0101. The logic state of address inputs
A2, A1, and A0 determine the 3 LSBs of the device
address (Figure 13). Connect A2, A1, and A0 to DV
DD
for a high logic state or DGND for a low logic state.
Therefore, a maximum of eight MAX11014/MAX11015
devices can be connected on the same bus at one
time.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves SDA
high during the high period of the clock pulse. Monitor
the acknowledge bits to detect an unsuccessful data
transfer. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault occurs. In
the event of an unsuccessful data transfer, the bus
master should reattempt communication at a later time.
The MAX11014/MAX11015 continuously wait for a
START condition followed by its slave address. When
the device recognizes its slave address, it is ready to
accept or send data depending on bit 8, the R/W bit.
High-Speed Mode
At power-up, the bus timing is set for fast mode (F/S
mode, up to 400kHz I2C clock), which limits interface
speed. Switch to high-speed mode (HS mode, up to
3.4MHz I2C clock) to increase interface speed. The
interface is capable of supporting slow (up to 100kHz),
fast (up to 400kHz), and high-speed (up to 3.4MHz)
protocols. See Figure 14.
______________________________________________________________________________________ 27
Automatic RF MESFET Amplifier
Drain-Current Controllers
Transfer from F/S mode to HS mode by addressing all
devices on the bus with the HS-mode master code
0000 1XXX (X = don’t care). After successfully receiv-
ing the HS-mode master code, the MAX11014/
MAX11015 issue a NACK, allowing SDA to be pulled
high for one cycle.
(Figure 13) and a write bit (R/W = 0). After writing the
8th bit, the MAX11014/MAX11015 (the slave) issue an
acknowledge signal by pulling SDA low for one clock.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 15 and
17, Table 1, and the Command Byte section. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
the command byte, write 2 data bytes, allowing for two
additional acknowledge signals after each byte. The
master ends the write cycle by issuing a STOP condition.
When operating in HS mode, a STOP condition returns
the bus to F/S mode. See the High-Speed Mode section.
After the NACK, the MAX11014/MAX11015 operate in
HS mode. Send a repeated START (S ) followed by a
r
slave address to initiate HS-mode communication. If
the master generates a STOP condition, the
MAX11014/MAX11015 return to F/S mode. Use a
repeated START (S ) condition in place of a stop (P)
r
condition to leave the bus active and the mode
unchanged.
The MAX11014/MAX11015’s internal conversion clock
frequency is 4.8MHz (typ), resulting in a typical conver-
sion time of 4.6µs. Figure 15 shows a complete write
cycle.
Command Byte/Data Bytes (Write Cycle)
Begin a write cycle by issuing a START condition
(through the master), followed by 7 slave address bits
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 14. F/S-Mode to HS-Mode Transfer
MASTER TO SLAVE
SLAVE TO MASTER
4-BYTE WRITE CYCLE
8
8
NUMBER OF BITS
1
7
1
1
8
1
1
1
1
SLAVE
ADDRESS
S
W A
COMMAND BYTE
A
DATA BYTE
A
DATA BYTE
A
P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS.
Figure 15. Write Cycle
28 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Command Byte/Data Bytes (Read Cycle)
Default Reads
A standard I2C read command involves writing the
slave address, command byte, slave address byte
again, and then reading the data at SDA. This is
detailed in the 5-byte read cycle sequence in Figure
16. Read from the MAX11014/MAX11015 through the
default read command to avoid writing a command
byte and second slave address byte. See the default
read sequence in Figure 16.
Begin a read cycle by issuing a START condition fol-
lowed by writing a 7-bit address (Figure 18) and a read
bit (R/W = 1). After writing the 8th bit, the
MAX11014/MAX11015 (the slave) issue an acknowl-
edge signal by pulling SDA low for one clock cycle.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 16, 18,
19, Table 1, and the Command Byte section. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
writing the command byte, issue a repeated START
condition (Sr), write the slave address byte again, and
write a 9th bit for an acknowledge signal. After a third
acknowledge signal, read out the 2 bytes at SDA. After
reading the first byte, the master should send an
acknowledge (A). After reading the second byte, the
master should send a not-acknowledge (N) followed by
a stop signal.
Begin a default read cycle by writing the slave address
byte followed by an acknowledge bit. Read out the next
2 data bytes, with acknowledge bits from the master to
the slave following each byte. Continue to acknowledge
the data by sending acknowledge (A) signals. After
reading the final byte, the master should send a not-
acknowledge (N) followed by a stop signal. The default
read cycle reads out the data from the register (located
in Table 2) of the previously assigned command byte.
See Figure 18. This default read feature is useful for 2-
wire reads to maximize the data throughput without
having the overhead of setting the slave address and
command byte each time.
MASTER TO SLAVE
SLAVE TO MASTER
5-BYTE READ CYCLE
1
7
1
1
8
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SLAVE
ADDRESS
SLAVE
ADDRESS
S
R A
COMMAND BYTE
A Sr
R
A
DATA BYTE
N
DATA BYTE
N P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS
DEFAULT READ CYCLE
7
1
1
1
8
1
8
1
1
NUMBER OF BITS
SLAVE
ADDRESS
S
R
A
DATA BYTE
A
DATA BYTE
N P OR Sr
Figure 16. Read Cycle
______________________________________________________________________________________ 29
Automatic RF MESFET Amplifier
Drain-Current Controllers
SCL
SDA
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
C6
C5
C4
C3
C2
C1
C0
ACK
START
SDA
DIRECTION
IN
OUT
IN
OUT
SCL
SDA
D15
D14
D13
D12
D11
D10
D8
D9
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
STOP
IN
SDA
DIRECTION
IN
OUT
IN
OUT
2
Figure 17. MAX11014/MAX11015 I C Write Timing
SCL
SDA
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
C6
C5
C4
C3
C2
C1
C0
ACK
START
SDA
DIRECTION
IN
OUT
IN
OUT
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
D12
D11
D10
D9
D8
ACK
ACK
Sr
SDA
DIRECTION
IN
OUT
IN
SCL
D7
D6
D5
D4
D3
D2
D1
D0
NACK
SDA
P
SDA
DIRECTION
OUT
IN
2
Figure 18. MAX11014/MAX11015 I C Read Timing
3± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
SCL
SDA
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
C6
C5
C4
C3
C2
C1
C0
ACK
START
SDA
IN
OUT, DATA FROM LAST READ COMMAND BYTE REGISTER
IN
DIRECTION
SCL
D7
D6
D5
D4
D3
D2
D1
D0
NACK
SDA
STOP
OUT
IN
SDA
DIRECTION
2
Figure 19. MAX11014/MAX11015 I C Default Read Timing
cates the register’s read/write access. C7 is the MSB of
the command byte and C0 is the LSB. Following the
command byte, write or read 2 data bytes to/from bits
D15–D0. D15 is the MSB of the 2 data bytes and D0 is
the LSB. See Figures 9, 10, 17, 18, and 19 and the
Register Descriptions section.
Command Byte
Begin a write or read to the MAX11014/MAX11015 by
writing a command byte at DIN/SDA. Set bit C7 to 1 for
a read operation. Set bit C7 to 0 for a write operation.
See Table 1. The remaining bits, C6–C0, determine the
register accessed by the command byte. Table 2 indi-
Table 10 Input Command ꢃits
24-ꢃIT SERIAL INPUT WORD
DATA ꢃITS
COMMAND ꢃYTE
MSꢃ
LSꢃ
C7
R/W
C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
______________________________________________________________________________________ 31
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 20 Reꢂister Listinꢂ
HEX CODE
REGISTER DESCRIPTION
MNEMONIC
WRITE
62
—
READ
—
ADC Conversion
ADCCON
ALMFLAG
IPDAC1
THRUDAC1
VH1
ALARM Flag Register
F8
—
Channel 1 DAC Input
48
4A
28
24
20
44
2A
26
22
40
4C
4E
34
30
2C
46
36
32
2E
42
—
Channel 1 DAC Input and Output
—
Channel 1 High GATE Voltage ALARM Threshold
Channel 1 High Sense Voltage ALARM Threshold
Channel 1 High Temperature ALARM Threshold
Channel 1 K Parameter
A8
A4
A0
—
IH1
TH1
USRK1
VL1
Channel 1 Low GATE Voltage ALARM Threshold
Channel 1 Low Sense Voltage ALARM Threshold
Channel 1 Low Temperature ALARM Threshold
AA
A6
A2
—
IL1
TL1
Channel 1 V
VSET1
IPDAC2
THRUDAC2
VH2
SET
Channel 2 DAC Input
—
Channel 2 DAC Input and Output
—
Channel 2 High GATE Voltage ALARM Threshold
Channel 2 High Sense Voltage ALARM Threshold
Channel 2 High Temperature ALARM Threshold
Channel 2 K Parameter
B4
B0
AC
—
IH2
TH2
USRK2
VL2
Channel 2 Low GATE Voltage ALARM Threshold
Channel 2 Low Sense Voltage ALARM Threshold
Channel 2 Low Temperature ALARM Threshold
B6
B2
AE
—
IL2
TL2
Channel 2 V
VSET2
FIFO
SET
First-In First-Out Memory
Flag Register
80
F6
BC
B8
—
FLAG
—
Hardware ALARM Configuration
Hardware Configuration
LUT Address
ALMHCFG
HCFG
LUTADD
LUTDAT
PGACAL
SHUT
3C
38
7A
7C
5E
64
3E
74
3A
66
LUT Data
FC
—
PGA Calibration Control
Shutdown
—
Software ALARM Configuration
Software Clear
ALMSCFG
SCLR
BE
—
Software Configuration
Software Load DAC
SCFG
LDAC
BA
—
sequent register accessed. Tables 3–27 detail the vari-
ous read and write internal registers and their power-on
reset states.
Register Descriptions
The MAX11014/MAX11015 communicate between the
internal registers and external bus lines through the
serial interface. Table 1 details the command bits
(C7–C0) and the data bits (D15–D0) of the serial input
word. Table 2 details the command byte and the sub-
On power-up, the MAX11014/MAX11015 are in full
power-down mode (see the SHUT (Write) section). To
change to normal power mode, write two commands to
32 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 30 TH1 and TH2 (Read/Write)
ꢃIT
D1.
D14
D13
D12
D11
D1±
D9
D8
D7
D6
D.
D4
D3
D2
D1
D±
RESET
STATE
X
X
X
X
0
1
1
1
1
1
1
1
1
1
1
1
ꢃIT ꢁALUE
(°C)
MSB
(sign)
LSB
0.125
X
X
X
X
128
64
32
16
8
4
2
1
0.5
0.25
X = Don’t care.
Table 40 Hiꢂh/Loꢄ Temperature ALARM Threshold Examples
TEMPERATURE
SETTING
DATA ꢃITS D11–D±
(TWO’S COMPLEMENT)
-40°C
-1.625°C
0°C
1110 1100 0000
1111 1111 0011
0000 0000 0000
0000 1101 1001
0011 0100 1000
+27.125°C
+105°C
Table .0 TL1 and TL2 (Read/Write)
ꢃIT
D1. D14
D13
D12
D11
D1±
D9
D8
D7
D6
D.
D4
D3
D2
D1
D±
RESET
STATE
X
X
X
X
X
X
1
0
0
0
0
0
0
0
0
0
0
0
ꢃIT ꢁALUE
(°C)
MSB
(sign)
LSB
0.125
X
X
128
64
32
16
8
4
2
1
0.5
0.25
X = Don’t care.
the shutdown register. Set the FULLPD bit to 0 (other
bits in the shutdown register are ignored) on the first
command. A second command to this register acti-
vates the internal blocks.
TL1 and TL2 (Read/Write)
Set the external channel 1 and channel 2 low tempera-
ture ALARM thresholds by writing command bytes 22h
and 2Eh, respectively. Following the command byte,
write 12 bits of data to bits D11–D0. Read the low tem-
perature channel 1 and channel 2 ALARM thresholds
by writing command bytes A2h and AEh, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Temper-
ature data must be written and read in two’s-comple-
ment format, with the LSB corresponding to +0.125°C.
See Table 5. The POR value of the low temperature
ALARM threshold registers is 1000 0000 0000, which
corresponds to -256.0°C. See Figures 25 and 27 for
ALARM examples.
TH1 and TH2 (Read/Write)
Set the external channel 1 and channel 2 high tempera-
ture ALARM thresholds by writing command bytes 20h
and 2Ch, respectively. Following the command byte,
write 12 bits of data to bits D11–D0. Read the high tem-
perature channel 1 and channel 2 ALARM thresholds
by writing command bytes A0h and ACh, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Temper-
ature data must be written and read in two’s-comple-
ment format, with the LSB corresponding to +0.125°C.
See Table 3. The POR value of the high temperature
ALARM threshold registers is 0111 1111 1111, which
corresponds to +255.875°C. See Table 4 for examples
of channel 1/channel 2 high and low temperature
threshold settings. See Figures 25 and 27 for ALARM
examples.
IH1 and IH2 (Read/Write)
Set the channel 1 and channel 2 high sense voltage
ALARM thresholds by writing command bytes 24h and
30h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the high sense
voltage channel 1 and channel 2 ALARM thresholds by
writing command bytes A4h and B0h, respectively.
______________________________________________________________________________________ 33
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 60 IH1 and IH2 (Read/Write)
ꢃIT
D1.
D14
D13
D12
D11
D1±
1
D9
1
D8
1
D7
1
D6
1
D.
1
D4
1
D3
1
D2
1
D1
1
D±
1
RESET
STATE
X
X
X
X
1
ꢃIT ꢁALUE
X
X
X
X
MSB
—
—
—
—
—
—
—
—
—
—
LSB
X = Don’t care.
Table 70 IL1 and IL2 (Read/Write)
ꢃIT
D1.
D14
D13
D12
D11
D1±
0
D9
0
D8
0
D7
0
D6
0
D.
0
D4
0
D3
0
D2
0
D1
0
D±
0
RESET
STATE
X
X
X
X
0
ꢃIT ꢁALUE
X
X
X
X
MSB
—
—
—
—
—
—
—
—
—
—
LSB
X = Don’t care.
Table 80 ꢁH1 and ꢁH2 (Read/Write)
ꢃIT
D1.
D14
D13
D12
D11
D1±
1
D9
1
D8
1
D7
1
D6
1
D.
1
D4
1
D3
1
D2
1
D1
1
D±
1
RESET
STATE
X
X
X
X
1
ꢃIT ꢁALUE
X
X
X
X
MSB
—
—
—
—
—
—
—
—
—
—
LSB
X = Don’t care.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Sense volt-
age data must be written and read in straight binary
format. See Table 6. The POR value of the high sense
voltage ALARM threshold registers is 1111 1111 1111.
See Figures 25 and 27 for ALARM examples.
VH1 and VH2 (Read/Write)
Set the channel 1 and channel 2 high GATE voltage
ALARM thresholds by writing command bytes 28h and
34h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the high GATE
voltage channel 1 and channel 2 ALARM thresholds by
writing command bytes A8h and B4h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Voltage data
must be written and read in straight binary format. See
Table 8. The POR value of the high GATE voltage
ALARM threshold registers is 1111 1111 1111. See
Figure 7 for a GATE voltage example. See Figures 25
and 27 for ALARM examples.
The sense voltage is measured between RCS_+ and
RCS_-. A reading of 1111 1111 1111 corresponds to
V
/ 4. A reading of 0000 0000 0000 corre-
REFDAC
sponds to 0mV.
IL1 and IL2 (Read/Write)
Set the channel 1 and channel 2 low sense voltage
ALARM thresholds by writing command bytes 26h and
32h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the low sense volt-
age channel 1 and channel 2 ALARM thresholds by
writing command bytes A6h and B2h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Sense volt-
age data must be written and read in straight binary
format. See Table 7. The POR value of the low sense
voltage ALARM threshold registers is 0000 0000 0000.
See Figures 25 and 27 for ALARM examples.
VL1 and VL2 (Read/Write)
Set the channel 1 and channel 2 low GATE voltage
ALARM thresholds by writing command bytes 2Ah and
36h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the low GATE volt-
age channel 1 and channel 2 ALARM thresholds by
writing command bytes AAh and B6h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Voltage data
must be written and read in straight binary format. See
Table 9. The POR value of the low GATE voltage
ALARM threshold registers is 0000 0000 0000. See
Figure 7 for a GATE voltage example. See Figures 25
and 27 for ALARM examples.
The sense voltage is measured between RCS_+ and
RCS_-. A reading of 1111 1111 1111 corresponds to
V
/ 4. A reading of 0000 0000 0000 corre-
REFDAC
sponds to 0mV.
34 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 90 ꢁL1 and ꢁL2 (Read/Write)
ꢃIT
D1.
D14
D13
D12
D11
D1±
0
D9
0
D8
0
D7
0
D6
0
D.
0
D4
0
D3
0
D2
0
D1
0
D±
0
RESET
STATE
X
X
X
X
0
ꢃIT ꢁALUE
X
X
X
X
MSB
—
—
—
—
—
—
—
—
—
—
LSB
X = Don’t care.
Table 1±0 HCFG (Read/Write)
ꢃIT NAME
DATA ꢃIT
D15–D12
D11
RESET STATE
FUNCTION
X
X
0
0
0
0
X
Don’t care.
CH2OCM1
CH2OCM0
CH1OCM1
CH1OCM0
X
Maximum GATE2 voltage control bits.
D10
D9
Maximum GATE1 voltage control bits.
Don’t care.
D8
D7
ADC monitor bit. Set to 1 to load ADC results into the FIFO. Set to 0 to not
load any ADC results into the FIFO. The value of ADCMON does NOT
affect whether the results from any particular ADC conversion are
checked against ALARM limits or examined for changes to the
ADCMON
D6
0
V
equations.
DAC(CODE)
CKSEL1
CKSEL0
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Clock mode and CNVST configuration bits.
ADC reference select bits.
ADCREF1
ADCREF0
DACREF1
DACREF0
DAC reference select bits.
Timed Acquisitions and Conversions sections. Set the
ADCREF1/0 bits, D3 and D2, to determine the ADC ref-
erence source. See Table 10c. Set the DACREF1/0 bits,
D1 and D0, to determine the DAC reference source.
See Table 10d.
HCFG (Read/Write)
Select each channel’s maximum GATE voltage, clock
mode, ADC monitoring, DAC and ADC reference
modes by setting bits D10–D0 in the hardware configu-
ration register. Set the command byte to 38h to write to
the hardware configuration register. Set the command
byte to B8h to read from the hardware configuration
register. Bits D15–D11 are don’t care. Set the
CH2OCM1/0 bits, D10 and D9, to determine the maxi-
mum positive GATE2 output voltage. Set the
CH1OCM1/0 bits, D8 and D7, to determine the maxi-
mum positive GATE1 output voltage. See Table 10.
SCFG (Read/Write)
Write to the software configuration register to determine
whether a V
calculation value is loaded to
DAC(CODE)
the DAC input register or DAC input and output regis-
ter. This register also sets the control modes for the K
parameter and temperature lookup values in the
V
calculation. Set the command byte to 3Ah
DAC(CODE)
Set the ADCMON bit, D6, to 1 to load the ADC results
into the FIFO. Set ADCMON to 0 to not load ADC
results into the FIFO. Set the CKSEL1/0 bits, D5 and
D4, to determine the conversion and acquisition timing
clock modes. See Table 10b. Also, see the Internally
Timed Acquisitions and Conversions and the Externally
to write to the software configuration register. Set the
command byte to BAh to read from the software config-
uration register.
______________________________________________________________________________________ 3.
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 1±a0 Maximum GATE_ ꢁoltaꢂe Modes
CH_OCM1
CH_OCM±
FUNCTION
Maximum positive voltage at GATE_ = AGND.
0
0
1
1
0
1
0
1
Maximum positive voltage at GATE_ = AGND + 250mV.
Maximum positive voltage at GATE_ = AGND + 500mV.
Maximum positive voltage at GATE_ = AGND + 750mV.
Table 1±b0 Cloꢀk Modes
CONꢁERSION
CKSEL1
CKSEL±
ACQUISITION/SAMPLING
CLOCK
Internally timed acquisitions and conversions. Default state. Begin a
conversion by writing to the ADC conversion register to convert all
channels specified in this register.
0
0
Internal
Internally timed acquisitions and conversions. Begin a conversion by
pulling CNVST low only once for at least 20ns to convert all of the
channels selected in the ADC conversion register.
0
1
1
0
Internal
Reserved
Do not use.
Externally timed single acquisitions. Conversions internally timed.
Begin each individual conversion by pulling CNVST low for each
channel converted. See the Electrical Characteristics table for CNVST
timing. The MAX11014/MAX11015 acquire while CNVST is low and
sample when CNVST returns high.
1
1
Internal
Table 1±ꢀ0 ADC Referenꢀe Modes
ADCREF1
ADCREF±
ADC ꢁOLTAGE REFERENCE
0
1
1
X
0
1
External. Bypass REFADC with a 0.1µF capacitor to AGND.
Internal. Leave REFADC unconnected.
Internal. Bypass REFADC with a 0.1µF capacitor to AGND for better noise performance.
X = Don’t care.
Table 1±d0 DAC Referenꢀe Modes
DACREF1
DACREF±
DAC ꢁOLTAGE REFERENCE
External. Bypass REFDAC with a 0.1µF capacitor to AGND.
Internal. Leave REFDAC unconnected.
0
1
1
X
0
1
Internal. Bypass REFDAC with a 0.1µF capacitor to AGND for better noise performance.
X = Don’t care.
Bits D15–D12 of the software configuration register are
don’t care. Set the LDAC2 bit, D11, to 1 to load the new
Set the T2COMP1/0 bits, D10 and D9, to control the
channel 2 temperature LUT. See Table 11a. Set the
KSRC2-2/1/0 bits, D8, D7, and D6, to control the chan-
nel 2 K parameter LUT. See Table 11b and the SRAM
LUTs section.
value of V
, upon completion of a V
DAC2(CODE)
DAC2
calculation, into both the channel 2 DAC input and out-
put registers. See Figure 20. Set to 0 to load the new
value of V
, upon completion of a V
DAC2(CODE)
DAC2
calculation, to only the channel 2 DAC input register.
36 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Set the LDAC1 bit, D5, to 1 to load the new value of
, upon completion of a V calculation,
LUT [K] = The interpolated, fractional 12-bit K LUT
K
V
value. The K LUT data is derived from a variety of
DAC1
DAC1(CODE)
into both the channel 1 DAC input and output registers.
Set to 0 to load the new value of V , upon comple-
sources, including the V
register value, the K para-
SET
meter register value, or various ADC channels. See the
DAC1
tion of a V
calculation, to only the channel 1
SRAM LUTs section.
DAC1(CODE)
DAC input register. Set the T1COMP1/0 bits, D4 and
D3, to control the channel 1 temperature LUT. See
Table 11a. Set the KSRC1-2/1/0 bits, D2, D1, and D0 to
control the channel 1 K parameter LUT. See Table 11b
and the SRAM LUTs section.
LUT
[TEMP] = The interpolated, fractional 12-bit
TEMP
two’s-complement temperature LUT value. The tempera-
ture LUT data is derived from either internal or external
temperature values.See the SRAM LUTs section.
When the KSRC_-2/KSRC_-1/KSRC_-0 bits are set to
000 and T_COMP1/T_COMP0 bits are set to 00 or 01,
the V
Set the channel 1/channel 2 DAC code by writing to the
respective channel’s DAC input registers, DAC input
equation simplifies to:
DAC(CODE)
and output registers, or V
registers. Write to the
SET
DAC input registers (Table 16) and use a subsequent
write to the software load DAC register (Table 21) to
control the timing of the update. Write to the DAC input
and output registers (Table 17) to set the DAC output
voltage code directly, independent of the software load
V
= V
SET(CODE)
DAC(CODE)
Note: This is a special case and will not trigger a
calculation unless a sample already exists. This
functionality should be accessed by the THRUDAC
registers.
V
GATE
DAC register bits. Write to the V
registers (Table 14)
SET
to include LUT data in the DAC code. Writing to the
registers triggers a V calculation by the
For temperature samples or sampled KLUT sources to
automatically trigger V
must be configured to provide these samples.
Therefore, the ADC conversion register (Table 19) must
have the relevant channel bits set and the ADC must
be in a suitable clocking mode, regardless of the
ADCMON bit setting.
V
SET
DAC(CODE)
calculations, the ADC
DAC(CODE)
following equation:
V
= V
(1 + LUT [K] x LUT
[TEMP])
DAC(CODE)
SET(CODE)
K
TEMP
where
V
= The modified channel1/channel 2 12-bit
= The 12-bit DAC code written to the chan-
DAC(CODE)
DAC code.
V
SET(CODE)
nel 1/channel 2 V
registers.
SET
CHANNEL 1/CHANNEL 2 DAC
INPUT REGISTERS:
CHANNEL 1/CHANNEL 2 DAC
INPUT AND OUTPUT REGISTERS:
LDAC
REGISTER
CHANNEL 1/ CHANNEL 2 DAC
OUTPUT VOLTAGE
(IPDAC1/IPDAC2
THRUDAC1/THRUDAC2)
(THRUDAC1/
THRUDAC2)
V
DAC
CALCULATION
LDAC_ BITS
SET TO 1 IN
SCFG REGISTER
Figure 20. DAC Register Format
______________________________________________________________________________________ 37
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 110 SCFG (Read/Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D12
X
Don’t care.
Channel 2 load DAC. Set to 1 to load the new value of V
,
DAC2(CODE)
upon completion of a V
calculation, into both the channel 2
DAC2(CODE)
DAC input and output registers. When set to 1, BUSY pulses high after a
new V
output is calculated. Set to 0 to load the new value of
DAC2
LDAC2
D11
0
V
, upon completion of a V
calculation, to only the
DAC2(CODE)
DAC2(CODE)
channel 2 DAC input register. When set to 0, set the DACCH2 bit high in
the software load DAC register to transfer the V calculation
DAC(CODE)
value from the DAC input register to the DAC output.
T2COMP1
T2COMP0
KSRC2-2
KSRC2-1
KSRC2-0
D10
D9
D8
D7
D6
0
0
0
0
0
Channel 2 temperature LUT control bits.
Channel 2 K LUT control bits.
Channel 1 load DAC. Set to 1 to load the new value of V
, upon
DAC1
completion of a V
calculation, into both the channel 1 DAC
DAC1(CODE)
input and output registers. When set to 1, BUSY pulses high after a new
output is calculated. Set to 0 to load the new value of V
V
,
DAC1
DAC1
LDAC1
D5
0
upon completion of a V
calculation, to only the channel 1
DAC1(CODE)
DAC input register. When set to 0, set the DACCH1 bit high in the
software load DAC register to transfer the V calculation value
DAC(CODE)
from the DAC input register to the DAC output.
T1COMP1
T1COMP0
KSRC1-2
KSRC1-1
KSRC1-0
D4
D3
D2
D1
D0
0
0
0
0
0
Channel 1 temperature LUT control bits.
Channel 1 K LUT control bits.
38 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 11a0 Channel 1/Channel 2 Temperature LUT Control Modes
T_COMP1
T_COMP±
FUNCTION
A change in temperature does not trigger a V
calculation. Any V
DAC(CODE)
DAC(CODE)
0
0
calculation triggered in another way does not include the temperature lookup. This bit setting
simplifies the V
calculation to V
= V
(1 + LUT [K]).
SET(CODE) K
DAC(CODE)
DAC(CODE)
A change in temperature does not trigger a V
calculation. Any V
DAC(CODE)
DAC(CODE)
calculation triggered in another way does not include the temperature lookup. This bit setting
simplifies the V calculation to V = V (1 - LUT [K]).
0
1
1
1
0
1
DAC(CODE)
DAC(CODE)
SET(CODE)
K
A change in the channel 1/channel 2 external temperature sensor reading triggers a
calculation for the corresponding DAC channel. When a V calculation
V
DAC(CODE)
DAC(CODE)
is triggered, the calculation includes the temperature lookup function.
A change in the internal temperature sensor reading triggers a V
calculation for the
DAC(CODE)
corresponding channel. When a V
the temperature lookup function.
calculation is triggered, the calculation includes
DAC(CODE)
Table 11b0 Channel 1/Channel 2 K LUT Control Modes
KSRC_-2
KSRC_-1
KSRC_-±
FUNCTION
No K LUT operations performed. This bit setting simplifies the V
DAC(CODE)
0
0
0
calculation to:
V
= V
(1 + LUT [TEMP])
TEMP
DAC(CODE)
SET(CODE)
The V
The V
The V
calculation simplifies to:
DAC(CODE)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
V
= V
(1 + LUT [VSET] x LUT
[TEMP])
[TEMP])
DAC(CODE)
SET(CODE)
K
TEMP
calculation simplifies to:
DAC(CODE)
V
= V
(1 - LUT [USRK] x LUT
SET(CODE) K
DAC(CODE)
TEMP
calculation simplifies to:
DAC(CODE)
V
= V
(1 + LUT [sense voltage] x LUT
[TEMP])
TEMP
DAC(CODE)
SET(CODE)
K
The V
The V
The V
calculation simplifies to:
DAC(CODE)
V
= V
(1 + LUT [ADCIN_] x LUT
[TEMP])
TEMP
DAC(CODE)
SET(CODE)
K
calculation simplifies to:
DAC(CODE)
V
= V
+ USRK x LUT [VSET] x LUT
[TEMP]
TEMP
DAC(CODE)
SET(CODE)
K
calculation simplifies to:
DAC(CODE)
V
= V
+ USRK x LUT [sense voltage] x LUT
[TEMP]
TEMP
DAC(CODE)
SET(CODE)
K
The V
calculation simplifies to:
DAC(CODE)
V
= V
+ USRK x LUT [ADCIN_] x LUT
[TEMP]
TEMP
DAC(CODE)
SET(CODE)
K
______________________________________________________________________________________ 39
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 120 ALMHCFG (Read/Write)
RESET
STATE
ꢃIT NAME
DATA ꢃIT
FUNCTION
X
D15–D12
X
Don’t care.
Internal temperature conversion bit. Set to 1 to cause ALARM comparisons for
channel 2 to use the internal temperature conversion result. Set to 0 to cause ALARM
comparisons for channel 2 to use the external temperature conversion result.
INTEMP
D11
0
ALARM comparator bit. Set to 1 to configure the ALARM output in comparator mode.
Set to 0 to configure the ALARM output in interrupt mode.
ALMCMP
VGHYST1
VGHYST0
ITHYST1
ITHYST0
D10
D9
D8
D7
D6
0
0
0
0
0
GATE voltage hysteresis bits. The VGHYST_ bits control the built-in hysteresis level
when using the ALARM function in windowing mode for GATE voltage
measurements. The same value is used for the GATE voltage ALARM measurements
in both channels.
Sense voltage/temperature hysteresis bits. The ITHYST_ bits control the built-in
hysteresis level when using the ALARM function in windowing mode for sense
voltage and temperature measurements. The same value is used for the sense
voltage and temperature ALARM measurements in both channels.
ALM2CLMP1
ALM2CLMP0
ALM1CLMP1
ALM1CLMP0
D5
D4
D3
D2
0
0
0
0
Channel 2 ALARM clamp bits.
Channel 1 ALARM clamp bits.
ALARM polarity bit. Set to 1 to force the ALARM output to be active-low. Set to 0 to
force the ALARM output to be active-high.
ALMPOL
D1
0
ALARM open-drain/push-pull output bit. Set to 1 to configure the ALARM output as
open-drain. An external pullup or pulldown resistor is required. Multiple ALARM
outputs can be wired together onto a single line in open-drain mode. Set to 0 to
configure the ALARM output as a push-pull output (no external resistor required).
ALMOPN
D0
0
ALMHCFG (Read/Write)
sense voltage and temperature ALARM hysteresis
level. This hysteresis level applies to both channel 1
and channel 2. See Table 12b.
The hardware ALARM configuration register controls
the active states of the ALARM output. Set the com-
mand byte to 3Ch to write to the hardware ALARM con-
figuration register. Set the command byte to BCh to
read the hardware ALARM configuration register. Bits
D15–D12 are don’t care. Set the INTEMP bit, D11, to 1
to cause ALARM comparisons for channel 2 to use the
internal temperature conversion result. Set the
ALMCMP bit, D10, to 1 to set the ALARM output in
comparator mode. Set ALMCMP to 0 to set the ALARM
output in interrupt mode. See Figure 25.
Set the ALM2CLMP1/0 bits, D5 and D4, to control
whether or not the GATE2 output is clamped to the
external voltage at ACLAMP2. See Table 12c. Set the
ALM1CLMP1/0 bits, D3 and D2, to control whether or
not the GATE1 output is clamped to the external volt-
age at ACLAMP1. See Table 12c and the Automatic
GATE Clamping section. Set the ALMPOL bit, D1, to 1
make the ALARM output active-low. Set ALMPOL to 0
to make the ALARM output active-high. Set the
ALMOPN bit, D0, to 1 to make the ALARM output an
open-drain output. Set ALMOPN to 0 to force the
ALARM output to be push-pull.
When operating in windowing mode, set the
VGHYST1/0 bits, D9 and D8, to control the GATE_ volt-
age ALARM hysteresis level. This hysteresis level
applies to both channel 1 and channel 2. See Table
12a and Figure 25. When operating in windowing
mode, set the ITHYST1/0 bits, D7 and D6, to control the
4± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 12a0 GATE ꢁoltaꢂe Hcsteresis Levels
ꢁGHYST1
ꢁGHYST±
FUNCTION
0
0
0
1
8 LSBs of hysteresis.
16 LSBs of hysteresis.
1
1
0
1
32 LSBs of hysteresis.
64 LSBs of hysteresis.
Table 12b0 Sense ꢁoltaꢂe/Temperature Hcsteresis Levels
ITHYST1
ITHYST±
FUNCTION
0
0
1
1
0
1
0
1
8 LSBs of hysteresis.
16 LSBs of hysteresis.
32 LSBs of hysteresis.
64 LSBs of hysteresis.
Table 12ꢀ0 ALARM Clamp Modes
ALM_CLMP1
ALM_CLMP±
FUNCTION
Default state. The GATE_ outputs are clamped to the respective external voltage applied at
ACLAMP_ independent of alarms. GATE_ remains clamped until this register value is changed
or a software clear command is issued.
0
0
The corresponding ALARM bit in the ALARM flag register goes high if an alarm condition is
triggered by a conversion of sense voltage, temperature, or GATE_ voltage. However, the
GATE_ outputs are not clamped.
0
1
1
0
Fully automatic clamping. The GATE_ outputs are clamped to the respective external voltage
applied at ACLAMP_ when an alarm condition is triggered. The clamp is removed if a
subsequent temperature or sense voltage conversion removes the alarm condition. GATE_
remains clamped when a GATE_ voltage alarm is triggered. For a GATE_ voltage alarm,
ALM_CLMP 10 mode functions the same as 11 mode. This exception breaks the feedback
loop created by sampling GATE_ voltage and then clamping the same signal.
Semi-automatic clamping. The GATE_ outputs are clamped to the respective external voltage
applied at ACLAMP_ when an alarm condition is triggered. If an ALARM condition is triggered,
the ALM_CLMP bits are overwritten to 00, causing a permanent clamp condition. Clear this
permanent clamp condition with a subsequent write to reset the ALM_CLMP bits.
1
1
ALMSCFG (Read/Write)
Set the TALARM2 bit, D9, to 1 to enable alarm function-
ality for channel 2 temperature measurements. Set the
TWIN2 bit, D8, to 1 to monitor the channel 2 tempera-
ture with the ALARM comparator in windowing mode.
Set TWIN2 to 0 to monitor the channel 2 temperature
with the ALARM comparator in hysteresis mode. Set the
IALARM2 bit, D7, to 1 to enable alarm functionality for
channel 2 sense voltage (RCS2+ to RCS2-) measure-
ments. Set the IWIN2 bit, D6, to 1 to monitor the chan-
nel 2 sense voltage with the ALARM comparator in
windowing mode. Set IWIN2 to 0 to monitor the channel
2 sense voltage with the ALARM comparator in hystere-
sis mode.
The software ALARM configuration register controls
which voltage and temperature channels trigger the
ALARM output and whether the ALARM comparators
operate in windowing or hysteresis mode. Set the com-
mand byte to 3Eh to write to the software ALARM con-
figuration register. Set the command byte to BEh to
read the software ALARM configuration register. Bits
D15–D12 are don’t care. Set the VALARM2 bit, D11, to
1 to enable alarm functionality for GATE2 voltage mea-
surements. Set the VWIN2 bit, D10, to 1 to monitor the
GATE2 voltage with the ALARM comparator in window-
ing mode. Set VWIN2 to 0 to monitor the GATE2 voltage
with the ALARM comparator in hysteresis mode.
______________________________________________________________________________________ 41
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 130 ALMSCFG (Read/Write)
ꢃIT NAME DATA ꢃIT RESET STATE
FUNCTION
X
D15–D12
D11
X
0
Don’t care.
Channel 2 GATE voltage ALARM bit. Set to 1 to enable the alarm functionality for
GATE2 voltage measurements. Set to 0 to disable the alarm functionality for GATE2
voltage measurements.
VALARM2
Channel 2 GATE voltage windowing bit. Set to 1 to monitor the GATE2 voltage with the
ALARM comparator in windowing mode. Set to 0 to monitor the GATE2 voltage with the
ALARM comparator in hysteresis mode.
VWIN2
TALARM2
TWIN2
D10
D9
0
0
0
Channel 2 temperature ALARM bit. Set to 1 to enable the alarm functionality for
channel 2 temperature measurements. Set to 0 to disable the alarm functionality for
channel 2 temperature measurements.
Channel 2 temperature windowing bit. Set to 1 to monitor the channel 2 temperature
with the ALARM comparator in windowing mode. Set to 0 to monitor the channel 2
temperature with the ALARM comparator in hysteresis mode.
D8
Channel 2 sense voltage ALARM bit. Set to 1 to enable the alarm functionality for
channel 2 sense voltage measurements. Set to 0 to disable the alarm functionality for
channel 2 sense voltage measurements.
IALARM2
IWIN2
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Channel 2 sense voltage windowing bit. Set to 1 to monitor the channel 2 sense
voltage with the ALARM comparator in windowing mode. Set to 0 to monitor the
channel 2 sense voltage with the ALARM comparator in hysteresis mode.
Channel 1 GATE voltage ALARM bit. Set to 1 to enable the alarm functionality for
GATE1 voltage measurements. Set to 0 to disable the alarm functionality for GATE1
voltage measurements.
VALARM1
VWIN1
Channel 1 GATE voltage windowing bit. Set to 1 to monitor the GATE1 voltage with the
ALARM comparator in windowing mode. Set to 0 to monitor the GATE1 voltage with the
ALARM comparator in hysteresis mode.
Channel 1 temperature ALARM bit. Set to 1 to enable the alarm functionality for
channel 1 temperature measurements. Set to 0 to disable the alarm functionality for
channel 1 temperature measurements.
TALARM1
TWIN1
Channel 1 temperature windowing bit. Set to 1 to monitor the channel 1 temperature
with the ALARM comparator in windowing mode. Set to 0 to monitor the channel 1
temperature with the ALARM comparator in hysteresis mode.
Channel 1 sense voltage ALARM bit. Set to 1 to enable the alarm functionality for
channel 1 sense voltage measurements. Set to 0 to disable the alarm functionality for
channel 1 sense voltage measurements.
IALARM1
IWIN1
Channel 1 sense voltage windowing bit. Set to 1 to monitor the channel 1 sense
voltage with the ALARM comparator in windowing mode. Set to 0 to monitor the
channel 1 sense voltage with the ALARM comparator in hysteresis mode.
42 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 140 ꢁSET1 and ꢁSET2 (Write)
ꢃIT NAME
X
DATA ꢃIT
D15–D12
D11–D0
RESET STATE
FUNCTION
X
Don’t care.
VSET11–VSET0
0000 0000 0000 VSET11 is the MSB and VSET0 is the LSB. Data format is straight binary.
Table 1.0 USRK1 and USRK2 (Write)
ꢃIT NAME
X
DATA ꢃIT
D15–D12
D11–D0
RESET STATE
FUNCTION
X
Don’t care.
K11 is the MSB and K0 is the LSB. Data format is straight binary.
K11–K0
N/A
Set the VALARM1 bit, D5, to 1 to enable alarm function-
ality for GATE1 voltage measurements. Set the VWIN1
bit, D4, to 1 to monitor the GATE1 voltage with the
ALARM comparator in windowing mode. Set VWIN1 to 0
to monitor the GATE1 voltage with the ALARM compara-
tor in hysteresis mode. Set the TALARM1 bit, D3, to 1 to
enable alarm functionality for channel 1 temperature
measurements. Set the TWIN1 bit, D2, to 1 to monitor the
channel 1 temperature with the ALARM comparator in
windowing mode. Set TWIN1 to 0 to monitor the channel
1 temperature with the ALARM comparator in hysteresis
mode. Set the IALARM1 bit, D1, to 1 to enable alarm
functionality for channel 1 sense voltage (RCS1+ to
RCS1-) measurements. Set the IWIN1 bit, D0, to 1 to
monitor the channel 1 sense voltage with the ALARM
comparator in windowing mode. Set IWIN1 to 0 to moni-
tor the channel 1 sense voltage with the ALARM com-
parator in hysteresis mode.
USRK1 and USRK2 (Write)
Write to the channel 1/channel 2 K parameter registers
to set the LUT [K] code in the V
equation.
DAC(CODE)
K
The K parameter register value is loaded into the
equation when the KSRC_ bits in the soft-
V
DAC(CODE)
ware configuration register are set to 010, 101, 110, or
111. See Table 11b. Use the K parameter as an index
to the K LUT or as a multiplier for the V
DAC(CODE)
by writing to the soft-
equation in place of V
SET(CODE)
ware configuration register. See Table 11. Set the com-
mand byte to 44h to write to the channel 1 K parameter
register. Set the command byte to 46h to write to the
channel 2 K parameter register. See Table 15. Bits
D15–D12 are don’t care. Bits D11–D0 contain the
straight binary data.
IPDAC1 and IPDAC2 (Write)
Write to the channel 1/channel 2 DAC input registers to
load the DAC code and bypass a V
calcula-
DAC(CODE)
VSET1 and VSET2 (Write)
tion. Transfer the code written to the DAC input registers
to the channel 1/channel 2 DAC output registers by set-
ting the corresponding DACCH_ bit high in the software
load DAC register. Set the command byte to 48h and
4Ch, respectively, to write to the channel 1/channel 2
DAC input registers. See Table 16. Bits D15–D12 are
don’t care. Bits D11–D0 contain the straight binary data.
Write to the channel 1/channel 2 V
registers to set
SET
the V
code in the V
equations.
SET(CODE)
DAC(CODE)
Writing to these registers triggers a V
calcu-
DAC(CODE)
lation. That code is then loaded into either the channel
1/channel 2 DAC input register or channel 1/channel 2
DAC input and output register, depending on the state
of the LDAC1/LDAC2 bits in the software configuration
register. Set the command byte to 40h to write to the
Writing to these registers overwrites any previous val-
ues loaded from the V
calculation.
DAC(CODE)
channel 1 V
register. Set the command byte to 42h
SET
to write to the channel 2 V
register. See Table 14.
SET
Bits D15–D12 are don’t care. Bits D11–D0 contain the
straight binary data.
______________________________________________________________________________________ 43
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 160 IPDAC1 and IPDAC2 (Write)
ꢃIT NAME
X
DATA ꢃIT
D15–D12
D11–D0
RESET STATE
FUNCTION
X
Don’t care.
DAC11–DAC0
0000 0000 0000 DAC11 is the MSB and DAC0 is the LSB. Data format is straight binary.
Table 170 THRUDAC1 and THRUDAC2 (Write)
ꢃIT NAME
X
DATA ꢃIT
D15–D12
D11–D0
RESET STATE
FUNCTION
X
Don’t care.
DAC11–DAC0
N/A
DAC11 is the MSB and DAC0 is the LSB. Data format is straight binary.
Table 180 PGACAL (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D5
X
Don’t care.
Channel 2 high-side calibration bit. Set to 1 to short circuit the current-
sense amplifier inputs so that only the offset is apparent at the
PGAOUT2 output and the channel 2 current-sense conversion.
HVCAL2
HVCAL1
D4
D3
0
0
Channel 1 high-side calibration bit. Set to 1 to short circuit the current-
sense amplifier inputs so that only the offset is apparent at the
PGAOUT1 output and the channel 1 current-sense conversion.
Acquisition/tracking bit. Set to 0 to force the next current-sense
calibration to run in acquisition mode. Set to 1 to force the next
calibration to run in tracking mode. Set TRACK to 0 the first time through
a calibration.
TRACK
DOCAL
D2
D1
D0
0
0
0
Dual calibration bit. Set to 1 to run a current-sense self-calibration routine
in both channels 1 and 2. At the end of the calibration routine, DOCAL is
set to 0. When DOCAL and SELFTIME are both set to 1, the internal timer
is reset at the end of the routine and waits another 13ms before
performing the next self-timed calibration.
Self-time bit. Set to 1 to perform a calibration of the current-sense
amplifier in both channels 1 and 2 on a self-timed periodic basis
(approximately every 15ms). When set to the default state of 0,
calibration only occurs when DOCAL is set to 1.
SELFTIME
THRUDAC1 and THRUDAC2 (Write)
PGACAL (Write)
Write to the PGA calibration control register to calibrate
the channel 1 and channel 2 current-sense amplifiers.
Set the command byte to 5Eh to write to the PGA cali-
bration control register. See Table 18. Bits D15–D5 are
don’t care. Set the HVCAL2 bit, D4, to 1 to short circuit
the channel 2 current-sense amplifier inputs so that
only the offset is apparent at the PGAOUT2 output. Set
the HVCAL1 bit, D3, to 1 short circuit the channel 1 cur-
rent-sense amplifier inputs so that only the offset is
apparent at the PGAOUT1 output. Determine the input
channel offset (+12mV, typ) by setting the HVCAL_bits
and commanding a sense-voltage ADC conversion.
Write to the channel 1/channel 2 DAC input and output
registers to load the DAC code directly to the respec-
tive DAC output and bypass a V
calculation.
DAC(CODE)
Set the command byte to 4Ah and 4Eh, respectively, to
write to the channel 1/channel 2 DAC input and output
registers. See Table 17. Bits D15–D12 are don’t care.
Bits D11–D0 contain the straight binary data.
Writing to these registers overwrites any previous val-
ues loaded from the V
calculation.
DAC(CODE)
44 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
The current-sense calibration routine offers two opera-
Convert any combination of ADC channels through the
ADC conversion register. When requesting a conver-
sion of more than one channel, the channels are con-
verted in numerical order from CH0 to CH10.
tion modes: acquisition and tracking. In acquisition
mode, the calibration routine operates continuously
until the error is minimized to 50µV or less. In tracking
mode, the routine operates every 15ms to minimize
interference and allow the calibration routine more
averaging time. A sample-and-hold circuit prevents
switching noise on GATE_ during tracking mode. Set
the TRACK bit, D2, to 0 to run the calibration routine in
acquisition mode. Set TRACK to 1 to run the calibration
routine in tracking mode. Set TRACK to 0 for the first
calibration.
Setting the CONCONV bit to 1 may cause the FIFO to
overflow if data is not read out quickly enough.
Continuous-conversion mode is only available in clock
modes 00 and 01. See the Clock Mode 00 and Clock
Mode 01 sections. The ADC does not trigger a busy
signal when the CONCONV bit is set. If a temperature
channel is included in the scan when CONCONV is set,
the internal reference and temperature sensor remain
powered up until CONCONV is set to 0. Similarly, if an
ADC measurement using the internal reference is
included in the scan, the internal reference is turned on
prior to the first conversion and remains on until
CONCONV is set to 0.
Set the DOCAL bit, D1, to 1 to run a current-sense
self-calibration routine in both channel 1 and channel 2.
At the end of the calibration routine, DOCAL is set back
to 0. Set the SELFTIME bit, D0, to 1 to perform a cur-
rent-sense calibration on a periodic basis, typically
every 15ms. Use the DOCAL bit in conjunction with the
SELFTIME bit. When a calibration routine is command-
ed by DOCAL, and SELFTIME is set to 1, the internal
timer is reset at the end of the routine and waits another
15ms before performing the next self-timed calibration.
In clock modes 00 and 01, when the CONCONV bit is
set to 0 and the current scan (not just the current con-
version) is completed, the ADC goes to an idle state
awaiting the next command. The BUSY output is set
high when the CONCONV bit is set to 0 and remains
high until the current scan is completed. See the BUSY
Output section.
The self-calibration routine can be commanded when
the DACs are powered down, but the results are not
accurate. For best results, run the calibration after the
SHUT (Write)
Shut down all internal blocks, as well as the DACs,
ADCs, and gate-drive amplifiers individually, through
the shutdown register. See Table 20. Set the command
byte to 64h to write to the shutdown register. Bits
D15–D12 are don’t care. Set the FULLPD bit, D11, to 1
DAC power-up time, t
.
DPUEXT
ADCCON (Write)
Write to the ADC conversion register to convert the
ADCIN_, GATE_, internal DAC and sense voltages. The
ADC conversion register also converts the internal and
external temperature readings and sets the interface for
continuous conversion. See Table 19. Set the com-
mand byte to 62h to write to the ADC conversion regis-
ter. Bits D15–D12 are don’t-care bits. The ADCMON bit
in the hardware configuration register must be set to 1
to load ADC results into the FIFO. Set the CONCONV
bit, D11, to 1 for continuous ADC conversions.
to shut down all internal blocks and reduce AV
sup-
DD
ply current to 0.8µA. The FULLPD bit is set to 1 at
power-up. Set the FULLPD bit to 0 before writing any
other commands to activate all internal blocks and
functionality.
Set the FBGON bit, D10, to 1 to keep the internal
bandgap reference powered up. Set the WDGPD bit,
D9, to 1 to turn off the watchdog oscillator and prevent
self-monitoring of the watchdog timer. Set the OSCPD
bit, D8, to 1 to power down the internal oscillator. Set
the PD2-3 bit, D7, to 1 to power down the channel 2
current-sense amplifier. Set the PD2-2 bit, D6, to 1 to
power down the channel 2 gate-drive amplifier. Set the
PD2-1 bit, D5, to 1 to power down the channel 2 DAC
summing node. Set the PD2-0 bit, D4, to 1 to power
down the channel 2 DAC. Set the PD1-3 bit, D3, to 1 to
power down the channel 1 current-sense amplifier. Set
the PD1-2 bit, D2, to 1 to power down the channel 1
gate-drive amplifier. Set the PD1-1 bit, D1, to 1 to
power down the channel 1 DAC summing node. Set the
PD1-0 bit, D0, to 1 to power down the channel 1 DAC.
Set the CH10 bit, D10, to 1 to convert the ADCIN2 volt-
age. Set the CH9 bit, D9, to 1 to convert the GATE2
voltage. Set the CH8 bit, D8, to 1 to convert the channel
2 DAC code. Set the CH7 bit, D7, to 1 to convert the
channel 2 sense voltage. Set the CH6 bit, D6, to 1 to
convert the channel 2 external temperature sensor
measurement. Set the CH5 bit, D5, to 1 to convert the
ADCIN1 voltage. Set the CH4 bit, D4, to 1 to convert
the GATE1 voltage. Set the CH3 bit, D3, to 1 to convert
the channel 1 DAC code. Set the CH2 bit, D2, to 1 to
convert the channel 1 sense voltage. Set the CH1 bit,
D1, to 1 to convert the channel 1 external temperature
sensor measurement. Set the CH0 bit, D0, to 1 to con-
vert the internal temperature sensor measurement.
______________________________________________________________________________________ 4.
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 190 ADCCON (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D12
X
Don’t care.
Set to 1 to command continuous ADC conversions. The ADCMON bit in
the hardware configuration register must be to set to 1 to load ADC
results into the FIFO. Continuous conversions are only applicable in clock
modes 00 and 01. When CONCONV is set to 1, the ADC continuously
converts the channels selected by the ADC conversion register using the
conversion mode selected by the CKSEL1/CKSEL0 bits. Results are
accumulated in the FIFO. Empty the FIFO quickly enough to prevent
overflow conditions.
CONCONV
D11
0
CH10
CH9
D10
D9
0
0
Set to 1 to convert the ADCIN2 voltage in the next ADC conversion cycle.
Set to 1 to convert the GATE2 voltage in the next ADC conversion cycle.
Also, the PD2-3 bit in the shutdown register must be set to 0.
Set to 1 to convert the channel 2 DAC code in the next ADC conversion
cycle.
CH8
CH7
D8
D7
0
0
Set to 1 to convert the channel 2 sense voltage in the next ADC
conversion cycle.
Set to 1 to convert the channel 2 external temperature-sensor
measurement in the next ADC conversion cycle.
CH6
CH5
CH4
D6
D5
D4
0
0
0
Set to 1 to convert the ADCIN1 voltage in the next ADC conversion cycle.
Set to 1 to convert the GATE1 voltage in the next ADC conversion cycle.
Also, the PD1-3 bit in the shutdown register must be set to 0.
Set to 1 to convert the channel 1 DAC code in the next ADC conversion
cycle.
CH3
CH2
CH1
CH0
D3
D2
D1
D0
0
0
0
0
Set to 1 to convert the channel 1 sense voltage in the next ADC
conversion cycle.
Set to 1 to convert the channel 1 external temperature sensor
measurement in the next ADC conversion cycle.
Set to 1 to convert the internal temperature sensor measurement in the
next ADC conversion cycle.
For maximum accuracy, power up all internal blocks
prior to a calibration (MAX11014). The MAX11015 does
not require the current-sense amplifier to be powered
up for a calibration.
Set the DACCH2 bit, D1, to 1 to load the channel 2
DAC output register with the value stored in the chan-
nel 2 DAC input register. Set the DACCH1 bit, D0, to 1
to load the channel 1 DAC output register with the
value stored in the channel 1 DAC input register. See
Figure 20.
LDAC (Write)
Write to the software load DAC register to load the val-
ues stored in the DAC input registers to their respective
DAC output registers. Set the command byte to 66h to
write to the software load DAC register. See Table 21.
Bits D15–D2 are don’t care.
46 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 2±0 SHUT (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D12
X
Don’t care.
Set to 1 to power down all internal blocks. FULLPD takes precedence
over any of the other power-down control bits. All commands in progress
are suspended and the DACs and ADC are disabled. The serial
interface remains functional. FULLPD is set to 1 on power-up. Set the
FULLPD bit to 0 after power-up and before writing any other commands
to activate all internal blocks.
FULLPD
FBGON
D11
D10
1
0
Set to 1 to force the internal bandgap voltage block to power up, remain
powered up between conversions, and avoid the 50µs reference power-
up delay time. Forcing the internal reference to remain on increases the
power dissipation. Set FBGON to its default state of 0 to power the
bandgap voltage as required by the ADC.
Set to 1 to turn off the watchdog oscillator. The watchdog oscillator
monitors the internal ALU and resets the logic state to the startup
condition after 80ms. This reduces power consumption but prevents the
self-monitoring function of the watchdog timer.
WDGPD
OSCPD
D9
D8
0
0
Set to 1 to power down the internal oscillator. OSCPD is automatically
reset to 0 after receiving the next interface command.
PD2-3
PD2-2
D7
D6
1
1
Set to 1 to power down the channel 2 current-sense amplifier.
Set to 1 to power down the channel 2 gate-drive amplifier.
Set to 1 to power down the channel 2 DAC summing node
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
PD2-1
D5
1
PD2-0
PD1-3
PD1-2
D4
D3
D2
1
1
1
Set to 1 to power down the channel 2 DAC.
Set to 1 to power down the channel 1 current-sense amplifier.
Set to 1 to power down the channel 1 gate-drive amplifier.
Set to 1 to power down the channel 1 DAC summing node
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
PD1-1
PD1-0
D1
D0
1
1
Set to 1 to power down the channel 1 DAC.
Table 210 LDAC (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D2
X
Don’t care.
Set to 1 to load the channel 2 DAC output register with the value stored
in the channel 2 DAC input register.
DACCH2
DACCH1
D1
D0
N/A
N/A
Set to 1 to load the channel 1 DAC output register with the value stored
in the channel 1 DAC input register.
______________________________________________________________________________________ 47
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 220 SCLR (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D7
X
Don’t care.
Write the following sequence to perform a full reset and return all internal
registers to their respective reset state:
Write to the software clear register once with FULLRESET = 0 and
ARMRESET = 1. Write a second word to the software clear register with
FULLRESET = 1 and ARMRESET = 0.
The full reset takes effect after completion of the second write to this
register.
After a full software reset, the internal registers return to their power-on
state, but the internal oscillator remains running (unlike at power-up).
After a full software reset, it is not necessary to set the FULLPD bit to 0
(as it is on a normal power-on reset) before attempting any other
commands. The BUSY output is set high and the ALU initializes internal
RAM before setting BUSY low.
FULLRESET
ARMRESET
D6
D5
N/A
0
Set to 1 to reset all ALARM threshold registers and the ALARM flag
register.
ALMSCLR
D4
D3
N/A
N/A
Set to 1 to force the ALU to clear the pointers and lookup value cache to
their power-up values. This forces an LUT operation and a V
DAC(CODE)
CACHECLR
calculation for the next sample, regardless of whether the sample
produces a table pointer that is different.
FIFOCLR
DAC2CLR
DAC1CLR
D2
D1
D0
N/A
N/A
N/A
Set to 1 to reset the FIFO address pointers and clear the FIFO’s contents.
Set to 1 to reset the channel 2 DAC input and output registers.
Set to 1 to reset the channel 1 DAC input and output registers.
Table 230 LUTADD (Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
LUTWORD7–
LUTWORD0
Set these 8 bits to determine the number of LUT words to be
read/written.
D15–D8
0000 0000
LUTADD7–
LUTADD0
Set these 8 bits to determine the base address for the read/write
operation.
D7–D0
0000 0000
SCLR (Write)
with FULLRESET = 1 and ARMRESET = 0. The full
reset takes effect after completion of the second
write to this register.
Write to the software clear register to reset all of the
internal registers, clear the internal ALU or reset the
FIFO pointers and clear the FIFO. This register also
resets the ALARM threshold registers, ALARM flag reg-
ister and the DAC registers. Set the command byte to
74h to write to the software clear register. See Table 22.
Bits D15–D7 are don’t care. The FULLRESET bit, D6,
and ARMRESET bit, D5, provide functionality for a full
reset. Write the following sequence to perform a full
reset and return all internal register bits to their respec-
tive reset state:
Set the ALMSCLR bit, D4, to 1 to reset all ALARM thresh-
old register bits and the ALARM flag register bits. Set the
CACHECLR bit, D3, to 1 to force the ALU to clear the
pointers and lookup value cache to their power-up val-
ues. This forces a LUT operation and a V
cal-
DAC(CODE)
culation for the next sample, regardless of whether the
sample produces a table pointer that is different. Set the
FIFOCLR bit, D2, to 1, reset the FIFO address pointers,
and clear the FIFO’s contents. Set the DAC2CLR bit, D1,
to 1 to reset the channel 2 DAC input and output register
bits. Set the DAC1CLR bit, D0, to 1 to reset the channel 1
DAC input and output register bits.
•
Write to the software clear register once with
FULLRESET = 0 and ARMRESET = 1.
•
Write a second word to the software clear register
48 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 240 LUTDAT (Read/Write)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
LUTDAT15–
LUTDAT0
D15–D0
N/A
The 16-bit data word written to the LUT data or configuration memory space.
Table 2.0 FIFO
DATA ꢃITS
CONꢁERSION-DATA ORIGIN
CHANNEL TAG
D11
D1±–D1
D±
D1.
0
D14
0
D13
0
D12
0
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
—
—
—
—
—
—
—
—
—
—
—
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Internal temperature sensor.
Channel 1 external temperature sensor.
Channel 1 sense voltage.
Channel 1 DAC input register.
Channel 1 GATE voltage.
ADCIN1 voltage.
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
Channel 2 external temperature sensor.
Channel 2 sense voltage.
Channel 2 DAC input register.
Channel 2 GATE voltage.
ADCIN2 voltage.
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
Reserved.
LUT data value. See Table 28. Bit D12 is the MSB for the
LUT configuration words. Bit D11 is the MSB for all other
LUT reads.
1
1
0
D12
D11
—
LSB
Conversion may be corrupted. This occurs only when
arriving data causes the FIFO to overflow at the same time
data is being read out.
1
1
1
1
1
1
0
1
MSB
MSB
—
—
LSB
LSB
Empty FIFO. The current value of the flag register is read
out in place of the FIFO data.
LUTADD (Write)
LUTDAT (Read/Write)
Write or read LUT data through the LUT data register.
Set the command byte to 7Ch to write to the LUT data
register. Set the command byte to FCh to read from the
LUT data register. Write 16 bits of data to the LUT data
register to load individual address locations with lookup
data. See Table 24. The address in the LUT memory
space is automatically incremented after each LUT
data register write command.
Write to the LUT address register to determine the num-
ber of write/read LUT locations, the base address
pointer, and the LUT configuration word. See Table 23.
Set the command byte to 7Ah to write to the LUT
address register. Set the LUTWORD bits, D15–D8, to
the number of LUT words to be read/written. Set the
LUTADD bits, D7–D0, to determine the base address
for the read/write operation.
If the top of LUT memory is reached before the
LUTWORD limit is reached, the LUT data register
read/write is discontinued. Write 00h to the LUTWORD
bits to abort an LUT read/write. See the SRAM LUTs
section for details on programming the various
LUT addresses. See Table 28 for a map of the LUT
address locations.
Differentiate LUT data from ADC data from the unique
LUT data channel tag 110_. See Table 25.
______________________________________________________________________________________ 49
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 260 FLAG (Read)
RESET
ꢃIT NAME
DATA ꢃIT
FUNCTION
X
D15–D7
X
Don’t care.
RESTART is set to 1 after either a watchdog timer reset or by commanding a
software reset through the software clear register’s FULL RESET function.
RESTART returns to 0 after a power-on reset or a flag register read command.
RESTART
D6
0
ALUBUSY is set to 1 when the ALU is performing other tasks not covered by
specific status bits elsewhere in this register. This includes, for example, the
internal memory initialization after power-up.
ALUBUSY
PGABUSY
ADCBUSY
VGBUSY
D5
D4
D3
D2
D1
0
0
0
1
1
PGABUSY is set to 1 when the ALU is performing a PGA calibration (whether
commanded or self-timed).
ADCBUSY is set to 1 when the ADC is busy, an ALARM value is being checked,
or the ADC results are being loaded into the FIFO. ADCBUSY returns to 0 after
the ADC completes all of the conversions in the current scan.
VGBUSY is set to 1 when the ALU is performing a lookup and interpolation or
V
calculation for either channel.
DAC(CODE)
FIFOEMP is set to 1 when the FIFO is empty and contains no data. FIFOEMP is
reset to 0 if data is written into the FIFO. Writing to the software clear register with
FIFOCLR set to 1 causes the FIFO to be cleared, which then sets FIFOEMP to 1.
FIFOEMP
FIFOOVR functions in one of two modes:
1) Reading the ADC data: FIFOOVR is set to 1 if the FIFO has a data overflow.
FIFOOVR is reset to 0 by reading the flag register or by clearing the FIFO
through the software clear register. Emptying the FIFO does not clear the
FIFOOVR bit.
FIFOOVR
D0
0
2) Reading the LUT data: When commanding an LUT read, the FIFO is no longer
allowed to overflow (as it is for normal ADC monitoring). FIFOOVR is set to 1 if
the LUT is full and set to 0 if the LUT is not full, for that instant in time only.
FIFO
FLAG (Read)
Read from the flag register to determine the source of a
busy condition. Set the command byte to F6h to read
the flag register. Bits D15–D7 are don’t care. See Table
26. The RESTART bit, D6, is set to 1 after either a
watchdog timer reset or by commanding a software
reset through the software clear register’s FULL RESET
function. RESTART is reset to a 0 after a power-on reset
or a flag register read command. The ALUBUSY bit,
D5, is set to 1 when the ALU is performing other tasks
not covered by specific status bits elsewhere in this
register. The PGABUSY bit, D4, is set to 1 when the
ALU is performing a PGA calibration.
Read the oldest result in the FIFO by writing command
byte 80h and reading the next 16 bits at DOUT in SPI
2
mode and SDA in I C mode. Bits D15–D12 (channel
tag) identify which ADC or LUT channel is being con-
verted. Bits D11–D0 contain the ADC/LUT conversion
results for that specific channel. Bit D11 is the MSB and
bit D0 is the LSB for all ADC and LUT data, with the
exception of the LUT configuration words. When read-
ing the LUT configuration registers, bit D12 is the MSB
and bit D0 is the LSB. See Table 25.
.± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 270 ALMFLAG (Read)
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
X
D15–D12
X
Don’t care.
HIGH-V2 is set to 1 when the GATE2 voltage exceeds the high threshold
setting. HIGH-V2 is reset to 0 by either a read of the ALARM flag register
or a software clear command.
HIGH-V2
LOW-V2
HIGH-I2
LOW-I2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
LOW-V2 is set to 1 when the GATE2 voltage decreases below the low
threshold setting. LOW-V2 is reset to 0 by either a read of the ALARM
flag register or a software clear command.
HIGH-I2 is set to 1 when the channel 2 sense voltage exceeds the high
threshold setting. HIGH-I2 is reset to 0 by either a read of the ALARM
flag register or a software clear command.
LOW-I2 is set to 1 when the channel 2 sense voltage decreases below
the low threshold setting. LOW-I2 is reset to 0 by either a read of the
ALARM flag register or a software clear command.
HIGH-T2 is set to 1 when the channel 2 external temperature exceeds
the high threshold setting. HIGH-T2 is reset to 0 by either a read of the
ALARM flag register or a software clear command.
HIGH-T2
LOW-T2
HIGH-V1
LOW-V1
HIGH-I1
LOW-I1
LOW-T2 is set to a 1 when the channel 2 external temperature
decreases below the low threshold setting. LOW-T2 is reset to 0 by
either a read of the ALARM flag register or a software clear command.
HIGH-V1 is set to 1 when the GATE1 voltage exceeds the high threshold
setting. HIGH-V1 is reset to 0 by either a read of the ALARM flag register
or a software clear command.
LOW-V1 is set to 1 when the GATE1 voltage decreases below the low
threshold setting. LOW-V1 is reset to 0 by either a read of the ALARM
flag register or a software clear command.
HIGH-I1 is set to 1 when the channel 1 sense voltage exceeds the high
threshold setting. HIGH-I1 is reset to 0 by either a read of the ALARM
flag register or a software clear command.
LOW-I1 is set to 1 when the channel 1 sense voltage decreases below
the low threshold setting. LOW-I1 is reset to 0 by either a read of the
ALARM flag register or a software clear command.
HIGH-T1 is set to 1 when the channel 1 external temperature exceeds
the high threshold setting. HIGH-T1 is reset to 0 by either a read of the
ALARM flag register or a software clear command.
HIGH-T1
LOW-T1
LOW-T1 is set to a 1 when the channel 1 external temperature
decreases below the low threshold setting. LOW-T1 is reset to 0 by
either a read of the ALARM flag register or a software clear command.
______________________________________________________________________________________ .1
Automatic RF MESFET Amplifier
Drain-Current Controllers
The ADCBUSY bit, D3, is set to 1 when the ADC is
busy, an ALARM value is being checked, or the ADC
results are being loaded into the FIFO. ADCBUSY
returns to 0 after the ADC completes all of the conver-
sions in the current scan. The VGBUSY bit, D2, is set to
1 when the ALU is performing a lookup and interpola-
when the channel 1 external temperature exceeds the
high threshold setting. The LOW-T1 bit, D0, is set to a 1
when the channel 1 external temperature decreases
below the low threshold setting.
FIFO Description
The MAX11014/MAX11015’s FIFO stores 15 ADC sam-
ples or 16 SRAM LUT data words. Read the FIFO to
load the FIFO data onto DOUT in SPI mode and SDA in
tion or V
calculation for either channel. The
DAC(CODE)
FIFOEMP bit, D1, is set to 1 when the FIFO is empty
and contains no data. FIFOEMP is reset to 0 if data is
written into the FIFO. Writing to the software clear regis-
ter with FIFOCLR set to 1 causes the FIFO to be
cleared, which then sets FIFOEMP to 1.
2
I C mode. See Table 25. The ADC sample data
includes a 4-bit channel tag, followed by 12 bits of
data. The ADC channel tags indicate the source for the
temperature or voltage result. The LUT data includes a
3-bit channel tag for LUT configuration word data and a
4-bit tag for all other LUT data. The LUT tags indicate
whether the LUT data is temperature (T) or numerical
(K)-based. Do not mix ADC results with LUT results in
the FIFO.
The functionality of the FIFOOVR bit, D0, depends on
whether the FIFO is loaded with ADC data or LUT data.
FIFOOVR functions in one of two modes:
1) Reading the ADC data: FIFOOVR is set to 1 if the
FIFO has a data overflow. FIFOOVR is reset to 0
only by reading the flag register or by clearing the
FIFO through the software clear register. Emptying
the FIFO does not clear the FIFOOVR bit.
The FIFO allows overflows of ADC data and it always
contains the 15 most recent ADC conversion results.
Read the FIFO quickly enough to prevent an overflow
condition. Detect if the FIFO has overflowed (indicating
a loss of data) by inspecting the FIFOOVR bit in the flag
register.
The FIFO does not overflow while outputting SRAM LUT
data. Count how many words are output in order
(through the numerical representation of the LUTWORD
bits in the LUT address register) to tell which LUT data
word is being supplied.
2) Reading the LUT data: When commanding a LUT
read, the FIFO is no longer allowed to overflow.
FIFOOVR is set to 1 if the LUT is full and set to 0 if
the LUT is not full, for that instant in time only. See
the FIFO Description section.
ALMFLAG (Read)
Read the ALARM flag register to determine the source of
an alarm condition. Set the command byte to F8h to read
the ALARM flag register. Bits D15–D12 are don’t care.
See Table 27. Bits D11–D0 are all reset to 0 following a
read of the ALARM flag register or a software clear com-
mand. The HIGH-V2 bit, D11, is set to 1 when the GATE2
voltage exceeds the high threshold setting. The LOW-V2
bit, D10, is set to 1 when the GATE2 voltage decreases
below the low threshold setting. The HIGH-I2 bit, D9, is
set to 1 when the channel 2 sense voltage exceeds the
high threshold setting. The LOW-I2 bit, D8, is set to 1
when the channel 2 sense voltage decreases below the
low threshold setting. The HIGH-T2 bit, D7, is set to 1
when the channel 2 external temperature exceeds the
high threshold setting. The LOW-T2 bit, D6, is set to a 1
when the channel 2 external temperature decreases
below the low threshold setting.
ADC Monitoring Mode
Each time the ADC converts a sample in ADC monitor-
ing mode, the data word and its 4-bit channel tag are
moved into the FIFO. Load the data from the FIFO to
2
DOUT in SPI mode and SDA in I C mode by writing
command byte 80h.
The hardware configuration register’s ADCMON bit
determines whether ADC samples are loaded into the
FIFO. See Table 10. Set ADCMON to 1 to store ADC
samples in the FIFO. Set to 0 to not load ADC results
into the FIFO. The value of ADCMON does not affect
whether the results from any particular ADC conversion
are checked against the ALARM thresholds or exam-
ined for changes to the V
equations.
DAC(CODE)
After reading out all of the ADC FIFO data, the flag regis-
ter sets the FIFOEMP bit to 1. If a FIFO read command is
issued with the FIFO empty, the FIFO returns a channel
tag of 1111 and the 12 flag register bits. See Table 25.
The HIGH-V1 bit, D5, is set to 1 when the GATE1 volt-
age exceeds the high threshold setting. The LOW-V1
bit, D4, is set to 1 when the GATE1 voltage decreases
below the low threshold setting. The HIGH-I1 bit, D3, is
set to 1 when the channel 1 sense voltage exceeds the
high threshold setting. The LOW-I1 bit, D2, is set to 1
when the channel 1 sense voltage decreases below the
low threshold setting. The HIGH-T1 bit, D1, is set to 1
The FIFO allows interface reads to be simultaneous with
the arrival of new ADC sample or LUT data words. But
when the FIFO is full and overflowing, if an ADC sample
arrives at exactly the same time as an interface read,
there is a possibility of data corruption. This condition is
.2 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
FULL-SCALE TRANSITION
111...111
111...110
111...101
FS = V
REFADC
011....111
011....110
1 LSB = V
/ 4096
REFADC
000....010
000....001
000....000
111....111
111....110
111....101
000...011
000...010
000...001
000...000
100....001
100....000
0
-256°C
+255.5°C
FS
0
1
2
3
FS - 3/2 LSB
TEMPERATURE °C
INPUT VOLTAGE (LSB)
Figure 22. Temperature Transfer Function
Figure 21. ADC Transfer Function
indicated by channel tag 1110 (rather than the usual
ADC channel tag). In this case, only that particular data
item is corrupted and all other FIFO contents remain
valid and can be accessed with subsequent reads.
Output Data Format
All conversion data results are output in 2-byte format,
MSB first. Data transitions on DOUT on the falling
edges of SCLK in SPI mode. Data transitions on SDA
2
on the rising edge of SCL in I C mode. Figures 10, 18,
Read the FIFO quickly enough to prevent overflow
conditions to entirely avoid the risk of data corruption. At
fast serial-interface clock rates, it is possible to read data
from the FIFO faster than the ADC loads it. Set a continu-
ous ADC scan in progress and continuously read the
FIFO. Assuming the FIFO is being emptied more quickly
than it is being filled, the continuous FIFO reads supply a
mixture of empty channel tags (1111 and the flag regis-
ter value), mixed in with the valid ADC results. Separate
the valid ADC results from the flag register data based
on the 4-bit channel tag.
and 19 illustrate the MAX11014/MAX11015’s read tim-
ing. See Figures 21 and 22 for ADC and temperature
transfer functions, respectively.
ADC Transfer Function
Data is output in straight binary format, with the excep-
tion of temperature results/alarms, which are two’s
complement. Figure 21 shows the unipolar transfer
function for single-ended inputs. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = V
/ 2.5V
REFADC
for unipolar operation, and 1 LSB = +0.125°C for tem-
perature measurements.
SRAM LUT Read Mode
After an LUT data register read command, data from
the SRAM LUTs is copied into the FIFO. Load the data
PGAOUT Outputs
The PGAOUT output voltages are derived from a sense
voltage conversion. The dual current-sense amplifiers
amplify the voltage between RCS_+ and RCS_- by four
and add an offset voltage (+12mV nominally). The cur-
rent-sense amplifiers scale voltages up to +625mV. The
MAX11014’s Class A control loop detailed in Figure 5.
The MAX11015’s Class AB analog control is detailed in
Figure 6. Calculate the PGAOUT_ voltage with the fol-
lowing equation:
2
from the FIFO to DOUT in SPI mode and SDA in I C
mode by reading the FIFO. If SRAM LUT data is written
to the FIFO faster than its read out, the FIFO fills up.
The copying of data is suspended until the FIFO is read
again. If the FIFO is read more quickly than the SRAM
LUT loads the values, the data is interspersed with
error channel tags (1111 and the flag register value)
and valid LUT data.
V
= V
−[4 x (V
+ − V
−) + 12mV]
PGAOUT
REFADC
RCS
RCS
______________________________________________________________________________________ .3
Automatic RF MESFET Amplifier
Drain-Current Controllers
CNVST
ADCBUSY
(FLAG REGISTER BIT)
ALUBUSY
(FLAG REGISTER BIT)
BUSY (OUTPUT)
GATE1/2 OUTPUT
BUSY TIMING: EXAMPLE 1
CNVST
ADCBUSY
(FLAG REGISTER BIT)
ALUBUSY
(FLAG REGISTER BIT)
BUSY OUTPUT
BUSY TIMING: EXAMPLE 2
Figure 23. BUSY Timing
Write to the HVCAL_ bits in the PGA calibration control
register to short circuit the current-sense amplifier
inputs so that only the offset is apparent at the
PGAOUT_ output and ADC input.
ADC is converting (for all clock modes). This prevents
the continuous ADC activity from masking other
BUSY events.
The serial interface remains available regardless of the
state of BUSY, although certain commands are not
appropriate. For example, if BUSY is high for an ADC
operation, reading the FIFO does not produce the
result for the current conversion. Also, if BUSY triggers
due to an ADC conversion, do not enter a second con-
version command until BUSY returns low, indicating the
previous conversion is complete.
BUSY Output
The BUSY output goes high for a variety of reasons.
The possible causes of BUSY pulsing high include:
•
•
•
The ADC is converting, but not in continuous con-
version mode
The internal ALU core is performing a power-up
initialization
See Figure 23 for a pair of BUSY timing examples. In
example 1, an externally timed ADC conversion trig-
gers the ADCBUSY bit in the flag register and forces
The internal ALU core is performing a V
calculation
DAC(CODE)
BUSY high. Next, a V
calculation triggers the
DAC(CODE)
•
•
The internal ALU core is performing another function
The self-calibration routine is taking place
ALUBUSY bit in the flag register and holds BUSY high.
In example 2, the V
requested.
calculation is not
DAC(CODE)
When the CONCONV bit is set in the ADC conversion
register, the BUSY output does not trigger when the
.4 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
1111 1111 1111
MOST POSITIVE VALUE
(DEFAULT FOR HIGH
THRESHOLD REGISTERS)
ACTUAL
MEASUREMENT
VALUE; THEREFORE,
ALARM TRIGGERS
HIGH THRESHOLD
REGISTER VALUE
BUILT IN 8–64 LSBs
OF HYSTERESIS
WINDOW OF VALUES THAT DO N0T TRIGGER AN ALARM
BUILT IN 8–64 LSBs
OF HYSTERESIS
LOW THRESHOLD
REGISTER VALUE
0000 0000 0000
MOST NEGATIVE VALUE
(DEFAULT FOR LOW
THRESHOLD REGISTERS)
Figure 24. ALARM Window Comparator Example
VOLTAGE OR
TEMPERATURE
MEASUREMENT VALUE
HIGH
THRESHOLD
REGISTER
BUILT-IN
HYSTERESIS
BUILT-IN
HYSTERESIS
LOW
THRESHOLD
REGISTER
ALARM
COMPARATOR
(ACTIVE-LOW)
ALARM INTERRUPT
(ACTIVE-LOW)
TIME
READ ALARM
READ ALARM
READ ALARM
FLAG REGISTER
FLAG REGISTER
FLAG REGISTER
Figure 25. ALARM Window-Mode Timing Example
______________________________________________________________________________________ ..
Automatic RF MESFET Amplifier
Drain-Current Controllers
1111 1111 1111
MOST POSITIVE VALUE
(DEFAULT FOR HIGH
THRESHOLD REGISTERS)
ACTUAL MEASUREMENT
VALUE, THEREFORE
ALARM TRIGGERS
ALARM TRIGGERED
WHEN EXCEEDING
THIS LEVEL
HIGH THRESHOLD
REGISTER VALUE
ALARM REMOVED
AFTER CROSSING
BACK BELOW THIS
LEVEL
LOW THRESHOLD
REGISTER VALUE
WINDOW OF VALUES THAT DO NOT TRIGGER AN ALARM
0000 0000 0000
MOST NEGATIVE VALUE
(DEFAULT FOR LOW
THRESHOLD REGISTERS)
Figure 26. ALARM Hysteresis Comparator Example
register vary the built-in hysteresis between 8 and 64
LSBs. The built-in hysteresis acts as a noise filter to
prevent unnecessary switching when a sample value is
varying slightly around the threshold. The alarm condi-
tion remains in place until the measured value rises
above the low threshold value or falls below the high
threshold value. Figure 25 details a window-mode tim-
ing example.
ALARM Output
The ALARM output asserts when the corresponding
channel’s temperature or voltage readings exceed the
respective high or low ALARM threshold. Each time the
sense voltage, temperature (external for either channel,
internal for channel 2), or GATE_ voltage is converted,
the measured value is compared to the high and low
ALARM threshold values.
The ALARM output operates in interrupt or comparator
mode. In interrupt mode, the ALARM output asserts until
the alarm flag register is read. In comparator mode, the
ALARM output reflects the internal alarm state and
remains asserted for as long as the alarm conditions are
breached. The ALARM output deasserts after the win-
dowing or hysteresis conditions are satisfied.
The ALARM comparison operates in either window or
hysteresis mode. When operating in window compara-
tor mode (TWIN_, IWIN_, or VGWIN_ bits in the soft-
ware ALARM configuration register set to 1), the ADC
output values are monitored to ensure that the values
are between both the high and low ALARM threshold
register values. See Table 13 and Figure 24.
When operating in hysteresis comparator mode
(TWIN_, IWIN_, or VGWIN_ bits in the software ALARM
configuration register set to 0), the ADC output values
are monitored to ensure that the values are below the
Window comparisons include built-in hysteresis levels,
ensuring the ALARM output does not trigger repeatedly
when sampling values around the threshold. The
ALMHYST bits in the hardware ALARM configuration
.6 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
VOLTAGE OR
TEMPERATURE
MEASUREMENT VALUE
HIGH
THRESHOLD
REGISTER
LOW
THRESHOLD
REGISTER
ALARM
COMPARATOR
(ACTIVE-LOW)
ALARM INTERRUPT
(ACTIVE-LOW)
READ ALARM
READ ALARM
TIME
FLAG REGISTER
FLAG REGISTER
Figure 27. ALARM Hysteresis-Mode Timing Example
high set ALARM threshold register value. See Figure
26. If an ADC output value exceeds its respective
ALARM high threshold register value, the ALARM out-
put triggers. The alarm condition remains in place until
the measured value falls below the low threshold value.
Figure 27 details a hysteresis-mode timing example.
Each channel has four possible ALM_CLMP1/
ALM_CLMP0 values:
• ALM_CLMP1/ALM_CLMP0 = 00
Power-on reset state. GATE_ clamps through a
series 2.4kΩ resistor to the ACLAMP_, regardless
of any alarm condition. Reset these 2 bits before
attempting to change the DAC voltage.
When operating in interrupt mode, the ALARM output
triggers when the measured ADC output value exceeds
either the high or low threshold. However, in interrupt
mode, the ALARM output remains active until reading
the ALARM flag register. Reading the ALARM flag reg-
ister resets the flag bits and the ALARM output.
• ALM_CLMP1/ALM_CLMP0 = 01
The automatic GATE_ clamp is disabled in this mode.
The GATE_ outputs are not affected by any alarm
conditions. The ALARM output function operates nor-
mally (samples beyond their thresholds still cause
alarm flags to be set and ALARM behaves according
to the comparator/interrupt mode).
The default values for the high and low threshold regis-
ters are the extremes of the measured range (all 1s or
all 0s, respectively). The ALARM output can be config-
ured to be open-drain or push-pull and active-high or
active-low through the hardware ALARM configuration
register. See Table 12. At power-up, the ALARM output
is configured as an active-high output that operates in
interrupt mode.
• ALM_CLMP1/ALM_CLMP0 = 10
This mode provides fully automatic clamping. Prior to
an alarm condition, the GATE_ voltage is controlled
by the sense voltage (MAX11014) or the DAC setting
(MAX11015). When an alarm condition triggers, the
GATE_ voltage clamps to ACLAMP_. The clamp is
applied as long as the alarm condition is valid. The
GATE_ clamp is released when a subsequent ADC
conversion clears the alarm condition. The GATE_
voltage is then restored to the sense voltage/DAC set-
ting. Configure the ALARM output in comparator
mode to assert when the GATE_ clamp is active.
Automatic GATE Clamping
Configure the ALARM output to clamp the GATE1 out-
put to ACLAMP1 or GATE2 output to ACLAMP2 in
response to an alarm condition through the hardware
ALARM configuration register. See Table 12c. Set the
ALM_CLMP_ bits, D5–D2, to clamp the respective
channel’s GATE output.
______________________________________________________________________________________ .7
Automatic RF MESFET Amplifier
Drain-Current Controllers
For a GATE_ voltage alarm condition, GATE_ remains
clamped and ALM_CLMP 10 mode functions the same
as 11 mode. This exception breaks the feedback loop
that would have otherwise been created by sampling the
GATE_ voltage and then clamping that same voltage.
2) Issue a single read command of the LUT data reg-
ister. The MAX11014/MAX11015 then fill the FIFO
with the requested LUT data, starting with the data
at the LUTADD base address and incrementing
until reaching either the top of memory or the num-
ber of locations based on the LUTWORD code.
•
ALM_CLMP1/ALM_CLMP0 = 11
This mode provides semi-automatic clamping. Prior
to an alarm condition, the GATE_ voltage is controlled
by the sense voltage (MAX11014) or the DAC setting
(MAX11015). When an alarm condition is triggered,
the GATE_ voltage clamps to ACLAMP_. The clamp
holds the GATE_ output in this condition, even if sub-
sequent ADC samples are taken and all ALARM
channels are cleared. To release the clamp, rewrite
the ALM_CLMP1/ALM_CLMP0 bits to 11 or 01.
3) Read each of the 16-bit LUT data words (including
the 3- or 4-bit channel tag) from the FIFO at DOUT
2
in SPI mode and SDA in I C mode.
Begin a LUT write or read command by writing to the
LUT address register. See Table 23. This register sets
the LUT base address and the number of LUT locations
to be read in a subsequent read of the LUT data regis-
ter. Set the command byte to 7Ah to write to the LUT
address register. Set the LUTWORD bits, D15–D8, to
the number of LUT words (1 to 48) to be output during
a LUT read operation. Set the LUTADD bits, D7–D0, to
point to the base address of the LUT data. The
TLUT1-0 to TLUT1-47 (channel 1) values are stored at
addresses 00h to 2Fh. The TLUT2-0 to TLUT2-47
(channel 2) values are stored at addresses 30h to 5Fh.
The KLUT1-0 to KLUT1-47 (channel 1) values are
stored at addresses 60h to 8Fh. The KLUT2-0 to
KLUT2-47 (channel 2) values are stored at addresses
90h to BFh.
OPSAFE Inputs
Set the OPSAFE1 and OPSAFE2 inputs high to clamp
the GATE1 and GATE2 outputs to the externally applied
voltage at ACLAMP1 and ACLAMP2, respectively.
OPSAFE1/OPSAFE2 override any software commands.
The ALM_CLMP1/ALM_CLMP0 bits in the hardware
ALARM configuration register also provide clamping
functionality.
SRAM LUTs
The MAX11014/MAX11015 implement four independent
lookup tables (LUTs). The LUTs are temperature based
(TLUT) and numeric based (KLUT). Channel 1 and
channel 2 each have a separate T and K LUT. Each
LUT can store up to 48 separate data words. See
Figure 28. In addition to storing data values, the LUT
memory also contains configuration registers that spec-
ify LUT size, hysteresis bit value, and step size. Table
28 details how the LUTs are configured in memory.
The LUTs are defined by setting the following parameters:
1) The table’s base value
2) The step size of the table (how far apart the
entriesare)
3) The hysteresis threshold size
4) The size of the LUT (the number of entries)
LUT Configuration
Write a LUT configuration sequence to initialize the step
size, hysteresis threshold size, and size of the LUT.
Determine the respective channel’s temperature or K
LUT configuration with the following sequence:
Write data to the LUTs with the following sequence:
1) Write to the LUT address register to set the base
address for the first data word (the LUTWORD bits
are don’t care in LUT writes).
1) Set the LUTADD bits in the LUT address register to
C0h (TLUT1), C1h (TLUT2), C2h (KLUT1) or C3h
(KLUT2). See Table 28a.
2) Write to the LUT data register to write data values.
Each time the LUT data register is written, the
address in the LUT memory space is automatically
incremented.
2) Write to the LUT data register (LUTDAT15–LUTDAT0)
to initialize the step size, hysteresis threshold size,
and size of the LUT. See Table 28b.
Read data from the LUTs with the following sequence:
1) Write to the LUT address register to set the base
address for the first data word and the number of
LUT words to be read.
.8 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
HARD ADDRESS VALUE
KLUT2BASE
KLUT1BASE
0xC7
HARD ADDRESS VALUE
HARD ADDRESS VALUE
HARD ADDRESS VALUE
0xC6
0xC5
0xC4
0xC3
0xC2
TLUT2BASE
TLUT1BASE
KLUT2CNFG
KLUT1CNFG
TLUT2CNFG
TLUT1CNFG
KLUT2 VALUE 48
KLUT2 VALUE 47
HARD ADDRESS VALUE
HARD ADDRESS VALUE
HARD ADDRESS VALUE
HARD ADDRESS VALUE
0xC1
0xC0
0xBF
0xBE
KLUT2 VALUE 1
KLUT2 VALUE 0
KLUT1 VALUE 47
KLUT1 VALUE 46
0x91
0x90
HARD ADDRESS VALUE
0x8F
0x8E
0x61
0x60
0x5F
0x5E
KLUT1 VALUE 1
KLUT1 VALUE 0
TLUT2 VALUE 47
HARD ADDRESS VALUE
TLUT2 VALUE 46
TLUT2 VALUE 1
TLUT2 VALUE 0
TLUT1 VALUE 47
0x31
0x30
HARD ADDRESS VALUE
0x2F
0x2E
TLUT1 VALUE 46
TLUT1 VALUE 1
TLUT1 VALUE 0
0x01
0x00
HARD ADDRESS VALUE
Figure 28. LUT Memory Space
______________________________________________________________________________________ .9
Automatic RF MESFET Amplifier
Drain-Current Controllers
bit threshold. Using the temperature LUT as an exam-
Table 280 LUT Addresses
ple, if the HYS value is 101 (16 bits) and the latest tem-
perature measurement differs from the last one by more
than 2°C, a new TLUT operation is performed and a
new TLUT value is calculated. Bits D3–D0 set the LUT
step size. See Table 28c. The step size is based on the
LUTADD7–LUTADD±
HEX
FUNCTION
0000 0000 to 0010 1111 00 to 2F TLUT1-0 to TLUT1-47
0011 0000 to 0101 1111 30 to 5F TLUT2-0 to TLUT2-47
0110 0000 to 1000 1111 60 to 8F KLUT1-0 to KLUT1-47
1001 0000 to 1011 1111 90 to BF KLUT2-0 to KLUT2-47
N
value of 2 , with N equaling the digital value of the
0
STEP bits. Set the step size between 1 (2 ) and 512
9
10
15
(2 ). Locations 1010 (2 ) to 1111 (2 ) are reserved.
Do not write to these locations.
1100 0000
1100 0001
1100 0010
1100 0011
1100 0100
1100 0101
1100 0110
1100 0111
C0
C1
C2
C3
C4
C5
C6
C7
TLUT1 configuration
TLUT2 configuration
KLUT1 configuration
KLUT2 configuration
TLUT1 base
LUT Base
The following two-step sequence determines the
respective channel’s temperature or K LUT base value:
1) Set the LUTADD bits in the LUT address register to
C4h (TLUT1), C5h (TLUT2), C6h (KLUT1) and C7h
(KLUT2). See Table 28d.
TLUT2 base
KLUT1 base
KLUT2 base
2) Write to the LUT data register (LUTDAT15–
LUTDAT0) to initialize the base word. The KLUT
base value is stored in binary format, with the LSB
equaling 1. The TLUT base value is stored in two’s-
complement format, with the LSB equaling
+0.125°C.
When performing a write operation, the first 3 LUTDAT
bits, D15, D14, and D13 are don’t care. When perform-
ing a read operation, these bits are set to the LUT data
channel tag 110. Bits D12–D7 set the size of the LUT in
binary format. Set the LUT size between 8 (001000)
and 48 (110000). Bits D6, D5, and D4 set the hysteresis
Table 28a0 LUT Data Reꢂister Memorc Map
LUTADD7–
LUTADD±
(HEX)
LUTDAT1.
LUTDAT±
ADDRESS
NAME
D1.
1
D14
D13
0
D12
X
D11
MSB
MSB
MSB
MSB
D1± D9 D8 D7 D6 D. D4 D3 D2 D1 D±
TLUT1
TLUT2
KLUT1
KLUT2
00 to 2F
30 to 5F
60 to 8F
90 to BF
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSB
LSB
LSB
LSB
1
0
X
1
0
X
1
0
X
TLUT1
Configuration
C0
C1
C2
C3
1
1
1
1
1
1
1
1
0
0
0
0
See Table 28b for bit details.
See Table 28b for bit details.
See Table 28b for bit details.
See Table 28b for bit details.
TLUT2
Configuration
KLUT1
Configuration
KLUT2
Configuration
TLUT1 Base
TLUT2 Base
KLUT1 Base
KLUT2 Base
C4
C5
C6
C7
1
1
1
1
1
1
1
1
0
0
0
0
X
X
X
X
MSB
MSB
MSB
MSB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSB
LSB
LSB
LSB
X = Don’t care.
6± ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 28b0 LUT Confiꢂuration
RESET
ꢃIT NAME
SIZE5
DATA ꢃIT
D12
D11
D10
D9
FUNCTION
0
0
0
0
0
0
SIZE4
The SIZE field is a straight binary representation of the size of the respective LUT.
SIZE5 is the MSB of the 6 SIZE bits. SIZE0 is the LSB. Set the size of the LUT between
eight entries (001000) and 48 entries (110000).
SIZE3
SIZE2
SIZE1
D8
SIZE0
D7
The HYS2, HYS1, and HYS0 bits set the hysteresis bit threshold for each LUT. When
the difference between the last index value and the next index value is less than the
value set by HYS2, HYS1, and HYS0 bits, the LUT operation for that parameter is
omitted and the last value calculated for the respective LUT is used.
HYS2
D6
0
Set the HYS2 (MSB), HYS1, and HYS0 (LSB) bits to the following hysteresis bit values:
000: 0 bits (a new LUT operation is always performed)
001: 1 bit (if the value differs by 1 bit, a new LUT operation is performed)
010: 2 bits
011: 4 bits
100: 8 bits
101: 16 bits
110: 32 bits
111: 64 bits
HYS1
D5
0
HYS0
STEP3
STEP2
STEP1
STEP0
D4
D3
D2
D1
D0
0
0
0
0
0
The STEP3–STEP0 bits determine the LUT 12-bit step size. The step size is a 2N value.
The N value is determined by the STEP bits, with STEP3 being the MSB and STEP0
the LSB. See Table 28c for the TLUT and KLUT step-size equivalents.
Table 28ꢀ0 LUT Confiꢂuration Step Sizes
TLUT STEP-SIZE
EQUIꢁALENT
KLUT STEP-SIZE
EQUIꢁALENT
STEP3
STEP2
STEP1
STEP±
LUT STEP SIZE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
+0.125°C
+0.25°C
1
2
4
+0.5°C
4
8
+1°C
8
16
32
64
128
256
512
+2°C
16
32
64
128
256
512
+4°C
+8°C
+16°C
+32°C
+64°C
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
______________________________________________________________________________________ 61
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 28d0 LUT ꢃase
ꢃIT NAME
DATA ꢃIT
RESET STATE
FUNCTION
The base value signifies the starting point for the LUT. The KLUT base
value is stored in binary format, with the LSB equaling 1. The TLUT base
value is stored in two’s-complement format, with the LSB equaling
+0.125°C.
BASE11–BASE0
D11–D0
N/A
KLUT2BASE
0xC7
0xC6
KLUT1BASE
TLUT2BASE
0xC5
0xC4
TLUT1BASE = 1111 0001 0000 (-30˚C)
KLUT2CNFG
0xC3
0xC2
KLUT1CNFG
TLUT2CNFG
0xC1
0xC0
T LUT1CNFG = 0 0100 0xxx 0111
0x08
TLUT1 VALUE 8 = UNUSED
TLUT1 VALUE 7
+82°C
0x07
0x06
TLUT1 VALUE 6
TLUT1 VALUE 5
TLUT1 VALUE 4
TLUT1 VALUE 3
TLUT1 VALUE 2
TLUT1 VALUE 1
TLUT1 VALUE 0
+66°C
+50°C
0x05
0x04
+34°C
+18°C
+2°C
0x03
0x02
-14°C
0x01
0x00
TLUT1 BASE = -30°C
Figure 29. TLUT Example
Both the T and K LUTs contain 12-bit data. The TLUT
data is stored in two’s-complement format with decimal
values ranging from -2048/2048 (-1) to +2047/2048
(+0.9995) in steps of approximately 0.0005.
The temperature LUT data is stored in two’s-complement
format. Figure 29 details a channel 1 TLUT example with
eight entries where the base temperature is -30°C and
the step size is 128 (+16°C between each entry).
The KLUT data is stored in binary format with decimal
values ranging from 0 to +4095/4096 (0.9998) in steps
of approximately 0.0002.
62 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
KLUT2BASE
KLUT1BASE = 0011 0011 0011 (819d)
TLUT2BASE
0xC7
0xC6
0xC5
0xC4
TLUT1BASE
KLUT2CNFG
0xC3
0xC2
KLUT1CNFG = 0 0100 1xxx 1000
TLUT2CNFG
0xC1
0xC0
T LUT1CNFG
KLUT1 VALUE 9 = UNUSED
KLUT1 VALUE 8
0x68
1.7499V
1.5936V
KLUT1 VALUE 7
0x67
0x66
KLUT1 VALUE 6
1.4374V
1.2811V
KLUT1 VALUE 5
0x65
0x64
KLUT1 VALUE 4
KLUT1 VALUE 3
1.1249V
0x63
0x62
0.9686V
0.8124V
KLUT1 VALUE 2
KLUT1 VALUE 1
KLUT1 VALUE 0
0.6561V
0x61
0x60
KLUT1 BASE = 0.4999V
Figure 30. KLUT Example
The KLUT data is stored in straight binary format.
Figure 30 details a channel 1 KLUT example with nine
entries, a range of 0.5V to 1.7V, and a step size of 256.
Internally Timed Acquisitions
and Conversions
Clock Mode 00
In clock mode 00, power-up, acquisition, conversion,
and power-down are all initiated by writing to the ADC
conversion register and performed automatically using
the internal oscillator. This is the default clock mode.
With ADCMON set to 1, the ADC sets the BUSY output
high, powers up, scans all requested channels, stores
the results in the FIFO, and then powers down. After the
scan is complete, the BUSY output is pulled low and
the results are available in the FIFO.
Assuming V
= +2.5V, the base value (819d) is
REFDAC
determined by the following equation:
0.5V
2.5V
x 4096 = 819d
______________________________________________________________________________________ 63
Automatic RF MESFET Amplifier
Drain-Current Controllers
t
t
t
ACQ11
CNV11
ACQ11
CNVST
BUSY
END OF SCAN,
REFERENCE AND
TEMPERATURE SENSOR
POWER DOWN
IDLE, BUT REFERENCE
AND TEMPERATURE
SENSOR STAY
IDLE, BUT REFERENCE
AND TEMPERATURE
SENSOR STAY
INT REFERENCE POWERS UP IN 45μs
TEMP CONVERSION IN 30μs
INTERNALLY*
POWERED UP
POWERED UP
AUTOMATICALLY
CH5 LOADED
INTO THE FIFO
CH10 LOADED
INTO THE FIFO
CH0 (INTERNAL
TEMPERATURE) RESULT
LOADED INTO THE FIFO
WRITE TO THE ADC
CONVERSION REGISTER TO
SET UP THE SCAN
*ALL TIMING SPECIFICATIONS ARE TYPICAL.
CLOCK MODE 11 EXAMPLE 1: COMMAND A SCAN OF CHANNELS 0, 5, AND 10 WITH AN INTERNAL REFERENCE.
Figure 31. Clock Mode 11 Timing Example 1
Clock Mode 01
In clock mode 01, power-up, acquisition, conversion,
and power-down are all initiated by a single CNVST low
pulse and performed automatically using the internal
oscillator. Initiate a scan by writing to the ADC conver-
sion register to indicate which channels to convert.
Then set CNVST low for at least 20ns only once to con-
vert all of the channels selected in the ADC conversion
register. With ADCMON set to 1, the ADC sets the
BUSY output high, powers up, scans all requested
channels, stores the results in the FIFO, and powers
down. After the scan is complete, the BUSY output is
pulled low and the results are available in the FIFO.
Internal and external temperature conversions are inter-
nally timed. Set CNVST low for at least 20ns to acquire
a temperature conversion. The BUSY output goes high
while sampling and the internal reference typically
requires 45µs to power up. The temperature sensor cir-
cuit requires 5µs to power up. Temperature conversion
results are available after an additional 30µs. The typi-
cal conversion time of the initial temperature sensor
scan is 80µs. Subsequent temperature scans only take
30µs typically as the internal reference and tempera-
ture sensor circuits are already powered. See the
Electrical Characteristics table for more details.
Set CNVST low for at least 1.5µs to acquire a voltage
conversion using the external reference. The BUSY out-
put goes high while sampling and the conversion
results are available after an additional 3.5µs (typ).
Externally Timed Acquisitions and
Conversions
Clock Mode 10
Clock mode 10 is reserved. Do not use this clock mode.
Set CNVST low for at least 50µs to trigger an initial volt-
age conversion using the internal reference. The BUSY
output goes high and the conversion results are avail-
able after an additional 3.5µs typically. Additional volt-
age conversions do not require the acquisition time of
powering up the internal reference. Set CNVST low for
at least 1.5µs to power up the ADC and place it in track
mode. The BUSY output goes high while sampling and
the conversion results are available after 5.6µs.
Clock Mode 11
In clock mode 11, conversions are initiated by CNVST
one at a time and performed using the internal oscilla-
tor. See Figures 31 and 32 for a pair of clock mode 11
timing examples. Initiate a conversion by writing to the
ADC conversion register and pulling CNVST low for at
least 1.5µs for each channel converted. Different timing
parameters apply to whether the conversion is a tem-
perature, a voltage using the external reference, or a
voltage using the internal reference conversion.
64 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
t
t
ACQ11
CNV11
t
PUINT
CNVST
BUSY
END OF SCAN,
REFERENCE AND
TEMPERATURE SENSOR
POWER DOWN
IDLE, BUT REFERENCE
AND TEMPERATURE
SENSOR STAY
IDLE, BUT REFERENCE
STAYS POWERED UP
TEMPERATURE CONVERSION IN
INTERNALLY*
INT REFERENCE POWERS UP IN 45μs
30μs
POWERED UP
AUTOMATICALLY
CH5 LOADED
INTO THE FIFO
CH10 LOADED
INTO THE FIFO
CH6 (EXTERNAL
TEMPERATURE) RESULT
LOADED INTO THE FIFO
WRITE TO THE ADC
CONVERSION REGISTER TO
SET UP THE SCAN
*ALL TIMING SPECIFICATIONS ARE TYPICAL.
CLOCK MODE TIMING EXAMPLE 2: COMMANDS A SCAN OF CHANNELS 5, 6, AND 10 WITH AN INTERNAL REFERENCE.
Figure 32. Clock Mode 11 Timing Example 2
•
CKSEL1/CKSEL0 = 11 and is then changed to
another value:
Changing Clock Modes During ADC
Conversions
If the hardware configuration register’s CKSEL1 or
CKSEL0 bits are changed while the ADC is performing
a conversion (or series of conversions), the
MAX11014/MAX11015 reacts in one of three ways:
If waiting for an external trigger, the MAX11014/
MAX11015 immediately exit clock mode 11, power
down the ADC, and go idle. The BUSY output
stays low and waits for the external trigger.
If a conversion sequence is in progress, that con-
version is completed and then the ADC goes idle.
•
CKSEL1/CKSEL0 = 00 and is then changed to
another value:
The ADC completes the already triggered series of
conversions and then goes idle. The BUSY output
remains high until the conversions are completed.
The MAX11014/MAX11015 then responds according
to commands with the new clock mode.
Applications Information
Layout Considerations
For the external temperature sensor to perform to spec-
ifications, care must be taken to place the
MAX11014/MAX11015 as close as is practical to the
remote diode. Traces of DXP_ and DXN_ should not be
routed across noisy lines and buses. DXP_ and DXN_
routes should be guarded by ground traces on either
sides and should be routed over a quiet ground plane.
Traces should be wide enough (> 10mm) to lower
inductance, which tends to pick up radiated noise.
•
CKSEL1/CKSEL0 = 01 and is then changed to
another value:
If waiting for the initial external trigger, the
MAX11014/MAX11015 immediately exit clock
mode 01, power down the ADC, and go idle.
If a conversion sequence is in progress, that conver-
sion is completed and then the ADC goes idle. The
BUSY output remains high until the conversions are
completed. The MAX11014/MAX11015 then respond
according to commands with the new clock mode.
______________________________________________________________________________________ 6.
Automatic RF MESFET Amplifier
Drain-Current Controllers
error (residual error). The ideal, theoretical minimum
Definitions
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution
(N bits):
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX11014/MAX11015 is measured using the end-
point method.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS noise plus distortion. RMS noise plus distortion
includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset:
ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
SINAD (dB) = 20 x log (SIGNAL
/ NOISE
)
RMS
RMS
ADC Gain Error
When a positive full-scale voltage is applied to the con-
verter inputs, the digital output is all ones (FFFh). The
transition from FFEh to FFFh occurs at 1.5 LSB below
full scale. Gain error is the amount of deviation between
the measured full-scale transition point and the ideal
full-scale transition point with the offset error removed.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
DAC Offset Error
DAC offset error is determined by loading a code of all
zeros into the DAC and measuring the analog output
voltage.
ENOB = (SINAD − 1.76) / 6.02
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all 1s into the DAC.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
2
2
2
2
2
V
+ V + V + V + V
3 4 5 6
2
Aperture Jitter
THD = 20 x log
V
1
Aperture jitter, t , is the statistical distribution of the
AJ
variation in the sampling instant.
where V is the fundamental amplitude, and V through
1
2
V are the amplitudes of the first five harmonics.
6
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest
spectral component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
66 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
ADC Channel-to-Channel Crosstalk
Pin Configuration
Bias the ON channel to midscale. Apply a full-scale sine-
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
PGAOUT2
PGAOUT1
FILT4
N.C.
OPSAFE1
OPSAFE2
24
23
22
37
38
39
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f and
1
21 FILT3
20 FILT2
19 FILT1
BUSY 40
f , are present at the inputs. The intermodulation prod-
2
DV
DD
41
42
43
ucts are (f
f ), (2 x f ), (2 x f ), (2 x f
f ), (2 x f
2 2
1
2
1
2
1
DGND
f ). The individual input tone levels are at -7dBFS.
1
MAX11014
MAX11015
18
GATE1
CNVST
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
17 ACLAMP1
16 N.C.
ALARM 44
CS/A0 45
GATEV
SPI/I2C
N.C./A2
15
46
47
48
SS
14 GATE2
13
ACLAMP2
SCLK/SCL
2
3
4
5
6
7
8
9
10
1
11
12
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
TQFN
7mm x 7mm X ±08mm
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
ADC Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
error when the power supply is moved from the minimum
operating voltage to the maximum operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full scale as the power-supply voltage
changes from its nominal value. PSR assumes the
converter’s linearity is unaffected by changes in the
power-supply voltage.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 67
Automatic RF MESFET Amplifier
Drain-Current Controllers
Typical Operating Circuit
+5V
+5V
EXTERNAL
REFERENCE
DRAIN
SUPPLY
SCLK/SCL
DIN/SDA
RCS1+
RCS1-
CS/A0
N.C./A2
DOUT/A1
ALARM
BUSY
μC
GATE1
DGND
+5V
RF
OUTPUT
SPI/I2C
ADCIN1
ADCIN2
MAX11014
MAX11015
RF
INTPUT
OPSAFE1
ACLAMP1
ACLAMP2
OPSAFE2
FILT1
FILT2
CNVST
(AT MESFET)
(AT MESFET)
DRAIN
SUPPLY
DXP1
FILT3
FILT4
RCS2+
DXN1
DXP2
+5V
RCS2-
GATE2
DXN2
RF
OUTPUT
RF
INTPUT
-5V
68 ______________________________________________________________________________________
Automatic RF MESFET Amplifier
Drain-Current Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to ꢄꢄꢄ0maxim-iꢀ0ꢀom/paꢀkaꢂes.)
E
DETAIL A
(NE-1) X
e
E/2
k
e
D/2
C
(ND-1) X
e
D2
D
L
D2/2
b
L
E2/2
C
L
k
DETAIL B
E2
e
C
C
L
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
21-0144
E
2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
21-0144
E
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 69
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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